io: add display unit

added rendering for modes 3,4,5
also changed how memory structuring works

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

.github/workflows/clang.yml

@@ -9,19 +9,19 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v3
-      - uses: cachix/install-nix-action@v20
+      - uses: cachix/install-nix-action@v27
         with:
           extra_nix_config: |
             auto-optimise-store = true
             experimental-features = nix-command flakes
-      - uses: cachix/cachix-action@v12
+      - uses: cachix/cachix-action@v15
         with:
           name: pain
           authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
 
 
       - name: setup
-        run: nix develop .#matar-clang -c meson setup $BUILDDIR
+        run: nix develop .#matar-clang -c meson setup $BUILDDIR -Dgdb_debug=true
 
       - name: fmt
         run: nix develop .#matar-clang -c ninja clang-format-check -C $BUILDDIR
@@ -29,8 +29,8 @@ jobs:
       - name: lint
         run: nix develop .#matar-clang -c ninja clang-tidy -C $BUILDDIR
 
-      - name: tests
-        run: nix develop .#matar-clang -c ninja test -C $BUILDDIR
-
       - name: build
         run: nix develop .#matar-clang -c ninja -C $BUILDDIR
+
+      - name: tests
+        run: nix develop .#matar-clang -c ninja test -C $BUILDDIR

.github/workflows/gcc.yml

@@ -9,22 +9,22 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v3
-      - uses: cachix/install-nix-action@v20
+      - uses: cachix/install-nix-action@v27
         with:
           extra_nix_config: |
             auto-optimise-store = true
             experimental-features = nix-command flakes
-      - uses: cachix/cachix-action@v12
+      - uses: cachix/cachix-action@v15
         with:
           name: pain
           authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
 
 
       - name: setup
-        run: nix develop .#matar -c meson setup $BUILDDIR
-
-      - name: tests
-        run: nix develop .#matar -c ninja test -C $BUILDDIR
+        run: nix develop .#matar -c meson setup $BUILDDIR -Dgdb_debug=true
 
       - name: build
         run: nix develop .#matar -c ninja -C $BUILDDIR
+
+      - name: tests
+        run: nix develop .#matar -c ninja test -C $BUILDDIR

.gitignore

@@ -3,5 +3,5 @@ result
 build/
 .cache/
 *~
-#*#
+\#*\#
 .#*

README.md

@@ -5,18 +5,77 @@ But if you are curious (probably not), read ahead
 # Dependencies
 ## Tested toolchains
 
-- LLVM 16.0.6
-- GCC 12.3.0
+- LLVM 18.1.7
+- GCC 14.1.0
 
-In theory, any toolchain supporting at least the C++20 standard should work.
+In theory, any toolchain supporting at least the c++23 standard should work.
 I am using LLVM's clang and libcxx as the primary toolchain.
 
 ## Static libraries
 
-| Name   | Version   | Required? |
-|:------:|:----------|:---------:|
-| fmt    | >= 10.1.1 | yes       |
-| catch2 | >= 3.4    | for tests |
+| Name   | Version | Required? | Purpose   |
+|:------:|:--------|:---------:|:---------:|
+| catch2 | >= 3.4  | no        | for tests |
 
 This goes without saying but using a different toolchain to compile these libraries before linking probably won't work.
-I will add meson wrap support once LLVM 17 is out, since I want to get rid of fmt.
+
+# Status
+- [x] CPU
+
+  - [x] Arm
+    - [x] Dissassembler
+    - [x] Execution
+
+  - [x] Thumb
+    - [x] Dissassembler
+    - [x] Execution
+    
+- [ ] Bus
+  - [x] Cycle counting with CPU
+  - [x] Reading memory
+  - [x] Writing memory
+  
+- [ ] Scheduler (maybe?)
+  - [ ] Sync PPU and CPU
+  - [ ] Sync APU and CPU
+  - [ ] Sync other stuff
+
+- [ ] I/O
+  - [ ] PPU
+  - [ ] APU
+  - [ ] Timers
+  - [ ] DMA
+  - [ ] Keypad
+
+- Debugging
+  - [x] GDB Remote Serial Protocol support
+  
+- Misc
+  - [ ] Save/Load states
+  - [x] Header Parsing
+
+- Internal utilities
+  - [x] Bit manipulation
+  - [x] A global logger
+  - [x] TCP Server (for GDB RSP)
+  - [x] SHA256 hash (why? idk)
+
+## Available unit tests so far
+- CPU
+  - Arm
+    - Disassembler
+    - Execution
+  - Thumb
+    - Disassembler
+    - Execution
+- Bus
+  - Memory read/writes
+  - Cycle Counting
+- Some internal utility tests (idk why)
+  
+
+-----
+
+# LOG
+- June 11, 2024: After almost an year, I have come back to this silly abandoned project, will probably complete it soon.
+- June 16, 2024: I ought to complete this soon

apps/target/main.cc

@@ -1,14 +1,13 @@
 #include "bus.hh"
 #include "cpu/cpu.hh"
-#include "memory.hh"
 #include "util/loglevel.hh"
 #include <array>
+#include <chrono>
 #include <cstdlib>
 #include <fstream>
 #include <iostream>
 #include <memory>
-#include <ostream>
-#include <unistd.h>
+#include <thread>
 #include <vector>
 
 // NOLINTBEGIN
@@ -16,7 +15,7 @@
 int
 main(int argc, const char* argv[]) {
     std::vector<uint8_t> rom;
-    std::array<uint8_t, matar::Memory::BIOS_SIZE> bios = { 0 };
+    std::array<uint8_t, matar::Bus::BIOS_SIZE> bios = { 0 };
 
     auto usage = [argv]() {
         std::cerr << "Usage: " << argv[0] << " <file> [-b <bios>]" << std::endl;
@@ -66,7 +65,7 @@ main(int argc, const char* argv[]) {
         ifile.seekg(0, std::ios::end);
         bios_size = ifile.tellg();
 
-        if (bios_size != matar::Memory::BIOS_SIZE) {
+        if (bios_size != matar::Bus::BIOS_SIZE) {
             throw std::ios::failure("BIOS file has invalid size",
                                     std::error_code());
         }
@@ -88,12 +87,14 @@ main(int argc, const char* argv[]) {
     matar::set_log_level(matar::LogLevel::Debug);
 
     try {
-        matar::Memory memory(std::move(bios), std::move(rom));
-        matar::Bus bus(memory);
+        std::shared_ptr<matar::Bus> bus =
+          matar::Bus::init(std::move(bios), std::move(rom));
+
         matar::Cpu cpu(bus);
+
         while (true) {
             cpu.step();
-            sleep(2);
+            //    std::this_thread::sleep_for(std::chrono::milliseconds(10));
         }
     } catch (const std::exception& e) {
         std::cerr << "Exception: " << e.what() << std::endl;

flake.lock

@@ -5,11 +5,11 @@
         "nixpkgs-lib": "nixpkgs-lib"
       },
       "locked": {
-        "lastModified": 1693611461,
-        "narHash": "sha256-aPODl8vAgGQ0ZYFIRisxYG5MOGSkIczvu2Cd8Gb9+1Y=",
+        "lastModified": 1717285511,
+        "narHash": "sha256-iKzJcpdXih14qYVcZ9QC9XuZYnPc6T8YImb6dX166kw=",
         "owner": "hercules-ci",
         "repo": "flake-parts",
-        "rev": "7f53fdb7bdc5bb237da7fefef12d099e4fd611ca",
+        "rev": "2a55567fcf15b1b1c7ed712a2c6fadaec7412ea8",
         "type": "github"
       },
       "original": {
@@ -20,11 +20,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1695318763,
-        "narHash": "sha256-FHVPDRP2AfvsxAdc+AsgFJevMz5VBmnZglFUMlxBkcY=",
+        "lastModified": 1717868076,
+        "narHash": "sha256-c83Y9t815Wa34khrux81j8K8ET94ESmCuwORSKm2bQY=",
         "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "e12483116b3b51a185a33a272bf351e357ba9a99",
+        "rev": "cd18e2ae9ab8e2a0a8d715b60c91b54c0ac35ff9",
         "type": "github"
       },
       "original": {
@@ -36,20 +36,14 @@
     },
     "nixpkgs-lib": {
       "locked": {
-        "dir": "lib",
-        "lastModified": 1693471703,
-        "narHash": "sha256-0l03ZBL8P1P6z8MaSDS/MvuU8E75rVxe5eE1N6gxeTo=",
-        "owner": "NixOS",
-        "repo": "nixpkgs",
-        "rev": "3e52e76b70d5508f3cec70b882a29199f4d1ee85",
-        "type": "github"
+        "lastModified": 1717284937,
+        "narHash": "sha256-lIbdfCsf8LMFloheeE6N31+BMIeixqyQWbSr2vk79EQ=",
+        "type": "tarball",
+        "url": "https://github.com/NixOS/nixpkgs/archive/eb9ceca17df2ea50a250b6b27f7bf6ab0186f198.tar.gz"
       },
       "original": {
-        "dir": "lib",
-        "owner": "NixOS",
-        "ref": "nixos-unstable",
-        "repo": "nixpkgs",
-        "type": "github"
+        "type": "tarball",
+        "url": "https://github.com/NixOS/nixpkgs/archive/eb9ceca17df2ea50a250b6b27f7bf6ab0186f198.tar.gz"
       }
     },
     "root": {

include/bus.hh

@@ -1,23 +1,111 @@
 #pragma once
 
+#include "header.hh"
+#include "io/io.hh"
 #include "memory.hh"
 #include <memory>
+#include <vector>
 
 namespace matar {
+enum CpuAccess {
+    Sequential,
+    NonSequential
+};
+
+enum CpuAccessWidth {
+    Word,
+    Halfword,
+    Byte
+};
+
 class Bus {
+  private:
+    struct Private {
+        explicit Private() = default;
+    };
+
   public:
-    Bus(const Memory& memory);
+    static constexpr uint32_t BIOS_SIZE = 1024 * 16;
 
-    uint8_t read_byte(size_t address);
-    void write_byte(size_t address, uint8_t byte);
+    Bus(Private, std::array<uint8_t, BIOS_SIZE>&&, std::vector<uint8_t>&&);
 
-    uint16_t read_halfword(size_t address);
-    void write_halfword(size_t address, uint16_t halfword);
+    static std::shared_ptr<Bus> init(std::array<uint8_t, BIOS_SIZE>&&,
+                                     std::vector<uint8_t>&&);
 
-    uint32_t read_word(size_t address);
-    void write_word(size_t address, uint32_t word);
+    uint8_t read_byte(uint32_t address, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
+        return read_byte(address);
+    };
+    void write_byte(uint32_t address, uint8_t byte, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
+        write_byte(address, byte);
+    };
+
+    uint16_t read_halfword(uint32_t address, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
+        return read_halfword(address);
+    }
+    void write_halfword(uint32_t address, uint16_t halfword, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
+        write_halfword(address, halfword);
+    }
+
+    uint32_t read_word(uint32_t address, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Word>(address, access);
+        return read_word(address);
+    }
+    void write_word(uint32_t address, uint32_t word, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Word>(address, access);
+        write_word(address, word);
+    }
+
+    uint8_t read_byte(uint32_t address);
+    void write_byte(uint32_t address, uint8_t byte);
+
+    uint16_t read_halfword(uint32_t address);
+    void write_halfword(uint32_t address, uint16_t halfword);
+
+    uint32_t read_word(uint32_t address);
+    void write_word(uint32_t address, uint32_t word);
+
+    // not sure what else to do?
+    void internal_cycle() { cycles++; }
+    uint32_t get_cycles() { return cycles; }
 
   private:
-    std::shared_ptr<Memory> memory;
+    template<CpuAccessWidth W>
+    void add_cpu_cycles(uint32_t address, CpuAccess access) {
+        auto cc = cycle_map[address >> 24 & 0xF];
+        if constexpr (W == CpuAccessWidth::Word) {
+            cycles += (access == CpuAccess::Sequential ? cc.s32 : cc.n32);
+        } else {
+            cycles += (access == CpuAccess::Sequential ? cc.s16 : cc.n16);
+        }
+    }
+
+    template<typename T>
+    T read(uint32_t address) const;
+
+    template<typename T>
+    void write(uint32_t address, T value);
+
+    uint32_t cycles = 0;
+    struct cycle_count {
+        uint8_t n16; // non sequential 8/16 bit width access
+        uint8_t n32; // non sequential 32 bit width access
+        uint8_t s16; // seuquential 8/16 bit width access
+        uint8_t s32; // sequential 32 bit width access
+    };
+    std::array<cycle_count, 0x10> cycle_map;
+    static constexpr decltype(cycle_map) init_cycle_count();
+
+    std::unique_ptr<IoDevices> io;
+    Memory<BIOS_SIZE> bios     = {};
+    Memory<0x40000> board_wram = {};
+    Memory<0x80000> chip_wram  = {};
+    Memory<> rom;
+
+    Header header;
+    void parse_header();
 };
 }

include/cpu/alu.hh

@@ -1,6 +1,5 @@
 #pragma once
 #include <cstdint>
-#include <fmt/ostream.h>
 
 namespace matar {
 enum class ShiftType {
@@ -40,5 +39,17 @@ struct Shift {
 };
 
 uint32_t
-eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
+eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry);
+
+uint32_t
+sub(uint32_t a, uint32_t b, bool& carry, bool& overflow);
+
+uint32_t
+add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
+
+uint32_t
+sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
+
+uint8_t
+multiplier_array_cycles(uint32_t x, bool zeroes_only = false);
 }

include/cpu/arm/instruction.hh

@@ -2,10 +2,13 @@
 #include "cpu/alu.hh"
 #include "cpu/psr.hh"
 #include <cstdint>
-#include <fmt/ostream.h>
+#include <string>
 #include <variant>
 
-namespace matar::arm {
+namespace matar {
+class Cpu;
+
+namespace arm {
 
 // https://en.cppreference.com/w/cpp/utility/variant/visit
 template<class... Ts>
@@ -23,7 +26,7 @@ struct BranchAndExchange {
 
 struct Branch {
     bool link;
-    uint32_t offset;
+    int32_t offset;
 };
 
 struct Multiply {
@@ -209,16 +212,19 @@ using InstructionData = std::variant<BranchAndExchange,
                                      SoftwareInterrupt>;
 
 struct Instruction {
-    Condition condition;
-    InstructionData data;
-
     Instruction(uint32_t insn);
-    Instruction(Condition condition, InstructionData data) noexcept
+    Instruction(Condition condition, InstructionData data)
       : condition(condition)
       , data(data) {};
 
+    void exec(Cpu& cpu);
+
 #ifdef DISASSEMBLER
     std::string disassemble();
 #endif
+
+    Condition condition;
+    InstructionData data;
 };
 }
+}

include/cpu/arm/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh'
+)

include/cpu/cpu.hh

@@ -1,21 +1,122 @@
+#pragma once
+
+#include "arm/instruction.hh"
 #include "bus.hh"
+#include "cpu/psr.hh"
+#include "thumb/instruction.hh"
+#include <cstdint>
+#include <memory>
+
+#ifdef GDB_DEBUG
+#include <unordered_set>
+#endif
 
 namespace matar {
-class CpuImpl;
+
+#ifdef GDB_DEBUG
+class GdbRsp;
+#endif
 
 class Cpu {
   public:
-    Cpu(const Bus& bus) noexcept;
-    Cpu(const Cpu&)            = delete;
-    Cpu(Cpu&&)                 = delete;
-    Cpu& operator=(const Cpu&) = delete;
-    Cpu& operator=(Cpu&&)      = delete;
-
-    ~Cpu();
+    Cpu(std::shared_ptr<Bus> bus) noexcept;
 
     void step();
+    void chg_mode(const Mode to);
 
+    void exec(arm::Instruction& instruction);
+    void exec(thumb::Instruction& instruction);
+
+#ifdef GDB_DEBUG
+    bool breakpoint_reached() {
+        if (breakpoints.contains(pc - 2 * (cpsr.state() == State::Arm
+                                             ? arm::INSTRUCTION_SIZE
+                                             : thumb::INSTRUCTION_SIZE))) {
+            return true;
+        }
+        return false;
+    }
+#endif
   private:
-    std::unique_ptr<CpuImpl> impl;
+    friend void arm::Instruction::exec(Cpu& cpu);
+    friend void thumb::Instruction::exec(Cpu& cpu);
+
+    static constexpr uint8_t GPR_COUNT = 16;
+
+    static constexpr uint8_t GPR_FIQ_FIRST = 8;
+    static constexpr uint8_t GPR_SVC_FIRST = 13;
+    static constexpr uint8_t GPR_ABT_FIRST = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST = 13;
+    static constexpr uint8_t GPR_UND_FIRST = 13;
+    static constexpr uint8_t GPR_OLD_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr = {}; // general purpose registers
+
+    Psr cpsr = {}; // current program status register
+    Psr spsr = {}; // status program status register
+
+    static constexpr uint8_t SP_INDEX = 13;
+    static_assert(SP_INDEX < GPR_COUNT);
+    uint32_t& sp = gpr[SP_INDEX];
+
+    static constexpr uint8_t LR_INDEX = 14;
+    static_assert(LR_INDEX < GPR_COUNT);
+    uint32_t& lr = gpr[LR_INDEX];
+
+    static constexpr uint8_t PC_INDEX = 15;
+    static_assert(PC_INDEX < GPR_COUNT);
+    uint32_t& pc = gpr[PC_INDEX];
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_OLD_FIRST - 1> old;
+    } gpr_banked = {}; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked = {}; // banked saved program status registers
+
+    void internal_cycle() { bus->internal_cycle(); }
+
+    // whether read is going to be sequential or not
+    CpuAccess next_access = CpuAccess::Sequential;
+
+    // raw instructions in the pipeline
+    std::array<uint32_t, 2> opcodes = {};
+
+    void advance_pc_arm();
+    void advance_pc_thumb();
+
+    template<State S>
+    void flush_pipeline() {
+        if constexpr (S == State::Arm) {
+            opcodes[0] = bus->read_word(pc, CpuAccess::NonSequential);
+            advance_pc_arm();
+            opcodes[1] = bus->read_word(pc, CpuAccess::Sequential);
+            advance_pc_arm();
+        } else {
+            opcodes[0] = bus->read_halfword(pc, CpuAccess::NonSequential);
+            advance_pc_thumb();
+            opcodes[1] = bus->read_halfword(pc, CpuAccess::Sequential);
+            advance_pc_thumb();
+        }
+        next_access = CpuAccess::Sequential;
+    }
+
+#ifdef GDB_DEBUG
+    friend class GdbRsp;
+    std::unordered_set<uint32_t> breakpoints = {};
+#endif
 };
 }

include/cpu/meson.build

@@ -1,3 +1,8 @@
 headers += files(
+  'alu.hh',
   'cpu.hh',
+  'psr.hh'
 )
+
+subdir('arm')
+subdir('thumb')

include/cpu/psr.hh

@@ -1,7 +1,6 @@
 #pragma once
 
 #include <cstdint>
-#include <fmt/ostream.h>
 
 namespace matar {
 enum class Mode {
@@ -61,7 +60,7 @@ stringify(Condition cond) {
         CASE(GT)
         CASE(LE)
         case Condition::AL: {
-            // empty
+            return "";
         }
     }
 
@@ -72,7 +71,7 @@ stringify(Condition cond) {
 
 class Psr {
   public:
-    // clear the reserved bits i.e, [8:27]
+    Psr() = default;
     Psr(uint32_t raw);
 
     uint32_t raw() const;
@@ -116,7 +115,6 @@ class Psr {
 
   private:
     static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
-    static constexpr uint32_t PSR_CLEAR_MODE     = 0xFFFFFFE0;
 
     uint32_t psr;
 };

include/cpu/thumb/instruction.hh

@@ -3,10 +3,13 @@
 #include "cpu/alu.hh"
 #include "cpu/psr.hh"
 #include <cstdint>
-#include <fmt/ostream.h>
+#include <string>
 #include <variant>
 
-namespace matar::thumb {
+namespace matar {
+class Cpu;
+
+namespace thumb {
 
 // https://en.cppreference.com/w/cpp/utility/variant/visit
 template<class... Ts>
@@ -170,7 +173,7 @@ stringify(HiRegisterOperations::OpCode opcode) {
 }
 
 struct PcRelativeLoad {
-    uint8_t word;
+    uint16_t word;
     uint8_t rd;
 };
 
@@ -206,20 +209,19 @@ struct LoadStoreHalfword {
 };
 
 struct SpRelativeLoad {
-    uint8_t word;
+    uint16_t word;
     uint8_t rd;
     bool load;
 };
 
 struct LoadAddress {
-    uint8_t word;
+    uint16_t word;
     uint8_t rd;
     bool sp;
 };
 
 struct AddOffsetStackPointer {
-    uint8_t word;
-    bool sign;
+    int16_t word;
 };
 
 struct PushPopRegister {
@@ -235,19 +237,21 @@ struct MultipleLoad {
 };
 
 struct ConditionalBranch {
-    uint16_t offset;
+    int32_t offset;
     Condition condition;
 };
 
-struct SoftwareInterrupt {};
+struct SoftwareInterrupt {
+    uint8_t vector;
+};
 
 struct UnconditionalBranch {
-    uint16_t offset;
+    int32_t offset;
 };
 
 struct LongBranchWithLink {
     uint16_t offset;
-    bool high;
+    bool low;
 };
 
 using InstructionData = std::variant<MoveShiftedRegister,
@@ -271,12 +275,17 @@ using InstructionData = std::variant<MoveShiftedRegister,
                                      LongBranchWithLink>;
 
 struct Instruction {
-    InstructionData data;
-
     Instruction(uint16_t insn);
+    Instruction(InstructionData data)
+      : data(data) {}
+
+    void exec(Cpu& cpu);
 
 #ifdef DISASSEMBLER
     std::string disassemble();
 #endif
+
+    InstructionData data;
 };
 }
+}

include/cpu/thumb/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh'
+)

include/io/display/display.hh

@@ -0,0 +1,159 @@
+#include "memory.hh"
+#include <array>
+#include <bit>
+#include <cstdint>
+#include <sys/types.h>
+
+// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
+namespace matar {
+namespace display {
+static constexpr int LCD_WIDTH = 240;
+
+// there are 5 modes
+static constexpr uint N_MODES = 6;
+// there are 4 backgrounds that can be layered depending on mode
+// there is also 1 object layer
+static constexpr uint N_BACKGROUNDS = 4;
+
+static constexpr uint32_t PRAM_START = 0x5000000;
+static constexpr uint32_t VRAM_START = 0x6000000;
+static constexpr uint32_t OAM_START  = 0x7000000;
+
+template<typename T, typename = std::enable_if_t<std::is_arithmetic_v<T>>>
+struct Point {
+    T x;
+    T y;
+};
+
+struct Color {
+  public:
+    Color(uint16_t raw)
+      : red(raw & 0b11111)
+      , green(raw >> 5 & 0b11111)
+      , blue(raw >> 10 & 0b11111) {}
+
+    uint16_t read() const {
+        return (red & 0b11111) | ((green << 5) & 0b11111) |
+               ((blue << 10) & 0b11111);
+    }
+
+  private:
+    uint8_t red;
+    uint8_t green;
+    uint8_t blue;
+};
+
+struct DisplayControl {
+    struct {
+        uint8_t mode : 3;
+        int : 1; // unused
+        bool frame_select_1 : 1;
+        bool hblank_free_interval : 1;
+        bool obj_character_vram_mapping : 1;
+        bool forced_blank : 1;
+        bool screen_display_0 : 1;
+        bool screen_display_1 : 1;
+        bool screen_display_2 : 1;
+        bool screen_display_3 : 1;
+        bool screen_display_obj : 1;
+        bool window_display_0 : 1;
+        bool window_display_1 : 1;
+        bool obj_window_display : 1;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value); };
+    void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
+};
+
+struct DisplayStatus {
+    struct {
+        bool vblank_flag : 1;
+        bool hblank_flag : 1;
+        bool vcounter_flag : 1;
+        bool vblank_irq_enable : 1;
+        bool hblank_irq_enable : 1;
+        bool vcounter_irq_enable : 1;
+        int : 2; // unused
+        uint8_t vcount_setting : 8;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value); };
+    void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
+};
+
+struct BackgroundControl {
+    struct {
+        uint8_t priority : 2;
+        uint8_t character_base_block : 2;
+        int : 2; // unused
+        bool mosaic : 1;
+        bool colors256 : 1;
+        uint8_t screen_base_block : 5;
+        bool bg_2_3_wraparound : 1;
+        uint8_t screen_size : 2;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value); };
+    void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
+};
+
+struct RotationScaling {
+    // these are all 16 bit signed "fixed point" floats
+    // shifted by 8
+    int16_t a;
+    int16_t b;
+    int16_t c;
+    int16_t d;
+
+    // following points have 28 bit signed "fixed point" floats as coords
+    // shifted by 8
+    Point<int32_t> ref;
+
+  private:
+    Point<int32_t> internal [[maybe_unused]]
+    ;
+};
+
+struct Display {
+  public:
+    using u16 = uint16_t;
+
+    Memory<0x400> pram;
+    Memory<0x18000> vram;
+    Memory<0x400> oam;
+
+    DisplayControl lcd_control;
+    DisplayStatus general_lcd_status;
+    u16 vertical_counter;
+    BackgroundControl bg_control[4];
+    Point<u16> bg0_offset;
+    Point<u16> bg1_offset;
+    Point<u16> bg2_offset;
+    Point<u16> bg3_offset;
+    RotationScaling bg2_rot_scale;
+    RotationScaling bg3_rot_scale;
+    u16 win0_horizontal_dimensions;
+    u16 win1_horizontal_dimensions;
+    u16 win0_vertical_dimensions;
+    u16 win1_vertical_dimensions;
+    u16 inside_win_0_1;
+    u16 outside_win;
+    u16 mosaic_size;
+    u16 color_special_effects_selection;
+    u16 alpha_blending_coefficients;
+    u16 brightness_coefficient;
+
+  private:
+    // 1 color is 16 bits in ARGB555 format
+    std::array<std::array<uint16_t, LCD_WIDTH>, N_BACKGROUNDS> scanline_buffers;
+
+    template<int MODE,
+             typename = std::enable_if_t<MODE == 3 || MODE == 4 || MODE == 5>>
+    void render_bitmap_mode();
+
+    template<int LAYER, typename = std::enable_if_t<LAYER >= 0 && LAYER <= 3>>
+    void render_text_layer();
+};
+}
+}
+// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

include/io/dma.hh

@@ -0,0 +1,39 @@
+#include <bit>
+#include <cstdint>
+
+namespace matar {
+// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
+struct DmaControl {
+    struct {
+        int : 4; // this is supposed to be 5 bits, however, to align the struct
+                 // to 16 bits, we will adjust for the first LSB in the
+                 // read/write
+        uint8_t dst_adjustment : 2;
+        uint8_t src_adjustment : 2;
+        bool repeat : 1;
+        bool transfer_32 : 1;
+        int : 1;
+        uint8_t start_timing : 2;
+        bool irq_enable : 1;
+        bool enable : 1;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value) << 1; };
+    void write(uint16_t raw) {
+        value = std::bit_cast<decltype(value)>(static_cast<uint16_t>(raw >> 1));
+    };
+};
+
+struct Dma {
+    using u16 = uint16_t;
+
+    struct {
+        u16 source[2];
+        u16 destination[2];
+        u16 word_count;
+        DmaControl control;
+    } channels[4];
+};
+// NOLINTEND(cppcoreguidelines-avoid-c-arrays)
+
+}

include/io/io.hh

@@ -0,0 +1,43 @@
+#pragma once
+
+#include "display/display.hh"
+#include "dma.hh"
+#include "sound.hh"
+#include <cstdint>
+#include <memory>
+
+namespace matar {
+class Bus; // forward declaration
+
+class IoDevices {
+  public:
+    IoDevices(std::weak_ptr<Bus>);
+
+    uint8_t read_byte(uint32_t) const;
+    void write_byte(uint32_t, uint8_t);
+
+    uint32_t read_word(uint32_t) const;
+    void write_word(uint32_t, uint32_t);
+
+    uint16_t read_halfword(uint32_t) const;
+    void write_halfword(uint32_t, uint16_t);
+
+  private:
+    struct {
+        using u16 = uint16_t;
+        bool post_boot_flag;
+        bool interrupt_master_enabler;
+        u16 interrupt_enable;
+        u16 interrupt_request_flags;
+        u16 waitstate_control;
+        bool low_power_mode;
+    } system = {};
+
+    display::Display display = {};
+    Sound sound              = {};
+    Dma dma                  = {};
+
+    std::weak_ptr<Bus> bus;
+    friend class Bus;
+};
+}

include/io/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'io.hh'
+)

include/io/sound.hh

@@ -0,0 +1,66 @@
+#include <cstdint>
+
+// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
+
+/*
+  4000060h  2  R/W  SOUND1CNT_L Channel 1 Sweep register       (NR10)
+  4000062h  2  R/W  SOUND1CNT_H Channel 1 Duty/Length/Envelope (NR11, NR12)
+  4000064h  2  R/W  SOUND1CNT_X Channel 1 Frequency/Control    (NR13, NR14)
+  4000066h     -    -           Not used
+  4000068h  2  R/W  SOUND2CNT_L Channel 2 Duty/Length/Envelope (NR21, NR22)
+  400006Ah     -    -           Not used
+  400006Ch  2  R/W  SOUND2CNT_H Channel 2 Frequency/Control    (NR23, NR24)
+  400006Eh     -    -           Not used
+  4000070h  2  R/W  SOUND3CNT_L Channel 3 Stop/Wave RAM select (NR30)
+  4000072h  2  R/W  SOUND3CNT_H Channel 3 Length/Volume        (NR31, NR32)
+  4000074h  2  R/W  SOUND3CNT_X Channel 3 Frequency/Control    (NR33, NR34)
+  4000076h     -    -           Not used
+  4000078h  2  R/W  SOUND4CNT_L Channel 4 Length/Envelope      (NR41, NR42)
+  400007Ah     -    -           Not used
+  400007Ch  2  R/W  SOUND4CNT_H Channel 4 Frequency/Control    (NR43, NR44)
+  400007Eh     -    -           Not used
+  4000080h  2  R/W  SOUNDCNT_L  Control Stereo/Volume/Enable   (NR50, NR51)
+  4000082h  2  R/W  SOUNDCNT_H  Control Mixing/DMA Control
+  4000084h  2  R/W  SOUNDCNT_X  Control Sound on/off           (NR52)
+  4000086h     -    -           Not used
+  4000088h  2  BIOS SOUNDBIAS   Sound PWM Control
+  400008Ah  ..   -    -         Not used
+  4000090h 2x10h R/W  WAVE_RAM  Channel 3 Wave Pattern RAM (2 banks!!)
+  40000A0h  4    W    FIFO_A    Channel A FIFO, Data 0-3
+  40000A4h  4    W    FIFO_B    Channel B FIFO, Data 0-3
+*/
+
+struct Sound {
+    using u16 = uint16_t;
+
+    // channel 1
+    u16 ch1_sweep;
+    u16 ch1_duty_length_env;
+    u16 ch1_freq_control;
+
+    // channel 2
+    u16 ch2_duty_length_env;
+    u16 ch2_freq_control;
+
+    // channel 3
+    u16 ch3_stop_wave_ram_select;
+    u16 ch3_length_volume;
+    u16 ch3_freq_control;
+    u16 ch3_wave_pattern[8];
+
+    // channel 4
+    u16 ch4_length_env;
+    u16 ch4_freq_control;
+
+    // control
+    u16 ctrl_stereo_volume;
+    u16 ctrl_mixing;
+    u16 ctrl_sound_on_off;
+    u16 pwm_control;
+
+    // fifo
+    u16 fifo_a[2];
+    u16 fifo_b[2];
+};
+
+// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

include/memory.hh

@@ -1,61 +1,60 @@
 #pragma once
 
-#include "header.hh"
 #include <array>
 #include <cstddef>
 #include <cstdint>
-#include <unordered_map>
 #include <vector>
 
+// ill use [] instead of at because i dont want if (...) throw conditions for
+// all accesses to improve performance (?)
+
+// we are also not gonna perform bound checks, as i expect the user to handle
+// those
+
 namespace matar {
+template<std::size_t N = 0>
 class Memory {
+    // we can use either a vector or an array with this
+    using Container = std::
+      conditional_t<(N != 0), std::array<uint8_t, N>, std::vector<uint8_t>>;
+
   public:
-    static constexpr size_t BIOS_SIZE = 1024 * 16;
+    Memory() = default;
+    Memory(auto x)
+      : memory(x) {}
 
-    Memory(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
+    uint8_t read_byte(std::size_t idx) const { return memory[idx]; }
 
-    uint8_t read(size_t address) const;
-    void write(size_t address, uint8_t byte);
+    void write_byte(std::size_t idx, uint8_t byte) { memory[idx] = byte; }
+
+    uint16_t read_halfword(std::size_t idx) const {
+        return memory[idx] | memory[idx + 1] << 8;
+    }
+
+    void write_halfword(std::size_t idx, uint16_t halfword) {
+        memory[idx]     = halfword & 0xFF;
+        memory[idx + 1] = halfword >> 8 & 0xFF;
+    }
+
+    uint32_t read_word(std::size_t idx) const {
+        return memory[idx] | memory[idx + 1] << 8 | memory[idx + 2] << 16 |
+               memory[idx + 3] << 24;
+    }
+
+    void write_word(std::size_t idx, uint32_t word) {
+        memory[idx]     = word & 0xFF;
+        memory[idx + 1] = word >> 8 & 0xFF;
+        memory[idx + 2] = word >> 16 & 0xFF;
+        memory[idx + 3] = word >> 24 & 0xFF;
+    }
+
+    uint8_t& operator[](std::size_t idx) { return memory.at(idx); }
+
+    Container& data() { return memory; }
+
+    std::size_t size() const { return memory.size(); }
 
   private:
-#define MEMORY_REGION(name, start, end)                                        \
-    static constexpr size_t name##_START = start;                              \
-    static constexpr size_t name##_END   = end;
-
-#define DECL_MEMORY(name, ident, start, end)                                   \
-    MEMORY_REGION(name, start, end)                                            \
-    std::array<uint8_t, name##_END - name##_START + 1> ident;
-
-    MEMORY_REGION(BIOS, 0x00000000, 0x00003FFF)
-    std::array<uint8_t, BIOS_SIZE> bios;
-    static_assert(BIOS_END - BIOS_START + 1 == BIOS_SIZE);
-
-    // board working RAM
-    DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
-
-    // chip working RAM
-    DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
-
-    // palette RAM
-    DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
-
-    // video RAM
-    DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
-
-    // OAM OBJ attributes
-    DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
-
-#undef DECL_MEMORY
-
-    MEMORY_REGION(ROM_0, 0x08000000, 0x09FFFFFF)
-    MEMORY_REGION(ROM_1, 0x0A000000, 0x0BFFFFFF)
-    MEMORY_REGION(ROM_2, 0x0C000000, 0x0DFFFFFF)
-
-#undef MEMORY_REGION
-
-    std::unordered_map<size_t, uint8_t> invalid_mem;
-    std::vector<uint8_t> rom;
-    Header header;
-    void parse_header();
+    Container memory;
 };
 }

include/meson.build

@@ -1,5 +1,4 @@
 headers = files(
-  'memory.hh',
   'bus.hh',
   'header.hh',
 )
@@ -8,5 +7,6 @@ inc = include_directories('.')
 
 subdir('cpu')
 subdir('util')
+subdir('io')
 
 install_headers(headers, subdir: meson.project_name(), preserve_path: true)

meson.build

@@ -4,32 +4,20 @@ project('matar', 'cpp',
   default_options : ['warning_level=3',
                      'werror=true',
                      'optimization=3',
-                     'cpp_std=c++20',
+                     'cpp_std=c++23',
                      'default_library=static'])
 
+lib_cpp_args = []
 compiler = meson.get_compiler('cpp')
 
-'''
-TODO: use <print> and <format> instead of libfmt once LLVM 17 is out
-
-if compiler.has_argument('-std=c++2c')
-  add_global_arguments('-std=c++2c', language: 'cpp')
-elif compiler.has_argument('-std=c++23')
-  add_global_arguments('-std=c++23', language: 'cpp')
-elif compiler.has_argument('-std=c++2b')
-  add_global_arguments('-std=c++2b', language: 'cpp')
-elif compiler.has_argument('-std=c++20')
-  add_global_arguments('-std=c++20', language: 'cpp')
-else
-  error(compiler.get_id() + ' ' + compiler.version() + 'does not meet the compiler requirements')
+if get_option('disassembler')
+  lib_cpp_args += '-DDISASSEMBLER'
 endif
 
-if compiler.has_argument('-fexperimental-library')
-  add_global_arguments('-fexperimental-library', language: 'cpp')
-else
-  error(compiler.get_id() + ' ' + compiler.version() + 'does not support -fexperimental-library')
+if get_option('gdb_debug')
+  lib_cpp_args += '-DGDB_DEBUG'
 endif
-'''
+
 
 subdir('include')
 subdir('src')

meson.options

@@ -1,2 +1,3 @@
 option('tests', type : 'boolean', value : true, description: 'enable tests')
 option('disassembler', type: 'boolean', value: true, description: 'enable disassembler')
+option('gdb_debug', type: 'boolean', value: false, description: 'enable GDB RSP server')

nix/matar-clang.nix

@@ -1,17 +1,10 @@
 { ... }: {
   perSystem = { pkgs, src, ... }:
     let
-      llvm = pkgs.llvmPackages_16;
+      llvm = pkgs.llvmPackages_18;
       stdenv = llvm.libcxxStdenv;
 
       libraries = with pkgs; [
-        ((pkgs.fmt.override {
-          inherit stdenv;
-          enableShared = false;
-        }).overrideAttrs (oa: {
-          cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
-        })).dev
-
         (catch2_3.override { inherit stdenv; }).out
       ];
     in
@@ -19,7 +12,7 @@
       packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
       devShells.matar-clang = pkgs.callPackage ./shell.nix {
         inherit libraries stdenv;
-        tools = with pkgs; [ clang-tools_16 ];
+        tools = with pkgs; [ (clang-tools_18.override { enableLibcxx = true; }) ];
       };
     };
 }

nix/matar.nix

@@ -1,13 +1,14 @@
 { ... }: {
   perSystem = { pkgs, src, ... }:
     let
+      stdenv = pkgs.gcc14Stdenv;
+
       libraries = with pkgs; [
-        (pkgs.fmt.override { enableShared = false; }).dev
-        catch2_3.out
+        (catch2_3.override { inherit stdenv; }).out
       ];
     in
     {
-      packages.matar = pkgs.callPackage ./build.nix { inherit src libraries; };
-      devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries; };
+      packages.matar = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
+      devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries stdenv; };
     };
 }

src/bus.cc

@@ -1,55 +1,365 @@
 #include "bus.hh"
+#include "io/io.hh"
+#include "util/crypto.hh"
 #include "util/log.hh"
-#include <memory>
 
 namespace matar {
-Bus::Bus(const Memory& memory)
-  : memory(std::make_shared<Memory>(memory)) {}
+
+// Constants
+#define MEMORY(AREA, start)                                                    \
+    static constexpr uint32_t AREA##_START = start;                            \
+    static constexpr uint8_t AREA##_REGION = (AREA##_START >> 24) & 0xFF;
+
+MEMORY(BIOS, 0x0000000);
+MEMORY(BOARD_WRAM, 0x2000000);
+MEMORY(CHIP_WRAM, 0x3000000);
+MEMORY(PRAM, display::PRAM_START);
+MEMORY(VRAM, display::VRAM_START);
+MEMORY(OAM, display::OAM_START);
+MEMORY(ROM_0, 0x8000000);
+MEMORY(ROM_1, 0xA000000);
+MEMORY(ROM_2, 0xC000000);
+static constexpr uint32_t IO_START = 0x4000000;
+static constexpr uint32_t IO_END   = 0x40003FE;
+
+#undef MEMORY
+
+Bus::Bus(Private,
+         std::array<uint8_t, BIOS_SIZE>&& bios,
+         std::vector<uint8_t>&& rom)
+  : cycle_map(init_cycle_count())
+  , bios(std::move(bios))
+  , rom(std::move(rom)) {
+    std::string bios_hash = crypto::sha256(this->bios.data());
+    static constexpr std::string_view expected_hash =
+      "fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
+
+    if (bios_hash != expected_hash) {
+        glogger.warn("BIOS hash failed to match, run at your own risk"
+                     "\nExpected : {} "
+                     "\nGot      : {}",
+                     expected_hash,
+                     bios_hash);
+    }
+
+    parse_header();
+
+    glogger.info("Memory successfully initialised");
+    glogger.info("Cartridge Title: {}", header.title);
+};
+
+std::shared_ptr<Bus>
+Bus::init(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom) {
+    auto self =
+      std::make_shared<Bus>(Private(), std::move(bios), std::move(rom));
+    self->io = std::make_unique<IoDevices>(self);
+    return self;
+}
+
+constexpr decltype(Bus::cycle_map)
+Bus::init_cycle_count() {
+    /*
+      Region        Bus   Read      Write     Cycles
+      BIOS ROM      32    8/16/32   -         1/1/1
+      Work RAM 32K  32    8/16/32   8/16/32   1/1/1
+      I/O           32    8/16/32   8/16/32   1/1/1
+      OAM           32    8/16/32   16/32     1/1/1 *
+      Work RAM 256K 16    8/16/32   8/16/32   3/3/6 **
+      Palette RAM   16    8/16/32   16/32     1/1/2 *
+      VRAM          16    8/16/32   16/32     1/1/2 *
+      GamePak ROM   16    8/16/32   -         5/5/8 **|***
+      GamePak Flash 16    8/16/32   16/32     5/5/8 **|***
+      GamePak SRAM  8     8         8         5     **
+
+    Timing Notes:
+
+      *   Plus 1 cycle if GBA accesses video memory at the same time.
+      **  Default waitstate settings, see System Control chapter.
+      *** Separate timings for sequential, and non-sequential accesses.
+      One cycle equals approx. 59.59ns (ie. 16.78MHz clock).
+    */
+
+    decltype(cycle_map) map;
+    map.fill({ 1, 1, 1, 1 });
+
+    /* used fill instead of this
+    map[BIOS_REGION]      = { 1, 1, 1, 1 };
+    map[CHIP_WRAM_REGION] = { 1, 1, 1, 1 };
+    map[IO_REGION]        = { 1, 1, 1, 1 };
+    map[OAM_REGION]       = { 1, 1, 1, 1 };
+    */
+    map[BOARD_WRAM_REGION] = { .n16 = 3, .n32 = 6, .s16 = 3, .s32 = 6 };
+    map[PRAM_REGION]       = { .n16 = 1, .n32 = 2, .s16 = 1, .s32 = 2 };
+    map[VRAM_REGION]       = { .n16 = 1, .n32 = 2, .s16 = 1, .s32 = 2 };
+    // TODO: GamePak access cycles
+
+    return map;
+}
+
+template<typename T>
+T
+Bus::read(uint32_t address) const {
+
+    // this is cleaned than std::enable_if
+    static_assert(std::is_same_v<T, uint8_t> || std::is_same_v<T, uint16_t> ||
+                    std::is_same_v<T, uint32_t>,
+                  "Can only read uint8_t, uin16_t or uint32_t");
+
+    constexpr int N = std::is_same_v<T, uint8_t>    ? 1
+                      : std::is_same_v<T, uint16_t> ? 2
+                      : std::is_same_v<T, uint32_t> ? 4
+                                                    : 0;
+
+    switch (address >> 24 & 0xF) {
+#define MATCHES(AREA, area)                                                    \
+    case AREA##_REGION: {                                                      \
+        uint32_t i = address - AREA##_START;                                   \
+        if (i > area.size() - N)                                               \
+            break;                                                             \
+        if constexpr (std::is_same_v<T, uint8_t>)                              \
+            return area.read_byte(i);                                          \
+        else if constexpr (std::is_same_v<T, uint16_t>)                        \
+            return area.read_halfword(i);                                      \
+        else if constexpr (std::is_same_v<T, uint32_t>)                        \
+            return area.read_word(i);                                          \
+    }
+
+#define MATCHES_PAK(AREA, area)                                                \
+    case AREA##_REGION + 1:                                                    \
+        MATCHES(AREA, area)
+
+        MATCHES(BIOS, bios)
+        MATCHES(BOARD_WRAM, board_wram)
+        MATCHES(CHIP_WRAM, chip_wram)
+        MATCHES(PRAM, io->display.pram)
+        MATCHES(VRAM, io->display.vram)
+        MATCHES(OAM, io->display.oam)
+
+        MATCHES_PAK(ROM_0, rom)
+        MATCHES_PAK(ROM_1, rom)
+        MATCHES_PAK(ROM_2, rom)
+#undef MATCHES_PAK
+#undef MATCHES
+    }
+
+    glogger.error("invalid memory region read at {:08x}", address);
+
+    if constexpr (std::is_same_v<T, uint8_t>)
+        return 0xFF;
+    else if constexpr (std::is_same_v<T, uint16_t>)
+        return 0xFFFF;
+    else if constexpr (std::is_same_v<T, uint32_t>)
+        return 0xFFFFFFFF;
+}
+
+template<typename T>
+void
+Bus::write(uint32_t address, T value) {
+    static_assert(std::is_same_v<T, uint8_t> || std::is_same_v<T, uint16_t> ||
+                    std::is_same_v<T, uint32_t>,
+                  "Can only write uint8_t, uin16_t or uint32_t");
+
+    constexpr int N = std::is_same_v<T, uint8_t>    ? 1
+                      : std::is_same_v<T, uint16_t> ? 2
+                      : std::is_same_v<T, uint32_t> ? 4
+                                                    : 0;
+
+    switch (address >> 24 & 0xF) {
+#define MATCHES(AREA, area)                                                    \
+    case AREA##_REGION: {                                                      \
+        uint32_t i = address - AREA##_START;                                   \
+        if (i > area.size() - N)                                               \
+            break;                                                             \
+        if constexpr (std::is_same_v<T, uint8_t>)                              \
+            area.write_byte(i, value);                                         \
+        else if constexpr (std::is_same_v<T, uint16_t>)                        \
+            area.write_halfword(i, value);                                     \
+        else if constexpr (std::is_same_v<T, uint32_t>)                        \
+            area.write_word(i, value);                                         \
+        return;                                                                \
+    }
+
+        MATCHES(BOARD_WRAM, board_wram)
+        MATCHES(CHIP_WRAM, chip_wram)
+        MATCHES(PRAM, io->display.pram)
+        MATCHES(VRAM, io->display.vram)
+        MATCHES(OAM, io->display.oam)
+
+#undef MATCHES
+    }
+
+    glogger.error("invalid memory region written at {:08x}", address);
+}
 
 uint8_t
-Bus::read_byte(size_t address) {
-    return memory->read(address);
+Bus::read_byte(uint32_t address) {
+    if (address >= IO_START && address <= IO_END)
+        return io->read_byte(address);
+
+    return read<uint8_t>(address);
 }
 
 void
-Bus::write_byte(size_t address, uint8_t byte) {
-    memory->write(address, byte);
+Bus::write_byte(uint32_t address, uint8_t byte) {
+    if (address >= IO_START && address <= IO_END) {
+        io->write_byte(address, byte);
+        return;
+    }
+
+    write<uint8_t>(address, byte);
 }
 
 uint16_t
-Bus::read_halfword(size_t address) {
+Bus::read_halfword(uint32_t address) {
     if (address & 0b01)
         glogger.warn("Reading a non aligned halfword address");
 
-    return memory->read(address) | memory->read(address + 1) << 8;
+    if (address >= IO_START && address <= IO_END)
+        return io->read_halfword(address);
+
+    return read<uint16_t>(address);
 }
 
 void
-Bus::write_halfword(size_t address, uint16_t halfword) {
+Bus::write_halfword(uint32_t address, uint16_t halfword) {
     if (address & 0b01)
         glogger.warn("Writing to a non aligned halfword address");
 
-    memory->write(address, halfword & 0xFF);
-    memory->write(address + 1, halfword >> 8 & 0xFF);
+    if (address >= IO_START && address <= IO_END) {
+        io->write_halfword(address, halfword);
+        return;
+    }
+
+    write<uint16_t>(address, halfword);
 }
 
 uint32_t
-Bus::read_word(size_t address) {
+Bus::read_word(uint32_t address) {
     if (address & 0b11)
         glogger.warn("Reading a non aligned word address");
 
-    return memory->read(address) | memory->read(address + 1) << 8 |
-           memory->read(address + 2) << 16 | memory->read(address + 3) << 24;
+    if (address >= IO_START && address <= IO_END)
+        return io->read_word(address);
+
+    return read<uint32_t>(address);
 }
 
 void
-Bus::write_word(size_t address, uint32_t word) {
+Bus::write_word(uint32_t address, uint32_t word) {
     if (address & 0b11)
         glogger.warn("Writing to a non aligned word address");
 
-    memory->write(address, word & 0xFF);
-    memory->write(address + 1, word >> 8 & 0xFF);
-    memory->write(address + 2, word >> 16 & 0xFF);
-    memory->write(address + 3, word >> 24 & 0xFF);
+    if (address >= IO_START && address <= IO_END) {
+        io->write_word(address, word);
+        return;
+    }
+
+    write<uint32_t>(address, word);
+}
+
+void
+Bus::parse_header() {
+    if (rom.size() < header.HEADER_SIZE) {
+        throw std::out_of_range(
+          "ROM is not large enough to even have a header");
+    }
+
+    // entrypoint
+    header.entrypoint =
+      rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
+
+    // nintendo logo
+    if (rom[0x9C] != 0x21)
+        glogger.info("HEADER: BIOS debugger bits not set to 0");
+
+    // game info
+    header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
+
+    switch (rom[0xAC]) {
+        case 'A':
+            header.unique_code = Header::UniqueCode::Old;
+            break;
+        case 'B':
+            header.unique_code = Header::UniqueCode::New;
+            break;
+        case 'C':
+            header.unique_code = Header::UniqueCode::Newer;
+            break;
+        case 'F':
+            header.unique_code = Header::UniqueCode::Famicom;
+            break;
+        case 'K':
+            header.unique_code = Header::UniqueCode::YoshiKoro;
+            break;
+        case 'P':
+            header.unique_code = Header::UniqueCode::Ereader;
+            break;
+        case 'R':
+            header.unique_code = Header::UniqueCode::Warioware;
+            break;
+        case 'U':
+            header.unique_code = Header::UniqueCode::Boktai;
+            break;
+        case 'V':
+            header.unique_code = Header::UniqueCode::DrillDozer;
+            break;
+
+        default:
+            glogger.error("HEADER: invalid unique code: {}", rom[0xAC]);
+    }
+
+    header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
+
+    switch (rom[0xAF]) {
+        case 'J':
+            header.i18n = Header::I18n::Japan;
+            break;
+        case 'P':
+            header.i18n = Header::I18n::Europe;
+            break;
+        case 'F':
+            header.i18n = Header::I18n::French;
+            break;
+        case 'S':
+            header.i18n = Header::I18n::Spanish;
+            break;
+        case 'E':
+            header.i18n = Header::I18n::Usa;
+            break;
+        case 'D':
+            header.i18n = Header::I18n::German;
+            break;
+        case 'I':
+            header.i18n = Header::I18n::Italian;
+            break;
+
+        default:
+            glogger.error("HEADER: invalid destination/language: {}",
+                          rom[0xAF]);
+    }
+
+    if (rom[0xB2] != 0x96)
+        glogger.error("HEADER: invalid fixed byte at 0xB2");
+
+    for (uint32_t i = 0xB5; i < 0xBC; i++) {
+        if (rom[i] != 0x00)
+            glogger.error("HEADER: invalid fixed bytes at 0xB5");
+    }
+
+    header.version = rom[0xBC];
+
+    // checksum
+    {
+        uint32_t i = 0xA0, chk = 0;
+        while (i <= 0xBC)
+            chk -= rom[i++];
+        chk -= 0x19;
+        chk &= 0xFF;
+
+        if (chk != rom[0xBD])
+            glogger.error("HEADER: checksum does not match");
+    }
+
+    // multiboot not required right now
 }
 }

src/cpu/alu.cc

@@ -1,9 +1,10 @@
-#include "alu.hh"
+#include "cpu/alu.hh"
 #include "util/bits.hh"
+#include <bit>
 
 namespace matar {
 uint32_t
-eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
+eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry) {
     uint32_t eval = 0;
 
     switch (shift_type) {
@@ -48,4 +49,60 @@ eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
 
     return eval;
 }
+
+uint32_t
+sub(uint32_t a, uint32_t b, bool& carry, bool& overflow) {
+    bool s1 = get_bit(a, 31);
+    bool s2 = get_bit(b, 31);
+
+    uint32_t result = a - b;
+
+    carry    = a >= b;
+    overflow = s1 != s2 && s2 == get_bit(result, 31);
+
+    return result;
+}
+
+uint32_t
+add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
+    bool s1 = get_bit(a, 31);
+    bool s2 = get_bit(b, 31);
+
+    uint64_t result = a + b + c;
+
+    carry    = get_bit(result, 32);
+    overflow = s1 == s2 && s2 != get_bit(result, 31);
+
+    return result & 0xFFFFFFFF;
+}
+
+uint32_t
+sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
+    bool s1 = get_bit(a, 31);
+    bool s2 = get_bit(b, 31);
+
+    uint64_t result = a - b - !c;
+
+    carry    = get_bit(result, 32);
+    overflow = s1 != s2 && s2 == get_bit(result, 31);
+
+    return result & 0xFFFFFFFF;
+}
+
+uint8_t
+multiplier_array_cycles(uint32_t x, bool zeroes_only) {
+    // set zeroes_only to evaluate first condition that checks ones to false
+
+    if ((!zeroes_only && (x & 0xFFFFFF00) == 0xFFFFFF00) ||
+        (x & 0xFFFFFF00) == 0)
+        return 1;
+    if ((!zeroes_only && (x & 0xFFFF0000) == 0xFFFF0000) ||
+        (x & 0xFFFF0000) == 0)
+        return 2;
+    if ((!zeroes_only && (x & 0xFF000000) == 0xFF000000) ||
+        (x & 0xFF000000) == 0)
+        return 3;
+    return 4;
+};
+
 }

src/cpu/arm/disassembler.cc

@@ -1,5 +1,6 @@
-#include "instruction.hh"
+#include "cpu/arm/instruction.hh"
 #include "util/bits.hh"
+#include <format>
 
 namespace matar::arm {
 std::string
@@ -9,15 +10,18 @@ Instruction::disassemble() {
     return std::visit(
       overloaded{
         [condition](BranchAndExchange& data) {
-            return fmt::format("BX{} R{:d}", condition, data.rn);
+            return std::format("BX{} R{:d}", condition, data.rn);
         },
         [condition](Branch& data) {
-            return fmt::format(
-              "B{}{} 0x{:06X}", (data.link ? "L" : ""), condition, data.offset);
+            return std::format(
+              "B{}{} {:#06x}",
+              (data.link ? "L" : ""),
+              condition,
+              static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
         },
         [condition](Multiply& data) {
             if (data.acc) {
-                return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
+                return std::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
                                    condition,
                                    (data.set ? "S" : ""),
                                    data.rd,
@@ -25,7 +29,7 @@ Instruction::disassemble() {
                                    data.rs,
                                    data.rn);
             } else {
-                return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
+                return std::format("MUL{}{} R{:d},R{:d},R{:d}",
                                    condition,
                                    (data.set ? "S" : ""),
                                    data.rd,
@@ -34,7 +38,7 @@ Instruction::disassemble() {
             }
         },
         [condition](MultiplyLong& data) {
-            return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
+            return std::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
                                (data.uns ? 'U' : 'S'),
                                (data.acc ? "MLAL" : "MULL"),
                                condition,
@@ -46,7 +50,7 @@ Instruction::disassemble() {
         },
         [](Undefined) { return std::string("UND"); },
         [condition](SingleDataSwap& data) {
-            return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
+            return std::format("SWP{}{} R{:d},R{:d},[R{:d}]",
                                condition,
                                (data.byte ? "B" : ""),
                                data.rd,
@@ -62,18 +66,18 @@ Instruction::disassemble() {
                     expression = "";
                 } else {
                     expression =
-                      fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
+                      std::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
                 }
             } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
                 // Shifts are always immediate in single data transfer
-                expression = fmt::format(",{}R{:d},{} #{:d}",
+                expression = std::format(",{}R{:d},{} #{:d}",
                                          (data.up ? '+' : '-'),
                                          shift->rm,
                                          stringify(shift->data.type),
                                          shift->data.operand);
             }
 
-            return fmt::format(
+            return std::format(
               "{}{}{}{} R{:d},[R{:d}{}]{}",
               (data.load ? "LDR" : "STR"),
               condition,
@@ -91,15 +95,15 @@ Instruction::disassemble() {
                 if (data.offset == 0) {
                     expression = "";
                 } else {
-                    expression = fmt::format(
+                    expression = std::format(
                       ",{}#{:d}", (data.up ? '+' : '-'), data.offset);
                 }
             } else {
                 expression =
-                  fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
+                  std::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
             }
 
-            return fmt::format(
+            return std::format(
               "{}{}{}{} R{:d},[R{:d}{}]{}",
               (data.load ? "LDR" : "STR"),
               condition,
@@ -115,12 +119,12 @@ Instruction::disassemble() {
 
             for (uint8_t i = 0; i < 16; i++) {
                 if (get_bit(data.regs, i))
-                    fmt::format_to(std::back_inserter(regs), "R{:d},", i);
+                    std::format_to(std::back_inserter(regs), "R{:d},", i);
             };
 
             regs.pop_back();
 
-            return fmt::format("{}{}{}{} R{:d}{},{{{}}}{}",
+            return std::format("{}{}{}{} R{:d}{},{{{}}}{}",
                                (data.load ? "LDM" : "STM"),
                                condition,
                                (data.up ? 'I' : 'D'),
@@ -132,12 +136,12 @@ Instruction::disassemble() {
         },
         [condition](PsrTransfer& data) {
             if (data.type == PsrTransfer::Type::Mrs) {
-                return fmt::format("MRS{} R{:d},{}",
+                return std::format("MRS{} R{:d},{}",
                                    condition,
                                    data.operand,
                                    (data.spsr ? "SPSR_all" : "CPSR_all"));
             } else {
-                return fmt::format(
+                return std::format(
                   "MSR{} {}_{},{}{}",
                   condition,
                   (data.spsr ? "SPSR" : "CPSR"),
@@ -153,9 +157,9 @@ Instruction::disassemble() {
 
             if (const uint32_t* operand =
                   std::get_if<uint32_t>(&data.operand)) {
-                op_2 = fmt::format("#{:d}", *operand);
+                op_2 = std::format("#{:d}", *operand);
             } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
-                op_2 = fmt::format("R{:d},{} {}{:d}",
+                op_2 = std::format("R{:d},{} {}{:d}",
                                    shift->rm,
                                    stringify(shift->data.type),
                                    (shift->data.immediate ? '#' : 'R'),
@@ -165,7 +169,7 @@ Instruction::disassemble() {
             switch (data.opcode) {
                 case OpCode::MOV:
                 case OpCode::MVN:
-                    return fmt::format("{}{}{} R{:d},{}",
+                    return std::format("{}{}{} R{:d},{}",
                                        stringify(data.opcode),
                                        condition,
                                        (data.set ? "S" : ""),
@@ -175,13 +179,13 @@ Instruction::disassemble() {
                 case OpCode::TEQ:
                 case OpCode::CMP:
                 case OpCode::CMN:
-                    return fmt::format("{}{} R{:d},{}",
+                    return std::format("{}{} R{:d},{}",
                                        stringify(data.opcode),
                                        condition,
                                        data.rn,
                                        op_2);
                 default:
-                    return fmt::format("{}{}{} R{:d},R{:d},{}",
+                    return std::format("{}{}{} R{:d},R{:d},{}",
                                        stringify(data.opcode),
                                        condition,
                                        (data.set ? "S" : ""),
@@ -191,11 +195,11 @@ Instruction::disassemble() {
             }
         },
         [condition](SoftwareInterrupt) {
-            return fmt::format("SWI{}", condition);
+            return std::format("SWI{}", condition);
         },
         [condition](CoprocessorDataTransfer& data) {
-            std::string expression = fmt::format(",#{:d}", data.offset);
-            return fmt::format(
+            std::string expression = std::format(",#{:d}", data.offset);
+            return std::format(
               "{}{}{} p{:d},c{:d},[R{:d}{}]{}",
               (data.load ? "LDC" : "STC"),
               condition,
@@ -207,7 +211,7 @@ Instruction::disassemble() {
               (data.pre ? (data.write ? "!" : "") : expression));
         },
         [condition](CoprocessorDataOperation& data) {
-            return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
+            return std::format("CDP{} p{},{},c{},c{},c{},{}",
                                condition,
                                data.cpn,
                                data.cp_opc,
@@ -217,7 +221,7 @@ Instruction::disassemble() {
                                data.cp);
         },
         [condition](CoprocessorRegisterTransfer& data) {
-            return fmt::format("{}{} p{},{},R{},c{},c{},{}",
+            return std::format("{}{} p{},{},R{},c{},c{},{}",
                                (data.load ? "MRC" : "MCR"),
                                condition,
                                data.cpn,

src/cpu/arm/exec.cc

@@ -1,14 +1,15 @@
-#include "cpu/cpu-impl.hh"
+#include "bus.hh"
+#include "cpu/cpu.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
 namespace matar {
 void
-CpuImpl::exec(const arm::Instruction instruction) {
-    Condition cond            = instruction.condition;
-    arm::InstructionData data = instruction.data;
+Cpu::exec(arm::Instruction& instruction) {
+    bool is_flushed = false;
 
-    if (!cpsr.condition(cond)) {
+    if (!cpsr.condition(instruction.condition)) {
+        advance_pc_arm();
         return;
     }
 
@@ -26,16 +27,28 @@ CpuImpl::exec(const arm::Instruction instruction) {
 
     std::visit(
       overloaded{
-        [this, pc_warn](BranchAndExchange& data) {
-            State state = static_cast<State>(data.rn & 1);
+        [this, pc_warn, &is_flushed](BranchAndExchange& data) {
+            /*
+              S -> reading instruction in step()
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              Total = 2S + N cycles
+                      1S done, S+N taken care of by flush_pipeline()
+            */
+
+            uint32_t addr = gpr[data.rn];
+            State state   = static_cast<State>(get_bit(addr, 0));
 
             pc_warn(data.rn);
 
+            if (state != cpsr.state())
+                glogger.info_bold("State changed");
+
             // set state
             cpsr.set_state(state);
 
             // copy to PC
-            pc = gpr[data.rn];
+            pc = addr;
 
             // ignore [1:0] bits for arm and 0 bit for thumb
             rst_bit(pc, 0);
@@ -43,21 +56,40 @@ CpuImpl::exec(const arm::Instruction instruction) {
             if (state == State::Arm)
                 rst_bit(pc, 1);
 
-            // pc is affected so flush the pipeline
+            // PC is affected so flush the pipeline
             is_flushed = true;
         },
-        [this](Branch& data) {
+        [this, &is_flushed](Branch& data) {
+            /*
+              S -> reading instruction in step()
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              Total = 2S + N cycles
+                      1S done, S+N taken care of by flush_pipeline()
+            */
+
             if (data.link)
                 gpr[14] = pc - INSTRUCTION_SIZE;
 
-            // data.offset accounts for two instructions ahead when
-            // disassembling, so need to adjust
-            pc = static_cast<int32_t>(pc) - 2 * INSTRUCTION_SIZE + data.offset;
+            pc += data.offset;
 
             // pc is affected so flush the pipeline
             is_flushed = true;
         },
         [this, pc_error](Multiply& data) {
+            /*
+              S -> reading instruction in step()
+              mI -> m internal cycles
+              I -> only when accumulating
+              let v = data at rn
+              m = 1 if bits [32:8] of v are all zero or all one
+              m = 2         [32:16]
+              m = 3         [32:24]
+              m = 4         otherwise
+
+              Total = S + mI or S + (m+1)I
+            */
+
             if (data.rd == data.rm)
                 glogger.error("rd and rm are not distinct in {}",
                               typeid(data).name());
@@ -66,8 +98,17 @@ CpuImpl::exec(const arm::Instruction instruction) {
             pc_error(data.rd);
             pc_error(data.rd);
 
-            gpr[data.rd] =
-              gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
+            // mI
+            for (int i = 0; i < multiplier_array_cycles(gpr[data.rs]); i++)
+                internal_cycle();
+
+            gpr[data.rd] = gpr[data.rm] * gpr[data.rs];
+
+            if (data.acc) {
+                gpr[data.rd] += gpr[data.rn];
+                // 1I
+                internal_cycle();
+            }
 
             if (data.set) {
                 cpsr.set_z(gpr[data.rd] == 0);
@@ -76,6 +117,19 @@ CpuImpl::exec(const arm::Instruction instruction) {
             }
         },
         [this, pc_error](MultiplyLong& data) {
+            /*
+              S -> reading instruction in step()
+              (m+1)I -> m + 1 internal cycles
+              I -> only when accumulating
+              let v = data at rs
+              m = 1 if bits [32:8] of v are all zeroes (or all ones if signed)
+              m = 2         [32:16]
+              m = 3         [32:24]
+              m = 4         otherwise
+
+              Total = S + (m+1)I or S + (m+2)I
+            */
+
             if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
                 data.rdlo == data.rm)
                 glogger.error("rdhi, rdlo and rm are not distinct in {}",
@@ -86,6 +140,16 @@ CpuImpl::exec(const arm::Instruction instruction) {
             pc_error(data.rm);
             pc_error(data.rs);
 
+            // 1I
+            if (data.acc)
+                internal_cycle();
+
+            // m+1 internal cycles
+            for (int i = 0;
+                 i <= multiplier_array_cycles(gpr[data.rs], data.uns);
+                 i++)
+                internal_cycle();
+
             if (data.uns) {
                 auto cast = [](uint32_t x) -> uint64_t {
                     return static_cast<uint64_t>(x);
@@ -120,21 +184,56 @@ CpuImpl::exec(const arm::Instruction instruction) {
                 cpsr.set_v(0);
             }
         },
-        [](Undefined) { glogger.warn("Undefined instruction"); },
+        [](Undefined) {
+            // this should be 2S + N + I, should i flush the pipeline? i
+            // dont know. TODO: study
+            glogger.warn("Undefined instruction");
+        },
         [this, pc_error](SingleDataSwap& data) {
+            /*
+              N -> reading instruction in step()
+              N -> unrelated read
+              S -> related write
+              I -> earlier read value is written to register
+              Total = S + 2N +I
+            */
+
             pc_error(data.rm);
             pc_error(data.rn);
             pc_error(data.rd);
 
             if (data.byte) {
-                gpr[data.rd] = bus->read_byte(gpr[data.rn]);
-                bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
+                gpr[data.rd] =
+                  bus->read_byte(gpr[data.rn], CpuAccess::NonSequential);
+                bus->write_byte(
+                  gpr[data.rn], gpr[data.rm] & 0xFF, CpuAccess::Sequential);
             } else {
-                gpr[data.rd] = bus->read_word(gpr[data.rn]);
-                bus->write_word(gpr[data.rn], gpr[data.rm]);
+                gpr[data.rd] =
+                  bus->read_word(gpr[data.rn], CpuAccess::NonSequential);
+                bus->write_word(
+                  gpr[data.rn], gpr[data.rm], CpuAccess::Sequential);
             }
+
+            internal_cycle();
+            // last write address is unrelated to next
+            next_access = CpuAccess::NonSequential;
         },
-        [this, pc_warn, pc_error](SingleDataTransfer& data) {
+        [this, pc_warn, pc_error, &is_flushed](SingleDataTransfer& data) {
+            /*
+              Load
+              ====
+              S   -> reading instruction in step()
+              N   -> read from target
+              I   -> stored in register
+              N+S -> if PC is written - taken care of by flush_pipeline()
+              Total = S + N + I or 2S + 2N + I
+
+              Store
+              =====
+              N -> calculating memory address
+              N -> write at target
+              Total = 2N
+            */
             uint32_t offset  = 0;
             uint32_t address = gpr[data.rn];
 
@@ -170,10 +269,6 @@ CpuImpl::exec(const arm::Instruction instruction) {
                 cpsr.set_c(carry);
             }
 
-            // PC is always two instructions ahead
-            if (data.rn == PC_INDEX)
-                address -= 2 * INSTRUCTION_SIZE;
-
             if (data.pre)
                 address += (data.up ? offset : -offset);
 
@@ -181,22 +276,34 @@ CpuImpl::exec(const arm::Instruction instruction) {
             if (data.load) {
                 // byte
                 if (data.byte)
-                    gpr[data.rd] = bus->read_byte(address);
+                    gpr[data.rd] =
+                      bus->read_byte(address, CpuAccess::NonSequential);
                 // word
                 else
-                    gpr[data.rd] = bus->read_word(address);
+                    gpr[data.rd] =
+                      bus->read_word(address, CpuAccess::NonSequential);
+
+                // N + S
+                if (data.rd == PC_INDEX)
+                    is_flushed = true;
+
+                // I
+                internal_cycle();
                 // store
             } else {
                 // take PC into consideration
+                uint32_t value = gpr[data.rd];
+
                 if (data.rd == PC_INDEX)
-                    address += INSTRUCTION_SIZE;
+                    value += INSTRUCTION_SIZE;
 
                 // byte
                 if (data.byte)
-                    bus->write_byte(address, gpr[data.rd] & 0xFF);
+                    bus->write_byte(
+                      address, value & 0xFF, CpuAccess::NonSequential);
                 // word
                 else
-                    bus->write_word(address, gpr[data.rd]);
+                    bus->write_word(address, value, CpuAccess::NonSequential);
             }
 
             if (!data.pre)
@@ -205,10 +312,26 @@ CpuImpl::exec(const arm::Instruction instruction) {
             if (!data.pre || data.write)
                 gpr[data.rn] = address;
 
-            if (data.rd == PC_INDEX && data.load)
-                is_flushed = true;
+            // last read/write is unrelated, this will be overwriten if
+            // flushed
+            next_access = CpuAccess::NonSequential;
         },
-        [this, pc_warn, pc_error](HalfwordTransfer& data) {
+        [this, pc_warn, pc_error, &is_flushed](HalfwordTransfer& data) {
+            /*
+              Load
+              ====
+              S   -> reading instruction in step()
+              N   -> read from target
+              I   -> stored in register
+              N+S -> if PC is written - taken care of by flush_pipeline()
+              Total = S + N + I or 2S + 2N + I
+
+              Store
+              =====
+              N -> calculating memory address
+              N -> write at target
+              Total = 2N
+            */
             uint32_t address = gpr[data.rn];
             uint32_t offset  = 0;
 
@@ -230,10 +353,6 @@ CpuImpl::exec(const arm::Instruction instruction) {
                 offset = data.offset;
             }
 
-            // PC is always two instructions ahead
-            if (data.rn == PC_INDEX)
-                address -= 2 * INSTRUCTION_SIZE;
-
             if (data.pre)
                 address += (data.up ? offset : -offset);
 
@@ -243,7 +362,8 @@ CpuImpl::exec(const arm::Instruction instruction) {
                 if (data.sign) {
                     // halfword
                     if (data.half) {
-                        gpr[data.rd] = bus->read_halfword(address);
+                        gpr[data.rd] =
+                          bus->read_halfword(address, CpuAccess::NonSequential);
 
                         // sign extend the halfword
                         gpr[data.rd] =
@@ -251,7 +371,8 @@ CpuImpl::exec(const arm::Instruction instruction) {
 
                         // byte
                     } else {
-                        gpr[data.rd] = bus->read_byte(address);
+                        gpr[data.rd] =
+                          bus->read_byte(address, CpuAccess::NonSequential);
 
                         // sign extend the byte
                         gpr[data.rd] =
@@ -259,17 +380,28 @@ CpuImpl::exec(const arm::Instruction instruction) {
                     }
                     // unsigned halfword
                 } else if (data.half) {
-                    gpr[data.rd] = bus->read_halfword(address);
+                    gpr[data.rd] =
+                      bus->read_halfword(address, CpuAccess::NonSequential);
                 }
+
+                // I
+                internal_cycle();
+
+                if (data.rd == PC_INDEX)
+                    is_flushed = true;
+
                 // store
             } else {
+                uint32_t value = gpr[data.rd];
+
                 // take PC into consideration
                 if (data.rd == PC_INDEX)
-                    address += INSTRUCTION_SIZE;
+                    value += INSTRUCTION_SIZE;
 
                 // halfword
                 if (data.half)
-                    bus->write_halfword(address, gpr[data.rd]);
+                    bus->write_halfword(
+                      address, value & 0xFFFF, CpuAccess::NonSequential);
             }
 
             if (!data.pre)
@@ -278,21 +410,41 @@ CpuImpl::exec(const arm::Instruction instruction) {
             if (!data.pre || data.write)
                 gpr[data.rn] = address;
 
-            if (data.rd == PC_INDEX && data.load)
-                is_flushed = true;
+            // last read/write is unrelated, this will be overwriten if
+            // flushed
+            next_access = CpuAccess::NonSequential;
         },
-        [this, pc_error](BlockDataTransfer& data) {
+        [this, pc_error, &is_flushed](BlockDataTransfer& data) {
+            /*
+              Load
+              ====
+              S       -> reading instruction in step()
+              N       -> unrelated read from target
+              (n-1) S -> next n - 1 related reads from target
+              I       -> stored in register
+              N+S     -> if PC is written - taken care of by
+              flush_pipeline() Total = nS + N + I or (n+1)S + 2N + I
+
+              Store
+              =====
+              N       -> calculating memory address
+              N       -> unrelated write at target
+              (n-1) S -> next n - 1 related writes
+              Total = 2N + (n-1)S
+            */
+
+            static constexpr uint8_t alignment = 4; // word
+
             uint32_t address = gpr[data.rn];
             Mode mode        = cpsr.mode();
-            uint8_t alignment = 4; // word
-            uint8_t i         = 0;
-            uint8_t n_regs    = std::popcount(data.regs);
+            int8_t i         = 0;
+            CpuAccess access = CpuAccess::NonSequential;
 
             pc_error(data.rn);
 
             if (cpsr.mode() == Mode::User && data.s) {
-                glogger.error("Bit S is set outside priviliged modes in {}",
-                              typeid(data).name());
+                glogger.error("Bit S is set outside priviliged modes in block "
+                              "data transfer");
             }
 
             // we just change modes to load user registers
@@ -301,60 +453,85 @@ CpuImpl::exec(const arm::Instruction instruction) {
                 chg_mode(Mode::User);
 
                 if (data.write) {
-                    glogger.error(
-                      "Write-back enable for user bank registers in {}",
-                      typeid(data).name());
+                    glogger.error("Write-back enable for user bank registers "
+                                  "in block data transfer");
                 }
             }
 
-            // account for decrement
-            if (!data.up)
-                address -= (n_regs - 1) * alignment;
-
+            // increment beforehand
             if (data.pre)
                 address += (data.up ? alignment : -alignment);
 
             if (data.load) {
-                if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
+                if (get_bit(data.regs, PC_INDEX)) {
+                    is_flushed = true;
+
                     // current mode's spsr is already loaded when it was
                     // switched
+                    if (data.s)
                         spsr = cpsr;
                 }
 
+                if (data.up) {
                     for (i = 0; i < GPR_COUNT; i++) {
                         if (get_bit(data.regs, i)) {
-                        gpr[i] = bus->read_word(address);
+                            gpr[i] = bus->read_word(address, access);
                             address += alignment;
+                            access = CpuAccess::Sequential;
                         }
                     }
                 } else {
+                    for (i = GPR_COUNT - 1; i >= 0; i--) {
+                        if (get_bit(data.regs, i)) {
+                            gpr[i] = bus->read_word(address, access);
+                            address -= alignment;
+                            access = CpuAccess::Sequential;
+                        }
+                    }
+                }
+
+                // I
+                internal_cycle();
+            } else {
+                if (data.up) {
                     for (i = 0; i < GPR_COUNT; i++) {
                         if (get_bit(data.regs, i)) {
-                        bus->write_word(address, gpr[i]);
+                            bus->write_word(address, gpr[i], access);
                             address += alignment;
+                            access = CpuAccess::Sequential;
                         }
                     }
-            }
-
-            if (!data.pre)
-                address += (data.up ? alignment : -alignment);
-
-            // reset back to original address + offset if incremented earlier
-            if (data.up)
-                address -= n_regs * alignment;
-            else
+                } else {
+                    for (i = GPR_COUNT - 1; i >= 0; i--) {
+                        if (get_bit(data.regs, i)) {
+                            bus->write_word(address, gpr[i], access);
                             address -= alignment;
+                            access = CpuAccess::Sequential;
+                        }
+                    }
+                }
+            }
+
+            // fix increment
+            if (data.pre)
+                address += (data.up ? -alignment : alignment);
 
             if (!data.pre || data.write)
                 gpr[data.rn] = address;
 
-            if (data.load && get_bit(data.regs, PC_INDEX))
-                is_flushed = true;
-
             // load back the original mode registers
             chg_mode(mode);
+
+            // last read/write is unrelated, this will be overwriten if
+            // flushed
+            next_access = CpuAccess::NonSequential;
         },
         [this, pc_error](PsrTransfer& data) {
+            /*
+              S -> prefetched instruction in step()
+              Total = 1S cycle
+            */
+
             if (data.spsr && cpsr.mode() == Mode::User) {
                 glogger.error("Accessing SPSR in User mode in {}",
                               typeid(data).name());
@@ -371,6 +548,11 @@ CpuImpl::exec(const arm::Instruction instruction) {
                     pc_error(data.operand);
 
                     if (cpsr.mode() != Mode::User) {
+                        if (!data.spsr) {
+                            Psr tmp = Psr(gpr[data.operand]);
+                            chg_mode(tmp.mode());
+                        }
+
                         psr.set_all(gpr[data.operand]);
                     }
                     break;
@@ -384,7 +566,25 @@ CpuImpl::exec(const arm::Instruction instruction) {
                     break;
             }
         },
-        [this, pc_error](DataProcessing& data) {
+        [this, pc_error, &is_flushed](DataProcessing& data) {
+            /*
+              Always
+              ======
+              S -> prefetched instruction in step()
+
+              With Register specified shift
+              =============================
+              I -> internal cycle
+
+              When PC is written
+              ==================
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              S+N taken care of by flush_pipeline()
+
+              Total = S or S + I or 2S + N + I or 2S + N cycles
+            */
+
             using OpCode = DataProcessing::OpCode;
 
             uint32_t op_1 = gpr[data.rn];
@@ -414,49 +614,15 @@ CpuImpl::exec(const arm::Instruction instruction) {
                 // PC is 12 bytes ahead when shifting
                 if (data.rn == PC_INDEX)
                     op_1 += INSTRUCTION_SIZE;
+
+                // 1I when register specified shift
+                if (!shift->data.immediate)
+                    internal_cycle();
             }
 
             bool overflow = cpsr.v();
             bool carry    = cpsr.c();
 
-            auto sub = [&carry, &overflow](uint32_t a, uint32_t b) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                uint32_t result = a - b;
-
-                carry    = b <= a;
-                overflow = s1 != s2 && s2 == get_bit(result, 31);
-                return result;
-            };
-
-            auto add = [&carry, &overflow](
-                         uint32_t a, uint32_t b, bool c = 0) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                // 33 bits
-                uint64_t result_ = a + b + c;
-                uint32_t result  = result_ & 0xFFFFFFFF;
-
-                carry    = get_bit(result_, 32);
-                overflow = s1 == s2 && s2 != get_bit(result, 31);
-                return result;
-            };
-
-            auto sbc = [&carry,
-                        &overflow](uint32_t a, uint32_t b, bool c) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                uint64_t result_ = a - b + c - 1;
-                uint32_t result  = result_ & 0xFFFFFFFF;
-
-                carry    = get_bit(result_, 32);
-                overflow = s1 != s2 && s2 == get_bit(result, 31);
-                return result;
-            };
-
             switch (data.opcode) {
                 case OpCode::AND:
                 case OpCode::TST:
@@ -469,23 +635,23 @@ CpuImpl::exec(const arm::Instruction instruction) {
                     break;
                 case OpCode::SUB:
                 case OpCode::CMP:
-                    result = sub(op_1, op_2);
+                    result = sub(op_1, op_2, carry, overflow);
                     break;
                 case OpCode::RSB:
-                    result = sub(op_2, op_1);
+                    result = sub(op_2, op_1, carry, overflow);
                     break;
                 case OpCode::ADD:
                 case OpCode::CMN:
-                    result = add(op_1, op_2);
+                    result = add(op_1, op_2, carry, overflow);
                     break;
                 case OpCode::ADC:
-                    result = add(op_1, op_2, carry);
+                    result = add(op_1, op_2, carry, overflow, carry);
                     break;
                 case OpCode::SBC:
-                    result = sbc(op_1, op_2, carry);
+                    result = sbc(op_1, op_2, carry, overflow, carry);
                     break;
                 case OpCode::RSC:
-                    result = sbc(op_2, op_1, carry);
+                    result = sbc(op_2, op_1, carry, overflow, carry);
                     break;
                 case OpCode::ORR:
                     result = op_1 | op_2;
@@ -528,14 +694,20 @@ CpuImpl::exec(const arm::Instruction instruction) {
                     is_flushed = true;
             }
         },
-        [this](SoftwareInterrupt) {
+        [this, &is_flushed](SoftwareInterrupt) {
             chg_mode(Mode::Supervisor);
-            pc   = 0x08;
+            pc         = 0x00;
             spsr       = cpsr;
+            is_flushed = true;
         },
         [](auto& data) {
             glogger.error("Unimplemented {} instruction", typeid(data).name());
         } },
-      data);
+      instruction.data);
+
+    if (is_flushed)
+        flush_pipeline<State::Arm>();
+    else
+        advance_pc_arm();
 }
 }

src/cpu/arm/instruction.cc

@@ -1,6 +1,5 @@
-#include "instruction.hh"
+#include "cpu/arm/instruction.hh"
 #include "util/bits.hh"
-#include <iterator>
 
 namespace matar::arm {
 Instruction::Instruction(uint32_t insn)
@@ -14,12 +13,10 @@ Instruction::Instruction(uint32_t insn)
         // Branch
     } else if ((insn & 0x0E000000) == 0x0A000000) {
         bool link      = get_bit(insn, 24);
-        uint32_t offset = bit_range(insn, 0, 23);
+        int32_t offset = static_cast<int32_t>(bit_range(insn, 0, 23));
 
         // lsh 2 and sign extend the 26 bit offset to 32 bits
-        offset = (static_cast<int32_t>(offset) << 8) >> 6;
-
-        offset += 2 * INSTRUCTION_SIZE;
+        offset = (offset << 8) >> 6;
 
         data = Branch{ .link = link, .offset = offset };
 

src/cpu/cpu-impl.cc

@@ -1,145 +0,0 @@
-#include "cpu-impl.hh"
-#include "util/bits.hh"
-#include "util/log.hh"
-#include <algorithm>
-#include <cstdio>
-#include <type_traits>
-
-namespace matar {
-CpuImpl::CpuImpl(const Bus& bus) noexcept
-  : bus(std::make_shared<Bus>(bus))
-  , gpr({ 0 })
-  , cpsr(0)
-  , spsr(0)
-  , is_flushed(false)
-  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
-  , spsr_banked({ 0, 0, 0, 0, 0 }) {
-    cpsr.set_mode(Mode::Supervisor);
-    cpsr.set_irq_disabled(true);
-    cpsr.set_fiq_disabled(true);
-    cpsr.set_state(State::Arm);
-    glogger.info("CPU successfully initialised");
-
-    // PC always points to two instructions ahead
-    // PC - 2 is the instruction being executed
-    pc += 2 * arm::INSTRUCTION_SIZE;
-}
-
-/* change modes */
-void
-CpuImpl::chg_mode(const Mode to) {
-    Mode from = cpsr.mode();
-
-    if (from == to)
-        return;
-
-/* TODO: replace visible registers with view once I understand how to
- * concatenate views */
-#define STORE_BANKED(mode, MODE)                                               \
-    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
-              gpr.begin() + gpr.size() - 1,                                    \
-              gpr_banked.mode.begin())
-
-    switch (from) {
-        case Mode::Fiq:
-            STORE_BANKED(fiq, FIQ);
-            spsr_banked.fiq = spsr;
-            break;
-
-        case Mode::Supervisor:
-            STORE_BANKED(svc, SVC);
-            spsr_banked.svc = spsr;
-            break;
-
-        case Mode::Abort:
-            STORE_BANKED(abt, ABT);
-            spsr_banked.abt = spsr;
-            break;
-
-        case Mode::Irq:
-            STORE_BANKED(irq, IRQ);
-            spsr_banked.irq = spsr;
-            break;
-
-        case Mode::Undefined:
-            STORE_BANKED(und, UND);
-            spsr_banked.und = spsr;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#define RESTORE_BANKED(mode, MODE)                                             \
-    std::copy(gpr_banked.mode.begin(),                                         \
-              gpr_banked.mode.end(),                                           \
-              gpr.begin() + GPR_##MODE##_FIRST)
-
-    switch (to) {
-        case Mode::Fiq:
-            RESTORE_BANKED(fiq, FIQ);
-            spsr = spsr_banked.fiq;
-            break;
-
-        case Mode::Supervisor:
-            RESTORE_BANKED(svc, SVC);
-            spsr = spsr_banked.svc;
-            break;
-
-        case Mode::Abort:
-            RESTORE_BANKED(abt, ABT);
-            spsr = spsr_banked.abt;
-            break;
-
-        case Mode::Irq:
-            RESTORE_BANKED(irq, IRQ);
-            spsr = spsr_banked.irq;
-            break;
-
-        case Mode::Undefined:
-            RESTORE_BANKED(und, UND);
-            spsr = spsr_banked.und;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#undef RESTORE_BANKED
-
-    cpsr.set_mode(to);
-}
-
-void
-CpuImpl::step() {
-    // Current instruction is two instructions behind PC
-    uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
-
-    if (cpsr.state() == State::Arm) {
-        uint32_t x = bus->read_word(cur_pc);
-        arm::Instruction instruction(x);
-
-        exec(instruction);
-
-#ifdef DISASSEMBLER
-        glogger.info("{:#034b}", x);
-        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
-#endif
-
-        if (is_flushed) {
-            // if flushed, do not increment the PC, instead set it to two
-            // instructions ahead to account for flushed "fetch" and "decode"
-            // instructions
-            pc += 2 * arm::INSTRUCTION_SIZE;
-            is_flushed = false;
-        } else {
-            // if not flushed continue like normal
-            pc += arm::INSTRUCTION_SIZE;
-        }
-    }
-}
-}

src/cpu/cpu-impl.hh

@@ -1,64 +0,0 @@
-#pragma once
-
-#include "bus.hh"
-#include "cpu/arm/instruction.hh"
-#include "cpu/psr.hh"
-
-#include <cstdint>
-
-namespace matar {
-class CpuImpl {
-  public:
-    CpuImpl(const Bus& bus) noexcept;
-
-    void step();
-    void chg_mode(const Mode to);
-    void exec(const arm::Instruction instruction);
-
-    // TODO: get rid of this
-#ifndef MATAR_CPU_TESTS
-  private:
-#endif
-
-    static constexpr uint8_t GPR_COUNT = 16;
-
-    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
-    static constexpr uint8_t GPR_SVC_FIRST     = 13;
-    static constexpr uint8_t GPR_ABT_FIRST     = 13;
-    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
-    static constexpr uint8_t GPR_UND_FIRST     = 13;
-    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
-
-    std::shared_ptr<Bus> bus;
-    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
-
-    Psr cpsr; // current program status register
-    Psr spsr; // status program status register
-
-    static constexpr uint8_t PC_INDEX = 15;
-    static_assert(PC_INDEX < GPR_COUNT);
-
-    uint32_t& pc = gpr[PC_INDEX];
-
-    bool is_flushed;
-
-    struct {
-        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
-        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
-        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
-        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
-        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
-
-        // visible registers before the mode switch
-        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
-    } gpr_banked; // banked general purpose registers
-
-    struct {
-        Psr fiq;
-        Psr svc;
-        Psr abt;
-        Psr irq;
-        Psr und;
-    } spsr_banked; // banked saved program status registers
-};
-}

src/cpu/cpu.cc

@@ -1,14 +1,172 @@
 #include "cpu/cpu.hh"
-#include "cpu-impl.hh"
+#include "cpu/arm/instruction.hh"
+#include "cpu/thumb/instruction.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
 
 namespace matar {
-Cpu::Cpu(const Bus& bus) noexcept
-  : impl(std::make_unique<CpuImpl>(bus)){};
+Cpu::Cpu(std::shared_ptr<Bus> bus) noexcept
+  : bus(bus) {
+    cpsr.set_mode(Mode::Supervisor);
+    cpsr.set_irq_disabled(true);
+    cpsr.set_fiq_disabled(true);
+    cpsr.set_state(State::Arm);
+    glogger.info("CPU successfully initialised");
 
-Cpu::~Cpu() = default;
+    // PC always points to two instructions ahead
+    flush_pipeline<State::Arm>();
+}
+
+/* change modes */
+void
+Cpu::chg_mode(const Mode to) {
+    Mode from = cpsr.mode();
+
+    if (from == to)
+        return;
+
+/* TODO: replace visible registers with view once I understand how to
+ * concatenate views */
+#define STORE_BANKED(mode, MODE)                                               \
+    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
+              gpr.end() - 1,                                                   \
+              gpr_banked.mode.begin())
+
+    switch (from) {
+        case Mode::Fiq:
+            STORE_BANKED(fiq, FIQ);
+            spsr_banked.fiq = spsr;
+            std::copy(gpr_banked.old.begin(),
+                      gpr_banked.old.end() - 2, // dont copy R13 and R14
+                      gpr.begin() + GPR_OLD_FIRST);
+            break;
+
+        case Mode::Supervisor:
+            STORE_BANKED(svc, SVC);
+            spsr_banked.svc = spsr;
+            break;
+
+        case Mode::Abort:
+            STORE_BANKED(abt, ABT);
+            spsr_banked.abt = spsr;
+            break;
+
+        case Mode::Irq:
+            STORE_BANKED(irq, IRQ);
+            spsr_banked.irq = spsr;
+            break;
+
+        case Mode::Undefined:
+            STORE_BANKED(und, UND);
+            spsr_banked.und = spsr;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            // we only take care of r13 and r14, because FIQ takes care of the
+            // rest
+            gpr_banked.old[5] = gpr[13];
+            gpr_banked.old[6] = gpr[14];
+            break;
+    }
+
+#undef STORE_BANKED
+
+#define RESTORE_BANKED(mode, MODE)                                             \
+    std::copy(gpr_banked.mode.begin(),                                         \
+              gpr_banked.mode.end(),                                           \
+              gpr.begin() + GPR_##MODE##_FIRST)
+
+    switch (to) {
+        case Mode::Fiq:
+            RESTORE_BANKED(fiq, FIQ);
+            spsr = spsr_banked.fiq;
+            std::copy(gpr.begin() + GPR_FIQ_FIRST,
+                      gpr.end() - 2, // dont copy R13 and R14
+                      gpr_banked.old.begin());
+            break;
+
+        case Mode::Supervisor:
+            RESTORE_BANKED(svc, SVC);
+            spsr = spsr_banked.svc;
+            break;
+
+        case Mode::Abort:
+            RESTORE_BANKED(abt, ABT);
+            spsr = spsr_banked.abt;
+            break;
+
+        case Mode::Irq:
+            RESTORE_BANKED(irq, IRQ);
+            spsr = spsr_banked.irq;
+            break;
+
+        case Mode::Undefined:
+            RESTORE_BANKED(und, UND);
+            spsr = spsr_banked.und;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            gpr[13] = gpr_banked.old[5];
+            gpr[14] = gpr_banked.old[6];
+            break;
+    }
+
+#undef RESTORE_BANKED
+
+    cpsr.set_mode(to);
+    glogger.info_bold("Mode changed from {:b} to {:b}",
+                      static_cast<uint32_t>(from),
+                      static_cast<uint32_t>(to));
+}
 
 void
 Cpu::step() {
-    impl->step();
-};
+    // halfword align
+    rst_bit(pc, 0);
+    if (cpsr.state() == State::Arm) {
+        // word align
+        rst_bit(pc, 1);
+
+        arm::Instruction instruction(opcodes[0]);
+
+        opcodes[0] = opcodes[1];
+        opcodes[1] = bus->read_word(pc, next_access);
+
+#ifdef DISASSEMBLER
+        glogger.info("0x{:08X} : {}",
+                     pc - 2 * arm::INSTRUCTION_SIZE,
+                     instruction.disassemble());
+#endif
+
+        exec(instruction);
+    } else {
+        thumb::Instruction instruction(opcodes[0]);
+
+        opcodes[0] = opcodes[1];
+        opcodes[1] = bus->read_halfword(pc, next_access);
+
+#ifdef DISASSEMBLER
+        glogger.info("0x{:08X} : {}",
+                     pc - 2 * thumb::INSTRUCTION_SIZE,
+                     instruction.disassemble());
+#endif
+
+        exec(instruction);
+    }
+}
+
+void
+Cpu::advance_pc_arm() {
+    rst_bit(pc, 0);
+    rst_bit(pc, 1);
+    pc += arm::INSTRUCTION_SIZE;
+};
+
+void
+Cpu::advance_pc_thumb() {
+    rst_bit(pc, 0);
+    pc += thumb::INSTRUCTION_SIZE;
+}
 }

src/cpu/meson.build

@@ -1,5 +1,4 @@
 lib_sources += files(
-  'cpu-impl.cc',
   'cpu.cc',
   'psr.cc',
   'alu.cc'

src/cpu/psr.cc

@@ -1,6 +1,5 @@
-#include "psr.hh"
+#include "cpu/psr.hh"
 #include "util/bits.hh"
-#include "util/log.hh"
 
 namespace matar {
 Psr::Psr(uint32_t raw)
@@ -13,17 +12,17 @@ Psr::raw() const {
 
 void
 Psr::set_all(uint32_t raw) {
-    psr = raw & ~PSR_CLEAR_RESERVED;
+    psr = raw;
 }
 
 Mode
 Psr::mode() const {
-    return static_cast<Mode>(psr & ~PSR_CLEAR_MODE);
+    return static_cast<Mode>(psr & 0b11111);
 }
 
 void
 Psr::set_mode(Mode mode) {
-    psr &= PSR_CLEAR_MODE;
+    psr &= 0b00000;
     psr |= static_cast<uint32_t>(mode);
 }
 
@@ -91,7 +90,7 @@ Psr::condition(Condition cond) const {
         case Condition::LE:
             return z() || (n() != v());
         case Condition::AL:
-            return true && state() == State::Arm;
+            return true;
     }
 
     return false;

src/cpu/thumb/disassembler.cc

@@ -1,5 +1,6 @@
-#include "instruction.hh"
+#include "cpu/thumb/instruction.hh"
 #include "util/bits.hh"
+#include <format>
 
 namespace matar::thumb {
 std::string
@@ -7,14 +8,14 @@ Instruction::disassemble() {
     return std::visit(
       overloaded{
         [](MoveShiftedRegister& data) {
-            return fmt::format("{} R{:d},R{:d},#{:d}",
+            return std::format("{} R{:d},R{:d},#{:d}",
                                stringify(data.opcode),
                                data.rd,
                                data.rs,
                                data.offset);
         },
         [](AddSubtract& data) {
-            return fmt::format("{} R{:d},R{:d},{}{:d}",
+            return std::format("{} R{:d},R{:d},{}{:d}",
                                stringify(data.opcode),
                                data.rd,
                                data.rs,
@@ -22,27 +23,27 @@ Instruction::disassemble() {
                                data.offset);
         },
         [](MovCmpAddSubImmediate& data) {
-            return fmt::format(
+            return std::format(
               "{} R{:d},#{:d}", stringify(data.opcode), data.rd, data.offset);
         },
         [](AluOperations& data) {
-            return fmt::format(
+            return std::format(
               "{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
         },
         [](HiRegisterOperations& data) {
             if (data.opcode == HiRegisterOperations::OpCode::BX) {
-                return fmt::format("{} R{:d}", stringify(data.opcode), data.rs);
+                return std::format("{} R{:d}", stringify(data.opcode), data.rs);
             }
 
-            return fmt::format(
+            return std::format(
               "{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
         },
 
         [](PcRelativeLoad& data) {
-            return fmt::format("LDR R{:d},[PC,#{:d}]", data.rd, data.word);
+            return std::format("LDR R{:d},[PC,#{:d}]", data.rd, data.word);
         },
         [](LoadStoreRegisterOffset& data) {
-            return fmt::format("{}{} R{:d},[R{:d},R{:d}]",
+            return std::format("{}{} R{:d},[R{:d},R{:d}]",
                                (data.load ? "LDR" : "STR"),
                                (data.byte ? "B" : ""),
                                data.rd,
@@ -51,11 +52,11 @@ Instruction::disassemble() {
         },
         [](LoadStoreSignExtendedHalfword& data) {
             if (!data.s && !data.h) {
-                return fmt::format(
+                return std::format(
                   "STRH R{:d},[R{:d},R{:d}]", data.rd, data.rb, data.ro);
             }
 
-            return fmt::format("{}{} R{:d},[R{:d},R{:d}]",
+            return std::format("{}{} R{:d},[R{:d},R{:d}]",
                                (data.s ? "LDS" : "LDR"),
                                (data.h ? 'H' : 'B'),
                                data.rd,
@@ -63,7 +64,7 @@ Instruction::disassemble() {
                                data.ro);
         },
         [](LoadStoreImmediateOffset& data) {
-            return fmt::format("{}{} R{:d},[R{:d},#{:d}]",
+            return std::format("{}{} R{:d},[R{:d},#{:d}]",
                                (data.load ? "LDR" : "STR"),
                                (data.byte ? "B" : ""),
                                data.rd,
@@ -71,34 +72,33 @@ Instruction::disassemble() {
                                data.offset);
         },
         [](LoadStoreHalfword& data) {
-            return fmt::format("{} R{:d},[R{:d},#{:d}]",
+            return std::format("{} R{:d},[R{:d},#{:d}]",
                                (data.load ? "LDRH" : "STRH"),
                                data.rd,
                                data.rb,
                                data.offset);
         },
         [](SpRelativeLoad& data) {
-            return fmt::format("{} R{:d},[SP,#{:d}]",
+            return std::format("{} R{:d},[SP,#{:d}]",
                                (data.load ? "LDR" : "STR"),
                                data.rd,
                                data.word);
         },
         [](LoadAddress& data) {
-            return fmt::format("ADD R{:d},{},#{:d}",
+            return std::format("ADD R{:d},{},#{:d}",
                                data.rd,
                                (data.sp ? "SP" : "PC"),
                                data.word);
         },
         [](AddOffsetStackPointer& data) {
-            return fmt::format(
-              "ADD SP,#{}{:d}", (data.sign ? '-' : '+'), data.word);
+            return std::format("ADD SP,#{:d}", data.word);
         },
         [](PushPopRegister& data) {
             std::string regs;
 
             for (uint8_t i = 0; i < 16; i++) {
                 if (get_bit(data.regs, i))
-                    fmt::format_to(std::back_inserter(regs), "R{:d},", i);
+                    std::format_to(std::back_inserter(regs), "R{:d},", i);
             };
 
             if (data.load) {
@@ -107,14 +107,14 @@ Instruction::disassemble() {
                 else
                     regs.pop_back();
 
-                return fmt::format("POP {{{}}}", regs);
+                return std::format("POP {{{}}}", regs);
             } else {
                 if (data.pclr)
                     regs += "LR";
                 else
                     regs.pop_back();
 
-                return fmt::format("PUSH {{{}}}", regs);
+                return std::format("PUSH {{{}}}", regs);
             }
         },
         [](MultipleLoad& data) {
@@ -122,27 +122,32 @@ Instruction::disassemble() {
 
             for (uint8_t i = 0; i < 16; i++) {
                 if (get_bit(data.regs, i))
-                    fmt::format_to(std::back_inserter(regs), "R{:d},", i);
+                    std::format_to(std::back_inserter(regs), "R{:d},", i);
             };
 
             regs.pop_back();
 
-            return fmt::format(
+            return std::format(
               "{} R{}!,{{{}}}", (data.load ? "LDMIA" : "STMIA"), data.rb, regs);
         },
-        [](SoftwareInterrupt) { return std::string("SWI"); },
+        [](SoftwareInterrupt& data) {
+            return std::format("SWI {:d}", data.vector);
+        },
         [](ConditionalBranch& data) {
-            return fmt::format("B{} {:d}",
+            return std::format(
+              "B{} #{:d}",
               stringify(data.condition),
-                               data.offset);
+              static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
         },
         [](UnconditionalBranch& data) {
-            return fmt::format("B {:d}", data.offset);
+            return std::format(
+              "B #{:d}",
+              static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
         },
         [](LongBranchWithLink& data) {
             // duh this manual be empty for H = 0
-            return fmt::format(
-              "BL{} {:d}", (data.high ? "H" : ""), data.offset);
+            return std::format(
+              "BL{} #{:d}", (data.low ? "" : "H"), data.offset);
         },
         [](auto) { return std::string("unknown instruction"); } },
       data);

src/cpu/thumb/exec.cc

@@ -0,0 +1,612 @@
+#include "bus.hh"
+#include "cpu/alu.hh"
+#include "cpu/cpu.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+namespace matar {
+void
+Cpu::exec(thumb::Instruction& instruction) {
+    bool is_flushed = false;
+    dbg(pc);
+
+    auto set_cc = [this](bool c, bool v, bool n, bool z) {
+        cpsr.set_c(c);
+        cpsr.set_v(v);
+        cpsr.set_n(n);
+        cpsr.set_z(z);
+    };
+
+    using namespace thumb;
+
+    std::visit(
+      overloaded{
+        [this, set_cc](MoveShiftedRegister& data) {
+            /*
+              S -> prefetched instruction in step()
+
+              Total = S cycle
+            */
+            if (data.opcode == ShiftType::ROR)
+                glogger.error("Invalid opcode in {}", typeid(data).name());
+
+            bool carry = cpsr.c();
+
+            uint32_t shifted =
+              eval_shift(data.opcode, gpr[data.rs], data.offset, carry);
+
+            gpr[data.rd] = shifted;
+
+            set_cc(carry, cpsr.v(), get_bit(shifted, 31), shifted == 0);
+        },
+        [this, set_cc](AddSubtract& data) {
+            /*
+              S -> prefetched instruction in step()
+
+              Total = S cycle
+            */
+            uint32_t offset =
+              data.imm ? static_cast<uint32_t>(static_cast<int8_t>(data.offset))
+                       : gpr[data.offset];
+            uint32_t result = 0;
+            bool carry      = cpsr.c();
+            bool overflow   = cpsr.v();
+
+            switch (data.opcode) {
+                case AddSubtract::OpCode::ADD:
+                    result = add(gpr[data.rs], offset, carry, overflow);
+                    break;
+                case AddSubtract::OpCode::SUB:
+                    result = sub(gpr[data.rs], offset, carry, overflow);
+                    break;
+            }
+
+            gpr[data.rd] = result;
+            set_cc(carry, overflow, get_bit(result, 31), result == 0);
+        },
+        [this, set_cc](MovCmpAddSubImmediate& data) {
+            /*
+              S -> prefetched instruction in step()
+
+              Total = S cycle
+            */
+            uint32_t result = 0;
+            bool carry      = cpsr.c();
+            bool overflow   = cpsr.v();
+
+            switch (data.opcode) {
+                case MovCmpAddSubImmediate::OpCode::MOV:
+                    result = data.offset;
+                    carry  = 0;
+                    break;
+                case MovCmpAddSubImmediate::OpCode::ADD:
+                    result = add(gpr[data.rd], data.offset, carry, overflow);
+                    break;
+                case MovCmpAddSubImmediate::OpCode::SUB:
+                case MovCmpAddSubImmediate::OpCode::CMP:
+                    result = sub(gpr[data.rd], data.offset, carry, overflow);
+                    break;
+            }
+
+            set_cc(carry, overflow, get_bit(result, 31), result == 0);
+            if (data.opcode != MovCmpAddSubImmediate::OpCode::CMP)
+                gpr[data.rd] = result;
+        },
+        [this, set_cc](AluOperations& data) {
+            /*
+              Data Processing
+              ===============
+              S -> prefetched instruction in step()
+              I -> only when register specified shift
+              Total = S or S + I cycles
+
+              Multiply
+              ========
+              S -> reading instruction in step()
+              mI -> m internal cycles
+              let v = data at rn
+              m = 1 if bits [32:8] of v are all zero or all one
+              m = 2         [32:16]
+              m = 3         [32:24]
+              m = 4         otherwise
+
+              Total = S + mI cycles
+            */
+            uint32_t op_1   = gpr[data.rd];
+            uint32_t op_2   = gpr[data.rs];
+            uint32_t result = 0;
+
+            bool carry    = cpsr.c();
+            bool overflow = cpsr.v();
+
+            switch (data.opcode) {
+                case AluOperations::OpCode::AND:
+                case AluOperations::OpCode::TST:
+                    result = op_1 & op_2;
+                    break;
+                case AluOperations::OpCode::EOR:
+                    result = op_1 ^ op_2;
+                    break;
+                case AluOperations::OpCode::LSL:
+                    result = eval_shift(ShiftType::LSL, op_1, op_2, carry);
+                    internal_cycle();
+                    break;
+                case AluOperations::OpCode::LSR:
+                    result = eval_shift(ShiftType::LSR, op_1, op_2, carry);
+                    internal_cycle();
+                    break;
+                case AluOperations::OpCode::ASR:
+                    result = eval_shift(ShiftType::ASR, op_1, op_2, carry);
+                    internal_cycle();
+                    break;
+                case AluOperations::OpCode::ADC:
+                    result = add(op_1, op_2, carry, overflow, carry);
+                    break;
+                case AluOperations::OpCode::SBC:
+                    result = sbc(op_1, op_2, carry, overflow, carry);
+                    break;
+                case AluOperations::OpCode::ROR:
+                    result = eval_shift(ShiftType::ROR, op_1, op_2, carry);
+                    internal_cycle();
+                    break;
+                case AluOperations::OpCode::NEG:
+                    result = -op_2;
+                    break;
+                case AluOperations::OpCode::CMP:
+                    result = sub(op_1, op_2, carry, overflow);
+                    break;
+                case AluOperations::OpCode::CMN:
+                    result = add(op_1, op_2, carry, overflow);
+                    break;
+                case AluOperations::OpCode::ORR:
+                    result = op_1 | op_2;
+                    break;
+                case AluOperations::OpCode::MUL:
+                    result = op_1 * op_2;
+                    // mI cycles
+                    for (int i = 0; i < multiplier_array_cycles(op_2); i++)
+                        internal_cycle();
+                    break;
+                case AluOperations::OpCode::BIC:
+                    result = op_1 & ~op_2;
+                    break;
+                case AluOperations::OpCode::MVN:
+                    result = ~op_2;
+                    break;
+            }
+
+            if (data.opcode != AluOperations::OpCode::TST &&
+                data.opcode != AluOperations::OpCode::CMP &&
+                data.opcode != AluOperations::OpCode::CMN)
+                gpr[data.rd] = result;
+
+            set_cc(carry, overflow, get_bit(result, 31), result == 0);
+        },
+        [this, set_cc, &is_flushed](HiRegisterOperations& data) {
+            /*
+              Always
+              ======
+              S -> prefetched instruction in step()
+
+              When PC is written
+              ==================
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              S+N taken care of by flush_pipeline()
+
+              Total = S or 2S + N cycles
+            */
+
+            uint32_t op_1 = gpr[data.rd];
+            uint32_t op_2 = gpr[data.rs];
+
+            bool carry    = cpsr.c();
+            bool overflow = cpsr.v();
+
+            // PC is already current + 4, so dont need to do that
+            if (data.rd == PC_INDEX)
+                rst_bit(op_1, 0);
+
+            if (data.rs == PC_INDEX)
+                rst_bit(op_2, 0);
+
+            switch (data.opcode) {
+                case HiRegisterOperations::OpCode::ADD: {
+                    gpr[data.rd] = add(op_1, op_2, carry, overflow);
+
+                    if (data.rd == PC_INDEX)
+                        is_flushed = true;
+                } break;
+                case HiRegisterOperations::OpCode::CMP: {
+                    uint32_t result = sub(op_1, op_2, carry, overflow);
+                    set_cc(carry, overflow, get_bit(result, 31), result == 0);
+                } break;
+                case HiRegisterOperations::OpCode::MOV: {
+                    gpr[data.rd] = op_2;
+
+                    if (data.rd == PC_INDEX)
+                        is_flushed = true;
+                } break;
+                case HiRegisterOperations::OpCode::BX: {
+                    State state = static_cast<State>(get_bit(op_2, 0));
+
+                    if (state != cpsr.state())
+                        glogger.info_bold("State changed");
+
+                    // set state
+                    cpsr.set_state(state);
+
+                    // copy to PC
+                    pc = op_2;
+
+                    // ignore [1:0] bits for arm and 0 bit for thumb
+                    rst_bit(pc, 0);
+
+                    if (state == State::Arm)
+                        rst_bit(pc, 1);
+
+                    // pc is affected so flush the pipeline
+                    is_flushed = true;
+                } break;
+            }
+        },
+        [this](PcRelativeLoad& data) {
+            /*
+              S   -> reading instruction in step()
+              N   -> read from target
+              I   -> stored in register
+              Total = S + N + I cycles
+            */
+            uint32_t pc_ = pc;
+            rst_bit(pc_, 0);
+            rst_bit(pc_, 1);
+
+            gpr[data.rd] =
+              bus->read_word(pc_ + data.word, CpuAccess::NonSequential);
+
+            internal_cycle();
+
+            // last read is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this](LoadStoreRegisterOffset& data) {
+            /*
+              Load
+              ====
+              S   -> reading instruction in step()
+              N   -> read from target
+              I   -> stored in register
+              Total = S + N + I
+
+              Store
+              =====
+              N -> calculating memory address
+              N -> write at target
+              Total = 2N
+            */
+
+            uint32_t address = gpr[data.rb] + gpr[data.ro];
+
+            if (data.load) {
+                if (data.byte) {
+                    gpr[data.rd] =
+                      bus->read_byte(address, CpuAccess::NonSequential);
+                } else {
+                    gpr[data.rd] =
+                      bus->read_word(address, CpuAccess::NonSequential);
+                }
+                internal_cycle();
+            } else {
+                if (data.byte) {
+                    bus->write_byte(
+                      address, gpr[data.rd] & 0xFF, CpuAccess::NonSequential);
+                } else {
+                    bus->write_word(
+                      address, gpr[data.rd], CpuAccess::NonSequential);
+                }
+            }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this](LoadStoreSignExtendedHalfword& data) {
+            // Same cycles as above
+
+            uint32_t address = gpr[data.rb] + gpr[data.ro];
+
+            switch (data.s << 1 | data.h) {
+                case 0b00:
+                    bus->write_halfword(
+                      address, gpr[data.rd] & 0xFFFF, CpuAccess::NonSequential);
+                    break;
+                case 0b01:
+                    gpr[data.rd] =
+                      bus->read_halfword(address, CpuAccess::NonSequential);
+                    internal_cycle();
+                    break;
+                case 0b10:
+                    // sign extend and load the byte
+                    gpr[data.rd] = (static_cast<int32_t>(bus->read_byte(
+                                      address, CpuAccess::NonSequential))
+                                    << 24) >>
+                                   24;
+                    internal_cycle();
+                    break;
+                case 0b11:
+                    // sign extend the halfword
+                    gpr[data.rd] = (static_cast<int32_t>(bus->read_halfword(
+                                      address, CpuAccess::NonSequential))
+                                    << 16) >>
+                                   16;
+                    internal_cycle();
+                    break;
+
+                    // unreachable
+                default: {
+                }
+            }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this](LoadStoreImmediateOffset& data) {
+            // Same cycles as above
+
+            uint32_t address = gpr[data.rb] + data.offset;
+            dbg(address);
+
+            if (data.load) {
+                if (data.byte) {
+                    gpr[data.rd] =
+                      bus->read_byte(address, CpuAccess::NonSequential);
+                } else {
+                    gpr[data.rd] =
+                      bus->read_word(address, CpuAccess::NonSequential);
+                }
+                internal_cycle();
+            } else {
+                if (data.byte) {
+                    bus->write_byte(
+                      address, gpr[data.rd] & 0xFF, CpuAccess::NonSequential);
+                } else {
+                    bus->write_word(
+                      address, gpr[data.rd], CpuAccess::NonSequential);
+                }
+            }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this](LoadStoreHalfword& data) {
+            // Same cycles as above
+
+            uint32_t address = gpr[data.rb] + data.offset;
+
+            if (data.load) {
+                gpr[data.rd] =
+                  bus->read_halfword(address, CpuAccess::NonSequential);
+                internal_cycle();
+            } else {
+                bus->write_halfword(
+                  address, gpr[data.rd] & 0xFFFF, CpuAccess::NonSequential);
+            }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this](SpRelativeLoad& data) {
+            // Same cycles as above
+
+            uint32_t address = sp + data.word;
+
+            if (data.load) {
+                gpr[data.rd] = bus->read_word(address, CpuAccess::Sequential);
+                internal_cycle();
+            } else {
+                bus->write_word(address, gpr[data.rd], CpuAccess::Sequential);
+            }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this](LoadAddress& data) {
+            // 1S cycle in step()
+
+            if (data.sp) {
+                gpr[data.rd] = sp + data.word;
+            } else {
+                // PC is already current + 4, so dont need to do that
+                // force bit 1 to 0
+                gpr[data.rd] = (pc & ~(1 << 1)) + data.word;
+            }
+        },
+        [this](AddOffsetStackPointer& data) {
+            // 1S cycle in step()
+
+            sp += data.word;
+        },
+        [this, &is_flushed](PushPopRegister& data) {
+            /*
+              Load
+              ====
+              S       -> reading instruction in step()
+              N       -> unrelated read from target
+              (n-1) S -> next n - 1 related reads from target
+              I       -> stored in register
+              N+S     -> if PC is written - taken care of by flush_pipeline()
+              S       -> if PC, memory read for PC write
+              Total = nS + N + I or (n+2)S + 2N + I
+
+              Store
+              =====
+              N       -> calculating memory address
+              N       -> if LR, memory read for PC write
+              N/S     -> unrelated write at target
+              (n-1) S -> next n - 1 related writes
+              Total = 2N + nS or 2N + (n-1)S
+            */
+            static constexpr uint8_t alignment = 4;
+            CpuAccess access                   = CpuAccess::NonSequential;
+
+            if (data.load) {
+                for (uint8_t i = 0; i < 8; i++) {
+                    if (get_bit(data.regs, i)) {
+                        gpr[i] = bus->read_word(sp, access);
+                        sp += alignment;
+                        access = CpuAccess::Sequential;
+                    }
+                }
+
+                if (data.pclr) {
+                    pc = bus->read_word(sp, access);
+                    sp += alignment;
+                    is_flushed = true;
+                }
+
+                // I
+                internal_cycle();
+            } else {
+                if (data.pclr) {
+                    sp -= alignment;
+                    bus->write_word(sp, lr, access);
+                    access = CpuAccess::Sequential;
+                }
+
+                for (int8_t i = 7; i >= 0; i--) {
+                    if (get_bit(data.regs, i)) {
+                        sp -= alignment;
+                        bus->write_word(sp, gpr[i], access);
+                        access = CpuAccess::Sequential;
+                    }
+                }
+            }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this](MultipleLoad& data) {
+            /*
+              Load
+              ====
+              S       -> reading instruction in step()
+              N       -> unrelated read from target
+              (n-1) S -> next n - 1 related reads from target
+              I       -> stored in register
+              Total = nS + N + I
+
+              Store
+              =====
+              N       -> calculating memory address
+              N       -> unrelated write at target
+              (n-1) S -> next n - 1 related writes
+              Total = 2N + (n-1)S
+            */
+
+            static constexpr uint8_t alignment = 4;
+
+            uint32_t rb      = gpr[data.rb];
+            CpuAccess access = CpuAccess::NonSequential;
+
+            if (data.load) {
+                for (uint8_t i = 0; i < 8; i++) {
+                    if (get_bit(data.regs, i)) {
+                        gpr[i] = bus->read_word(rb, access);
+                        rb += alignment;
+                        access = CpuAccess::Sequential;
+                    }
+                }
+                internal_cycle();
+            } else {
+                for (uint8_t i = 0; i < 8; i++) {
+                    if (get_bit(data.regs, i)) {
+                        bus->write_word(rb, gpr[i], access);
+                        rb += alignment;
+                        access = CpuAccess::Sequential;
+                    }
+                }
+            }
+
+            gpr[data.rb] = rb;
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
+        },
+        [this, &is_flushed](ConditionalBranch& data) {
+            /*
+              S   -> reading instruction in step()
+              N+S -> if condition is true, branch and refill pipeline
+              Total = S or 2S + N
+            */
+
+            if (data.condition == Condition::AL)
+                glogger.warn("Condition 1110 (AL) is undefined");
+
+            if (!cpsr.condition(data.condition))
+                return;
+
+            pc += data.offset;
+            is_flushed = true;
+        },
+        [this, &is_flushed](SoftwareInterrupt& data) {
+            /*
+              S   -> reading instruction in step()
+              N+S -> refill pipeline
+              Total = 2S + N
+            */
+
+            // next instruction is one instruction behind PC
+            lr   = pc - INSTRUCTION_SIZE;
+            spsr = cpsr;
+            pc   = data.vector;
+            cpsr.set_state(State::Arm);
+            chg_mode(Mode::Supervisor);
+            is_flushed = true;
+        },
+        [this, &is_flushed](UnconditionalBranch& data) {
+            /*
+              S   -> reading instruction in step()
+              N+S -> branch and refill pipeline
+              Total = 2S + N
+            */
+
+            pc += data.offset;
+            is_flushed = true;
+        },
+        [this, &is_flushed](LongBranchWithLink& data) {
+            /*
+              S -> prefetched instruction in step()
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              Total = 2S + N cycles
+                      1S done, S+N taken care of by flush_pipeline()
+            */
+
+            // 12 bit integer
+            int32_t offset = data.offset;
+
+            if (data.low) {
+                uint32_t old_pc = pc;
+                offset <<= 1;
+
+                pc         = lr + offset;
+                lr         = (old_pc - INSTRUCTION_SIZE) | 1;
+                is_flushed = true;
+            } else {
+                // 12 + 11 = 23 bit
+                offset <<= 12;
+                // sign extend
+                offset = (offset << 9) >> 9;
+                lr     = pc + offset;
+            }
+        },
+        [](auto& data) {
+            glogger.error("Unknown thumb format : {}", typeid(data).name());
+        } },
+      instruction.data);
+
+    if (is_flushed)
+        flush_pipeline<State::Thumb>();
+    else
+        advance_pc_thumb();
+}
+}

src/cpu/thumb/instruction.cc

@@ -1,5 +1,6 @@
-#include "instruction.hh"
+#include "cpu/thumb/instruction.hh"
 #include "util/bits.hh"
+#include "util/log.hh"
 
 namespace matar::thumb {
 Instruction::Instruction(uint16_t insn) {
@@ -55,16 +56,20 @@ Instruction::Instruction(uint16_t insn) {
         HiRegisterOperations::OpCode opcode =
           static_cast<HiRegisterOperations::OpCode>(bit_range(insn, 8, 9));
 
+        if (opcode == HiRegisterOperations::OpCode::BX && hi_1)
+            glogger.warn("H1 set with BX");
+
         rd += (hi_1 ? LO_GPR_COUNT : 0);
         rs += (hi_2 ? LO_GPR_COUNT : 0);
 
         data = HiRegisterOperations{ .rd = rd, .rs = rs, .opcode = opcode };
         // Format 6: PC-relative load
     } else if ((insn & 0xF800) == 0x4800) {
-        uint8_t word = bit_range(insn, 0, 7);
+        uint16_t word = bit_range(insn, 0, 7);
         uint8_t rd    = bit_range(insn, 8, 10);
 
-        data = PcRelativeLoad{ .word = word, .rd = rd };
+        data =
+          PcRelativeLoad{ .word = static_cast<uint16_t>(word << 2), .rd = rd };
 
         // Format 7: Load/store with register offset
     } else if ((insn & 0xF200) == 0x5000) {
@@ -91,13 +96,16 @@ Instruction::Instruction(uint16_t insn) {
         };
 
         // Format 9: Load/store with immediate offset
-    } else if ((insn & 0xF000) == 0x6000) {
+    } else if ((insn & 0xE000) == 0x6000) {
         uint8_t rd     = bit_range(insn, 0, 2);
         uint8_t rb     = bit_range(insn, 3, 5);
         uint8_t offset = bit_range(insn, 6, 10);
         bool load      = get_bit(insn, 11);
         bool byte      = get_bit(insn, 12);
 
+        if (!byte)
+            offset <<= 2;
+
         data = LoadStoreImmediateOffset{
             .rd = rd, .rb = rb, .offset = offset, .load = load, .byte = byte
         };
@@ -109,40 +117,43 @@ Instruction::Instruction(uint16_t insn) {
         uint8_t offset = bit_range(insn, 6, 10);
         bool load      = get_bit(insn, 11);
 
+        offset <<= 1;
+
         data = LoadStoreHalfword{
             .rd = rd, .rb = rb, .offset = offset, .load = load
         };
 
         // Format 11: SP-relative load/store
     } else if ((insn & 0xF000) == 0x9000) {
-        uint8_t word = bit_range(insn, 0, 7);
+        uint16_t word = bit_range(insn, 0, 7);
         uint8_t rd    = bit_range(insn, 8, 10);
         bool load     = get_bit(insn, 11);
 
+        word <<= 2;
+
         data = SpRelativeLoad{ .word = word, .rd = rd, .load = load };
 
         // Format 12: Load address
     } else if ((insn & 0xF000) == 0xA000) {
-        uint8_t word = bit_range(insn, 0, 7);
+        uint16_t word = bit_range(insn, 0, 7);
         uint8_t rd    = bit_range(insn, 8, 10);
         bool sp       = get_bit(insn, 11);
 
-        data = LoadAddress{ .word = word, .rd = rd, .sp = sp };
-
-        // Format 12: Load address
-    } else if ((insn & 0xF000) == 0xA000) {
-        uint8_t word = bit_range(insn, 0, 7);
-        uint8_t rd   = bit_range(insn, 8, 10);
-        bool sp      = get_bit(insn, 11);
+        word <<= 2;
 
         data = LoadAddress{ .word = word, .rd = rd, .sp = sp };
 
         // Format 13: Add offset to stack pointer
     } else if ((insn & 0xFF00) == 0xB000) {
-        uint8_t word = bit_range(insn, 0, 6);
+        int16_t word = static_cast<int16_t>(bit_range(insn, 0, 6));
         bool sign    = get_bit(insn, 7);
 
-        data = AddOffsetStackPointer{ .word = word, .sign = sign };
+        word <<= 2;
+        word = static_cast<int16_t>(word * (sign ? -1 : 1));
+
+        data = AddOffsetStackPointer{
+            .word = word,
+        };
 
         // Format 14: Push/pop registers
     } else if ((insn & 0xF600) == 0xB400) {
@@ -162,30 +173,39 @@ Instruction::Instruction(uint16_t insn) {
 
         // Format 17: Software interrupt
     } else if ((insn & 0xFF00) == 0xDF00) {
-        data = SoftwareInterrupt{};
+        uint8_t vector = bit_range(insn, 0, 7);
+
+        data = SoftwareInterrupt{ .vector = vector };
 
         // Format 16: Conditional branch
     } else if ((insn & 0xF000) == 0xD000) {
-        uint16_t offset     = bit_range(insn, 0, 7);
+        int32_t offset      = bit_range(insn, 0, 7);
         Condition condition = static_cast<Condition>(bit_range(insn, 8, 11));
 
-        data = ConditionalBranch{ .offset = static_cast<uint16_t>(offset << 1),
-                                  .condition = condition };
+        offset <<= 1;
+
+        // sign extend the 9 bit integer
+        offset = (offset << 23) >> 23;
+
+        data = ConditionalBranch{ .offset = offset, .condition = condition };
 
         // Format 18: Unconditional branch
     } else if ((insn & 0xF800) == 0xE000) {
-        uint16_t offset = bit_range(insn, 0, 10);
+        int32_t offset = bit_range(insn, 0, 10);
 
-        data =
-          UnconditionalBranch{ .offset = static_cast<uint16_t>(offset << 1) };
+        offset <<= 1;
+
+        // sign extend the 12 bit integer
+        offset = (offset << 20) >> 20;
+
+        data = UnconditionalBranch{ .offset = offset };
 
         // Format 19: Long branch with link
     } else if ((insn & 0xF000) == 0xF000) {
         uint16_t offset = bit_range(insn, 0, 10);
-        bool high       = get_bit(insn, 11);
+        bool low        = get_bit(insn, 11);
 
-        data = LongBranchWithLink{ .offset = static_cast<uint16_t>(offset << 1),
-                                   .high   = high };
+        data = LongBranchWithLink{ .offset = offset, .low = low };
     }
 }
 }

src/cpu/thumb/meson.build

@@ -1,5 +1,6 @@
 lib_sources += files(
-  'instruction.cc'
+  'instruction.cc',
+  'exec.cc'
 )
 
 if get_option('disassembler')

src/gdb_rsp.cc

@@ -0,0 +1,487 @@
+#include "gdb_rsp.hh"
+#include "util/log.hh"
+#include <csignal>
+#include <numeric>
+#include <regex>
+#include <stdexcept>
+#include <string>
+
+namespace matar {
+
+template<typename... Args>
+static inline constexpr void
+gdb_log(const std::format_string<Args...>& fmt, Args&&... args) {
+    glogger.debug("GDB: {}", std::format(fmt, std::forward<Args>(args)...));
+}
+
+static inline void
+append_le(std::string& str, uint32_t value) {
+    // little endian only
+    str += std::format("{:02x}", value & 0xFF);
+    str += std::format("{:02x}", value >> 8 & 0xFF);
+    str += std::format("{:02x}", value >> 16 & 0xFF);
+    str += std::format("{:02x}", value >> 24 & 0xFF);
+}
+
+static inline std::string
+be_to_le(std::string str) {
+    if (str.length() != 8)
+        throw std::out_of_range("string is supposed to be 8 bytes");
+
+    std::string current;
+
+    for (int i = 7; i >= 0; i -= 2) {
+        current += str[i - 1];
+        current += str[i];
+    }
+
+    return current;
+}
+
+GdbRsp::GdbRsp(std::shared_ptr<Cpu> cpu, uint port)
+  : cpu(cpu) {
+    server.start(port);
+}
+
+void
+GdbRsp::start() {
+    server.run();
+
+    attach();
+
+    // attaching is not enough, we continue, until the last GDB communication
+    // happens for ARMv4t i.e, fetching of the CPSR
+    std::string msg;
+
+    while (msg != "$p19") {
+        msg = receive();
+        step(msg); // 25th (0x19) register is cpsr
+    }
+}
+
+void
+GdbRsp::attach() {
+    while (!attached) {
+        step();
+    }
+}
+
+void
+GdbRsp::satisfy_client() {
+    while (server.client_waiting() && attached) {
+        step();
+    }
+}
+
+void
+GdbRsp::step() {
+    std::string msg = receive();
+    step(msg);
+}
+
+void
+GdbRsp::step(std::string msg) {
+    switch (msg[0]) {
+        case '+':
+            break;
+        case '-':
+            break;
+        case '\x03':
+            gdb_log("ctrl+c interrupt received");
+            cmd_halted();
+            break;
+        case '$': {
+            acknowledge();
+            switch (msg[1]) {
+                case '?':
+                    cmd_halted();
+                    break;
+                case 'g':
+                    cmd_read_registers();
+                    break;
+                case 'G':
+                    cmd_write_registers(msg);
+                    break;
+                case 'p':
+                    cmd_read_register(msg);
+                    break;
+                case 'P':
+                    cmd_write_register(msg);
+                    break;
+                case 'm':
+                    cmd_read_memory(msg);
+                    break;
+                case 'M':
+                    cmd_write_memory(msg);
+                    break;
+                case 'z':
+                    cmd_rm_breakpoint(msg);
+                    break;
+                case 'Z':
+                    cmd_add_breakpoint(msg);
+                    break;
+                case 'c':
+                    cmd_continue();
+                    break;
+                case 'D':
+                    cmd_detach();
+                    break;
+                case 'Q':
+                    if (msg == "$QStartNoAckMode")
+                        ack_mode = true;
+                    send_ok();
+                    break;
+                case 'q':
+                    if (msg.starts_with("$qSupported")) {
+                        cmd_supported(msg);
+                        break;
+                    } else if (msg == "$qAttached") {
+                        cmd_attached();
+                        break;
+                    }
+                    [[fallthrough]];
+                default:
+                    gdb_log("unknown command");
+                    send_empty();
+            }
+            break;
+        }
+        default:
+            gdb_log("unknown message received");
+    }
+}
+
+std::string
+GdbRsp::receive() {
+    std::string msg = server.receive(1);
+    char ch         = msg[0];
+    uint checksum   = 0;
+
+    if (ch == '$') {
+        while ((ch = server.receive(1)[0]) != '#') {
+            checksum += static_cast<uint>(ch);
+            msg += ch;
+            if (msg.length() > MAX_MSG_LEN) {
+                throw std::logic_error("GDB: received message is too long");
+            }
+        }
+
+        if (std::stoul(server.receive(2), nullptr, 16) != (checksum & 0xFF)) {
+            gdb_log("{}", msg);
+            throw std::logic_error("GDB: bad message checksum");
+        }
+    }
+
+    gdb_log("received message \"{}\"", msg);
+    return msg;
+}
+
+std::string
+GdbRsp::make_packet(std::string raw) {
+    uint checksum = std::accumulate(raw.begin(), raw.end(), 0);
+    return std::format("${}#{:02x}", raw, checksum & 0xFF);
+}
+
+void
+GdbRsp::acknowledge() {
+    if (ack_mode)
+        server.send("+");
+}
+
+void
+GdbRsp::send_empty() {
+    server.send(make_packet(""));
+}
+
+void
+GdbRsp::send_ok() {
+    acknowledge();
+    server.send(make_packet("OK"));
+}
+
+void
+GdbRsp::notify_breakpoint_reached() {
+    gdb_log("reached breakpoint, sending signal");
+    server.send(make_packet(std::format("S{:02x}", SIGTRAP)));
+}
+
+void
+GdbRsp::cmd_attached() {
+    attached = true;
+
+    gdb_log("server is now attached");
+    server.send(make_packet("1"));
+}
+
+void
+GdbRsp::cmd_supported(std::string msg) {
+    std::string response;
+
+    if (msg.find("hwbreak+;") != std::string::npos)
+        response += "hwbreak+;";
+
+    // no acknowledgement mode
+    response += "QStartNoAckMode+";
+
+    gdb_log("sending response for qSupported");
+    server.send(make_packet(response));
+}
+
+void
+GdbRsp::cmd_halted() {
+    gdb_log("sending reason for upcoming halt");
+    server.send(make_packet(std::format("S{:02x}", SIGTRAP)));
+}
+
+void
+GdbRsp::cmd_read_registers() {
+    std::string response;
+
+    for (int i = 0; i < cpu->GPR_COUNT - 1; i++)
+        append_le(response, cpu->gpr[i]);
+
+    // for some reason this PC needs to be the address of executing instruction
+    // i.e, two instructions behind actual PC
+    append_le(response,
+              cpu->pc - 2 * (cpu->cpsr.state() == State::Arm
+                               ? arm::INSTRUCTION_SIZE
+                               : thumb::INSTRUCTION_SIZE));
+
+    gdb_log("sending register values");
+    server.send(make_packet(response));
+}
+
+void
+GdbRsp::cmd_write_registers(std::string msg) {
+    static std::regex rgx("\\$G([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 2 || sm[1].str().size() != 16 * 8) {
+        gdb_log("invalid arguments to write registers");
+        send_empty();
+        return;
+    }
+
+    try {
+        std::string values = sm[1].str();
+
+        for (uint i = 0, j = 0; i < values.length() - 8; i += 8, j++) {
+            cpu->gpr[i] = std::stoul(sm[i + 1].str(), nullptr, 16);
+            cpu->gpr[j] =
+              std::stoul(be_to_le(values.substr(i, 8)), nullptr, 16);
+        }
+
+        gdb_log("register values written");
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_read_register(std::string msg) {
+    std::string response;
+
+    try {
+        uint reg = std::stoul(msg.substr(2), nullptr, 16);
+        // 25th register is CPSR in gdb ARM
+        if (reg == 25)
+            append_le(response, cpu->cpsr.raw());
+        else if (reg < cpu->GPR_COUNT)
+            append_le(response, cpu->gpr[reg]);
+        else
+            response += "xxxxxxxx";
+
+        gdb_log("sending single register value");
+        server.send(make_packet(response));
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_write_register(std::string msg) {
+    static std::regex rgx("\\$P([0-9A-Fa-f]+)\\=([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 3 && sm[2].str().length() != 8) {
+        gdb_log("invalid arguments to write single register");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint reg       = std::stoul(sm[1].str(), nullptr, 16);
+        uint32_t value = std::stoul(be_to_le(sm[2].str()), nullptr, 16);
+
+        dbg(value);
+
+        if (reg == 25)
+            cpu->cpsr.set_all(value);
+        else if (reg < cpu->GPR_COUNT)
+            cpu->gpr[reg] = value;
+
+        gdb_log("single register value written");
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_read_memory(std::string msg) {
+    std::string response;
+
+    static std::regex rgx("\\$m([0-9A-Fa-f]+),([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 3) {
+        gdb_log("invalid arguments to read memory");
+        send_empty();
+        return;
+    }
+
+    uint32_t address = 0, length = 0;
+
+    try {
+        address = std::stoul(sm[1].str(), nullptr, 16);
+        length  = std::stoul(sm[2].str(), nullptr, 16);
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+        return;
+    }
+
+    for (uint i = 0; i < length; i++) {
+        response += std::format("{:02x}", cpu->bus->read_byte(address + i));
+    }
+
+    gdb_log("sending memory values values");
+    server.send(make_packet(response));
+}
+
+void
+GdbRsp::cmd_write_memory(std::string msg) {
+    static std::regex rgx("\\$M([0-9A-Fa-f]+),([0-9A-Fa-f]+):([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 4) {
+        gdb_log("invalid arguments to write memory");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint32_t address = std::stoul(sm[1].str(), nullptr, 16);
+        uint32_t length  = std::stoul(sm[2].str(), nullptr, 16);
+
+        std::string values = sm[3].str();
+
+        for (uint i = 0, j = 0; i < length && j < values.size(); i++, j += 2) {
+            cpu->bus->write_byte(
+              address + i, std::stoul(values.substr(j, 2), nullptr, 16) & 0xFF);
+        }
+
+        gdb_log("register values written");
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_rm_breakpoint(std::string msg) {
+    static std::regex rgx("\\$z(0|1),([0-9A-Fa-f]+),(2|3|4)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 4) {
+        gdb_log("invalid arguments to remove breakpoint");
+        send_empty();
+        return;
+    }
+
+    if (sm[1].str() != "0" && sm[0].str() != "1") {
+        gdb_log("unrecognized breakpoint type encountered");
+        send_empty();
+        return;
+    }
+
+    if (sm[3].str() != "3" && sm[3].str() != "4") {
+        gdb_log("only 32 bit breakpoints supported");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint32_t address = std::stoul(sm[2].str(), nullptr, 16);
+
+        cpu->breakpoints.erase(address);
+        gdb_log("breakpoint {:#08x} removed", address);
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_add_breakpoint(std::string msg) {
+    static std::regex rgx("\\$Z(0|1),([0-9A-Fa-f]+),(2|3|4)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+    dbg(sm.size());
+    dbg(sm[0].str());
+
+    if (sm.size() != 4) {
+        gdb_log("invalid arguments to add breakpoint");
+        send_empty();
+        return;
+    }
+
+    if (sm[1].str() != "0" && sm[0].str() != "1") {
+        gdb_log("unrecognized breakpoint type encountered");
+        send_empty();
+        return;
+    }
+
+    if (sm[3].str() != "3" && sm[3].str() != "4") {
+        gdb_log("only 32 bit breakpoints supported");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint32_t address = std::stoul(sm[2].str(), nullptr, 16);
+
+        cpu->breakpoints.insert(address);
+        gdb_log("breakpoint {:#08x} added", address);
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_detach() {
+    attached = false;
+    gdb_log("detached");
+    send_ok();
+}
+
+void
+GdbRsp::cmd_continue() {
+    // what to do?
+    gdb_log("cpu continued");
+    send_ok();
+}
+}

src/gdb_rsp.hh

@@ -0,0 +1,47 @@
+#include "cpu/cpu.hh"
+#include "util/tcp_server.hh"
+
+namespace matar {
+class GdbRsp {
+  public:
+    GdbRsp(std::shared_ptr<Cpu> cpu, uint port);
+    ~GdbRsp() = default;
+    void start();
+    void attach();
+    void satisfy_client();
+    void step();
+    void step(std::string msg);
+    void notify_breakpoint_reached();
+    inline bool is_attached() { return attached; }
+
+  private:
+    bool attached = false;
+
+    std::shared_ptr<Cpu> cpu;
+    net::TcpServer server;
+    std::string receive();
+    std::string make_packet(std::string raw);
+
+    bool ack_mode = true;
+    void acknowledge();
+    void send_empty();
+    void send_ok();
+
+    // Commands
+    void cmd_attached();
+    void cmd_supported(std::string msg);
+    void cmd_halted();
+    void cmd_read_registers();
+    void cmd_write_registers(std::string msg);
+    void cmd_read_register(std::string msg);
+    void cmd_write_register(std::string msg);
+    void cmd_read_memory(std::string msg);
+    void cmd_write_memory(std::string msg);
+    void cmd_rm_breakpoint(std::string msg);
+    void cmd_add_breakpoint(std::string msg);
+    void cmd_detach();
+    void cmd_continue();
+
+    static constexpr uint MAX_MSG_LEN = 4096;
+};
+}

src/io/display/display.cc

@@ -0,0 +1,23 @@
+#include "io/display/display.hh"
+
+namespace matar {
+namespace display {
+
+/*
+static constexpr uint LCD_HEIGHT = 160;
+static constexpr uint LCD_WIDTH  = 240;
+static constexpr uint BLANK      = 68;
+
+static constexpr uint PIXEL_CYCLES    = 4;                             // 4
+static constexpr uint HDRAW_CYCLES    = LCD_WIDTH * PIXEL_CYCLES + 46; // 1006
+static constexpr uint HBLANK_CYCLES   = BLANK * PIXEL_CYCLES - 46;     // 226
+static constexpr uint HREFRESH_CYCLES = HDRAW_CYCLES + HBLANK_CYCLES;  // 1232
+static constexpr uint VDRAW_CYCLES    = LCD_HEIGHT * HREFRESH_CYCLES;  // 197120
+static constexpr uint VBLANK_CYCLES   = BLANK * HREFRESH_CYCLES;       // 83776
+static constexpr uint VREFRESH_CYCLES = VDRAW_CYCLES + VBLANK_CYCLES;  // 280896
+*/
+
+void
+Display::mode_3() {}
+}
+}

src/io/display/meson.build

@@ -0,0 +1,3 @@
+lib_sources += files(
+  'display.cc'
+)

src/io/display/render.cc

@@ -0,0 +1,51 @@
+#include "io/display/display.hh"
+
+namespace matar {
+namespace display {
+
+struct TextScreen {
+    uint16_t tile_number : 10;
+    bool mirror_horizontal : 1;
+    bool mirror_vertical : 1;
+    uint8_t palette_number : 4;
+};
+
+// if 16th bit is set, this will denote the transparent color in rgb555 format
+static constexpr uint16_t TRANSPARENT_RGB555 = 0x8000;
+
+template<int MODE, typename>
+void
+Display::render_bitmap_mode() {
+    static constexpr std::size_t VIEWPORT_WIDTH = MODE == 5 ? 160 : 240;
+
+    for (int x = 0; x < LCD_WIDTH; x++) {
+        // pixel to texel for x
+        // shift by 8 cuz both ref.x and a are fixed point floats shifted by 8
+        int32_t x_ = (bg2_rot_scale.ref.x + x * bg2_rot_scale.a) >> 8;
+        int32_t y_ = (bg2_rot_scale.ref.y + x * bg2_rot_scale.c) >> 8;
+
+        // ignore handling area overflow for bitmap modes
+        // i am not sure how well this will turn out
+
+        std::size_t idx = y_ * VIEWPORT_WIDTH + x_;
+
+        // mode 3 and 5 takes 2 bytes per pixel
+        if constexpr (MODE != 4)
+            idx *= 2;
+
+        // offset
+        if constexpr (MODE != 3) {
+            std::size_t offset =
+              lcd_control.value.frame_select_1 ? 0xA000 : 0x0000;
+            idx += offset;
+        }
+
+        // read two bytes
+        if constexpr (MODE == 4)
+            scanline_buffers[2][x] = pram.read_halfword(vram.read_byte(idx));
+        else
+            scanline_buffers[2][x] = vram.read_halfword(idx);
+    }
+}
+}
+}

src/io/io.cc

@@ -0,0 +1,419 @@
+#include "io/io.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+namespace matar {
+#define ADDR static constexpr uint32_t
+
+// lcd
+ADDR DISPCNT  = 0x4000000;
+ADDR DISPSTAT = 0x4000004;
+ADDR VCOUNT   = 0x4000006;
+ADDR BG0CNT   = 0x4000008;
+ADDR BG1CNT   = 0x400000A;
+ADDR BG2CNT   = 0x400000C;
+ADDR BG3CNT   = 0x400000E;
+ADDR BG0HOFS  = 0x4000010;
+ADDR BG0VOFS  = 0x4000012;
+ADDR BG1HOFS  = 0x4000014;
+ADDR BG1VOFS  = 0x4000016;
+ADDR BG2HOFS  = 0x4000018;
+ADDR BG2VOFS  = 0x400001A;
+ADDR BG3HOFS  = 0x400001C;
+ADDR BG3VOFS  = 0x400001E;
+ADDR BG2PA    = 0x4000020;
+ADDR BG2PB    = 0x4000022;
+ADDR BG2PC    = 0x4000024;
+ADDR BG2PD    = 0x4000026;
+ADDR BG2X_L   = 0x4000028;
+ADDR BG2X_H   = 0x400002A;
+ADDR BG2Y_L   = 0x400002C;
+ADDR BG2Y_H   = 0x400002E;
+ADDR BG3PA    = 0x4000030;
+ADDR BG3PB    = 0x4000032;
+ADDR BG3PC    = 0x4000034;
+ADDR BG3PD    = 0x4000036;
+ADDR BG3X_L   = 0x4000038;
+ADDR BG3X_H   = 0x400003A;
+ADDR BG3Y_L   = 0x400003C;
+ADDR BG3Y_H   = 0x400003E;
+ADDR WIN0H    = 0x4000040;
+ADDR WIN1H    = 0x4000042;
+ADDR WIN0V    = 0x4000044;
+ADDR WIN1V    = 0x4000046;
+ADDR WININ    = 0x4000048;
+ADDR WINOUT   = 0x400004A;
+ADDR MOSAIC   = 0x400004C;
+ADDR BLDCNT   = 0x4000050;
+ADDR BLDALPHA = 0x4000052;
+ADDR BLDY     = 0x4000054;
+
+// sound
+ADDR SOUND1CNT_L = 0x4000060;
+ADDR SOUND1CNT_H = 0x4000062;
+ADDR SOUND1CNT_X = 0x4000064;
+ADDR SOUND2CNT_L = 0x4000068;
+ADDR SOUND2CNT_H = 0x400006C;
+ADDR SOUND3CNT_L = 0x4000070;
+ADDR SOUND3CNT_H = 0x4000072;
+ADDR SOUND3CNT_X = 0x4000074;
+ADDR SOUND4CNT_L = 0x4000078;
+ADDR SOUND4CNT_H = 0x400007C;
+ADDR SOUNDCNT_L  = 0x4000080;
+ADDR SOUNDCNT_H  = 0x4000082;
+ADDR SOUNDCNT_X  = 0x4000084;
+ADDR SOUNDBIAS   = 0x4000088;
+ADDR WAVE_RAM0_L = 0x4000090;
+ADDR WAVE_RAM0_H = 0x4000092;
+ADDR WAVE_RAM1_L = 0x4000094;
+ADDR WAVE_RAM1_H = 0x4000096;
+ADDR WAVE_RAM2_L = 0x4000098;
+ADDR WAVE_RAM2_H = 0x400009A;
+ADDR WAVE_RAM3_L = 0x400009C;
+ADDR WAVE_RAM3_H = 0x400009E;
+ADDR FIFO_A_L    = 0x40000A0;
+ADDR FIFO_A_H    = 0x40000A2;
+ADDR FIFO_B_L    = 0x40000A4;
+ADDR FIFO_B_H    = 0x40000A6;
+
+// dma
+ADDR DMA0SAD   = 0x40000B0;
+ADDR DMA0DAD   = 0x40000B4;
+ADDR DMA0CNT_L = 0x40000B8;
+ADDR DMA0CNT_H = 0x40000BA;
+ADDR DMA1SAD   = 0x40000BC;
+ADDR DMA1DAD   = 0x40000C0;
+ADDR DMA1CNT_L = 0x40000C4;
+ADDR DMA1CNT_H = 0x40000C6;
+ADDR DMA2SAD   = 0x40000C8;
+ADDR DMA2DAD   = 0x40000CC;
+ADDR DMA2CNT_L = 0x40000D0;
+ADDR DMA2CNT_H = 0x40000D2;
+ADDR DMA3SAD   = 0x40000D4;
+ADDR DMA3DAD   = 0x40000D8;
+ADDR DMA3CNT_L = 0x40000DC;
+ADDR DMA3CNT_H = 0x40000DE;
+
+// system
+ADDR POSTFLG = 0x4000300;
+ADDR IME     = 0x4000208;
+ADDR IE      = 0x4000200;
+ADDR IF      = 0x4000202;
+ADDR WAITCNT = 0x4000204;
+ADDR HALTCNT = 0x4000301;
+
+#undef ADDR
+
+IoDevices::IoDevices(std::weak_ptr<Bus> bus)
+  : bus(bus) {}
+
+uint8_t
+IoDevices::read_byte(uint32_t address) const {
+    uint16_t halfword = read_halfword(address & ~1);
+
+    if (address & 1)
+        halfword >>= 8;
+
+    return halfword & 0xFF;
+}
+
+void
+IoDevices::write_byte(uint32_t address, uint8_t byte) {
+    uint16_t halfword = read_halfword(address & ~1);
+
+    if (address & 1)
+        write_halfword(address & ~1,
+                       (static_cast<uint16_t>(byte) << 8) | (halfword & 0xFF));
+    else
+        write_halfword(address & ~1,
+                       (static_cast<uint16_t>(byte) | (halfword & 0xFF00)));
+}
+
+uint32_t
+IoDevices::read_word(uint32_t address) const {
+    return read_halfword(address) | read_halfword(address + 2) << 16;
+}
+
+void
+IoDevices::write_word(uint32_t address, uint32_t word) {
+    write_halfword(address, word & 0xFFFF);
+    write_halfword(address + 2, (word >> 16) & 0xFFFF);
+}
+
+uint16_t
+IoDevices::read_halfword(uint32_t address) const {
+    switch (address) {
+
+#define READ(name, var)                                                        \
+    case name:                                                                 \
+        return var;
+
+            // lcd
+        case DISPCNT:
+            return display.lcd_control.read();
+        case DISPSTAT:
+            return display.general_lcd_status.read();
+        case BG0CNT:
+            return display.bg_control[0].read();
+        case BG1CNT:
+            return display.bg_control[1].read();
+        case BG2CNT:
+            return display.bg_control[2].read();
+        case BG3CNT:
+            return display.bg_control[3].read();
+
+            READ(VCOUNT, display.vertical_counter)
+            READ(WININ, display.inside_win_0_1)
+            READ(WINOUT, display.outside_win)
+            READ(BLDCNT, display.color_special_effects_selection)
+            READ(BLDALPHA, display.alpha_blending_coefficients)
+
+            // sound
+            READ(SOUND1CNT_L, sound.ch1_sweep)
+            READ(SOUND1CNT_H, sound.ch1_duty_length_env)
+            READ(SOUND1CNT_X, sound.ch1_freq_control)
+            READ(SOUND2CNT_L, sound.ch2_duty_length_env)
+            READ(SOUND2CNT_H, sound.ch2_freq_control)
+            READ(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
+            READ(SOUND3CNT_H, sound.ch3_length_volume)
+            READ(SOUND3CNT_X, sound.ch3_freq_control)
+            READ(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
+            READ(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
+            READ(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
+            READ(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
+            READ(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
+            READ(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
+            READ(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
+            READ(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
+            READ(SOUND4CNT_L, sound.ch4_length_env);
+            READ(SOUND4CNT_H, sound.ch4_freq_control);
+            READ(SOUNDCNT_L, sound.ctrl_stereo_volume);
+            READ(SOUNDCNT_H, sound.ctrl_mixing);
+            READ(SOUNDCNT_X, sound.ctrl_sound_on_off);
+            READ(SOUNDBIAS, sound.pwm_control);
+
+            // dma
+        case DMA0CNT_H:
+            return dma.channels[0].control.read();
+        case DMA1CNT_H:
+            return dma.channels[1].control.read();
+        case DMA2CNT_H:
+            return dma.channels[2].control.read();
+        case DMA3CNT_H:
+            return dma.channels[3].control.read();
+
+            READ(DMA0SAD, dma.channels[0].source[0]);
+            READ(DMA0SAD + 2, dma.channels[0].source[1]);
+            READ(DMA0DAD, dma.channels[0].destination[0]);
+            READ(DMA0DAD + 2, dma.channels[0].destination[1]);
+            READ(DMA0CNT_L, dma.channels[0].word_count);
+            READ(DMA1SAD, dma.channels[1].source[0]);
+            READ(DMA1SAD + 2, dma.channels[1].source[1]);
+            READ(DMA1DAD, dma.channels[1].destination[0]);
+            READ(DMA1DAD + 2, dma.channels[1].destination[1]);
+            READ(DMA1CNT_L, dma.channels[1].word_count);
+            READ(DMA2SAD, dma.channels[2].source[0]);
+            READ(DMA2SAD + 2, dma.channels[2].source[1]);
+            READ(DMA2DAD, dma.channels[2].destination[0]);
+            READ(DMA2DAD + 2, dma.channels[2].destination[1]);
+            READ(DMA2CNT_L, dma.channels[2].word_count);
+            READ(DMA3SAD, dma.channels[3].source[0]);
+            READ(DMA3SAD + 2, dma.channels[3].source[1]);
+            READ(DMA3DAD, dma.channels[3].destination[0]);
+            READ(DMA3DAD + 2, dma.channels[3].destination[1]);
+            READ(DMA3CNT_L, dma.channels[3].word_count);
+
+            // system
+            READ(POSTFLG, system.post_boot_flag)
+            READ(IME, system.interrupt_master_enabler)
+            READ(IE, system.interrupt_enable);
+            READ(IF, system.interrupt_request_flags);
+            READ(WAITCNT, system.waitstate_control);
+
+#undef READ
+
+        default:
+            glogger.warn("Unused IO address read at 0x{:08X}", address);
+    }
+
+    return 0xFF;
+}
+
+void
+IoDevices::write_halfword(uint32_t address, uint16_t halfword) {
+    // set lower 16 bits for reference points (BG 2/3)
+    auto ref_low = [](uint32_t original, uint16_t low) {
+        return static_cast<int32_t>((original & 0xFFFF0000) | low);
+    };
+
+    // set upper 12 bits for reference points (BG 2/3)
+    // and sign extend
+    auto ref_high = [](uint32_t original, uint16_t high) {
+        return static_cast<int32_t>(
+          ((((high & 0xFFF) << 16) | (original & 0xFFFF)) << 4) >> 4);
+    };
+
+    switch (address) {
+
+#define WRITE(name, var)                                                       \
+    case name:                                                                 \
+        var = halfword;                                                        \
+        break;
+
+#define WRITE_2(name, var, val)                                                \
+    case name:                                                                 \
+        var = val;                                                             \
+        break;
+
+        // lcd
+        case DISPCNT:
+            display.lcd_control.write(halfword);
+            break;
+        case DISPSTAT:
+            display.general_lcd_status.write(halfword);
+            break;
+        case BG0CNT:
+            display.bg_control[0].write(halfword);
+            break;
+        case BG1CNT:
+            display.bg_control[1].write(halfword);
+            break;
+        case BG2CNT:
+            display.bg_control[2].write(halfword);
+            break;
+        case BG3CNT:
+            display.bg_control[3].write(halfword);
+            break;
+
+            WRITE(BG0HOFS, display.bg0_offset.x)
+            WRITE(BG0VOFS, display.bg0_offset.y)
+            WRITE(BG1HOFS, display.bg1_offset.x)
+            WRITE(BG1VOFS, display.bg1_offset.y)
+            WRITE(BG2HOFS, display.bg2_offset.x)
+            WRITE(BG2VOFS, display.bg2_offset.y)
+            WRITE(BG3HOFS, display.bg3_offset.x)
+            WRITE(BG3VOFS, display.bg3_offset.y)
+            WRITE(BG2PA, display.bg2_rot_scale.a)
+            WRITE(BG2PB, display.bg2_rot_scale.b)
+            WRITE(BG2PC, display.bg2_rot_scale.c)
+            WRITE(BG2PD, display.bg2_rot_scale.d)
+            WRITE_2(BG2X_L,
+                    display.bg2_rot_scale.ref.x,
+                    ref_low(display.bg2_rot_scale.ref.x, halfword));
+            WRITE_2(BG2X_H,
+                    display.bg2_rot_scale.ref.x,
+                    ref_high(display.bg2_rot_scale.ref.x, halfword));
+            WRITE_2(BG2Y_L,
+                    display.bg2_rot_scale.ref.y,
+                    ref_low(display.bg2_rot_scale.ref.y, halfword));
+            WRITE_2(BG2Y_H,
+                    display.bg2_rot_scale.ref.y,
+                    ref_high(display.bg2_rot_scale.ref.y, halfword));
+            WRITE(BG3PA, display.bg3_rot_scale.a)
+            WRITE(BG3PB, display.bg3_rot_scale.b)
+            WRITE(BG3PC, display.bg3_rot_scale.c)
+            WRITE(BG3PD, display.bg3_rot_scale.d)
+            WRITE_2(BG3X_L,
+                    display.bg3_rot_scale.ref.x,
+                    ref_low(display.bg3_rot_scale.ref.x, halfword));
+            WRITE_2(BG3X_H,
+                    display.bg3_rot_scale.ref.x,
+                    ref_high(display.bg3_rot_scale.ref.x, halfword));
+            WRITE_2(BG3Y_L,
+                    display.bg3_rot_scale.ref.y,
+                    ref_low(display.bg3_rot_scale.ref.y, halfword));
+            WRITE_2(BG3Y_H,
+                    display.bg3_rot_scale.ref.y,
+                    ref_high(display.bg3_rot_scale.ref.y, halfword));
+            WRITE(WIN0H, display.win0_horizontal_dimensions)
+            WRITE(WIN1H, display.win1_horizontal_dimensions)
+            WRITE(WIN0V, display.win0_vertical_dimensions)
+            WRITE(WIN1V, display.win1_vertical_dimensions)
+            WRITE(WININ, display.inside_win_0_1)
+            WRITE(WINOUT, display.outside_win)
+            WRITE(MOSAIC, display.mosaic_size)
+            WRITE(BLDCNT, display.color_special_effects_selection)
+            WRITE(BLDALPHA, display.alpha_blending_coefficients)
+            WRITE(BLDY, display.brightness_coefficient)
+
+            // sound
+            WRITE(SOUND1CNT_L, sound.ch1_sweep)
+            WRITE(SOUND1CNT_H, sound.ch1_duty_length_env)
+            WRITE(SOUND1CNT_X, sound.ch1_freq_control)
+            WRITE(SOUND2CNT_L, sound.ch2_duty_length_env)
+            WRITE(SOUND2CNT_H, sound.ch2_freq_control)
+            WRITE(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
+            WRITE(SOUND3CNT_H, sound.ch3_length_volume)
+            WRITE(SOUND3CNT_X, sound.ch3_freq_control)
+            WRITE(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
+            WRITE(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
+            WRITE(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
+            WRITE(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
+            WRITE(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
+            WRITE(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
+            WRITE(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
+            WRITE(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
+            WRITE(SOUND4CNT_L, sound.ch4_length_env);
+            WRITE(SOUND4CNT_H, sound.ch4_freq_control);
+            WRITE(SOUNDCNT_L, sound.ctrl_stereo_volume);
+            WRITE(SOUNDCNT_H, sound.ctrl_mixing);
+            WRITE(SOUNDCNT_X, sound.ctrl_sound_on_off);
+            WRITE(SOUNDBIAS, sound.pwm_control);
+            WRITE(FIFO_A_L, sound.fifo_a[0]);
+            WRITE(FIFO_A_H, sound.fifo_a[1]);
+            WRITE(FIFO_B_L, sound.fifo_b[0]);
+            WRITE(FIFO_B_H, sound.fifo_b[1]);
+
+            // dma
+        case DMA0CNT_H:
+            dma.channels[0].control.write(halfword);
+            break;
+        case DMA1CNT_H:
+            dma.channels[1].control.write(halfword);
+            break;
+        case DMA2CNT_H:
+            dma.channels[2].control.write(halfword);
+            break;
+        case DMA3CNT_H:
+            dma.channels[3].control.write(halfword);
+            break;
+
+            WRITE(DMA0SAD, dma.channels[0].source[0]);
+            WRITE(DMA0SAD + 2, dma.channels[0].source[1]);
+            WRITE(DMA0DAD, dma.channels[0].destination[0]);
+            WRITE(DMA0DAD + 2, dma.channels[0].destination[1]);
+            WRITE(DMA0CNT_L, dma.channels[0].word_count);
+            WRITE(DMA1SAD, dma.channels[1].source[0]);
+            WRITE(DMA1SAD + 2, dma.channels[1].source[1]);
+            WRITE(DMA1DAD, dma.channels[1].destination[0]);
+            WRITE(DMA1DAD + 2, dma.channels[1].destination[1]);
+            WRITE(DMA1CNT_L, dma.channels[1].word_count);
+            WRITE(DMA2SAD, dma.channels[2].source[0]);
+            WRITE(DMA2SAD + 2, dma.channels[2].source[1]);
+            WRITE(DMA2DAD, dma.channels[2].destination[0]);
+            WRITE(DMA2DAD + 2, dma.channels[2].destination[1]);
+            WRITE(DMA2CNT_L, dma.channels[2].word_count);
+            WRITE(DMA3SAD, dma.channels[3].source[0]);
+            WRITE(DMA3SAD + 2, dma.channels[3].source[1]);
+            WRITE(DMA3DAD, dma.channels[3].destination[0]);
+            WRITE(DMA3DAD + 2, dma.channels[3].destination[1]);
+            WRITE(DMA3CNT_L, dma.channels[3].word_count);
+
+            // system
+            WRITE_2(POSTFLG, system.post_boot_flag, halfword & 1)
+            WRITE_2(IME, system.interrupt_master_enabler, halfword & 1)
+            WRITE(IE, system.interrupt_enable);
+            WRITE(IF, system.interrupt_request_flags);
+            WRITE(WAITCNT, system.waitstate_control);
+            WRITE_2(HALTCNT, system.low_power_mode, get_bit(halfword, 7));
+
+#undef WRITE
+#undef WRITE_2
+
+        default:
+            glogger.warn("Unused IO address written at 0x{:08X}", address);
+    }
+    return;
+}
+
+}

src/io/meson.build

@@ -0,0 +1,3 @@
+lib_sources += files(
+  'io.cc'
+)

src/memory.cc

@@ -1,198 +0,0 @@
-#include "memory.hh"
-#include "header.hh"
-#include "util/bits.hh"
-#include "util/crypto.hh"
-#include "util/log.hh"
-#include <bitset>
-#include <stdexcept>
-
-namespace matar {
-Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-               std::vector<uint8_t>&& rom)
-  : bios(std::move(bios))
-  , board_wram({ 0 })
-  , chip_wram({ 0 })
-  , palette_ram({ 0 })
-  , vram({ 0 })
-  , oam_obj_attr({ 0 })
-  , rom(std::move(rom)) {
-    std::string bios_hash = crypto::sha256(this->bios);
-    static constexpr std::string_view expected_hash =
-      "fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
-
-    if (bios_hash != expected_hash) {
-        glogger.warn("BIOS hash failed to match, run at your own risk"
-                     "\nExpected : {} "
-                     "\nGot      : {}",
-                     expected_hash,
-                     bios_hash);
-    }
-
-    parse_header();
-
-    glogger.info("Memory successfully initialised");
-    glogger.info("Cartridge Title: {}", header.title);
-};
-
-#define MATCHES(area) address >= area##_START&& address <= area##_END
-
-uint8_t
-Memory::read(size_t address) const {
-    if (MATCHES(BIOS)) {
-        return bios[address];
-    } else if (MATCHES(BOARD_WRAM)) {
-        return board_wram[address - BOARD_WRAM_START];
-    } else if (MATCHES(CHIP_WRAM)) {
-        return chip_wram[address - CHIP_WRAM_START];
-    } else if (MATCHES(PALETTE_RAM)) {
-        return palette_ram[address - PALETTE_RAM_START];
-    } else if (MATCHES(VRAM)) {
-        return vram[address - VRAM_START];
-    } else if (MATCHES(OAM_OBJ_ATTR)) {
-        return oam_obj_attr[address - OAM_OBJ_ATTR_START];
-    } else if (MATCHES(ROM_0)) {
-        return rom[address - ROM_0_START];
-    } else if (MATCHES(ROM_1)) {
-        return rom[address - ROM_1_START];
-    } else if (MATCHES(ROM_2)) {
-        return rom[address - ROM_2_START];
-    } else {
-        glogger.error("Invalid memory region accessed");
-        return 0xFF;
-    }
-}
-
-void
-Memory::write(size_t address, uint8_t byte) {
-    if (MATCHES(BIOS)) {
-        bios[address] = byte;
-    } else if (MATCHES(BOARD_WRAM)) {
-        board_wram[address - BOARD_WRAM_START] = byte;
-    } else if (MATCHES(CHIP_WRAM)) {
-        chip_wram[address - CHIP_WRAM_START] = byte;
-    } else if (MATCHES(PALETTE_RAM)) {
-        palette_ram[address - PALETTE_RAM_START] = byte;
-    } else if (MATCHES(VRAM)) {
-        vram[address - VRAM_START] = byte;
-    } else if (MATCHES(OAM_OBJ_ATTR)) {
-        oam_obj_attr[address - OAM_OBJ_ATTR_START] = byte;
-    } else if (MATCHES(ROM_0)) {
-        rom[address - ROM_0_START] = byte;
-    } else if (MATCHES(ROM_1)) {
-        rom[address - ROM_1_START] = byte;
-    } else if (MATCHES(ROM_2)) {
-        rom[address - ROM_2_START] = byte;
-    } else {
-        glogger.error("Invalid memory region accessed");
-    }
-}
-
-#undef MATCHES
-
-void
-Memory::parse_header() {
-
-    if (rom.size() < header.HEADER_SIZE) {
-        throw std::out_of_range(
-          "ROM is not large enough to even have a header");
-    }
-
-    // entrypoint
-    header.entrypoint =
-      rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
-
-    // nintendo logo
-    if (rom[0x9C] != 0x21)
-        glogger.info("HEADER: BIOS debugger bits not set to 0");
-
-    // game info
-    header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
-
-    switch (rom[0xAC]) {
-        case 'A':
-            header.unique_code = Header::UniqueCode::Old;
-            break;
-        case 'B':
-            header.unique_code = Header::UniqueCode::New;
-            break;
-        case 'C':
-            header.unique_code = Header::UniqueCode::Newer;
-            break;
-        case 'F':
-            header.unique_code = Header::UniqueCode::Famicom;
-            break;
-        case 'K':
-            header.unique_code = Header::UniqueCode::YoshiKoro;
-            break;
-        case 'P':
-            header.unique_code = Header::UniqueCode::Ereader;
-            break;
-        case 'R':
-            header.unique_code = Header::UniqueCode::Warioware;
-            break;
-        case 'U':
-            header.unique_code = Header::UniqueCode::Boktai;
-            break;
-        case 'V':
-            header.unique_code = Header::UniqueCode::DrillDozer;
-            break;
-
-        default:
-            glogger.error("HEADER: invalid unique code: {}", rom[0xAC]);
-    }
-
-    header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
-
-    switch (rom[0xAF]) {
-        case 'J':
-            header.i18n = Header::I18n::Japan;
-            break;
-        case 'P':
-            header.i18n = Header::I18n::Europe;
-            break;
-        case 'F':
-            header.i18n = Header::I18n::French;
-            break;
-        case 'S':
-            header.i18n = Header::I18n::Spanish;
-            break;
-        case 'E':
-            header.i18n = Header::I18n::Usa;
-            break;
-        case 'D':
-            header.i18n = Header::I18n::German;
-            break;
-        case 'I':
-            header.i18n = Header::I18n::Italian;
-            break;
-
-        default:
-            glogger.error("HEADER: invalid destination/language: {}",
-                          rom[0xAF]);
-    }
-
-    if (rom[0xB2] != 0x96)
-        glogger.error("HEADER: invalid fixed byte at 0xB2");
-
-    for (size_t i = 0xB5; i < 0xBC; i++) {
-        if (rom[i] != 0x00)
-            glogger.error("HEADER: invalid fixed bytes at 0xB5");
-    }
-
-    header.version = rom[0xBC];
-
-    // checksum
-    {
-        size_t i = 0xA0, chk = 0;
-        while (i <= 0xBC)
-            chk -= rom[i++];
-        chk -= 0x19;
-        chk &= 0xFF;
-
-        if (chk != rom[0xBD])
-            glogger.error("HEADER: checksum does not match");
-    }
-
-    // multiboot not required right now
-}
-}

src/meson.build

@@ -1,27 +1,18 @@
 lib_sources = files(
-  'memory.cc',
-  'bus.cc'
+  'bus.cc',
 )
 
+if get_option('gdb_debug')
+  lib_sources += files('gdb_rsp.cc')
+endif
+
 subdir('util')
 subdir('cpu')
-
-lib_cpp_args = []
-
-fmt = dependency('fmt', version : '>=10.1.0', static: true)
-if not fmt.found()
-  fmt = dependency('fmt', version : '>=10.1.0', static: false)
-  lib_cpp_args += '-DFMT_HEADER_ONLY'
-endif
-
-if get_option('disassembler')
-  lib_cpp_args += '-DDISASSEMBLER'
-endif
+subdir('io')
 
 lib = library(
   meson.project_name(),
   lib_sources,
-  dependencies: [fmt],
   include_directories: inc,
   install: true,
   cpp_args: lib_cpp_args

src/util/bits.hh

@@ -35,6 +35,6 @@ inline Int
 bit_range(Int num, size_t start, size_t end) {
     // NOTE: we do not require -1 if it is a signed integral
     Int left =
-      std::numeric_limits<Int>::digits - (std::is_unsigned<Int>::value) - end;
+      std::numeric_limits<Int>::digits - (!std::is_signed<Int>::value) - end;
     return static_cast<Int>(num << left) >> (left + start);
 }

src/util/crypto.hh

@@ -2,7 +2,7 @@
 
 #include <array>
 #include <bit>
-#include <fmt/core.h>
+#include <format>
 #include <string>
 
 // Why I wrote this myself? I do not know
@@ -110,7 +110,7 @@ sha256(std::array<uint8_t, N>& data) {
 
     for (j = 0; j < 8; j++)
         for (i = 0; i < 4; i++)
-            fmt::format_to(std::back_inserter(string),
+            std::format_to(std::back_inserter(string),
                            "{:02x}",
                            ((h[j] >> (24 - i * 8)) & 0xFF));
 

src/util/log.hh

@@ -1,8 +1,7 @@
 #pragma once
 
 #include "util/loglevel.hh"
-#include <fmt/ostream.h>
-#include <iostream>
+#include <print>
 
 namespace logging {
 namespace ansi {
@@ -14,25 +13,25 @@ static constexpr auto BOLD    = "\033[1m";
 static constexpr auto RESET   = "\033[0m";
 }
 
-using fmt::print;
+using std::print;
 
 class Logger {
     using LogLevel = matar::LogLevel;
 
   public:
-    Logger(LogLevel level = LogLevel::Debug, FILE* stream = stderr)
+    Logger(LogLevel level = LogLevel::Debug, FILE* stream = stdout)
       : level(0)
       , stream(stream) {
         set_level(level);
     }
 
     template<typename... Args>
-    void log(const fmt::format_string<Args...>& fmt, Args&&... args) {
-        fmt::println(stream, fmt, std::forward<Args>(args)...);
+    void log(const std::format_string<Args...>& fmt, Args&&... args) {
+        std::println(stream, fmt, std::forward<Args>(args)...);
     }
 
     template<typename... Args>
-    void debug(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void debug(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Debug)) {
             print(stream, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
             log(fmt, std::forward<Args>(args)...);
@@ -41,7 +40,7 @@ class Logger {
     }
 
     template<typename... Args>
-    void info(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void info(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Info)) {
             print(stream, "{}[INFO] ", ansi::WHITE);
             log(fmt, std::forward<Args>(args)...);
@@ -50,7 +49,16 @@ class Logger {
     }
 
     template<typename... Args>
-    void warn(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void info_bold(const std::format_string<Args...>& fmt, Args&&... args) {
+        if (level & static_cast<uint8_t>(LogLevel::Info)) {
+            print(stream, "{}{}[INFO] ", ansi::WHITE, ansi::BOLD);
+            log(fmt, std::forward<Args>(args)...);
+            print(stream, ansi::RESET);
+        }
+    }
+
+    template<typename... Args>
+    void warn(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Warn)) {
             print(stream, "{}[WARN] ", ansi::YELLOW);
             log(fmt, std::forward<Args>(args)...);
@@ -59,7 +67,7 @@ class Logger {
     }
 
     template<typename... Args>
-    void error(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void error(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Error)) {
             print(stream, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
             log(fmt, std::forward<Args>(args)...);

src/util/meson.build

@@ -1,3 +1,8 @@
 lib_sources += files(
-  'log.cc'
+  'log.cc',
+  'tcp_server.cc'
 )
+
+if get_option('gdb_debug')
+  lib_sources += files('tcp_server.cc')
+endif

src/util/tcp_server.cc

@@ -0,0 +1,89 @@
+#include "tcp_server.hh"
+#include <netinet/tcp.h>
+
+#include <cstring>
+#include <format>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+namespace net {
+TcpServer::TcpServer()
+  : server_fd(0)
+  , client_fd(0) {}
+
+TcpServer::~TcpServer() {
+    close(server_fd);
+    close(client_fd);
+}
+
+bool
+TcpServer::client_waiting() {
+    int count = 0;
+    ioctl(client_fd, FIONREAD, &count);
+    return static_cast<bool>(count);
+}
+
+void
+TcpServer::run() {
+    socklen_t cli_addr_size = sizeof(client_addr);
+
+    client_fd = ::accept(
+      server_fd, reinterpret_cast<sockaddr*>(&client_addr), &cli_addr_size);
+
+    if (client_fd == -1)
+        throw std::runtime_error("accept failed");
+}
+
+void
+TcpServer::start(uint port) {
+    int opts  = 0;
+    server_fd = socket(PF_INET, SOCK_STREAM, 0);
+    if (server_fd == -1) {
+        throw std::runtime_error("creating socket failed");
+    }
+
+    int option = 1;
+
+    opts +=
+      setsockopt(server_fd, SOL_SOCKET, SO_REUSEADDR, &option, sizeof(option));
+    opts +=
+      setsockopt(server_fd, IPPROTO_TCP, TCP_NODELAY, &option, sizeof(option));
+
+    if (opts != 0) {
+        throw std::runtime_error("failed to set socket opts");
+    }
+
+    std::memset(&server_addr, 0, sizeof(server_addr));
+    server_addr.sin_family      = PF_INET;
+    server_addr.sin_addr.s_addr = htonl(INADDR_ANY);
+    server_addr.sin_port        = htons(port);
+
+    if (::bind(server_fd,
+               reinterpret_cast<sockaddr*>(&server_addr),
+               sizeof(server_addr)) == -1) {
+        throw std::runtime_error("binding socket failed");
+    }
+    if (::listen(server_fd, 1) == -1) {
+        throw std::runtime_error("listening failed");
+    }
+}
+
+void
+TcpServer::send(std::string msg) {
+    if (::send(client_fd, msg.data(), msg.length(), 0) == -1) {
+        throw std::runtime_error(
+          std::format("failed to send message: {}\n", strerror(errno)));
+    }
+}
+
+std::string
+TcpServer::receive(uint length) {
+    ssize_t num_bytes = recv(client_fd, msg, length, 0);
+    msg[num_bytes]    = '\0';
+    if (num_bytes < 0) {
+        throw std::runtime_error(
+          std::format("failed to receive messages: {}\n", strerror(errno)));
+    }
+    return std::string(msg);
+}
+}

src/util/tcp_server.hh

@@ -0,0 +1,28 @@
+#pragma once
+
+#include <netinet/in.h>
+#include <string>
+
+namespace net {
+
+class TcpServer {
+  public:
+    TcpServer();
+    ~TcpServer();
+
+    void run();
+    void start(uint port);
+    void send(std::string msg);
+    std::string receive(uint length);
+    std::string receive_all() { return receive(MAX_PACKET_SIZE); };
+    bool client_waiting();
+
+  private:
+    static constexpr uint MAX_PACKET_SIZE = 4096;
+    char msg[MAX_PACKET_SIZE];
+    int server_fd;
+    int client_fd;
+    sockaddr_in server_addr;
+    sockaddr_in client_addr;
+};
+}

tests/bus.cc

@@ -1,43 +1,128 @@
 #include "bus.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[bus]";
+#define TAG "[bus]"
 
 using namespace matar;
 
 class BusFixture {
   public:
     BusFixture()
-      : bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+      : bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
                       std::vector<uint8_t>(Header::HEADER_SIZE))) {}
 
   protected:
-    Bus bus;
+    std::shared_ptr<Bus> bus;
 };
 
-TEST_CASE_METHOD(BusFixture, "Byte", TAG) {
-    CHECK(bus.read_byte(3349) == 0);
+TEST_CASE("bios", TAG) {
+    std::array<uint8_t, Bus::BIOS_SIZE> bios = { 0 };
 
-    bus.write_byte(3349, 0xEC);
-    CHECK(bus.read_byte(3349) == 0xEC);
-    CHECK(bus.read_word(3349) == 0xEC);
-    CHECK(bus.read_halfword(3349) == 0xEC);
+    // populate bios
+    bios[0]      = 0xAC;
+    bios[0x3FFF] = 0x48;
+    bios[0x2A56] = 0x10;
+
+    auto bus =
+      Bus::init(std::move(bios), std::vector<uint8_t>(Header::HEADER_SIZE));
+
+    CHECK(bus->read_byte(0) == 0xAC);
+    CHECK(bus->read_byte(0x3FFF) == 0x48);
+    CHECK(bus->read_byte(0x2A56) == 0x10);
 }
 
-TEST_CASE_METHOD(BusFixture, "Halfword", TAG) {
-    CHECK(bus.read_halfword(33750745) == 0);
+TEST_CASE_METHOD(BusFixture, "board wram", TAG) {
+    bus->write_byte(0x2000000, 0xAC);
+    CHECK(bus->read_byte(0x2000000) == 0xAC);
 
-    bus.write_halfword(33750745, 0x1A4A);
-    CHECK(bus.read_halfword(33750745) == 0x1A4A);
-    CHECK(bus.read_word(33750745) == 0x1A4A);
-    CHECK(bus.read_byte(33750745) == 0x4A);
+    bus->write_byte(0x203FFFF, 0x48);
+    CHECK(bus->read_byte(0x203FFFF) == 0x48);
+
+    bus->write_byte(0x2022A56, 0x10);
+    CHECK(bus->read_byte(0x2022A56) == 0x10);
 }
 
-TEST_CASE_METHOD(BusFixture, "Word", TAG) {
-    CHECK(bus.read_word(100724276) == 0);
+TEST_CASE_METHOD(BusFixture, "chip wram", TAG) {
+    bus->write_byte(0x3000000, 0xAC);
+    CHECK(bus->read_byte(0x3000000) == 0xAC);
 
-    bus.write_word(100724276, 0x3ACC491D);
-    CHECK(bus.read_word(100724276) == 0x3ACC491D);
-    CHECK(bus.read_halfword(100724276) == 0x491D);
-    CHECK(bus.read_byte(100724276) == 0x1D);
+    bus->write_byte(0x3007FFF, 0x48);
+    CHECK(bus->read_byte(0x3007FFF) == 0x48);
+
+    bus->write_byte(0x3002A56, 0x10);
+    CHECK(bus->read_byte(0x3002A56) == 0x10);
 }
+
+TEST_CASE_METHOD(BusFixture, "palette ram", TAG) {
+    bus->write_byte(0x5000000, 0xAC);
+    CHECK(bus->read_byte(0x5000000) == 0xAC);
+
+    bus->write_byte(0x50003FF, 0x48);
+    CHECK(bus->read_byte(0x50003FF) == 0x48);
+
+    bus->write_byte(0x5000156, 0x10);
+    CHECK(bus->read_byte(0x5000156) == 0x10);
+}
+
+TEST_CASE_METHOD(BusFixture, "video ram", TAG) {
+    bus->write_byte(0x6000000, 0xAC);
+    CHECK(bus->read_byte(0x6000000) == 0xAC);
+
+    bus->write_byte(0x6017FFF, 0x48);
+    CHECK(bus->read_byte(0x6017FFF) == 0x48);
+
+    bus->write_byte(0x6012A56, 0x10);
+    CHECK(bus->read_byte(0x6012A56) == 0x10);
+}
+
+TEST_CASE_METHOD(BusFixture, "oam obj ram", TAG) {
+    bus->write_byte(0x7000000, 0xAC);
+    CHECK(bus->read_byte(0x7000000) == 0xAC);
+
+    bus->write_byte(0x70003FF, 0x48);
+    CHECK(bus->read_byte(0x70003FF) == 0x48);
+
+    bus->write_byte(0x7000156, 0x10);
+    CHECK(bus->read_byte(0x7000156) == 0x10);
+}
+
+TEST_CASE("rom", TAG) {
+    std::vector<uint8_t> rom(32 * 1024 * 1024, 0);
+
+    // populate rom
+    rom[0]         = 0xAC;
+    rom[0x1FFFFFF] = 0x48;
+    rom[0x0EF0256] = 0x10;
+
+    // 32 megabyte ROM
+    auto bus = Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(), std::move(rom));
+
+    SECTION("ROM1") {
+        CHECK(bus->read_byte(0x8000000) == 0xAC);
+        CHECK(bus->read_byte(0x9FFFFFF) == 0x48);
+        CHECK(bus->read_byte(0x8EF0256) == 0x10);
+    }
+
+    SECTION("ROM2") {
+        CHECK(bus->read_byte(0xA000000) == 0xAC);
+        CHECK(bus->read_byte(0xBFFFFFF) == 0x48);
+        CHECK(bus->read_byte(0xAEF0256) == 0x10);
+    }
+
+    SECTION("ROM3") {
+        CHECK(bus->read_byte(0xC000000) == 0xAC);
+        CHECK(bus->read_byte(0xDFFFFFF) == 0x48);
+        CHECK(bus->read_byte(0xCEF0256) == 0x10);
+    }
+}
+
+TEST_CASE_METHOD(BusFixture, "internal cycle", TAG) {
+    uint32_t cycles = bus->get_cycles();
+
+    bus->internal_cycle();
+    bus->internal_cycle();
+
+    CHECK(bus->get_cycles() == cycles + 2);
+}
+
+#undef TAG

tests/cpu/arm/instruction.cc

@@ -1,7 +1,7 @@
 #include "cpu/arm/instruction.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[arm][disassembly]";
+#define TAG "[arm][disassembly]"
 
 using namespace matar;
 using namespace arm;
@@ -31,15 +31,16 @@ TEST_CASE("Branch", TAG) {
 
     // last 24 bits = 8748995
     // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
-    // Also +8 since PC is two instructions ahead
-    CHECK(b->offset == 0xFE15FF14);
+    CHECK(b->offset == static_cast<int32_t>(0xfe15ff0c));
     CHECK(b->link == true);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "BL 0xFE15FF14");
+    // take prefetch into account
+    // offset + 8 = 0xfe15ff0c + 8 = -0x1ea00e4 + 8
+    CHECK(instruction.disassemble() == "BL -0x1ea00ec");
 
     b->link = false;
-    CHECK(instruction.disassemble() == "B 0xFE15FF14");
+    CHECK(instruction.disassemble() == "B -0x1ea00ec");
 #endif
 }
 
@@ -505,3 +506,5 @@ TEST_CASE("Software Interrupt", TAG) {
     CHECK(instruction.disassemble() == "SWIEQ");
 #endif
 }
+
+#undef TAG

tests/cpu/cpu-fixture.cc

@@ -0,0 +1,99 @@
+#include "cpu-fixture.hh"
+
+Psr
+CpuFixture::psr(bool spsr) {
+    uint32_t pc = getr(15);
+    Psr psr(0);
+    Cpu tmp = cpu;
+    arm::Instruction instruction(
+      Condition::AL,
+      arm::PsrTransfer{ .operand = 0,
+                        .spsr    = spsr,
+                        .type    = arm::PsrTransfer::Type::Mrs,
+                        .imm     = false });
+
+    tmp.exec(instruction);
+
+    psr.set_all(getr_(0, tmp));
+
+    // reset pc
+    setr(15, pc);
+    return psr;
+}
+
+void
+CpuFixture::set_psr(Psr psr, bool spsr) {
+    uint32_t pc  = getr(15);
+    uint32_t old = getr(0);
+    setr(0, psr.raw());
+
+    arm::Instruction instruction(
+      Condition::AL,
+      arm::PsrTransfer{ .operand = 0,
+                        .spsr    = spsr,
+                        .type    = arm::PsrTransfer::Type::Msr,
+                        .imm     = false });
+
+    cpu.exec(instruction);
+
+    setr(0, old);
+
+    // reset PC
+    setr(15, pc);
+}
+
+// We need these workarounds to just use the public API and not private
+// fields. Assuming that these work correctly is necessary. Besides, all that
+// matters is that the public API is correct.
+uint32_t
+CpuFixture::getr_(uint8_t r, Cpu tmp) {
+    uint32_t addr = 0x02000000;
+    uint32_t word = bus->read_word(addr);
+    uint32_t ret  = 0xFFFFFFFF;
+    uint8_t base  = r ? 0 : 1;
+
+    // set R0/R1 = addr
+    arm::Instruction zero(
+      Condition::AL,
+      arm::DataProcessing{ .operand = addr,
+                           .rd      = base,
+                           .rn      = 0,
+                           .set     = false,
+                           .opcode  = arm::DataProcessing::OpCode::MOV });
+
+    // get register
+    arm::Instruction get(
+      Condition::AL,
+      arm::SingleDataTransfer{ .offset = static_cast<uint16_t>(0),
+                               .rd     = r,
+                               .rn     = base,
+                               .load   = false,
+                               .write  = false,
+                               .byte   = false,
+                               .up     = true,
+                               .pre    = true });
+
+    tmp.exec(zero);
+    tmp.exec(get);
+
+    ret = bus->read_word(addr);
+
+    bus->write_word(addr, word);
+
+    return ret - (r == 15 ? 4 : 0); // +4 for rd = 15 in str
+}
+
+void
+CpuFixture::setr_(uint8_t r, uint32_t value, Cpu& cpu) {
+    // set register
+    arm::Instruction set(
+      Condition::AL,
+      arm::DataProcessing{
+        .operand = (r == 15 ? value - 8 : value), // account for pipeline flush
+        .rd      = r,
+        .rn      = 0,
+        .set     = false,
+        .opcode  = arm::DataProcessing::OpCode::MOV });
+
+    cpu.exec(set);
+}

tests/cpu/cpu-fixture.hh

@@ -0,0 +1,71 @@
+#include "cpu/cpu.hh"
+
+using namespace matar;
+
+class CpuFixture {
+  public:
+    CpuFixture()
+      : bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
+                      std::vector<uint8_t>(Header::HEADER_SIZE)))
+      , cpu(bus) {}
+
+  protected:
+    void exec(arm::InstructionData data, Condition condition = Condition::AL) {
+        // hack to account for one fetch cycle
+        bus->internal_cycle();
+
+        arm::Instruction instruction(condition, data);
+        cpu.exec(instruction);
+    }
+
+    void exec(thumb::InstructionData data) {
+        // hack to account for one fetch cycle
+        bus->internal_cycle();
+
+        thumb::Instruction instruction(data);
+        cpu.exec(instruction);
+    }
+
+    void reset(uint32_t value = 0) { setr(15, value + 8); }
+
+    uint32_t getr(uint8_t r) {
+        uint32_t pc = 0;
+
+        if (r != 15)
+            pc = getr_(15, cpu);
+
+        uint32_t ret = getr_(r, cpu);
+
+        if (r == 15)
+            pc = ret;
+
+        // undo PC advance
+        setr_(15, pc, cpu);
+
+        return ret;
+    }
+
+    void setr(uint8_t r, uint32_t value) {
+        uint32_t pc = getr_(15, cpu);
+        setr_(r, value, cpu);
+
+        // undo PC advance when r != 15
+        // when r is 15, setr_ takes account of pipeline flush
+        if (r != 15)
+            setr_(15, pc, cpu);
+    }
+
+    Psr psr(bool spsr = false);
+
+    void set_psr(Psr psr, bool spsr = false);
+
+    std::shared_ptr<Bus> bus;
+    Cpu cpu;
+
+  private:
+    // hack to get a register
+    uint32_t getr_(uint8_t r, Cpu tmp);
+
+    // hack to set a register
+    void setr_(uint8_t r, uint32_t value, Cpu& cpu);
+};

tests/cpu/meson.build

@@ -1,2 +1,6 @@
+tests_sources += files(
+  'cpu-fixture.cc'
+)
+
 subdir('arm')
 subdir('thumb')

tests/cpu/thumb/instruction.cc

@@ -1,7 +1,7 @@
 #include "cpu/thumb/instruction.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[thumb][disassembly]";
+#define TAG "[thumb][disassembly]"
 
 using namespace matar;
 using namespace thumb;
@@ -178,11 +178,12 @@ TEST_CASE("PC Relative Load", TAG) {
     PcRelativeLoad* ldr = nullptr;
 
     REQUIRE((ldr = std::get_if<PcRelativeLoad>(&instruction.data)));
-    CHECK(ldr->word == 230);
+    // 230 << 2
+    CHECK(ldr->word == 920);
     CHECK(ldr->rd == 2);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "LDR R2,[PC,#230]");
+    CHECK(instruction.disassemble() == "LDR R2,[PC,#920]");
 #endif
 }
 
@@ -247,21 +248,32 @@ TEST_CASE("Load/Store with Immediate Offset", TAG) {
     REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
     CHECK(ldr->rd == 5);
     CHECK(ldr->rb == 3);
-    CHECK(ldr->offset == 22);
+    // 22 << 4 when byte == false
+    CHECK(ldr->offset == 88);
     CHECK(ldr->byte == false);
     CHECK(ldr->load == false);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "STR R5,[R3,#22]");
+    CHECK(instruction.disassemble() == "STR R5,[R3,#88]");
 
-    ldr->byte = true;
+    ldr->load = true;
+    CHECK(instruction.disassemble() == "LDR R5,[R3,#88]");
+#endif
+
+    // byte
+    raw         = 0b0111010110011101;
+    instruction = Instruction(raw);
+
+    INFO(instruction.data.index());
+    REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
+    CHECK(ldr->byte == true);
+    CHECK(ldr->offset == 22);
+
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "STRB R5,[R3,#22]");
 
     ldr->load = true;
     CHECK(instruction.disassemble() == "LDRB R5,[R3,#22]");
-
-    ldr->byte = false;
-    CHECK(instruction.disassemble() == "LDR R5,[R3,#22]");
 #endif
 }
 
@@ -273,14 +285,15 @@ TEST_CASE("Load/Store Halfword", TAG) {
     REQUIRE((ldr = std::get_if<LoadStoreHalfword>(&instruction.data)));
     CHECK(ldr->rd == 5);
     CHECK(ldr->rb == 3);
-    CHECK(ldr->offset == 26);
+    // 26 << 1
+    CHECK(ldr->offset == 52);
     CHECK(ldr->load == false);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "STRH R5,[R3,#26]");
+    CHECK(instruction.disassemble() == "STRH R5,[R3,#52]");
 
     ldr->load = true;
-    CHECK(instruction.disassemble() == "LDRH R5,[R3,#26]");
+    CHECK(instruction.disassemble() == "LDRH R5,[R3,#52]");
 #endif
 }
 
@@ -291,14 +304,15 @@ TEST_CASE("SP-Relative Load/Store", TAG) {
 
     REQUIRE((ldr = std::get_if<SpRelativeLoad>(&instruction.data)));
     CHECK(ldr->rd == 4);
-    CHECK(ldr->word == 157);
+    // 157 << 2
+    CHECK(ldr->word == 628);
     CHECK(ldr->load == false);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "STR R4,[SP,#157]");
+    CHECK(instruction.disassemble() == "STR R4,[SP,#628]");
 
     ldr->load = true;
-    CHECK(instruction.disassemble() == "LDR R4,[SP,#157]");
+    CHECK(instruction.disassemble() == "LDR R4,[SP,#628]");
 #endif
 }
 
@@ -308,15 +322,16 @@ TEST_CASE("Load Adress", TAG) {
     LoadAddress* add = nullptr;
 
     REQUIRE((add = std::get_if<LoadAddress>(&instruction.data)));
-    CHECK(add->word == 143);
+    // 143 << 2
+    CHECK(add->word == 572);
     CHECK(add->rd == 1);
     CHECK(add->sp == false);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "ADD R1,PC,#143");
+    CHECK(instruction.disassemble() == "ADD R1,PC,#572");
 
     add->sp = true;
-    CHECK(instruction.disassemble() == "ADD R1,SP,#143");
+    CHECK(instruction.disassemble() == "ADD R1,SP,#572");
 #endif
 }
 
@@ -326,14 +341,21 @@ TEST_CASE("Add Offset to Stack Pointer", TAG) {
     AddOffsetStackPointer* add = nullptr;
 
     REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
-    CHECK(add->word == 37);
-    CHECK(add->sign == false);
+    // 37 << 2
+    CHECK(add->word == 148);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "ADD SP,#+37");
+    CHECK(instruction.disassemble() == "ADD SP,#148");
+#endif
 
-    add->sign = true;
-    CHECK(instruction.disassemble() == "ADD SP,#-37");
+    raw         = 0b1011000010100101;
+    instruction = Instruction(raw);
+
+    REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
+    CHECK(add->word == -148);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "ADD SP,#-148");
 #endif
 }
 
@@ -380,17 +402,19 @@ TEST_CASE("Multiple Load/Store", TAG) {
 }
 
 TEST_CASE("Conditional Branch", TAG) {
-    uint16_t raw = 0b1101100101110100;
+    uint16_t raw = 0b1101100110110100;
     Instruction instruction(raw);
     ConditionalBranch* b = nullptr;
 
     REQUIRE((b = std::get_if<ConditionalBranch>(&instruction.data)));
-    // 116 << 2
-    CHECK(b->offset == 232);
+    // (-76 << 1)
+    CHECK(b->offset == -152);
     CHECK(b->condition == Condition::LS);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "BLS 232");
+    // take prefetch into account
+    // offset + 4 = -152 + 4
+    CHECK(instruction.disassemble() == "BLS #-148");
 #endif
 }
 
@@ -402,7 +426,7 @@ TEST_CASE("SoftwareInterrupt") {
     REQUIRE((swi = std::get_if<SoftwareInterrupt>(&instruction.data)));
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "SWI");
+    CHECK(instruction.disassemble() == "SWI 51");
 #endif
 }
 
@@ -412,28 +436,32 @@ TEST_CASE("Unconditional Branch") {
     UnconditionalBranch* b = nullptr;
 
     REQUIRE((b = std::get_if<UnconditionalBranch>(&instruction.data)));
-    // 1843 << 2
-    REQUIRE(b->offset == 3686);
+    // (2147483443 << 1)
+    REQUIRE(b->offset == -410);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "B 3686");
+    // take prefetch into account
+    // offset + 4 = -410 + 4
+    CHECK(instruction.disassemble() == "B #-406");
 #endif
 }
 
 TEST_CASE("Long Branch with link") {
-    uint16_t raw = 0b1111010011101100;
+    uint16_t raw = 0b1111110011101100;
     Instruction instruction(raw);
     LongBranchWithLink* bl = nullptr;
 
     REQUIRE((bl = std::get_if<LongBranchWithLink>(&instruction.data)));
     // 1260 << 1
-    CHECK(bl->offset == 2520);
-    CHECK(bl->high == false);
+    CHECK(bl->offset == 1260);
+    CHECK(bl->low == true);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "BL 2520");
+    CHECK(instruction.disassemble() == "BL #1260");
 
-    bl->high = true;
-    CHECK(instruction.disassemble() == "BLH 2520");
+    bl->low = false;
+    CHECK(instruction.disassemble() == "BLH #1260");
 #endif
 }
+
+#undef TAG

tests/cpu/thumb/meson.build

@@ -1,3 +1,4 @@
 tests_sources += files(
-  'instruction.cc'
+  'instruction.cc',
+  'exec.cc'
 )

tests/memory.cc

@@ -1,121 +0,0 @@
-#include "memory.hh"
-#include <catch2/catch_test_macros.hpp>
-
-static constexpr auto TAG = "[memory]";
-
-using namespace matar;
-
-class MemFixture {
-  public:
-    MemFixture()
-      : memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
-               std::vector<uint8_t>(Header::HEADER_SIZE)) {}
-
-  protected:
-    Memory memory;
-};
-
-TEST_CASE_METHOD(MemFixture, "bios", TAG) {
-    memory.write(0, 0xAC);
-    CHECK(memory.read(0) == 0xAC);
-
-    memory.write(0x3FFF, 0x48);
-    CHECK(memory.read(0x3FFF) == 0x48);
-
-    memory.write(0x2A56, 0x10);
-    CHECK(memory.read(0x2A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "board wram", TAG) {
-    memory.write(0x2000000, 0xAC);
-    CHECK(memory.read(0x2000000) == 0xAC);
-
-    memory.write(0x203FFFF, 0x48);
-    CHECK(memory.read(0x203FFFF) == 0x48);
-
-    memory.write(0x2022A56, 0x10);
-    CHECK(memory.read(0x2022A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "chip wram", TAG) {
-    memory.write(0x3000000, 0xAC);
-    CHECK(memory.read(0x3000000) == 0xAC);
-
-    memory.write(0x3007FFF, 0x48);
-    CHECK(memory.read(0x3007FFF) == 0x48);
-
-    memory.write(0x3002A56, 0x10);
-    CHECK(memory.read(0x3002A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "palette ram", TAG) {
-    memory.write(0x5000000, 0xAC);
-    CHECK(memory.read(0x5000000) == 0xAC);
-
-    memory.write(0x50003FF, 0x48);
-    CHECK(memory.read(0x50003FF) == 0x48);
-
-    memory.write(0x5000156, 0x10);
-    CHECK(memory.read(0x5000156) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "video ram", TAG) {
-    memory.write(0x6000000, 0xAC);
-    CHECK(memory.read(0x6000000) == 0xAC);
-
-    memory.write(0x6017FFF, 0x48);
-    CHECK(memory.read(0x6017FFF) == 0x48);
-
-    memory.write(0x6012A56, 0x10);
-    CHECK(memory.read(0x6012A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "oam obj ram", TAG) {
-    memory.write(0x7000000, 0xAC);
-    CHECK(memory.read(0x7000000) == 0xAC);
-
-    memory.write(0x70003FF, 0x48);
-    CHECK(memory.read(0x70003FF) == 0x48);
-
-    memory.write(0x7000156, 0x10);
-    CHECK(memory.read(0x7000156) == 0x10);
-}
-
-TEST_CASE("rom", TAG) {
-    // 32 megabyte ROM
-    Memory memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
-                  std::vector<uint8_t>(32 * 1024 * 1024));
-
-    SECTION("ROM1") {
-        memory.write(0x8000000, 0xAC);
-        CHECK(memory.read(0x8000000) == 0xAC);
-
-        memory.write(0x9FFFFFF, 0x48);
-        CHECK(memory.read(0x9FFFFFF) == 0x48);
-
-        memory.write(0x8ef0256, 0x10);
-        CHECK(memory.read(0x8ef0256) == 0x10);
-    }
-
-    SECTION("ROM2") {
-        memory.write(0xA000000, 0xAC);
-        CHECK(memory.read(0xA000000) == 0xAC);
-
-        memory.write(0xBFFFFFF, 0x48);
-        CHECK(memory.read(0xBFFFFFF) == 0x48);
-
-        memory.write(0xAEF0256, 0x10);
-        CHECK(memory.read(0xAEF0256) == 0x10);
-    }
-
-    SECTION("ROM3") {
-        memory.write(0xC000000, 0xAC);
-        CHECK(memory.read(0xC000000) == 0xAC);
-
-        memory.write(0xDFFFFFF, 0x48);
-        CHECK(memory.read(0xDFFFFFF) == 0x48);
-
-        memory.write(0xCEF0256, 0x10);
-        CHECK(memory.read(0xCEF0256) == 0x10);
-    }
-}

tests/meson.build

@@ -6,19 +6,14 @@ src = include_directories('../src')
 
 tests_sources = files(
   'main.cc',
-  'bus.cc',
-  'memory.cc'
+  'bus.cc'
 )
 
+tests_cpp_args = lib_cpp_args
+
 subdir('cpu')
 subdir('util')
 
-tests_cpp_args = []
-
-if get_option('disassembler')
-  tests_cpp_args += '-DDISASSEMBLER'
-endif
-
 catch2 = dependency('catch2', version: '>=3.4.0', static: true)
 catch2_tests = executable(
   'matar_tests',

tests/util/bits.cc

@@ -1,7 +1,7 @@
 #include "util/bits.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[util][bits]";
+#define TAG "[util][bits]"
 
 TEST_CASE("8 bits", TAG) {
     uint8_t num = 45;
@@ -104,3 +104,5 @@ TEST_CASE("64 bits", TAG) {
     // 0b011010001
     CHECK(bit_range(num, 39, 47) == 209);
 }
+
+#undef TAG

tests/util/crypto.cc

@@ -1,7 +1,7 @@
 #include "util/crypto.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[util][crypto]";
+#define TAG "[util][crypto]"
 
 TEST_CASE("sha256 matar", TAG) {
     std::array<uint8_t, 5> data = { 'm', 'a', 't', 'a', 'r' };
@@ -19,3 +19,5 @@ TEST_CASE("sha256 forgis", TAG) {
     CHECK(crypto::sha256(data) ==
           "cfddca2ce2673f355518cbe2df2a8522693c54723a469e8b36a4f68b90d2b759");
 }
+
+#undef TAG