nix: add support to build with GCC

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

.clang-tidy

@@ -5,4 +5,5 @@ Checks: '
   , -cppcoreguidelines-pro-bounds-constant-array-index
   , -cppcoreguidelines-macro-usage
   , -cppcoreguidelines-avoid-const-or-ref-data-members
+  , -cppcoreguidelines-non-private-member-variables-in-classes
 '

.envrc

@@ -1 +1 @@
-use flake
+use flake .#matar-clang

.github/workflows/clang.yml

@@ -0,0 +1,36 @@
+name: matar-clang
+on: [push, pull_request, workflow_dispatch]
+
+env:
+  BUILDDIR: build
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - uses: cachix/install-nix-action@v20
+        with:
+          extra_nix_config: |
+            auto-optimise-store = true
+            experimental-features = nix-command flakes
+      - uses: cachix/cachix-action@v12
+        with:
+          name: pain
+          authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
+
+
+      - name: setup
+        run: nix develop .#matar-clang -c meson setup $BUILDDIR
+
+      - name: fmt
+        run: nix develop .#matar-clang -c ninja clang-format-check -C $BUILDDIR
+
+      - name: lint
+        run: nix develop .#matar-clang -c ninja clang-tidy -C $BUILDDIR
+
+      - name: tests
+        run: nix develop .#matar-clang -c ninja test -C $BUILDDIR
+
+      - name: build
+        run: nix develop .#matar-clang -c ninja -C $BUILDDIR

.github/workflows/gcc.yml

@@ -1,4 +1,4 @@
-name: matar
+name: matar-gcc
 on: [push, pull_request, workflow_dispatch]
 
 env:
@@ -14,18 +14,17 @@ jobs:
           extra_nix_config: |
             auto-optimise-store = true
             experimental-features = nix-command flakes
+      - uses: cachix/cachix-action@v12
+        with:
+          name: pain
+          authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
+
 
       - name: setup
-        run: nix develop -c meson setup $BUILDDIR
-
-      - name: fmt
-        run: nix develop -c ninja clang-format-check -C $BUILDDIR
-
-      - name: lint
-        run: nix develop -c ninja clang-tidy -C $BUILDDIR
+        run: nix develop .#matar -c meson setup $BUILDDIR
 
       - name: tests
-        run: nix develop -c ninja test -C $BUILDDIR
+        run: nix develop .#matar -c ninja test -C $BUILDDIR
 
       - name: build
-        run: nix develop -c ninja -C $BUILDDIR
+        run: nix develop .#matar -c ninja -C $BUILDDIR

apps/target/main.cc

@@ -15,7 +15,7 @@
 int
 main(int argc, const char* argv[]) {
     std::vector<uint8_t> rom;
-    std::array<uint8_t, Memory::BIOS_SIZE> bios = { 0 };
+    std::array<uint8_t, matar::Memory::BIOS_SIZE> bios = { 0 };
 
     auto usage = [argv]() {
         std::cerr << "Usage: " << argv[0] << " <file> [-b <bios>]" << std::endl;
@@ -65,7 +65,7 @@ main(int argc, const char* argv[]) {
         ifile.seekg(0, std::ios::end);
         bios_size = ifile.tellg();
 
-        if (bios_size != Memory::BIOS_SIZE) {
+        if (bios_size != matar::Memory::BIOS_SIZE) {
             throw std::ios::failure("BIOS file has invalid size",
                                     std::error_code());
         }
@@ -82,17 +82,21 @@ main(int argc, const char* argv[]) {
     }
 
     std::flush(std::cout);
-    std::flush(std::cerr);
+    std::flush(std::cout);
 
-    {
-        Memory memory(std::move(bios), std::move(rom));
-        Bus bus(memory);
-        Cpu cpu(bus);
+    try {
+        matar::Memory memory(std::move(bios), std::move(rom));
+        matar::Bus bus(memory);
+        matar::Cpu cpu(bus);
         while (true) {
             cpu.step();
-            sleep(1);
+            sleep(2);
         }
+    } catch (const std::exception& e) {
+        std::cerr << "Exception: " << e.what() << std::endl;
+        return 1;
     }
+
     return 0;
 }
 

apps/target/meson.build

@@ -7,7 +7,7 @@ target_sources = files(
 )
 
 executable(
-  meson.project_name(),
+  'matar',
   target_sources,
   link_with: target_deps,
   include_directories: inc,

flake.lock

@@ -1,23 +1,60 @@
 {
   "nodes": {
+    "flake-parts": {
+      "inputs": {
+        "nixpkgs-lib": "nixpkgs-lib"
+      },
+      "locked": {
+        "lastModified": 1693611461,
+        "narHash": "sha256-aPODl8vAgGQ0ZYFIRisxYG5MOGSkIczvu2Cd8Gb9+1Y=",
+        "owner": "hercules-ci",
+        "repo": "flake-parts",
+        "rev": "7f53fdb7bdc5bb237da7fefef12d099e4fd611ca",
+        "type": "github"
+      },
+      "original": {
+        "owner": "hercules-ci",
+        "repo": "flake-parts",
+        "type": "github"
+      }
+    },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1694911158,
-        "narHash": "sha256-5WENkcO8O5SuA5pozpVppLGByWfHVv/1wOWgB2+TfV4=",
+        "lastModified": 1695318763,
+        "narHash": "sha256-FHVPDRP2AfvsxAdc+AsgFJevMz5VBmnZglFUMlxBkcY=",
         "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "46423a1a750594236673c1d741def4e93cf5a8f7",
+        "rev": "e12483116b3b51a185a33a272bf351e357ba9a99",
         "type": "github"
       },
       "original": {
         "owner": "nixos",
-        "ref": "master",
+        "ref": "nixpkgs-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "nixpkgs-lib": {
+      "locked": {
+        "dir": "lib",
+        "lastModified": 1693471703,
+        "narHash": "sha256-0l03ZBL8P1P6z8MaSDS/MvuU8E75rVxe5eE1N6gxeTo=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "3e52e76b70d5508f3cec70b882a29199f4d1ee85",
+        "type": "github"
+      },
+      "original": {
+        "dir": "lib",
+        "owner": "NixOS",
+        "ref": "nixos-unstable",
         "repo": "nixpkgs",
         "type": "github"
       }
     },
     "root": {
       "inputs": {
+        "flake-parts": "flake-parts",
         "nixpkgs": "nixpkgs"
       }
     }

flake.nix

@@ -2,80 +2,39 @@
   description = "matar";
 
   inputs = {
-    nixpkgs.url = github:nixos/nixpkgs/master;
+    nixpkgs.url = github:nixos/nixpkgs/nixpkgs-unstable;
+    flake-parts.url = github:hercules-ci/flake-parts;
   };
 
-  outputs = { self, nixpkgs }:
-    let
+  outputs = inputs@{ self, nixpkgs, flake-parts }:
+    flake-parts.lib.mkFlake { inherit inputs; } {
+
       systems = [
         "x86_64-linux"
         "aarch64-linux"
       ];
 
-      eachSystem = with nixpkgs.lib; f: foldAttrs mergeAttrs { }
-        (map (s: mapAttrs (_: v: { ${s} = v; }) (f s)) systems);
-    in
-    eachSystem (system:
-      let
-        pkgs = import nixpkgs { inherit system; };
+      imports = [
+        ./nix
+      ];
 
-        # aliases
-        llvm = pkgs.llvmPackages_16;
-        stdenv = llvm.libcxxStdenv;
+      perSystem = { self', system, ... }:
+        let
+          pkgs = import nixpkgs { inherit system; };
 
-
-        # TODO: this is ugly
-        #dependencies
-        nativeBuildInputs = with pkgs;
-          [
-            meson
-            ninja
-
-            # libraries
-            pkg-config
-            cmake
-
-            ((pkgs.fmt.override {
-              inherit stdenv;
-              enableShared = false;
-            }).overrideAttrs (oa: {
-              cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
-            })).dev
-            (catch2_3.override { inherit stdenv; }).out
+          src = pkgs.lib.sourceFilesBySuffices ./. [
+            ".hh"
+            ".cc"
+            ".build"
+            "meson_options.txt"
           ];
-      in
-      rec {
-        packages = rec {
-          inherit (llvm) libcxxabi;
-          matar = stdenv.mkDerivation rec {
-            name = "matar";
-            version = "0.1";
-            src = pkgs.lib.sourceFilesBySuffices ./. [
-              ".hh"
-              ".cc"
-              ".build"
-              "meson_options.txt"
-            ];
-            outputs = [ "out" "dev" ];
-
-            inherit nativeBuildInputs;
-
-            enableParallelBuilding = true;
+        in
+        rec {
+          _module.args = {
+            inherit src pkgs;
           };
-          default = matar;
-        };
 
-        devShells = rec {
-          matar = pkgs.mkShell.override { inherit stdenv; } {
-            name = "matar";
-            packages = nativeBuildInputs ++ (with pkgs; [
-              # lsp
-              clang-tools_16
-            ]);
-          };
-          default = matar;
+          formatter = pkgs.nixpkgs-fmt;
         };
-
-        formatter = pkgs.nixpkgs-fmt;
-      });
+    };
 }

include/bus.hh

@@ -3,9 +3,10 @@
 #include "memory.hh"
 #include <memory>
 
+namespace matar {
 class Bus {
   public:
-    Bus(Memory& memory);
+    Bus(const Memory& memory);
 
     uint8_t read_byte(size_t address);
     void write_byte(size_t address, uint8_t byte);
@@ -19,3 +20,4 @@ class Bus {
   private:
     std::shared_ptr<Memory> memory;
 };
+}

include/cpu/cpu.hh

@@ -1,58 +1,21 @@
-#pragma once
-
 #include "bus.hh"
-#include "instruction.hh"
-#include "psr.hh"
 
-#include <cstdint>
-
-using std::size_t;
+namespace matar {
+class CpuImpl;
 
 class Cpu {
   public:
-    Cpu(Bus& bus);
+    Cpu(const Bus& bus) noexcept;
+    Cpu(const Cpu&)            = delete;
+    Cpu(Cpu&&)                 = delete;
+    Cpu& operator=(const Cpu&) = delete;
+    Cpu& operator=(Cpu&&)      = delete;
+
+    ~Cpu();
+
     void step();
 
   private:
-    static constexpr uint8_t GPR_COUNT = 16;
-
-    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
-    static constexpr uint8_t GPR_SVC_FIRST     = 13;
-    static constexpr uint8_t GPR_ABT_FIRST     = 13;
-    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
-    static constexpr uint8_t GPR_UND_FIRST     = 13;
-    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
-
-    std::shared_ptr<Bus> bus;
-    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
-
-    Psr cpsr; // current program status register
-    Psr spsr; // status program status register
-
-    static constexpr uint8_t PC_INDEX = 15;
-    uint32_t& pc                      = gpr[PC_INDEX];
-
-    bool is_flushed;
-
-    void chg_mode(const Mode to);
-    void exec_arm(const arm::Instruction instruction);
-
-    struct {
-        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
-        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
-        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
-        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
-        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
-
-        // visible registers before the mode switch
-        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
-    } gpr_banked; // banked general purpose registers
-
-    struct {
-        Psr fiq;
-        Psr svc;
-        Psr abt;
-        Psr irq;
-        Psr und;
-    } spsr_banked; // banked saved program status registers
+    std::unique_ptr<CpuImpl> impl;
 };
+}

include/cpu/meson.build

@@ -1,6 +1,3 @@
 headers += files(
   'cpu.hh',
-  'instruction.hh',
-  'psr.hh',
-  'utility.hh'
 )

include/cpu/utility.hh

@@ -1,99 +0,0 @@
-#pragma once
-
-#include <fmt/ostream.h>
-#include <ostream>
-
-static constexpr size_t ARM_INSTRUCTION_SIZE   = 4;
-static constexpr size_t THUMB_INSTRUCTION_SIZE = 2;
-
-enum class Mode {
-    /* M[4:0] in PSR */
-    User       = 0b10000,
-    Fiq        = 0b10001,
-    Irq        = 0b10010,
-    Supervisor = 0b10011,
-    Abort      = 0b10111,
-    Undefined  = 0b11011,
-    System     = 0b11111,
-};
-
-enum class State {
-    Arm   = 0,
-    Thumb = 1
-};
-
-enum class Condition {
-    EQ = 0b0000,
-    NE = 0b0001,
-    CS = 0b0010,
-    CC = 0b0011,
-    MI = 0b0100,
-    PL = 0b0101,
-    VS = 0b0110,
-    VC = 0b0111,
-    HI = 0b1000,
-    LS = 0b1001,
-    GE = 0b1010,
-    LT = 0b1011,
-    GT = 0b1100,
-    LE = 0b1101,
-    AL = 0b1110
-};
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const Condition cond);
-template<>
-struct fmt::formatter<Condition> : ostream_formatter {};
-
-enum class OpCode {
-    AND = 0b0000,
-    EOR = 0b0001,
-    SUB = 0b0010,
-    RSB = 0b0011,
-    ADD = 0b0100,
-    ADC = 0b0101,
-    SBC = 0b0110,
-    RSC = 0b0111,
-    TST = 0b1000,
-    TEQ = 0b1001,
-    CMP = 0b1010,
-    CMN = 0b1011,
-    ORR = 0b1100,
-    MOV = 0b1101,
-    BIC = 0b1110,
-    MVN = 0b1111
-};
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const OpCode cond);
-template<>
-struct fmt::formatter<OpCode> : ostream_formatter {};
-
-enum class ShiftType {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11
-};
-
-struct ShiftData {
-    ShiftType type;
-    bool immediate;
-    uint8_t operand;
-};
-
-struct Shift {
-    uint8_t rm;
-    ShiftData data;
-};
-
-uint32_t
-eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const ShiftType cond);
-template<>
-struct fmt::formatter<ShiftType> : ostream_formatter {};

include/header.hh

@@ -3,7 +3,10 @@
 #include <cstdint>
 #include <string>
 
+namespace matar {
 struct Header {
+    static constexpr uint8_t HEADER_SIZE = 192;
+
     enum class UniqueCode {
         Old,        // old games
         New,        // new games
@@ -42,3 +45,4 @@ struct Header {
     uint32_t multiboot_entrypoint;
     uint8_t slave_id;
 };
+}

include/memory.hh

@@ -4,14 +4,15 @@
 #include <array>
 #include <cstddef>
 #include <cstdint>
+#include <unordered_map>
 #include <vector>
 
+namespace matar {
 class Memory {
   public:
     static constexpr size_t BIOS_SIZE = 1024 * 16;
 
-    Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-           std::vector<uint8_t>&& rom) noexcept;
+    Memory(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
 
     uint8_t read(size_t address) const;
     void write(size_t address, uint8_t byte);
@@ -58,7 +59,9 @@ class Memory {
 
 #undef MEMORY_REGION
 
+    std::unordered_map<size_t, uint8_t> invalid_mem;
     std::vector<uint8_t> rom;
     Header header;
     void parse_header();
 };
+}

include/meson.build

@@ -4,6 +4,8 @@ headers = files(
   'header.hh',
 )
 
+inc = include_directories('.')
+
 subdir('cpu')
 
 install_headers(headers, subdir: meson.project_name(), preserve_path: true)

meson.build

@@ -30,8 +30,6 @@ else
 endif
 '''
 
-inc = include_directories('include')
-
 subdir('include')
 subdir('src')
 subdir('apps')

nix/build.nix

@@ -0,0 +1,23 @@
+{ stdenv
+, meson
+, ninja
+, pkg-config
+, src ? "../."
+, libraries ? [ ]
+}:
+
+stdenv.mkDerivation {
+  name = "matar";
+  version = "0.1";
+  inherit src;
+
+  outputs = [ "out" "dev" ];
+
+  nativeBuildInputs = [
+    meson
+    ninja
+    pkg-config
+  ] ++ libraries;
+
+  enableParallelBuilding = true;
+}

nix/default.nix

@@ -0,0 +1,11 @@
+{ ... }: {
+  imports = [
+    ./matar.nix
+    ./matar-clang.nix
+  ];
+
+  perSystem = { self', pkgs, ... }: {
+    packages.default = self'.packages.matar-clang;
+    devShells.default = self'.devShells.matar-clang;
+  };
+}

nix/matar-clang.nix

@@ -0,0 +1,25 @@
+{ ... }: {
+  perSystem = { pkgs, src, ... }:
+    let
+      llvm = pkgs.llvmPackages_16;
+      stdenv = llvm.libcxxStdenv;
+
+      libraries = with pkgs; [
+        ((pkgs.fmt.override {
+          inherit stdenv;
+          enableShared = false;
+        }).overrideAttrs (oa: {
+          cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
+        })).dev
+
+        (catch2_3.override { inherit stdenv; }).out
+      ];
+    in
+    {
+      packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
+      devShells.matar-clang = pkgs.callPackage ./shell.nix {
+        inherit libraries stdenv;
+        tools = with pkgs; [ clang-tools_16 ];
+      };
+    };
+}

nix/matar.nix

@@ -0,0 +1,13 @@
+{ ... }: {
+  perSystem = { pkgs, src, ... }:
+    let
+      libraries = with pkgs; [
+        (pkgs.fmt.override { enableShared = false; }).dev
+        catch2_3.out
+      ];
+    in
+    {
+      packages.matar = pkgs.callPackage ./build.nix { inherit src libraries; };
+      devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries; };
+    };
+}

nix/shell.nix

@@ -0,0 +1,20 @@
+{ stdenv
+, mkShell
+, meson
+, ninja
+, pkg-config
+, libraries ? [ ]
+, tools ? [ ]
+}:
+
+mkShell.override { inherit stdenv; } {
+  name = "matar";
+
+  packages = [
+    meson
+    ninja
+    pkg-config
+  ] ++ libraries ++ tools;
+
+  enableParallelBuilding = true;
+}

src/bus.cc

@@ -1,7 +1,8 @@
 #include "bus.hh"
 #include <memory>
 
-Bus::Bus(Memory& memory)
+namespace matar {
+Bus::Bus(const Memory& memory)
   : memory(std::make_shared<Memory>(memory)) {}
 
 uint8_t
@@ -31,5 +32,6 @@ Bus::read_word(size_t address) {
 
 void
 Bus::write_word(size_t address, uint32_t word) {
-    memory->write_halfword(address, word);
+    memory->write_word(address, word);
+}
 }

src/cpu/alu.cc

@@ -1,72 +1,7 @@
-#include "cpu/utility.hh"
+#include "alu.hh"
 #include "util/bits.hh"
-#include <bit>
-
-std::ostream&
-operator<<(std::ostream& os, const Condition cond) {
-
-#define CASE(cond)                                                             \
-    case Condition::cond:                                                      \
-        os << #cond;                                                           \
-        break;
-
-    switch (cond) {
-        CASE(EQ)
-        CASE(NE)
-        CASE(CS)
-        CASE(CC)
-        CASE(MI)
-        CASE(PL)
-        CASE(VS)
-        CASE(VC)
-        CASE(HI)
-        CASE(LS)
-        CASE(GE)
-        CASE(LT)
-        CASE(GT)
-        CASE(LE)
-        case Condition::AL: {
-            // empty
-        }
-    }
-
-#undef CASE
-
-    return os;
-}
-
-std::ostream&
-operator<<(std::ostream& os, const OpCode opcode) {
-
-#define CASE(opcode)                                                           \
-    case OpCode::opcode:                                                       \
-        os << #opcode;                                                         \
-        break;
-
-    switch (opcode) {
-        CASE(AND)
-        CASE(EOR)
-        CASE(SUB)
-        CASE(RSB)
-        CASE(ADD)
-        CASE(ADC)
-        CASE(SBC)
-        CASE(RSC)
-        CASE(TST)
-        CASE(TEQ)
-        CASE(CMP)
-        CASE(CMN)
-        CASE(ORR)
-        CASE(MOV)
-        CASE(BIC)
-        CASE(MVN)
-    }
-
-#undef CASE
-
-    return os;
-}
 
+namespace matar {
 uint32_t
 eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
     uint32_t eval = 0;
@@ -102,13 +37,11 @@ eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
             break;
         case ShiftType::ROR:
             if (amount == 0) {
-                bool old_carry = carry;
-
+                eval  = (value >> 1) | (carry << 31);
                 carry = get_bit(value, 0);
-                eval  = (value >> 1) | (old_carry << 31);
             } else {
-                carry = get_bit(value, (amount % 32 + 31) % 32);
                 eval  = std::rotr(value, amount);
+                carry = get_bit(value, (amount % 32 + 31) % 32);
             }
             break;
     }
@@ -135,3 +68,4 @@ operator<<(std::ostream& os, const ShiftType shift_type) {
 
     return os;
 }
+}

src/cpu/alu.hh

@@ -0,0 +1,35 @@
+#pragma once
+#include <cstdint>
+#include <fmt/ostream.h>
+
+namespace matar {
+enum class ShiftType {
+    LSL = 0b00,
+    LSR = 0b01,
+    ASR = 0b10,
+    ROR = 0b11
+};
+
+struct ShiftData {
+    ShiftType type;
+    bool immediate;
+    uint8_t operand;
+};
+
+struct Shift {
+    uint8_t rm;
+    ShiftData data;
+};
+
+uint32_t
+eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const ShiftType cond);
+}
+
+namespace fmt {
+template<>
+struct formatter<matar::ShiftType> : ostream_formatter {};
+}

src/cpu/arm/exec.cc

@@ -0,0 +1,543 @@
+#include "cpu/cpu-impl.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+using namespace logger;
+
+namespace matar {
+void
+CpuImpl::exec_arm(const arm::Instruction instruction) {
+    Condition cond            = instruction.condition;
+    arm::InstructionData data = instruction.data;
+
+    debug(cpsr.condition(cond));
+    if (!cpsr.condition(cond)) {
+        return;
+    }
+
+    auto pc_error = [](uint8_t r) {
+        if (r == PC_INDEX)
+            log_error("Using PC (R15) as operand register");
+    };
+
+    auto pc_warn = [](uint8_t r) {
+        if (r == PC_INDEX)
+            log_warn("Using PC (R15) as operand register");
+    };
+
+    using namespace arm;
+
+    std::visit(
+      overloaded{
+        [this, pc_warn](BranchAndExchange& data) {
+            State state = static_cast<State>(data.rn & 1);
+
+            pc_warn(data.rn);
+
+            // set state
+            cpsr.set_state(state);
+
+            // copy to PC
+            pc = gpr[data.rn];
+
+            // ignore [1:0] bits for arm and 0 bit for thumb
+            rst_bit(pc, 0);
+
+            if (state == State::Arm)
+                rst_bit(pc, 1);
+
+            // pc is affected so flush the pipeline
+            is_flushed = true;
+        },
+        [this](Branch& data) {
+            if (data.link)
+                gpr[14] = pc - INSTRUCTION_SIZE;
+
+            // data.offset accounts for two instructions ahead when
+            // disassembling, so need to adjust
+            pc = static_cast<int32_t>(pc) - 2 * INSTRUCTION_SIZE + data.offset;
+
+            // pc is affected so flush the pipeline
+            is_flushed = true;
+        },
+        [this, pc_error](Multiply& data) {
+            if (data.rd == data.rm)
+                log_error("rd and rm are not distinct in {}",
+                          typeid(data).name());
+
+            pc_error(data.rd);
+            pc_error(data.rd);
+            pc_error(data.rd);
+
+            gpr[data.rd] =
+              gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
+
+            if (data.set) {
+                cpsr.set_z(gpr[data.rd] == 0);
+                cpsr.set_n(get_bit(gpr[data.rd], 31));
+                cpsr.set_c(0);
+            }
+        },
+        [this, pc_error](MultiplyLong& data) {
+            if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
+                data.rdlo == data.rm)
+                log_error("rdhi, rdlo and rm are not distinct in {}",
+                          typeid(data).name());
+
+            pc_error(data.rdhi);
+            pc_error(data.rdlo);
+            pc_error(data.rm);
+            pc_error(data.rs);
+
+            if (data.uns) {
+                auto cast = [](uint32_t x) -> uint64_t {
+                    return static_cast<uint64_t>(x);
+                };
+
+                uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                                (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                                              cast(gpr[data.rdlo])
+                                          : 0);
+
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
+
+            } else {
+                auto cast = [](uint32_t x) -> int64_t {
+                    return static_cast<int64_t>(static_cast<int32_t>(x));
+                };
+
+                int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                               (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                                             cast(gpr[data.rdlo])
+                                         : 0);
+
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
+            }
+
+            if (data.set) {
+                cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
+                cpsr.set_n(get_bit(gpr[data.rdhi], 31));
+                cpsr.set_c(0);
+                cpsr.set_v(0);
+            }
+        },
+        [](Undefined) { log_warn("Undefined instruction"); },
+        [this, pc_error](SingleDataSwap& data) {
+            pc_error(data.rm);
+            pc_error(data.rn);
+            pc_error(data.rd);
+
+            if (data.byte) {
+                gpr[data.rd] = bus->read_byte(gpr[data.rn]);
+                bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
+            } else {
+                gpr[data.rd] = bus->read_word(gpr[data.rn]);
+                bus->write_word(gpr[data.rn], gpr[data.rm]);
+            }
+        },
+        [this, pc_warn, pc_error](SingleDataTransfer& data) {
+            uint32_t offset  = 0;
+            uint32_t address = gpr[data.rn];
+
+            if (!data.pre && data.write)
+                log_warn("Write-back enabled with post-indexing in {}",
+                         typeid(data).name());
+
+            if (data.rn == PC_INDEX && data.write)
+                log_warn("Write-back enabled with base register as PC {}",
+                         typeid(data).name());
+
+            if (data.write)
+                pc_warn(data.rn);
+
+            // evaluate the offset
+            if (const uint16_t* immediate =
+                  std::get_if<uint16_t>(&data.offset)) {
+                offset = *immediate;
+            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
+                uint8_t amount =
+                  (shift->data.immediate ? shift->data.operand
+                                         : gpr[shift->data.operand] & 0xFF);
+
+                bool carry = cpsr.c();
+
+                if (!shift->data.immediate)
+                    pc_error(shift->data.operand);
+                pc_error(shift->rm);
+
+                offset =
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+
+                cpsr.set_c(carry);
+            }
+
+            // PC is always two instructions ahead
+            if (data.rn == PC_INDEX)
+                address -= 2 * INSTRUCTION_SIZE;
+
+            if (data.pre)
+                address += (data.up ? offset : -offset);
+
+            // load
+            if (data.load) {
+                // byte
+                if (data.byte)
+                    gpr[data.rd] = bus->read_byte(address);
+                // word
+                else
+                    gpr[data.rd] = bus->read_word(address);
+                // store
+            } else {
+                // take PC into consideration
+                if (data.rd == PC_INDEX)
+                    address += INSTRUCTION_SIZE;
+
+                // byte
+                if (data.byte)
+                    bus->write_byte(address, gpr[data.rd] & 0xFF);
+                // word
+                else
+                    bus->write_word(address, gpr[data.rd]);
+            }
+
+            if (!data.pre)
+                address += (data.up ? offset : -offset);
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.rd == PC_INDEX && data.load)
+                is_flushed = true;
+        },
+        [this, pc_warn, pc_error](HalfwordTransfer& data) {
+            uint32_t address = gpr[data.rn];
+            uint32_t offset  = 0;
+
+            if (!data.pre && data.write)
+                log_error("Write-back enabled with post-indexing in {}",
+                          typeid(data).name());
+
+            if (data.sign && !data.load)
+                log_error("Signed data found in {}", typeid(data).name());
+
+            if (data.write)
+                pc_warn(data.rn);
+
+            // offset is register number (4 bits) when not an immediate
+            if (!data.imm) {
+                pc_error(data.offset);
+                offset = gpr[data.offset];
+            } else {
+                offset = data.offset;
+            }
+
+            // PC is always two instructions ahead
+            if (data.rn == PC_INDEX)
+                address -= 2 * INSTRUCTION_SIZE;
+
+            if (data.pre)
+                address += (data.up ? offset : -offset);
+
+            // load
+            if (data.load) {
+                // signed
+                if (data.sign) {
+                    // halfword
+                    if (data.half) {
+                        gpr[data.rd] = bus->read_halfword(address);
+
+                        // sign extend the halfword
+                        gpr[data.rd] =
+                          (static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
+
+                        // byte
+                    } else {
+                        gpr[data.rd] = bus->read_byte(address);
+
+                        // sign extend the byte
+                        gpr[data.rd] =
+                          (static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
+                    }
+                    // unsigned halfword
+                } else if (data.half) {
+                    gpr[data.rd] = bus->read_halfword(address);
+                }
+                // store
+            } else {
+                // take PC into consideration
+                if (data.rd == PC_INDEX)
+                    address += INSTRUCTION_SIZE;
+
+                // halfword
+                if (data.half)
+                    bus->write_halfword(address, gpr[data.rd]);
+            }
+
+            if (!data.pre)
+                address += (data.up ? offset : -offset);
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.rd == PC_INDEX && data.load)
+                is_flushed = true;
+        },
+        [this, pc_error](BlockDataTransfer& data) {
+            uint32_t address  = gpr[data.rn];
+            Mode mode         = cpsr.mode();
+            uint8_t alignment = 4; // word
+            uint8_t i         = 0;
+            uint8_t n_regs    = std::popcount(data.regs);
+
+            pc_error(data.rn);
+
+            if (cpsr.mode() == Mode::User && data.s) {
+                log_error("Bit S is set outside priviliged modes in {}",
+                          typeid(data).name());
+            }
+
+            // we just change modes to load user registers
+            if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
+                (!data.load && data.s)) {
+                chg_mode(Mode::User);
+
+                if (data.write) {
+                    log_error("Write-back enable for user bank registers in {}",
+                              typeid(data).name());
+                }
+            }
+
+            // account for decrement
+            if (!data.up)
+                address -= (n_regs - 1) * alignment;
+
+            if (data.pre)
+                address += (data.up ? alignment : -alignment);
+
+            if (data.load) {
+                if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
+                    // current mode's spsr is already loaded when it was
+                    // switched
+                    spsr = cpsr;
+                }
+
+                for (i = 0; i < GPR_COUNT; i++) {
+                    if (get_bit(data.regs, i)) {
+                        gpr[i] = bus->read_word(address);
+                        address += alignment;
+                    }
+                }
+            } else {
+                for (i = 0; i < GPR_COUNT; i++) {
+                    if (get_bit(data.regs, i)) {
+                        bus->write_word(address, gpr[i]);
+                        address += alignment;
+                    }
+                }
+            }
+
+            if (!data.pre)
+                address += (data.up ? alignment : -alignment);
+
+            // reset back to original address + offset if incremented earlier
+            if (data.up)
+                address -= n_regs * alignment;
+            else
+                address -= alignment;
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.load && get_bit(data.regs, PC_INDEX))
+                is_flushed = true;
+
+            // load back the original mode registers
+            chg_mode(mode);
+        },
+        [this, pc_error](PsrTransfer& data) {
+            if (data.spsr && cpsr.mode() == Mode::User) {
+                log_error("Accessing SPSR in User mode in {}",
+                          typeid(data).name());
+            }
+
+            Psr& psr = data.spsr ? spsr : cpsr;
+
+            switch (data.type) {
+                case PsrTransfer::Type::Mrs:
+                    pc_error(data.operand);
+                    gpr[data.operand] = psr.raw();
+                    break;
+                case PsrTransfer::Type::Msr:
+                    pc_error(data.operand);
+
+                    if (cpsr.mode() != Mode::User) {
+                        psr.set_all(gpr[data.operand]);
+                    }
+                    break;
+                case PsrTransfer::Type::Msr_flg:
+                    uint32_t operand =
+                      (data.imm ? data.operand : gpr[data.operand]);
+                    psr.set_n(get_bit(operand, 31));
+                    psr.set_z(get_bit(operand, 30));
+                    psr.set_c(get_bit(operand, 29));
+                    psr.set_v(get_bit(operand, 28));
+                    break;
+            }
+        },
+        [this, pc_error](DataProcessing& data) {
+            using OpCode = DataProcessing::OpCode;
+
+            uint32_t op_1 = gpr[data.rn];
+            uint32_t op_2 = 0;
+
+            uint32_t result = 0;
+
+            if (const uint32_t* immediate =
+                  std::get_if<uint32_t>(&data.operand)) {
+                op_2 = *immediate;
+            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
+                uint8_t amount =
+                  (shift->data.immediate ? shift->data.operand
+                                         : gpr[shift->data.operand] & 0xFF);
+
+                bool carry = cpsr.c();
+
+                if (!shift->data.immediate)
+                    pc_error(shift->data.operand);
+                pc_error(shift->rm);
+
+                op_2 =
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+
+                cpsr.set_c(carry);
+
+                // PC is 12 bytes ahead when shifting
+                if (data.rn == PC_INDEX)
+                    op_1 += INSTRUCTION_SIZE;
+            }
+
+            bool overflow = cpsr.v();
+            bool carry    = cpsr.c();
+
+            auto sub = [&carry, &overflow](uint32_t a, uint32_t b) -> uint32_t {
+                bool s1 = get_bit(a, 31);
+                bool s2 = get_bit(b, 31);
+
+                uint32_t result = a - b;
+
+                carry    = b <= a;
+                overflow = s1 != s2 && s2 == get_bit(result, 31);
+                return result;
+            };
+
+            auto add = [&carry, &overflow](
+                         uint32_t a, uint32_t b, bool c = 0) -> uint32_t {
+                bool s1 = get_bit(a, 31);
+                bool s2 = get_bit(b, 31);
+
+                // 33 bits
+                uint64_t result_ = a + b + c;
+                uint32_t result  = result_ & 0xFFFFFFFF;
+
+                carry    = get_bit(result_, 32);
+                overflow = s1 == s2 && s2 != get_bit(result, 31);
+                return result;
+            };
+
+            auto sbc = [&carry,
+                        &overflow](uint32_t a, uint32_t b, bool c) -> uint32_t {
+                bool s1 = get_bit(a, 31);
+                bool s2 = get_bit(b, 31);
+
+                uint64_t result_ = a - b + c - 1;
+                uint32_t result  = result_ & 0xFFFFFFFF;
+
+                carry    = get_bit(result_, 32);
+                overflow = s1 != s2 && s2 == get_bit(result, 31);
+                return result;
+            };
+
+            switch (data.opcode) {
+                case OpCode::AND:
+                case OpCode::TST:
+                    result = op_1 & op_2;
+                    result = op_1 & op_2;
+                    break;
+                case OpCode::EOR:
+                case OpCode::TEQ:
+                    result = op_1 ^ op_2;
+                    break;
+                case OpCode::SUB:
+                case OpCode::CMP:
+                    result = sub(op_1, op_2);
+                    break;
+                case OpCode::RSB:
+                    result = sub(op_2, op_1);
+                    break;
+                case OpCode::ADD:
+                case OpCode::CMN:
+                    result = add(op_1, op_2);
+                    break;
+                case OpCode::ADC:
+                    result = add(op_1, op_2, carry);
+                    break;
+                case OpCode::SBC:
+                    result = sbc(op_1, op_2, carry);
+                    break;
+                case OpCode::RSC:
+                    result = sbc(op_2, op_1, carry);
+                    break;
+                case OpCode::ORR:
+                    result = op_1 | op_2;
+                    break;
+                case OpCode::MOV:
+                    result = op_2;
+                    break;
+                case OpCode::BIC:
+                    result = op_1 & ~op_2;
+                    break;
+                case OpCode::MVN:
+                    result = ~op_2;
+                    break;
+            }
+
+            auto set_conditions = [this, carry, overflow, result]() {
+                cpsr.set_c(carry);
+                cpsr.set_v(overflow);
+                cpsr.set_n(get_bit(result, 31));
+                cpsr.set_z(result == 0);
+            };
+
+            if (data.set) {
+                if (data.rd == PC_INDEX) {
+                    if (cpsr.mode() == Mode::User)
+                        log_error("Running {} in User mode",
+                                  typeid(data).name());
+                    spsr = cpsr;
+                } else {
+                    set_conditions();
+                }
+            }
+
+            if (data.opcode == OpCode::TST || data.opcode == OpCode::TEQ ||
+                data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
+                set_conditions();
+            } else {
+                gpr[data.rd] = result;
+                if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
+                    is_flushed = true;
+            }
+        },
+        [this](SoftwareInterrupt) {
+            chg_mode(Mode::Supervisor);
+            pc   = 0x08;
+            spsr = cpsr;
+        },
+        [](auto& data) {
+            log_error("Unimplemented {} instruction", typeid(data).name());
+        } },
+      data);
+}
+}

src/cpu/arm/instruction.cc

@@ -1,9 +1,9 @@
-#include "cpu/instruction.hh"
-#include "cpu/utility.hh"
+#include "instruction.hh"
 #include "util/bits.hh"
 #include <iterator>
 
-using namespace arm;
+namespace matar {
+namespace arm {
 
 Instruction::Instruction(uint32_t insn)
   : condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
@@ -21,7 +21,7 @@ Instruction::Instruction(uint32_t insn)
         // lsh 2 and sign extend the 26 bit offset to 32 bits
         offset = (static_cast<int32_t>(offset) << 8) >> 6;
 
-        offset += 2 * ARM_INSTRUCTION_SIZE;
+        offset += 2 * INSTRUCTION_SIZE;
 
         data = Branch{ .link = link, .offset = offset };
 
@@ -46,7 +46,7 @@ Instruction::Instruction(uint32_t insn)
         uint8_t rdhi = bit_range(insn, 16, 19);
         bool set     = get_bit(insn, 20);
         bool acc     = get_bit(insn, 21);
-        bool uns     = get_bit(insn, 22);
+        bool uns     = !get_bit(insn, 22);
 
         data = MultiplyLong{ .rm   = rm,
                              .rs   = rs,
@@ -152,6 +152,8 @@ Instruction::Instruction(uint32_t insn)
 
         // Data Processing
     } else if ((insn & 0x0C000000) == 0x00000000) {
+        using OpCode = DataProcessing::OpCode;
+
         uint8_t rd    = bit_range(insn, 12, 15);
         uint8_t rn    = bit_range(insn, 16, 19);
         bool set      = get_bit(insn, 20);
@@ -166,13 +168,13 @@ Instruction::Instruction(uint32_t insn)
         } else if ((opcode == OpCode::TEQ || opcode == OpCode::CMN) && !set) {
             uint32_t operand = 0;
 
-            if (!imm) {
-                operand = bit_range(insn, 0, 3);
-            } else {
+            if (imm) {
                 uint32_t immediate = bit_range(insn, 0, 7);
                 uint8_t rotate     = bit_range(insn, 8, 11);
 
                 operand = std::rotr(immediate, rotate * 2);
+            } else {
+                operand = bit_range(insn, 0, 3);
             }
 
             data = PsrTransfer{ .operand = operand,
@@ -184,7 +186,7 @@ Instruction::Instruction(uint32_t insn)
         } else {
             std::variant<Shift, uint32_t> operand;
 
-            if (!imm) {
+            if (imm) {
                 uint32_t immediate = bit_range(insn, 0, 7);
                 uint8_t rotate     = bit_range(insn, 8, 11);
 
@@ -419,6 +421,8 @@ Instruction::disassemble() {
             }
         },
         [this](DataProcessing& data) {
+            using OpCode = DataProcessing::OpCode;
+
             std::string op_2;
 
             if (const uint32_t* operand =
@@ -495,3 +499,37 @@ Instruction::disassemble() {
         [](auto) { return std::string("unknown instruction"); } },
       data);
 }
+
+std::ostream&
+operator<<(std::ostream& os, const DataProcessing::OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case DataProcessing::OpCode::opcode:                                       \
+        os << #opcode;                                                         \
+        break;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(SUB)
+        CASE(RSB)
+        CASE(ADD)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(RSC)
+        CASE(TST)
+        CASE(TEQ)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MOV)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+
+    return os;
+}
+}
+}

src/cpu/arm/instruction.hh

@@ -1,7 +1,13 @@
-#include "cpu/utility.hh"
+#pragma once
+#include "cpu/alu.hh"
+#include "cpu/psr.hh"
 #include <cstdint>
+#include <fmt/ostream.h>
 #include <variant>
 
+namespace matar {
+namespace arm {
+
 template<class... Ts>
 struct overloaded : Ts... {
     using Ts::operator()...;
@@ -9,7 +15,8 @@ struct overloaded : Ts... {
 template<class... Ts>
 overloaded(Ts...) -> overloaded<Ts...>;
 
-namespace arm {
+static constexpr size_t INSTRUCTION_SIZE = 4;
+
 struct BranchAndExchange {
     uint8_t rn;
 };
@@ -80,6 +87,25 @@ struct BlockDataTransfer {
 };
 
 struct DataProcessing {
+    enum class OpCode {
+        AND = 0b0000,
+        EOR = 0b0001,
+        SUB = 0b0010,
+        RSB = 0b0011,
+        ADD = 0b0100,
+        ADC = 0b0101,
+        SBC = 0b0110,
+        RSC = 0b0111,
+        TST = 0b1000,
+        TEQ = 0b1001,
+        CMP = 0b1010,
+        CMN = 0b1011,
+        ORR = 0b1100,
+        MOV = 0b1101,
+        BIC = 0b1110,
+        MVN = 0b1111
+    };
+
     std::variant<Shift, uint32_t> operand;
     uint8_t rd;
     uint8_t rn;
@@ -156,6 +182,19 @@ struct Instruction {
     InstructionData data;
 
     Instruction(uint32_t insn);
+    Instruction(Condition condition, InstructionData data) noexcept
+      : condition(condition)
+      , data(data){};
+
     std::string disassemble();
 };
+
+std::ostream&
+operator<<(std::ostream& os, const DataProcessing::OpCode cond);
+}
+}
+
+namespace fmt {
+template<>
+struct formatter<matar::arm::DataProcessing::OpCode> : ostream_formatter {};
 }

src/cpu/arm/meson.build

@@ -0,0 +1,4 @@
+lib_sources += files(
+  'instruction.cc',
+  'exec.cc'
+)

src/cpu/cpu-impl.cc

@@ -0,0 +1,145 @@
+#include "cpu-impl.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+#include <algorithm>
+#include <cstdio>
+
+using namespace logger;
+
+namespace matar {
+CpuImpl::CpuImpl(const Bus& bus) noexcept
+  : bus(std::make_shared<Bus>(bus))
+  , gpr({ 0 })
+  , cpsr(0)
+  , spsr(0)
+  , is_flushed(false)
+  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
+  , spsr_banked({ 0, 0, 0, 0, 0 }) {
+    cpsr.set_mode(Mode::Supervisor);
+    cpsr.set_irq_disabled(true);
+    cpsr.set_fiq_disabled(true);
+    cpsr.set_state(State::Arm);
+    log_info("CPU successfully initialised");
+
+    // PC always points to two instructions ahead
+    // PC - 2 is the instruction being executed
+    pc += 2 * arm::INSTRUCTION_SIZE;
+}
+
+/* change modes */
+void
+CpuImpl::chg_mode(const Mode to) {
+    Mode from = cpsr.mode();
+
+    if (from == to)
+        return;
+
+/* TODO: replace visible registers with view once I understand how to
+ * concatenate views */
+#define STORE_BANKED(mode, MODE)                                               \
+    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
+              gpr.begin() + gpr.size() - 1,                                    \
+              gpr_banked.mode.begin())
+
+    switch (from) {
+        case Mode::Fiq:
+            STORE_BANKED(fiq, FIQ);
+            spsr_banked.fiq = spsr;
+            break;
+
+        case Mode::Supervisor:
+            STORE_BANKED(svc, SVC);
+            spsr_banked.svc = spsr;
+            break;
+
+        case Mode::Abort:
+            STORE_BANKED(abt, ABT);
+            spsr_banked.abt = spsr;
+            break;
+
+        case Mode::Irq:
+            STORE_BANKED(irq, IRQ);
+            spsr_banked.irq = spsr;
+            break;
+
+        case Mode::Undefined:
+            STORE_BANKED(und, UND);
+            spsr_banked.und = spsr;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            STORE_BANKED(old, SYS_USR);
+            break;
+    }
+
+#define RESTORE_BANKED(mode, MODE)                                             \
+    std::copy(gpr_banked.mode.begin(),                                         \
+              gpr_banked.mode.end(),                                           \
+              gpr.begin() + GPR_##MODE##_FIRST)
+
+    switch (to) {
+        case Mode::Fiq:
+            RESTORE_BANKED(fiq, FIQ);
+            spsr = spsr_banked.fiq;
+            break;
+
+        case Mode::Supervisor:
+            RESTORE_BANKED(svc, SVC);
+            spsr = spsr_banked.svc;
+            break;
+
+        case Mode::Abort:
+            RESTORE_BANKED(abt, ABT);
+            spsr = spsr_banked.abt;
+            break;
+
+        case Mode::Irq:
+            RESTORE_BANKED(irq, IRQ);
+            spsr = spsr_banked.irq;
+            break;
+
+        case Mode::Undefined:
+            RESTORE_BANKED(und, UND);
+            spsr = spsr_banked.und;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            STORE_BANKED(old, SYS_USR);
+            break;
+    }
+
+#undef RESTORE_BANKED
+
+    cpsr.set_mode(to);
+}
+
+void
+CpuImpl::step() {
+    // Current instruction is two instructions behind PC
+    uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
+
+    if (cpsr.state() == State::Arm) {
+        debug(cur_pc);
+        uint32_t x = bus->read_word(cur_pc);
+        arm::Instruction instruction(x);
+        log_info("{:#034b}", x);
+
+        exec_arm(instruction);
+
+        log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
+
+        if (is_flushed) {
+            // if flushed, do not increment the PC, instead set it to two
+            // instructions ahead to account for flushed "fetch" and "decode"
+            // instructions
+            pc += 2 * arm::INSTRUCTION_SIZE;
+            is_flushed = false;
+        } else {
+            // if not flushed continue like normal
+            pc += arm::INSTRUCTION_SIZE;
+        }
+    }
+}
+}

src/cpu/cpu-impl.hh

@@ -0,0 +1,59 @@
+#pragma once
+
+#include "bus.hh"
+#include "cpu/arm/instruction.hh"
+#include "cpu/psr.hh"
+
+#include <cstdint>
+
+namespace matar {
+class CpuImpl {
+  public:
+    CpuImpl(const Bus& bus) noexcept;
+
+    void step();
+    void chg_mode(const Mode to);
+    void exec_arm(const arm::Instruction instruction);
+
+    static constexpr uint8_t GPR_COUNT = 16;
+
+    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
+    static constexpr uint8_t GPR_SVC_FIRST     = 13;
+    static constexpr uint8_t GPR_ABT_FIRST     = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
+    static constexpr uint8_t GPR_UND_FIRST     = 13;
+    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+
+    Psr cpsr; // current program status register
+    Psr spsr; // status program status register
+
+    static constexpr uint8_t PC_INDEX = 15;
+    static_assert(PC_INDEX < GPR_COUNT);
+
+    uint32_t& pc = gpr[PC_INDEX];
+
+    bool is_flushed;
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
+    } gpr_banked; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked; // banked saved program status registers
+};
+}

src/cpu/cpu.cc

@@ -1,714 +1,14 @@
 #include "cpu/cpu.hh"
-#include "cpu/utility.hh"
-#include "util/bits.hh"
-#include "util/log.hh"
-#include <algorithm>
-#include <cstdio>
+#include "cpu-impl.hh"
 
-using namespace logger;
+namespace matar {
+Cpu::Cpu(const Bus& bus) noexcept
+  : impl(std::make_unique<CpuImpl>(bus)){};
 
-Cpu::Cpu(Bus& bus)
-  : bus(std::make_shared<Bus>(bus))
-  , gpr({ 0 })
-  , cpsr(0)
-  , spsr(0)
-  , is_flushed(false)
-  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
-  , spsr_banked({ 0, 0, 0, 0, 0 }) {
-    cpsr.set_mode(Mode::Supervisor);
-    cpsr.set_irq_disabled(true);
-    cpsr.set_fiq_disabled(true);
-    cpsr.set_state(State::Arm);
-    log_info("CPU successfully initialised");
-
-    // PC always points to two instructions ahead
-    // PC - 2 is the instruction being executed
-    pc += 2 * ARM_INSTRUCTION_SIZE;
-}
-
-/* change modes */
-void
-Cpu::chg_mode(const Mode to) {
-    Mode from = cpsr.mode();
-
-    if (from == to)
-        return;
-
-/* TODO: replace visible registers with view once I understand how to
- * concatenate views */
-#define STORE_BANKED(mode, MODE)                                               \
-    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
-              gpr.begin() + gpr.size() - 1,                                    \
-              gpr_banked.mode.begin())
-
-    switch (from) {
-        case Mode::Fiq:
-            STORE_BANKED(fiq, FIQ);
-            spsr_banked.fiq = spsr;
-            break;
-
-        case Mode::Supervisor:
-            STORE_BANKED(svc, SVC);
-            spsr_banked.svc = spsr;
-            break;
-
-        case Mode::Abort:
-            STORE_BANKED(abt, ABT);
-            spsr_banked.abt = spsr;
-            break;
-
-        case Mode::Irq:
-            STORE_BANKED(irq, IRQ);
-            spsr_banked.irq = spsr;
-            break;
-
-        case Mode::Undefined:
-            STORE_BANKED(und, UND);
-            spsr_banked.und = spsr;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#define RESTORE_BANKED(mode, MODE)                                             \
-    std::copy(gpr_banked.mode.begin(),                                         \
-              gpr_banked.mode.end(),                                           \
-              gpr.begin() + GPR_##MODE##_FIRST)
-
-    switch (to) {
-        case Mode::Fiq:
-            RESTORE_BANKED(fiq, FIQ);
-            spsr = spsr_banked.fiq;
-            break;
-
-        case Mode::Supervisor:
-            RESTORE_BANKED(svc, SVC);
-            spsr = spsr_banked.svc;
-            break;
-
-        case Mode::Abort:
-            RESTORE_BANKED(abt, ABT);
-            spsr = spsr_banked.abt;
-            break;
-
-        case Mode::Irq:
-            RESTORE_BANKED(irq, IRQ);
-            spsr = spsr_banked.irq;
-            break;
-
-        case Mode::Undefined:
-            RESTORE_BANKED(und, UND);
-            spsr = spsr_banked.und;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#undef RESTORE_BANKED
-
-    cpsr.set_mode(to);
-}
-
-void
-Cpu::exec_arm(const arm::Instruction instruction) {
-    auto cond = instruction.condition;
-    auto data = instruction.data;
-
-    if (!cpsr.condition(cond)) {
-        return;
-    }
-
-    auto pc_error = [](uint8_t r) {
-        if (r == PC_INDEX)
-            log_error("Using PC (R15) as operand register");
-    };
-
-    auto pc_warn = [](uint8_t r) {
-        if (r == PC_INDEX)
-            log_warn("Using PC (R15) as operand register");
-    };
-
-    using namespace arm;
-
-    std::visit(
-      overloaded{
-        [this, pc_warn](BranchAndExchange& data) {
-            State state = static_cast<State>(data.rn & 1);
-
-            pc_warn(data.rn);
-
-            // set state
-            cpsr.set_state(state);
-
-            // copy to PC
-            pc = gpr[data.rn];
-
-            // ignore [1:0] bits for arm and 0 bit for thumb
-            rst_bit(pc, 0);
-
-            if (state == State::Arm)
-                rst_bit(pc, 1);
-
-            // pc is affected so flush the pipeline
-            is_flushed = true;
-        },
-        [this](Branch& data) {
-            if (data.link)
-                gpr[14] = pc - ARM_INSTRUCTION_SIZE;
-
-            // data.offset accounts for two instructions ahead when
-            // disassembling, so need to adjust
-            pc =
-              static_cast<int32_t>(pc) - 2 * ARM_INSTRUCTION_SIZE + data.offset;
-
-            // pc is affected so flush the pipeline
-            is_flushed = true;
-        },
-        [this, pc_error](Multiply& data) {
-            if (data.rd == data.rm)
-                log_error("rd and rm are not distinct in {}",
-                          typeid(data).name());
-
-            pc_error(data.rd);
-            pc_error(data.rd);
-            pc_error(data.rd);
-
-            gpr[data.rd] =
-              gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
-
-            if (data.set) {
-                cpsr.set_z(gpr[data.rd] == 0);
-                cpsr.set_n(get_bit(gpr[data.rd], 31));
-                cpsr.set_c(0);
-            }
-        },
-        [this, pc_error](MultiplyLong& data) {
-            if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
-                data.rdlo == data.rm)
-                log_error("rdhi, rdlo and rm are not distinct in {}",
-                          typeid(data).name());
-
-            pc_error(data.rdhi);
-            pc_error(data.rdlo);
-            pc_error(data.rm);
-            pc_error(data.rs);
-            if (data.uns) {
-                uint64_t eval =
-                  static_cast<uint64_t>(gpr[data.rm]) *
-                    static_cast<uint64_t>(gpr[data.rs]) +
-                  (data.acc ? static_cast<uint64_t>(gpr[data.rdhi]) << 32 |
-                                static_cast<uint64_t>(gpr[data.rdlo])
-                            : 0);
-
-                gpr[data.rdlo] = bit_range(eval, 0, 31);
-                gpr[data.rdhi] = bit_range(eval, 32, 63);
-
-            } else {
-                int64_t eval =
-                  static_cast<int64_t>(gpr[data.rm]) *
-                    static_cast<int64_t>(gpr[data.rs]) +
-                  (data.acc ? static_cast<int64_t>(gpr[data.rdhi]) << 32 |
-                                static_cast<int64_t>(gpr[data.rdlo])
-                            : 0);
-
-                gpr[data.rdlo] = bit_range(eval, 0, 31);
-                gpr[data.rdhi] = bit_range(eval, 32, 63);
-            }
-
-            if (data.set) {
-                cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
-                cpsr.set_n(get_bit(gpr[data.rdhi], 31));
-                cpsr.set_c(0);
-                cpsr.set_v(0);
-            }
-        },
-        [](Undefined) { log_warn("Undefined instruction"); },
-        [this, pc_error](SingleDataSwap& data) {
-            pc_error(data.rm);
-            pc_error(data.rn);
-            pc_error(data.rd);
-
-            if (data.byte) {
-                gpr[data.rd] = bus->read_byte(gpr[data.rn]);
-                bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
-            } else {
-                gpr[data.rd] = bus->read_word(gpr[data.rn]);
-                bus->write_word(gpr[data.rn], gpr[data.rm]);
-            }
-        },
-        [this, pc_warn, pc_error](SingleDataTransfer& data) {
-            uint32_t offset  = 0;
-            uint32_t address = gpr[data.rn];
-
-            if (!data.pre && data.write)
-                log_warn("Write-back enabled with post-indexing in {}",
-                         typeid(data).name());
-
-            if (data.rn == PC_INDEX && data.write)
-                log_warn("Write-back enabled with base register as PC {}",
-                         typeid(data).name());
-
-            if (data.write)
-                pc_warn(data.rn);
-
-            // evaluate the offset
-            if (const uint16_t* immediate =
-                  std::get_if<uint16_t>(&data.offset)) {
-                offset = *immediate;
-            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
-                uint8_t amount =
-                  (shift->data.immediate ? shift->data.operand
-                                         : gpr[shift->data.operand] & 0xFF);
-
-                bool carry = cpsr.c();
-
-                if (!shift->data.immediate)
-                    pc_error(shift->data.operand);
-                pc_error(shift->rm);
-
-                offset =
-                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
-
-                cpsr.set_c(carry);
-            }
-
-            // PC is always two instructions ahead
-            if (data.rn == PC_INDEX)
-                address -= 2 * ARM_INSTRUCTION_SIZE;
-
-            if (data.pre)
-                address += (data.up ? offset : -offset);
-
-            debug(address);
-
-            // load
-            if (data.load) {
-                // byte
-                if (data.byte)
-                    gpr[data.rd] = bus->read_byte(address);
-                // word
-                else
-                    gpr[data.rd] = bus->read_word(address);
-                // store
-            } else {
-                // take PC into consideration
-                if (data.rd == PC_INDEX)
-                    address += ARM_INSTRUCTION_SIZE;
-
-                // byte
-                if (data.byte)
-                    bus->write_byte(address, gpr[data.rd] & 0xFF);
-                // word
-                else
-                    bus->write_word(address, gpr[data.rd]);
-            }
-
-            if (!data.pre)
-                address += (data.up ? offset : -offset);
-
-            if (!data.pre || data.write)
-                gpr[data.rn] = address;
-
-            if (data.rd == PC_INDEX && data.load)
-                is_flushed = true;
-        },
-        [this, pc_warn, pc_error](HalfwordTransfer& data) {
-            uint32_t address = gpr[data.rn];
-
-            if (!data.pre && data.write)
-                log_error("Write-back enabled with post-indexing in {}",
-                          typeid(data).name());
-
-            if (data.sign && !data.load)
-                log_error("Signed data found in {}", typeid(data).name());
-
-            if (data.write)
-                pc_warn(data.rn);
-
-            // offset is register number (4 bits) when not an immediate
-            if (!data.imm)
-                pc_error(data.offset);
-
-            if (data.pre)
-                address += (data.up ? data.offset : -data.offset);
-
-            // load
-            if (data.load) {
-                // signed
-                if (data.sign) {
-                    // halfword
-                    if (data.half) {
-                        gpr[data.rd] = bus->read_halfword(address);
-
-                        // sign extend the halfword
-                        gpr[data.rd] =
-                          (static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
-
-                        // byte
-                    } else {
-                        gpr[data.rd] = bus->read_byte(address);
-
-                        // sign extend the byte
-                        gpr[data.rd] =
-                          (static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
-                    }
-                    // unsigned halfword
-                } else if (data.half) {
-                    gpr[data.rd] = bus->read_halfword(address);
-                }
-                // store
-            } else {
-                // take PC into consideration
-                if (data.rd == PC_INDEX)
-                    address += ARM_INSTRUCTION_SIZE;
-
-                // halfword
-                if (data.half)
-                    bus->write_halfword(address, gpr[data.rd]);
-            }
-
-            if (!data.pre)
-                address += (data.up ? data.offset : -data.offset);
-
-            if (!data.pre || data.write)
-                gpr[data.rn] = address;
-
-            if (data.rd == PC_INDEX && data.load)
-                is_flushed = true;
-        },
-        [this, pc_error](BlockDataTransfer& data) {
-            uint32_t address  = gpr[data.rn];
-            Mode mode         = cpsr.mode();
-            uint8_t alignment = 4; // word
-            uint8_t i         = 0;
-            uint8_t n_regs    = std::popcount(data.regs);
-
-            pc_error(data.rn);
-
-            if (cpsr.mode() == Mode::User && data.s) {
-                log_error("Bit S is set outside priviliged modes in {}",
-                          typeid(data).name());
-            }
-
-            // we just change modes to load user registers
-            if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
-                (!data.load && data.s)) {
-                chg_mode(Mode::User);
-
-                if (data.write) {
-                    log_error("Write-back enable for user bank registers in {}",
-                              typeid(data).name());
-                }
-            }
-
-            // account for decrement
-            if (!data.up)
-                address -= (n_regs - 1) * alignment;
-
-            if (data.pre)
-                address += (data.up ? alignment : -alignment);
-
-            if (data.load) {
-                if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
-                    // current mode's spsr is already loaded when it was
-                    // switched
-                    spsr = cpsr;
-                }
-
-                for (i = 0; i < GPR_COUNT; i++) {
-                    if (get_bit(data.regs, i)) {
-                        gpr[i] = bus->read_word(address);
-                        address += alignment;
-                    }
-                }
-            } else {
-                for (i = 0; i < GPR_COUNT; i++) {
-                    if (get_bit(data.regs, i)) {
-                        bus->write_word(address, gpr[i]);
-                        address += alignment;
-                    }
-                }
-            }
-
-            if (!data.pre)
-                address += (data.up ? alignment : -alignment);
-
-            // reset back to original address + offset if incremented earlier
-            if (data.up)
-                address -= n_regs * alignment;
-
-            if (!data.pre || data.write)
-                gpr[data.rn] = address;
-
-            if (data.load && get_bit(data.regs, PC_INDEX))
-                is_flushed = true;
-
-            // load back the original mode registers
-            chg_mode(mode);
-        },
-        [this, pc_error](PsrTransfer& data) {
-            if (data.spsr && cpsr.mode() == Mode::User) {
-                log_error("Accessing SPSR in User mode in {}",
-                          typeid(data).name());
-            }
-
-            Psr& psr = data.spsr ? spsr : cpsr;
-
-            switch (data.type) {
-                case PsrTransfer::Type::Mrs:
-                    pc_error(data.operand);
-                    gpr[data.operand] = psr.raw();
-                    break;
-                case PsrTransfer::Type::Msr:
-                    pc_error(data.operand);
-
-                    if (cpsr.mode() != Mode::User) {
-                        psr.set_all(gpr[data.operand]);
-                    }
-                    break;
-                case PsrTransfer::Type::Msr_flg:
-                    psr.set_n(get_bit(data.operand, 31));
-                    psr.set_z(get_bit(data.operand, 30));
-                    psr.set_c(get_bit(data.operand, 29));
-                    psr.set_v(get_bit(data.operand, 28));
-                    break;
-            }
-        },
-        [this, pc_error](DataProcessing& data) {
-            uint32_t op_1 = gpr[data.rn];
-            uint32_t op_2 = 0;
-
-            uint32_t result = 0;
-
-            bool overflow = cpsr.v();
-            bool carry    = cpsr.c();
-            bool negative = cpsr.n();
-            bool zero     = cpsr.z();
-
-            if (const uint32_t* immediate =
-                  std::get_if<uint32_t>(&data.operand)) {
-                op_2 = *immediate;
-            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
-                uint8_t amount =
-                  (shift->data.immediate ? shift->data.operand
-                                         : gpr[shift->data.operand] & 0xFF);
-
-                bool carry = cpsr.c();
-
-                if (!shift->data.immediate)
-                    pc_error(shift->data.operand);
-                pc_error(shift->rm);
-
-                op_2 =
-                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
-
-                cpsr.set_c(carry);
-
-                // PC is 12 bytes ahead when shifting
-                if (data.rn == PC_INDEX)
-                    op_1 += ARM_INSTRUCTION_SIZE;
-            }
-
-            switch (data.opcode) {
-                case OpCode::AND: {
-                    result = op_1 & op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-                case OpCode::EOR: {
-                    result = op_1 ^ op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-                case OpCode::SUB: {
-                    bool s1  = get_bit(op_1, 31);
-                    bool s2  = get_bit(op_2, 31);
-                    result   = op_1 - op_2;
-                    negative = get_bit(result, 31);
-                    carry    = op_1 < op_2;
-                    overflow = s1 != s2 && s2 == negative;
-                } break;
-                case OpCode::RSB: {
-                    bool s1 = get_bit(op_1, 31);
-                    bool s2 = get_bit(op_2, 31);
-                    result  = op_2 - op_1;
-
-                    negative = get_bit(result, 31);
-                    carry    = op_2 < op_1;
-                    overflow = s1 != s2 && s1 == negative;
-                } break;
-                case OpCode::ADD: {
-                    bool s1 = get_bit(op_1, 31);
-                    bool s2 = get_bit(op_2, 31);
-
-                    // result_ is 33 bits
-                    uint64_t result_ = op_2 + op_1;
-                    result           = result_ & 0xFFFFFFFF;
-
-                    negative = get_bit(result, 31);
-                    carry    = get_bit(result_, 32);
-                    overflow = s1 == s2 && s1 != negative;
-                } break;
-                case OpCode::ADC: {
-                    bool s1 = get_bit(op_1, 31);
-                    bool s2 = get_bit(op_2, 31);
-
-                    uint64_t result_ = op_2 + op_1 + carry;
-                    result           = result_ & 0xFFFFFFFF;
-
-                    negative = get_bit(result, 31);
-                    carry    = get_bit(result_, 32);
-                    overflow = s1 == s2 && s1 != negative;
-                } break;
-                case OpCode::SBC: {
-                    bool s1 = get_bit(op_1, 31);
-                    bool s2 = get_bit(op_2, 31);
-
-                    uint64_t result_ = op_1 - op_2 + carry - 1;
-                    result           = result_ & 0xFFFFFFFF;
-
-                    negative = get_bit(result, 31);
-                    carry    = get_bit(result_, 32);
-                    overflow = s1 != s2 && s2 == negative;
-                } break;
-                case OpCode::RSC: {
-                    bool s1 = get_bit(op_1, 31);
-                    bool s2 = get_bit(op_2, 31);
-
-                    uint64_t result_ = op_1 - op_2 + carry - 1;
-                    result           = result_ & 0xFFFFFFFF;
-
-                    negative = get_bit(result, 31);
-                    carry    = get_bit(result_, 32);
-                    overflow = s1 != s2 && s1 == negative;
-                } break;
-                case OpCode::TST: {
-                    result = op_1 & op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-                case OpCode::TEQ: {
-                    result = op_1 ^ op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-                case OpCode::CMP: {
-                    bool s1 = get_bit(op_1, 31);
-                    bool s2 = get_bit(op_2, 31);
-
-                    result = op_1 - op_2;
-
-                    negative = get_bit(result, 31);
-                    carry    = op_1 < op_2;
-                    overflow = s1 != s2 && s2 == negative;
-                } break;
-                case OpCode::CMN: {
-                    bool s1 = get_bit(op_1, 31);
-                    bool s2 = get_bit(op_2, 31);
-
-                    uint64_t result_ = op_2 + op_1;
-                    result           = result_ & 0xFFFFFFFF;
-
-                    negative = get_bit(result, 31);
-                    carry    = get_bit(result_, 32);
-                    overflow = s1 == s2 && s1 != negative;
-                } break;
-                case OpCode::ORR: {
-                    result = op_1 | op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-                case OpCode::MOV: {
-                    result = op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-                case OpCode::BIC: {
-                    result = op_1 & ~op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-                case OpCode::MVN: {
-                    result = ~op_2;
-
-                    negative = get_bit(result, 31);
-                } break;
-            }
-
-            zero = result == 0;
-
-            debug(carry);
-            debug(overflow);
-            debug(zero);
-            debug(negative);
-
-            auto set_conditions = [this, carry, overflow, negative, zero]() {
-                cpsr.set_c(carry);
-                cpsr.set_v(overflow);
-                cpsr.set_n(negative);
-                cpsr.set_z(zero);
-            };
-
-            if (data.set) {
-                if (data.rd == 15) {
-                    if (cpsr.mode() == Mode::User)
-                        log_error("Running {} in User mode",
-                                  typeid(data).name());
-                } else {
-                    set_conditions();
-                }
-            }
-
-            if (data.opcode == OpCode::TST || data.opcode == OpCode::TEQ ||
-                data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
-                set_conditions();
-            } else {
-                gpr[data.rd] = result;
-                if (data.rd == 15 || data.opcode == OpCode::MVN)
-                    is_flushed = true;
-            }
-        },
-        [this](SoftwareInterrupt) {
-            chg_mode(Mode::Supervisor);
-            pc   = 0x08;
-            spsr = cpsr;
-        },
-        [](auto& data) {
-            log_error("Unimplemented {} instruction", typeid(data).name());
-        } },
-      data);
-}
+Cpu::~Cpu() = default;
 
 void
 Cpu::step() {
-    // Current instruction is two instructions behind PC
-    uint32_t cur_pc = pc - 2 * ARM_INSTRUCTION_SIZE;
-
-    if (cpsr.state() == State::Arm) {
-        debug(cur_pc);
-        uint32_t x = bus->read_word(cur_pc);
-        arm::Instruction instruction(x);
-        log_info("{:#034b}", x);
-
-        exec_arm(instruction);
-
-        log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
-
-        if (is_flushed) {
-            // if flushed, do not increment the PC, instead set it to two
-            // instructions ahead to account for flushed "fetch" and "decode"
-            // instructions
-            pc += 2 * ARM_INSTRUCTION_SIZE;
-            is_flushed = false;
-        } else {
-            // if not flushed continue like normal
-            pc += ARM_INSTRUCTION_SIZE;
-        }
-    }
+    impl->step();
+};
 }

src/cpu/meson.build

@@ -1,6 +1,8 @@
 lib_sources += files(
+  'cpu-impl.cc',
   'cpu.cc',
-  'instruction.cc',
   'psr.cc',
-  'utility.cc'
+  'alu.cc'
 )
+
+subdir('arm')

src/cpu/psr.cc

@@ -1,7 +1,8 @@
-#include "cpu/psr.hh"
+#include "psr.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
+namespace matar {
 Psr::Psr(uint32_t raw)
   : psr(raw & PSR_CLEAR_RESERVED) {}
 
@@ -90,8 +91,42 @@ Psr::condition(Condition cond) const {
         case Condition::LE:
             return z() || (n() != v());
         case Condition::AL:
-            return true;
+            return true && state() == State::Arm;
     }
 
     return false;
 }
+
+std::ostream&
+operator<<(std::ostream& os, const Condition cond) {
+
+#define CASE(cond)                                                             \
+    case Condition::cond:                                                      \
+        os << #cond;                                                           \
+        break;
+
+    switch (cond) {
+        CASE(EQ)
+        CASE(NE)
+        CASE(CS)
+        CASE(CC)
+        CASE(MI)
+        CASE(PL)
+        CASE(VS)
+        CASE(VC)
+        CASE(HI)
+        CASE(LS)
+        CASE(GE)
+        CASE(LT)
+        CASE(GT)
+        CASE(LE)
+        case Condition::AL: {
+            // empty
+        }
+    }
+
+#undef CASE
+
+    return os;
+}
+}

src/cpu/psr.hh

@@ -1,7 +1,42 @@
 #pragma once
 
-#include "utility.hh"
 #include <cstdint>
+#include <fmt/ostream.h>
+
+namespace matar {
+enum class Mode {
+    /* M[4:0] in PSR */
+    User       = 0b10000,
+    Fiq        = 0b10001,
+    Irq        = 0b10010,
+    Supervisor = 0b10011,
+    Abort      = 0b10111,
+    Undefined  = 0b11011,
+    System     = 0b11111,
+};
+
+enum class State {
+    Arm   = 0,
+    Thumb = 1
+};
+
+enum class Condition {
+    EQ = 0b0000,
+    NE = 0b0001,
+    CS = 0b0010,
+    CC = 0b0011,
+    MI = 0b0100,
+    PL = 0b0101,
+    VS = 0b0110,
+    VC = 0b0111,
+    HI = 0b1000,
+    LS = 0b1001,
+    GE = 0b1010,
+    LT = 0b1011,
+    GT = 0b1100,
+    LE = 0b1101,
+    AL = 0b1110
+};
 
 class Psr {
   public:
@@ -53,3 +88,13 @@ class Psr {
 
     uint32_t psr;
 };
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const Condition cond);
+}
+
+namespace fmt {
+template<>
+struct formatter<matar::Condition> : ostream_formatter {};
+}

src/memory.cc

@@ -4,11 +4,13 @@
 #include "util/log.hh"
 #include "util/utils.hh"
 #include <bitset>
+#include <stdexcept>
 
 using namespace logger;
 
+namespace matar {
 Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-               std::vector<uint8_t>&& rom) noexcept
+               std::vector<uint8_t>&& rom)
   : bios(std::move(bios))
   , board_wram({ 0 })
   , chip_wram({ 0 })
@@ -116,18 +118,24 @@ Memory::read_word(size_t address) const {
 }
 
 void
-Memory::write_word(size_t address, uint32_t halfword) {
+Memory::write_word(size_t address, uint32_t word) {
     if (address & 0b11)
         log_warn("Writing to a non aligned word address");
 
-    write(address, halfword & 0xFF);
-    write(address + 1, halfword >> 8 & 0xFF);
-    write(address + 2, halfword >> 16 & 0xFF);
-    write(address + 3, halfword >> 24 & 0xFF);
+    write(address, word & 0xFF);
+    write(address + 1, word >> 8 & 0xFF);
+    write(address + 2, word >> 16 & 0xFF);
+    write(address + 3, word >> 24 & 0xFF);
 }
 
 void
 Memory::parse_header() {
+
+    if (rom.size() < header.HEADER_SIZE) {
+        throw std::out_of_range(
+          "ROM is not large enough to even have a header");
+    }
+
     // entrypoint
     header.entrypoint =
       rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
@@ -225,3 +233,4 @@ Memory::parse_header() {
 
     // multiboot not required right now
 }
+}

src/meson.build

@@ -5,13 +5,22 @@ lib_sources = files(
 
 subdir('cpu')
 
-fmt = dependency('fmt', version : '>=10.1.0')
+
+lib_cpp_args = [ ]
+
+fmt = dependency('fmt', version : '>=10.1.0', static: true)
+if not fmt.found()
+  fmt = dependency('fmt', version : '>=10.1.0', static: false)
+  lib_cpp_args += 'DFMT_HEADER_ONLY'
+endif
+
 lib = library(
   meson.project_name(),
   lib_sources,
   dependencies: [fmt],
   include_directories: inc,
-  install: true
+  install: true,
+  cpp_args: lib_cpp_args
 )
 
 import('pkgconfig').generate(lib)

src/util/utils.hh

@@ -3,8 +3,6 @@
 #include <array>
 #include <bit>
 #include <fmt/core.h>
-#include <iomanip>
-#include <sstream>
 #include <string>
 
 // Why I wrote this myself? I do not know

tests/cpu/arm/instruction.cc

@@ -0,0 +1,471 @@
+#include "cpu/arm/instruction.hh"
+#include <catch2/catch_test_macros.hpp>
+
+#define TAG "disassembler"
+
+using namespace matar;
+using namespace arm;
+
+TEST_CASE("Branch and Exchange", TAG) {
+    uint32_t raw = 0b11000001001011111111111100011010;
+    Instruction instruction(raw);
+    BranchAndExchange* bx = nullptr;
+
+    REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
+    CHECK(instruction.condition == Condition::GT);
+
+    CHECK(bx->rn == 10);
+
+    CHECK(instruction.disassemble() == "BXGT R10");
+}
+
+TEST_CASE("Branch", TAG) {
+    uint32_t raw = 0b11101011100001010111111111000011;
+    Instruction instruction(raw);
+    Branch* b = nullptr;
+
+    REQUIRE((b = std::get_if<Branch>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    // last 24 bits = 8748995
+    // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
+    // Also +8 since PC is two instructions ahead
+    CHECK(b->offset == 0xFE15FF14);
+    CHECK(b->link == true);
+
+    CHECK(instruction.disassemble() == "BL 0xFE15FF14");
+
+    b->link = false;
+    CHECK(instruction.disassemble() == "B 0xFE15FF14");
+}
+
+TEST_CASE("Multiply", TAG) {
+    uint32_t raw = 0b00000000001110101110111110010000;
+    Instruction instruction(raw);
+    Multiply* mul = nullptr;
+
+    REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
+    CHECK(instruction.condition == Condition::EQ);
+
+    CHECK(mul->rm == 0);
+    CHECK(mul->rs == 15);
+    CHECK(mul->rn == 14);
+    CHECK(mul->rd == 10);
+    CHECK(mul->acc == true);
+    CHECK(mul->set == true);
+
+    CHECK(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
+
+    mul->acc = false;
+    mul->set = false;
+    CHECK(instruction.disassemble() == "MULEQ R10,R0,R15");
+}
+
+TEST_CASE("Multiply Long", TAG) {
+    uint32_t raw = 0b00010000100111100111011010010010;
+    Instruction instruction(raw);
+    MultiplyLong* mull = nullptr;
+
+    REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
+    CHECK(instruction.condition == Condition::NE);
+
+    CHECK(mull->rm == 2);
+    CHECK(mull->rs == 6);
+    CHECK(mull->rdlo == 7);
+    CHECK(mull->rdhi == 14);
+    CHECK(mull->acc == false);
+    CHECK(mull->set == true);
+    CHECK(mull->uns == true);
+
+    CHECK(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
+
+    mull->acc = true;
+    CHECK(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
+
+    mull->uns = false;
+    mull->set = false;
+    CHECK(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
+}
+
+TEST_CASE("Undefined", TAG) {
+    // notice how this is the same as single data transfer except the shift
+    // is now a register based shift
+    uint32_t raw = 0b11100111101000101010111100010110;
+    Instruction instruction(raw);
+
+    CHECK(instruction.condition == Condition::AL);
+    CHECK(instruction.disassemble() == "UND");
+}
+
+TEST_CASE("Single Data Swap", TAG) {
+    uint32_t raw = 0b10100001000010010101000010010110;
+    Instruction instruction(raw);
+    SingleDataSwap* swp = nullptr;
+
+    REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
+    CHECK(instruction.condition == Condition::GE);
+
+    CHECK(swp->rm == 6);
+    CHECK(swp->rd == 5);
+    CHECK(swp->rn == 9);
+    CHECK(swp->byte == false);
+
+    CHECK(instruction.disassemble() == "SWPGE R5,R6,[R9]");
+
+    swp->byte = true;
+    CHECK(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
+}
+
+TEST_CASE("Single Data Transfer", TAG) {
+    uint32_t raw = 0b11100111101000101010111100000110;
+    Instruction instruction(raw);
+    SingleDataTransfer* ldr = nullptr;
+    Shift* shift            = nullptr;
+
+    REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
+    CHECK(shift->rm == 6);
+    CHECK(shift->data.immediate == true);
+    CHECK(shift->data.type == ShiftType::LSL);
+    CHECK(shift->data.operand == 30);
+    CHECK(ldr->rd == 10);
+    CHECK(ldr->rn == 2);
+    CHECK(ldr->load == false);
+    CHECK(ldr->write == true);
+    CHECK(ldr->byte == false);
+    CHECK(ldr->up == true);
+    CHECK(ldr->pre == true);
+
+    ldr->load        = true;
+    ldr->byte        = true;
+    ldr->write       = false;
+    shift->data.type = ShiftType::ROR;
+    CHECK(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
+
+    ldr->up  = false;
+    ldr->pre = false;
+    CHECK(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
+
+    ldr->offset = static_cast<uint16_t>(9023);
+    CHECK(instruction.disassemble() == "LDRB R10,[R2],-#9023");
+
+    ldr->pre = true;
+    CHECK(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
+}
+
+TEST_CASE("Halfword Transfer", TAG) {
+    uint32_t raw = 0b00110001101011110010000010110110;
+    Instruction instruction(raw);
+    HalfwordTransfer* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::CC);
+
+    // offset is not immediate
+    CHECK(ldr->imm == 0);
+    // hence this offset is a register number (rm)
+    CHECK(ldr->offset == 6);
+    CHECK(ldr->half == true);
+    CHECK(ldr->sign == false);
+    CHECK(ldr->rd == 2);
+    CHECK(ldr->rn == 15);
+    CHECK(ldr->load == false);
+    CHECK(ldr->write == true);
+    CHECK(ldr->up == true);
+    CHECK(ldr->pre == true);
+
+    CHECK(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
+
+    ldr->pre  = false;
+    ldr->load = true;
+    ldr->sign = true;
+    ldr->up   = false;
+
+    CHECK(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
+
+    ldr->half = false;
+    CHECK(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
+
+    ldr->load = false;
+    // not a register anymore
+    ldr->imm    = 1;
+    ldr->offset = 90;
+    CHECK(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
+}
+
+TEST_CASE("Block Data Transfer", TAG) {
+    uint32_t raw = 0b10011001010101110100000101101101;
+    Instruction instruction(raw);
+    BlockDataTransfer* ldm = nullptr;
+
+    REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::LS);
+
+    {
+        uint16_t regs = 0;
+        regs |= 1 << 0;
+        regs |= 1 << 2;
+        regs |= 1 << 3;
+        regs |= 1 << 5;
+        regs |= 1 << 6;
+        regs |= 1 << 8;
+        regs |= 1 << 14;
+
+        CHECK(ldm->regs == regs);
+    }
+
+    CHECK(ldm->rn == 7);
+    CHECK(ldm->load == true);
+    CHECK(ldm->write == false);
+    CHECK(ldm->s == true);
+    CHECK(ldm->up == false);
+    CHECK(ldm->pre == true);
+
+    CHECK(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
+
+    ldm->write = true;
+    ldm->s     = false;
+    ldm->up    = true;
+
+    CHECK(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
+
+    ldm->regs &= ~(1 << 6);
+    ldm->regs &= ~(1 << 3);
+    ldm->regs &= ~(1 << 8);
+    ldm->load = false;
+    ldm->pre  = false;
+
+    CHECK(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
+}
+
+TEST_CASE("PSR Transfer", TAG) {
+    PsrTransfer* msr = nullptr;
+
+    SECTION("MRS") {
+        uint32_t raw = 0b01000001010011111010000000000000;
+        Instruction instruction(raw);
+        PsrTransfer* mrs = nullptr;
+
+        REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::MI);
+
+        CHECK(mrs->type == PsrTransfer::Type::Mrs);
+        // Operand is a register in the case of MRS (PSR -> Register)
+        CHECK(mrs->operand == 10);
+        CHECK(mrs->spsr == true);
+
+        CHECK(instruction.disassemble() == "MRSMI R10,SPSR_all");
+    }
+
+    SECTION("MSR") {
+        uint32_t raw = 0b11100001001010011111000000001000;
+        Instruction instruction(raw);
+        PsrTransfer* msr = nullptr;
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::AL);
+
+        CHECK(msr->type == PsrTransfer::Type::Msr);
+        // Operand is a register in the case of MSR (Register -> PSR)
+        CHECK(msr->operand == 8);
+        CHECK(msr->spsr == false);
+
+        CHECK(instruction.disassemble() == "MSR CPSR_all,R8");
+    }
+
+    SECTION("MSR_flg with register operand") {
+        uint32_t raw = 0b01100001001010001111000000001000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::VS);
+
+        CHECK(msr->type == PsrTransfer::Type::Msr_flg);
+        CHECK(msr->imm == 0);
+        CHECK(msr->operand == 8);
+        CHECK(msr->spsr == false);
+
+        CHECK(instruction.disassemble() == "MSRVS CPSR_flg,R8");
+    }
+
+    SECTION("MSR_flg with immediate operand") {
+        uint32_t raw = 0b11100011011010001111011101101000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::AL);
+
+        CHECK(msr->type == PsrTransfer::Type::Msr_flg);
+        CHECK(msr->imm == 1);
+
+        // 104 (32 bits) rotated by 2 * 7
+        CHECK(msr->operand == 27262976);
+        CHECK(msr->spsr == true);
+
+        CHECK(instruction.disassemble() == "MSR SPSR_flg,#27262976");
+    }
+}
+
+TEST_CASE("Data Processing", TAG) {
+    using OpCode = DataProcessing::OpCode;
+
+    uint32_t raw = 0b11100000000111100111101101100001;
+    Instruction instruction(raw);
+    DataProcessing* alu = nullptr;
+    Shift* shift        = nullptr;
+
+    REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    // operand 2 is a shifted register
+    REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
+    CHECK(shift->rm == 1);
+    CHECK(shift->data.immediate == true);
+    CHECK(shift->data.type == ShiftType::ROR);
+    CHECK(shift->data.operand == 22);
+
+    CHECK(alu->rd == 7);
+    CHECK(alu->rn == 14);
+    CHECK(alu->set == true);
+    CHECK(alu->opcode == OpCode::AND);
+
+    CHECK(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
+
+    shift->data.immediate = false;
+    shift->data.operand   = 2;
+    alu->set              = false;
+
+    CHECK(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
+
+    alu->operand = static_cast<uint32_t>(3300012);
+    CHECK(instruction.disassemble() == "AND R7,R14,#3300012");
+
+    SECTION("set-only operations") {
+        alu->set = true;
+
+        alu->opcode = OpCode::TST;
+        CHECK(instruction.disassemble() == "TST R14,#3300012");
+
+        alu->opcode = OpCode::TEQ;
+        CHECK(instruction.disassemble() == "TEQ R14,#3300012");
+
+        alu->opcode = OpCode::CMP;
+        CHECK(instruction.disassemble() == "CMP R14,#3300012");
+
+        alu->opcode = OpCode::CMN;
+        CHECK(instruction.disassemble() == "CMN R14,#3300012");
+    }
+
+    SECTION("destination operations") {
+        alu->opcode = OpCode::EOR;
+        CHECK(instruction.disassemble() == "EOR R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSB;
+        CHECK(instruction.disassemble() == "RSB R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::ADC;
+        CHECK(instruction.disassemble() == "ADC R7,R14,#3300012");
+
+        alu->opcode = OpCode::SBC;
+        CHECK(instruction.disassemble() == "SBC R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSC;
+        CHECK(instruction.disassemble() == "RSC R7,R14,#3300012");
+
+        alu->opcode = OpCode::ORR;
+        CHECK(instruction.disassemble() == "ORR R7,R14,#3300012");
+
+        alu->opcode = OpCode::MOV;
+        CHECK(instruction.disassemble() == "MOV R7,#3300012");
+
+        alu->opcode = OpCode::BIC;
+        CHECK(instruction.disassemble() == "BIC R7,R14,#3300012");
+
+        alu->opcode = OpCode::MVN;
+        CHECK(instruction.disassemble() == "MVN R7,#3300012");
+    }
+}
+
+TEST_CASE("Coprocessor Data Transfer", TAG) {
+    uint32_t raw = 0b10101101101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataTransfer* ldc = nullptr;
+
+    REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::GE);
+
+    CHECK(ldc->offset == 70);
+    CHECK(ldc->cpn == 1);
+    CHECK(ldc->crd == 15);
+    CHECK(ldc->rn == 5);
+    CHECK(ldc->load == false);
+    CHECK(ldc->write == true);
+    CHECK(ldc->len == false);
+    CHECK(ldc->up == true);
+    CHECK(ldc->pre == true);
+
+    CHECK(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
+
+    ldc->load  = true;
+    ldc->pre   = false;
+    ldc->write = false;
+    ldc->len   = true;
+
+    CHECK(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
+}
+
+TEST_CASE("Coprocessor Operand Operation", TAG) {
+    uint32_t raw = 0b11101110101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataOperation* cdp = nullptr;
+
+    REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    CHECK(cdp->crm == 6);
+    CHECK(cdp->cp == 2);
+    CHECK(cdp->cpn == 1);
+    CHECK(cdp->crd == 15);
+    CHECK(cdp->crn == 5);
+    CHECK(cdp->cp_opc == 10);
+
+    CHECK(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
+}
+
+TEST_CASE("Coprocessor Register Transfer", TAG) {
+    uint32_t raw = 0b11101110101001011111000101010110;
+    Instruction instruction(raw);
+    CoprocessorRegisterTransfer* mrc = nullptr;
+
+    REQUIRE(
+      (mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    CHECK(mrc->crm == 6);
+    CHECK(mrc->cp == 2);
+    CHECK(mrc->cpn == 1);
+    CHECK(mrc->rd == 15);
+    CHECK(mrc->crn == 5);
+    CHECK(mrc->load == false);
+    CHECK(mrc->cp_opc == 5);
+
+    CHECK(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
+}
+
+TEST_CASE("Software Interrupt", TAG) {
+    uint32_t raw = 0b00001111101010101010101010101010;
+    Instruction instruction(raw);
+
+    CHECK(instruction.condition == Condition::EQ);
+    CHECK(instruction.disassemble() == "SWIEQ");
+}
+
+#undef TAG

tests/cpu/arm/meson.build

@@ -0,0 +1,4 @@
+tests_sources += files(
+  'instruction.cc',
+  'exec.cc'
+)

tests/cpu/instruction.cc

@@ -1,468 +0,0 @@
-#include "cpu/instruction.hh"
-#include "cpu/utility.hh"
-#include <catch2/catch_test_macros.hpp>
-#include <cstdint>
-
-[[maybe_unused]] static constexpr auto TAG = "disassembler";
-
-using namespace arm;
-
-TEST_CASE("Branch and Exchange", TAG) {
-    uint32_t raw = 0b11000001001011111111111100011010;
-    Instruction instruction(raw);
-    BranchAndExchange* bx = nullptr;
-
-    REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::GT);
-
-    REQUIRE(bx->rn == 10);
-
-    REQUIRE(instruction.disassemble() == "BXGT R10");
-}
-
-TEST_CASE("Branch", TAG) {
-    uint32_t raw = 0b11101011100001010111111111000011;
-    Instruction instruction(raw);
-    Branch* b = nullptr;
-
-    REQUIRE((b = std::get_if<Branch>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::AL);
-
-    // last 24 bits = 8748995
-    // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
-    // Also +8 since PC is two instructions ahead
-    REQUIRE(b->offset == 0xFE15FF14);
-    REQUIRE(b->link == true);
-
-    REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
-
-    b->link = false;
-    REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
-}
-
-TEST_CASE("Multiply", TAG) {
-    uint32_t raw = 0b00000000001110101110111110010000;
-    Instruction instruction(raw);
-    Multiply* mul = nullptr;
-
-    REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::EQ);
-
-    REQUIRE(mul->rm == 0);
-    REQUIRE(mul->rs == 15);
-    REQUIRE(mul->rn == 14);
-    REQUIRE(mul->rd == 10);
-    REQUIRE(mul->acc == true);
-    REQUIRE(mul->set == true);
-
-    REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
-
-    mul->acc = false;
-    mul->set = false;
-    REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
-}
-
-TEST_CASE("Multiply Long", TAG) {
-    uint32_t raw = 0b00010000100111100111011010010010;
-    Instruction instruction(raw);
-    MultiplyLong* mull = nullptr;
-
-    REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::NE);
-
-    REQUIRE(mull->rm == 2);
-    REQUIRE(mull->rs == 6);
-    REQUIRE(mull->rdlo == 7);
-    REQUIRE(mull->rdhi == 14);
-    REQUIRE(mull->acc == false);
-    REQUIRE(mull->set == true);
-    REQUIRE(mull->uns == false);
-
-    REQUIRE(instruction.disassemble() == "SMULLNES R7,R14,R2,R6");
-
-    mull->acc = true;
-    REQUIRE(instruction.disassemble() == "SMLALNES R7,R14,R2,R6");
-
-    mull->uns = true;
-    mull->set = false;
-    REQUIRE(instruction.disassemble() == "UMLALNE R7,R14,R2,R6");
-}
-
-TEST_CASE("Undefined", TAG) {
-    // notice how this is the same as single data transfer except the shift
-    // is now a register based shift
-    uint32_t raw = 0b11100111101000101010111100010110;
-    Instruction instruction(raw);
-
-    REQUIRE(instruction.condition == Condition::AL);
-    REQUIRE(instruction.disassemble() == "UND");
-}
-
-TEST_CASE("Single Data Swap", TAG) {
-    uint32_t raw = 0b10100001000010010101000010010110;
-    Instruction instruction(raw);
-    SingleDataSwap* swp = nullptr;
-
-    REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::GE);
-
-    REQUIRE(swp->rm == 6);
-    REQUIRE(swp->rd == 5);
-    REQUIRE(swp->rn == 9);
-    REQUIRE(swp->byte == false);
-
-    REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
-
-    swp->byte = true;
-    REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
-}
-
-TEST_CASE("Single Data Transfer", TAG) {
-    uint32_t raw = 0b11100111101000101010111100000110;
-    Instruction instruction(raw);
-    SingleDataTransfer* ldr = nullptr;
-    Shift* shift            = nullptr;
-
-    REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::AL);
-
-    REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
-    REQUIRE(shift->rm == 6);
-    REQUIRE(shift->data.immediate == true);
-    REQUIRE(shift->data.type == ShiftType::LSL);
-    REQUIRE(shift->data.operand == 30);
-    REQUIRE(ldr->rd == 10);
-    REQUIRE(ldr->rn == 2);
-    REQUIRE(ldr->load == false);
-    REQUIRE(ldr->write == true);
-    REQUIRE(ldr->byte == false);
-    REQUIRE(ldr->up == true);
-    REQUIRE(ldr->pre == true);
-
-    ldr->load        = true;
-    ldr->byte        = true;
-    ldr->write       = false;
-    shift->data.type = ShiftType::ROR;
-    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
-
-    ldr->up  = false;
-    ldr->pre = false;
-    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
-
-    ldr->offset = static_cast<uint16_t>(9023);
-    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
-
-    ldr->pre = true;
-    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
-}
-
-TEST_CASE("Halfword Transfer", TAG) {
-    uint32_t raw = 0b00110001101011110010000010110110;
-    Instruction instruction(raw);
-    HalfwordTransfer* ldr = nullptr;
-
-    REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::CC);
-
-    // offset is not immediate
-    REQUIRE(ldr->imm == 0);
-    // hence this offset is a register number (rm)
-    REQUIRE(ldr->offset == 6);
-    REQUIRE(ldr->half == true);
-    REQUIRE(ldr->sign == false);
-    REQUIRE(ldr->rd == 2);
-    REQUIRE(ldr->rn == 15);
-    REQUIRE(ldr->load == false);
-    REQUIRE(ldr->write == true);
-    REQUIRE(ldr->up == true);
-    REQUIRE(ldr->pre == true);
-
-    REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
-
-    ldr->pre  = false;
-    ldr->load = true;
-    ldr->sign = true;
-    ldr->up   = false;
-
-    REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
-
-    ldr->half = false;
-    REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
-
-    ldr->load = false;
-    // not a register anymore
-    ldr->imm    = 1;
-    ldr->offset = 90;
-    REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
-}
-
-TEST_CASE("Block Data Transfer", TAG) {
-    uint32_t raw = 0b10011001010101110100000101101101;
-    Instruction instruction(raw);
-    BlockDataTransfer* ldm = nullptr;
-
-    REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::LS);
-
-    {
-        uint16_t regs = 0;
-        regs |= 1 << 0;
-        regs |= 1 << 2;
-        regs |= 1 << 3;
-        regs |= 1 << 5;
-        regs |= 1 << 6;
-        regs |= 1 << 8;
-        regs |= 1 << 14;
-
-        REQUIRE(ldm->regs == regs);
-    }
-
-    REQUIRE(ldm->rn == 7);
-    REQUIRE(ldm->load == true);
-    REQUIRE(ldm->write == false);
-    REQUIRE(ldm->s == true);
-    REQUIRE(ldm->up == false);
-    REQUIRE(ldm->pre == true);
-
-    REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
-
-    ldm->write = true;
-    ldm->s     = false;
-    ldm->up    = true;
-
-    REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
-
-    ldm->regs &= ~(1 << 6);
-    ldm->regs &= ~(1 << 3);
-    ldm->regs &= ~(1 << 8);
-    ldm->load = false;
-    ldm->pre  = false;
-
-    REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
-}
-
-TEST_CASE("PSR Transfer", TAG) {
-    PsrTransfer* msr = nullptr;
-
-    SECTION("MRS") {
-        uint32_t raw = 0b01000001010011111010000000000000;
-        Instruction instruction(raw);
-        PsrTransfer* mrs = nullptr;
-
-        REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
-        REQUIRE(instruction.condition == Condition::MI);
-
-        REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
-        // Operand is a register in the case of MRS (PSR -> Register)
-        REQUIRE(mrs->operand == 10);
-        REQUIRE(mrs->spsr == true);
-
-        REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
-    }
-
-    SECTION("MSR") {
-        uint32_t raw = 0b11100001001010011111000000001000;
-        Instruction instruction(raw);
-        PsrTransfer* msr = nullptr;
-
-        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
-        REQUIRE(instruction.condition == Condition::AL);
-
-        REQUIRE(msr->type == PsrTransfer::Type::Msr);
-        // Operand is a register in the case of MSR (Register -> PSR)
-        REQUIRE(msr->operand == 8);
-        REQUIRE(msr->spsr == false);
-
-        REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
-    }
-
-    SECTION("MSR_flg with register operand") {
-        uint32_t raw = 0b01100001001010001111000000001000;
-        Instruction instruction(raw);
-
-        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
-        REQUIRE(instruction.condition == Condition::VS);
-
-        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
-        REQUIRE(msr->imm == 0);
-        REQUIRE(msr->operand == 8);
-        REQUIRE(msr->spsr == false);
-
-        REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
-    }
-
-    SECTION("MSR_flg with immediate operand") {
-        uint32_t raw = 0b11100011011010001111011101101000;
-        Instruction instruction(raw);
-
-        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
-        REQUIRE(instruction.condition == Condition::AL);
-
-        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
-        REQUIRE(msr->imm == 1);
-
-        // 104 (32 bits) rotated by 2 * 7
-        REQUIRE(msr->operand == 27262976);
-        REQUIRE(msr->spsr == true);
-
-        REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
-    }
-}
-
-TEST_CASE("Data Processing", TAG) {
-    uint32_t raw = 0b11100010000111100111101101100001;
-    Instruction instruction(raw);
-    DataProcessing* alu = nullptr;
-    Shift* shift        = nullptr;
-
-    REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::AL);
-
-    // operand 2 is a shifted register
-    REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
-    REQUIRE(shift->rm == 1);
-    REQUIRE(shift->data.immediate == true);
-    REQUIRE(shift->data.type == ShiftType::ROR);
-    REQUIRE(shift->data.operand == 22);
-
-    REQUIRE(alu->rd == 7);
-    REQUIRE(alu->rn == 14);
-    REQUIRE(alu->set == true);
-    REQUIRE(alu->opcode == OpCode::AND);
-
-    REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
-
-    shift->data.immediate = false;
-    shift->data.operand   = 2;
-    alu->set              = false;
-
-    REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
-
-    alu->operand = static_cast<uint32_t>(3300012);
-    REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
-
-    SECTION("set-only operations") {
-        alu->set = true;
-
-        alu->opcode = OpCode::TST;
-        REQUIRE(instruction.disassemble() == "TST R14,#3300012");
-
-        alu->opcode = OpCode::TEQ;
-        REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
-
-        alu->opcode = OpCode::CMP;
-        REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
-
-        alu->opcode = OpCode::CMN;
-        REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
-    }
-
-    SECTION("destination operations") {
-        alu->opcode = OpCode::EOR;
-        REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
-
-        alu->opcode = OpCode::SUB;
-        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
-
-        alu->opcode = OpCode::RSB;
-        REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
-
-        alu->opcode = OpCode::SUB;
-        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
-
-        alu->opcode = OpCode::ADC;
-        REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
-
-        alu->opcode = OpCode::SBC;
-        REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
-
-        alu->opcode = OpCode::RSC;
-        REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
-
-        alu->opcode = OpCode::ORR;
-        REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
-
-        alu->opcode = OpCode::MOV;
-        REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
-
-        alu->opcode = OpCode::BIC;
-        REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
-
-        alu->opcode = OpCode::MVN;
-        REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
-    }
-}
-
-TEST_CASE("Coprocessor Data Transfer", TAG) {
-    uint32_t raw = 0b10101101101001011111000101000110;
-    Instruction instruction(raw);
-    CoprocessorDataTransfer* ldc = nullptr;
-
-    REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::GE);
-
-    REQUIRE(ldc->offset == 70);
-    REQUIRE(ldc->cpn == 1);
-    REQUIRE(ldc->crd == 15);
-    REQUIRE(ldc->rn == 5);
-    REQUIRE(ldc->load == false);
-    REQUIRE(ldc->write == true);
-    REQUIRE(ldc->len == false);
-    REQUIRE(ldc->up == true);
-    REQUIRE(ldc->pre == true);
-
-    REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
-
-    ldc->load  = true;
-    ldc->pre   = false;
-    ldc->write = false;
-    ldc->len   = true;
-
-    REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
-}
-
-TEST_CASE("Coprocessor Operand Operation", TAG) {
-    uint32_t raw = 0b11101110101001011111000101000110;
-    Instruction instruction(raw);
-    CoprocessorDataOperation* cdp = nullptr;
-
-    REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::AL);
-
-    REQUIRE(cdp->crm == 6);
-    REQUIRE(cdp->cp == 2);
-    REQUIRE(cdp->cpn == 1);
-    REQUIRE(cdp->crd == 15);
-    REQUIRE(cdp->crn == 5);
-    REQUIRE(cdp->cp_opc == 10);
-
-    REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
-}
-
-TEST_CASE("Coprocessor Register Transfer", TAG) {
-    uint32_t raw = 0b11101110101001011111000101010110;
-    Instruction instruction(raw);
-    CoprocessorRegisterTransfer* mrc = nullptr;
-
-    REQUIRE(
-      (mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
-    REQUIRE(instruction.condition == Condition::AL);
-
-    REQUIRE(mrc->crm == 6);
-    REQUIRE(mrc->cp == 2);
-    REQUIRE(mrc->cpn == 1);
-    REQUIRE(mrc->rd == 15);
-    REQUIRE(mrc->crn == 5);
-    REQUIRE(mrc->load == false);
-    REQUIRE(mrc->cp_opc == 5);
-
-    REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
-}
-
-TEST_CASE("Software Interrupt", TAG) {
-    uint32_t raw = 0b00001111101010101010101010101010;
-    Instruction instruction(raw);
-
-    REQUIRE(instruction.condition == Condition::EQ);
-    REQUIRE(instruction.disassemble() == "SWIEQ");
-}

tests/cpu/meson.build

@@ -1,3 +1 @@
-tests_sources += files(
-  'instruction.cc'
-)
+subdir('arm')

tests/meson.build

@@ -2,18 +2,20 @@ tests_deps = [
   lib
 ]
 
+src = include_directories('../src')
+
 tests_sources = files()
 
 subdir('cpu')
 
 catch2 = dependency('catch2-with-main', version: '>=3.4.0', static: true)
 catch2_tests = executable(
-  meson.project_name() + '_tests',
+  'matar_tests',
   tests_sources,
   dependencies: catch2,
   link_with: tests_deps,
-  include_directories: inc,
-  build_by_default: false
+  include_directories: [inc, src],
+  build_by_default: false,
 )
 
 test('catch2 tests', catch2_tests)