146 lines
3.8 KiB
C++
146 lines
3.8 KiB
C++
#include "cpu-impl.hh"
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#include "util/bits.hh"
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#include "util/log.hh"
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#include <algorithm>
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#include <cstdio>
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using namespace logger;
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namespace matar {
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CpuImpl::CpuImpl(const Bus& bus) noexcept
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: bus(std::make_shared<Bus>(bus))
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, gpr({ 0 })
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, cpsr(0)
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, spsr(0)
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, is_flushed(false)
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, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
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, spsr_banked({ 0, 0, 0, 0, 0 }) {
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cpsr.set_mode(Mode::Supervisor);
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cpsr.set_irq_disabled(true);
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cpsr.set_fiq_disabled(true);
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cpsr.set_state(State::Arm);
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log_info("CPU successfully initialised");
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// PC always points to two instructions ahead
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// PC - 2 is the instruction being executed
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pc += 2 * arm::INSTRUCTION_SIZE;
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}
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/* change modes */
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void
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CpuImpl::chg_mode(const Mode to) {
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Mode from = cpsr.mode();
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if (from == to)
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return;
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/* TODO: replace visible registers with view once I understand how to
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* concatenate views */
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#define STORE_BANKED(mode, MODE) \
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std::copy(gpr.begin() + GPR_##MODE##_FIRST, \
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gpr.begin() + gpr.size() - 1, \
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gpr_banked.mode.begin())
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switch (from) {
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case Mode::Fiq:
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STORE_BANKED(fiq, FIQ);
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spsr_banked.fiq = spsr;
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break;
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case Mode::Supervisor:
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STORE_BANKED(svc, SVC);
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spsr_banked.svc = spsr;
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break;
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case Mode::Abort:
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STORE_BANKED(abt, ABT);
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spsr_banked.abt = spsr;
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break;
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case Mode::Irq:
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STORE_BANKED(irq, IRQ);
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spsr_banked.irq = spsr;
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break;
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case Mode::Undefined:
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STORE_BANKED(und, UND);
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spsr_banked.und = spsr;
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break;
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case Mode::User:
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case Mode::System:
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STORE_BANKED(old, SYS_USR);
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break;
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}
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#define RESTORE_BANKED(mode, MODE) \
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std::copy(gpr_banked.mode.begin(), \
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gpr_banked.mode.end(), \
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gpr.begin() + GPR_##MODE##_FIRST)
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switch (to) {
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case Mode::Fiq:
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RESTORE_BANKED(fiq, FIQ);
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spsr = spsr_banked.fiq;
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break;
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case Mode::Supervisor:
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RESTORE_BANKED(svc, SVC);
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spsr = spsr_banked.svc;
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break;
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case Mode::Abort:
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RESTORE_BANKED(abt, ABT);
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spsr = spsr_banked.abt;
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break;
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case Mode::Irq:
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RESTORE_BANKED(irq, IRQ);
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spsr = spsr_banked.irq;
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break;
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case Mode::Undefined:
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RESTORE_BANKED(und, UND);
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spsr = spsr_banked.und;
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break;
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case Mode::User:
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case Mode::System:
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STORE_BANKED(old, SYS_USR);
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break;
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}
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#undef RESTORE_BANKED
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cpsr.set_mode(to);
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}
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void
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CpuImpl::step() {
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// Current instruction is two instructions behind PC
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uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
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if (cpsr.state() == State::Arm) {
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debug(cur_pc);
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uint32_t x = bus->read_word(cur_pc);
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arm::Instruction instruction(x);
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log_info("{:#034b}", x);
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exec_arm(instruction);
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log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
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if (is_flushed) {
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// if flushed, do not increment the PC, instead set it to two
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// instructions ahead to account for flushed "fetch" and "decode"
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// instructions
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pc += 2 * arm::INSTRUCTION_SIZE;
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is_flushed = false;
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} else {
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// if not flushed continue like normal
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pc += arm::INSTRUCTION_SIZE;
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}
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}
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}
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}
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