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natto1784:master natto1784:thumb natto1784:tests natto1784:build-system natto1784:test-public-api

1 Commits
master ... test-publi

Author SHA1 Message Date
Amneesh Singh
b918b75f27 tests: add some exec tests 
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
 2023-09-18 08:05:21 +05:30
85 changed files with 2120 additions and 9435 deletions
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1
.clang-tidy
View File

@@ -6,5 +6,4 @@ Checks: '
, -cppcoreguidelines-macro-usage
, -cppcoreguidelines-avoid-const-or-ref-data-members
, -cppcoreguidelines-non-private-member-variables-in-classes
, -cppcoreguidelines-avoid-non-const-global-variables
'

36
.github/workflows/clang.yml vendored
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@@ -1,36 +0,0 @@
name: matar-clang
on: [push, pull_request, workflow_dispatch]
env:
BUILDDIR: build
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: cachix/install-nix-action@v27
with:
extra_nix_config: |
auto-optimise-store = true
experimental-features = nix-command flakes
- uses: cachix/cachix-action@v15
with:
name: pain
authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
- name: setup
run: nix develop .#matar-clang -c meson setup $BUILDDIR -Dgdb_debug=true
- name: fmt
run: nix develop .#matar-clang -c ninja clang-format-check -C $BUILDDIR
- name: lint
run: nix develop .#matar-clang -c ninja clang-tidy -C $BUILDDIR
- name: build
run: nix develop .#matar-clang -c ninja -C $BUILDDIR
- name: tests
run: nix develop .#matar-clang -c ninja test -C $BUILDDIR

30
.github/workflows/gcc.yml vendored
View File

@@ -1,30 +0,0 @@
name: matar-gcc
on: [push, pull_request, workflow_dispatch]
env:
BUILDDIR: build
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: cachix/install-nix-action@v27
with:
extra_nix_config: |
auto-optimise-store = true
experimental-features = nix-command flakes
- uses: cachix/cachix-action@v15
with:
name: pain
authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
- name: setup
run: nix develop .#matar -c meson setup $BUILDDIR -Dgdb_debug=true
- name: build
run: nix develop .#matar -c ninja -C $BUILDDIR
- name: tests
run: nix develop .#matar -c ninja test -C $BUILDDIR

31
.github/workflows/main.yml vendored Normal file
View File

@@ -0,0 +1,31 @@
name: matar
on: [push, pull_request, workflow_dispatch]
env:
BUILDDIR: build
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: cachix/install-nix-action@v20
with:
extra_nix_config: |
auto-optimise-store = true
experimental-features = nix-command flakes
- name: setup
run: nix develop -c meson setup $BUILDDIR
- name: fmt
run: nix develop -c ninja clang-format-check -C $BUILDDIR
- name: lint
run: nix develop -c ninja clang-tidy -C $BUILDDIR
- name: tests
run: nix develop -c ninja test -C $BUILDDIR
- name: build
run: nix develop -c ninja -C $BUILDDIR

2
.gitignore vendored
View File

@@ -3,5 +3,5 @@ result
build/
.cache/
*~
\#*\#
#*#
.#*

75
README.md
View File

@@ -5,77 +5,18 @@ But if you are curious (probably not), read ahead
# Dependencies
## Tested toolchains
- LLVM 18.1.7
- GCC 14.1.0
- LLVM 16.0.6
- GCC 12.3.0
In theory, any toolchain supporting at least the c++23 standard should work.
In theory, any toolchain supporting at least the C++20 standard should work.
I am using LLVM's clang and libcxx as the primary toolchain.
## Static libraries
| Name | Version | Required? | Purpose |
|:------:|:--------|:---------:|:---------:|
| catch2 | >= 3.4 | no | for tests |
| Name | Version | Required? |
|:------:|:----------|:---------:|
| fmt | >= 10.1.1 | yes |
| catch2 | >= 3.4 | for tests |
This goes without saying but using a different toolchain to compile these libraries before linking probably won't work.
# Status
- [x] CPU
- [x] Arm
- [x] Dissassembler
- [x] Execution
- [x] Thumb
- [x] Dissassembler
- [x] Execution
- [ ] Bus
- [x] Cycle counting with CPU
- [x] Reading memory
- [x] Writing memory
- [ ] Scheduler (maybe?)
- [ ] Sync PPU and CPU
- [ ] Sync APU and CPU
- [ ] Sync other stuff
- [ ] I/O
- [ ] PPU
- [ ] APU
- [ ] Timers
- [ ] DMA
- [ ] Keypad
- Debugging
- [x] GDB Remote Serial Protocol support
- Misc
- [ ] Save/Load states
- [x] Header Parsing
- Internal utilities
- [x] Bit manipulation
- [x] A global logger
- [x] TCP Server (for GDB RSP)
- [x] SHA256 hash (why? idk)
## Available unit tests so far
- CPU
- Arm
- Disassembler
- Execution
- Thumb
- Disassembler
- Execution
- Bus
- Memory read/writes
- Cycle Counting
- Some internal utility tests (idk why)
-----
# LOG
- June 11, 2024: After almost an year, I have come back to this silly abandoned project, will probably complete it soon.
- June 16, 2024: I ought to complete this soon
I will add meson wrap support once LLVM 17 is out, since I want to get rid of fmt.

22
apps/target/main.cc
View File

@@ -1,13 +1,13 @@
#include "bus.hh"
#include "cpu/cpu.hh"
#include "util/loglevel.hh"
#include "memory.hh"
#include <array>
#include <chrono>
#include <cstdlib>
#include <fstream>
#include <iostream>
#include <memory>
#include <thread>
#include <ostream>
#include <unistd.h>
#include <vector>
// NOLINTBEGIN
@@ -15,7 +15,7 @@
int
main(int argc, const char* argv[]) {
std::vector<uint8_t> rom;
std::array<uint8_t, matar::Bus::BIOS_SIZE> bios = { 0 };
std::array<uint8_t, Memory::BIOS_SIZE> bios = { 0 };
auto usage = [argv]() {
std::cerr << "Usage: " << argv[0] << " <file> [-b <bios>]" << std::endl;
@@ -65,7 +65,7 @@ main(int argc, const char* argv[]) {
ifile.seekg(0, std::ios::end);
bios_size = ifile.tellg();
if (bios_size != matar::Bus::BIOS_SIZE) {
if (bios_size != Memory::BIOS_SIZE) {
throw std::ios::failure("BIOS file has invalid size",
std::error_code());
}
@@ -84,17 +84,13 @@ main(int argc, const char* argv[]) {
std::flush(std::cout);
std::flush(std::cout);
matar::set_log_level(matar::LogLevel::Debug);
try {
std::shared_ptr<matar::Bus> bus =
matar::Bus::init(std::move(bios), std::move(rom));
matar::Cpu cpu(bus);
Memory memory(std::move(bios), std::move(rom));
Bus bus(memory);
Cpu cpu(bus);
while (true) {
cpu.step();
// std::this_thread::sleep_for(std::chrono::milliseconds(10));
sleep(1);
}
} catch (const std::exception& e) {
std::cerr << "Exception: " << e.what() << std::endl;

2
apps/target/meson.build
View File

@@ -7,7 +7,7 @@ target_sources = files(
)
executable(
'matar',
meson.project_name(),
target_sources,
link_with: target_deps,
include_directories: inc,

39
flake.lock generated
View File

@@ -1,54 +1,23 @@
{
"nodes": {
"flake-parts": {
"inputs": {
"nixpkgs-lib": "nixpkgs-lib"
},
"locked": {
"lastModified": 1717285511,
"narHash": "sha256-iKzJcpdXih14qYVcZ9QC9XuZYnPc6T8YImb6dX166kw=",
"owner": "hercules-ci",
"repo": "flake-parts",
"rev": "2a55567fcf15b1b1c7ed712a2c6fadaec7412ea8",
"type": "github"
},
"original": {
"owner": "hercules-ci",
"repo": "flake-parts",
"type": "github"
}
},
"nixpkgs": {
"locked": {
"lastModified": 1717868076,
"narHash": "sha256-c83Y9t815Wa34khrux81j8K8ET94ESmCuwORSKm2bQY=",
"lastModified": 1694911158,
"narHash": "sha256-5WENkcO8O5SuA5pozpVppLGByWfHVv/1wOWgB2+TfV4=",
"owner": "nixos",
"repo": "nixpkgs",
"rev": "cd18e2ae9ab8e2a0a8d715b60c91b54c0ac35ff9",
"rev": "46423a1a750594236673c1d741def4e93cf5a8f7",
"type": "github"
},
"original": {
"owner": "nixos",
"ref": "nixpkgs-unstable",
"ref": "master",
"repo": "nixpkgs",
"type": "github"
}
},
"nixpkgs-lib": {
"locked": {
"lastModified": 1717284937,
"narHash": "sha256-lIbdfCsf8LMFloheeE6N31+BMIeixqyQWbSr2vk79EQ=",
"type": "tarball",
"url": "https://github.com/NixOS/nixpkgs/archive/eb9ceca17df2ea50a250b6b27f7bf6ab0186f198.tar.gz"
},
"original": {
"type": "tarball",
"url": "https://github.com/NixOS/nixpkgs/archive/eb9ceca17df2ea50a250b6b27f7bf6ab0186f198.tar.gz"
}
},
"root": {
"inputs": {
"flake-parts": "flake-parts",
"nixpkgs": "nixpkgs"
}
}

87
flake.nix
View File

@@ -2,39 +2,80 @@
description = "matar";
inputs = {
nixpkgs.url = github:nixos/nixpkgs/nixpkgs-unstable;
flake-parts.url = github:hercules-ci/flake-parts;
nixpkgs.url = github:nixos/nixpkgs/master;
};
outputs = inputs@{ self, nixpkgs, flake-parts }:
flake-parts.lib.mkFlake { inherit inputs; } {
outputs = { self, nixpkgs }:
let
systems = [
"x86_64-linux"
"aarch64-linux"
];
imports = [
./nix
];
eachSystem = with nixpkgs.lib; f: foldAttrs mergeAttrs { }
(map (s: mapAttrs (_: v: { ${s} = v; }) (f s)) systems);
in
eachSystem (system:
let
pkgs = import nixpkgs { inherit system; };
perSystem = { self', system, ... }:
let
pkgs = import nixpkgs { inherit system; };
# aliases
llvm = pkgs.llvmPackages_16;
stdenv = llvm.libcxxStdenv;
src = pkgs.lib.sourceFilesBySuffices ./. [
".hh"
".cc"
".build"
".options"
# TODO: this is ugly
#dependencies
nativeBuildInputs = with pkgs;
[
meson
ninja
# libraries
pkg-config
cmake
((pkgs.fmt.override {
inherit stdenv;
enableShared = false;
}).overrideAttrs (oa: {
cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
})).dev
(catch2_3.override { inherit stdenv; }).out
];
in
rec {
_module.args = {
inherit src pkgs;
};
in
rec {
packages = rec {
inherit (llvm) libcxxabi;
matar = stdenv.mkDerivation rec {
name = "matar";
version = "0.1";
src = pkgs.lib.sourceFilesBySuffices ./. [
".hh"
".cc"
".build"
"meson_options.txt"
];
outputs = [ "out" "dev" ];
formatter = pkgs.nixpkgs-fmt;
inherit nativeBuildInputs;
enableParallelBuilding = true;
};
default = matar;
};
};
devShells = rec {
matar = pkgs.mkShell.override { inherit stdenv; } {
name = "matar";
packages = nativeBuildInputs ++ (with pkgs; [
# lsp
clang-tools_16
]);
};
default = matar;
};
formatter = pkgs.nixpkgs-fmt;
});
}

106
include/bus.hh
View File

@@ -1,111 +1,21 @@
#pragma once
#include "header.hh"
#include "io/io.hh"
#include "memory.hh"
#include <memory>
#include <vector>
namespace matar {
enum CpuAccess {
Sequential,
NonSequential
};
enum CpuAccessWidth {
Word,
Halfword,
Byte
};
class Bus {
private:
struct Private {
explicit Private() = default;
};
public:
static constexpr uint32_t BIOS_SIZE = 1024 * 16;
Bus(const Memory& memory);
Bus(Private, std::array<uint8_t, BIOS_SIZE>&&, std::vector<uint8_t>&&);
uint8_t read_byte(size_t address);
void write_byte(size_t address, uint8_t byte);
static std::shared_ptr<Bus> init(std::array<uint8_t, BIOS_SIZE>&&,
std::vector<uint8_t>&&);
uint16_t read_halfword(size_t address);
void write_halfword(size_t address, uint16_t halfword);
uint8_t read_byte(uint32_t address, CpuAccess access) {
add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
return read_byte(address);
};
void write_byte(uint32_t address, uint8_t byte, CpuAccess access) {
add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
write_byte(address, byte);
};
uint16_t read_halfword(uint32_t address, CpuAccess access) {
add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
return read_halfword(address);
}
void write_halfword(uint32_t address, uint16_t halfword, CpuAccess access) {
add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
write_halfword(address, halfword);
}
uint32_t read_word(uint32_t address, CpuAccess access) {
add_cpu_cycles<CpuAccessWidth::Word>(address, access);
return read_word(address);
}
void write_word(uint32_t address, uint32_t word, CpuAccess access) {
add_cpu_cycles<CpuAccessWidth::Word>(address, access);
write_word(address, word);
}
uint8_t read_byte(uint32_t address);
void write_byte(uint32_t address, uint8_t byte);
uint16_t read_halfword(uint32_t address);
void write_halfword(uint32_t address, uint16_t halfword);
uint32_t read_word(uint32_t address);
void write_word(uint32_t address, uint32_t word);
// not sure what else to do?
void internal_cycle() { cycles++; }
uint32_t get_cycles() { return cycles; }
uint32_t read_word(size_t address);
void write_word(size_t address, uint32_t word);
private:
template<CpuAccessWidth W>
void add_cpu_cycles(uint32_t address, CpuAccess access) {
auto cc = cycle_map[address >> 24 & 0xF];
if constexpr (W == CpuAccessWidth::Word) {
cycles += (access == CpuAccess::Sequential ? cc.s32 : cc.n32);
} else {
cycles += (access == CpuAccess::Sequential ? cc.s16 : cc.n16);
}
}
template<typename T>
T read(uint32_t address) const;
template<typename T>
void write(uint32_t address, T value);
uint32_t cycles = 0;
struct cycle_count {
uint8_t n16; // non sequential 8/16 bit width access
uint8_t n32; // non sequential 32 bit width access
uint8_t s16; // seuquential 8/16 bit width access
uint8_t s32; // sequential 32 bit width access
};
std::array<cycle_count, 0x10> cycle_map;
static constexpr decltype(cycle_map) init_cycle_count();
std::unique_ptr<IoDevices> io;
Memory<BIOS_SIZE> bios = {};
Memory<0x40000> board_wram = {};
Memory<0x80000> chip_wram = {};
Memory<> rom;
Header header;
void parse_header();
std::shared_ptr<Memory> memory;
};
}

55
include/cpu/alu.hh
View File

@@ -1,55 +0,0 @@
#pragma once
#include <cstdint>
namespace matar {
enum class ShiftType {
LSL = 0b00,
LSR = 0b01,
ASR = 0b10,
ROR = 0b11
};
constexpr auto
stringify(ShiftType shift_type) {
#define CASE(type) \
case ShiftType::type: \
return #type;
switch (shift_type) {
CASE(LSL)
CASE(LSR)
CASE(ASR)
CASE(ROR)
}
#undef CASE
return "";
}
struct ShiftData {
ShiftType type;
bool immediate;
uint8_t operand;
};
struct Shift {
uint8_t rm;
ShiftData data;
};
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry);
uint32_t
sub(uint32_t a, uint32_t b, bool& carry, bool& overflow);
uint32_t
add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
uint32_t
sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
uint8_t
multiplier_array_cycles(uint32_t x, bool zeroes_only = false);
}

85
include/cpu/arm/instruction.hh
View File

@@ -1,16 +1,7 @@
#pragma once
#include "cpu/alu.hh"
#include "cpu/psr.hh"
#include "cpu/utility.hh"
#include <cstdint>
#include <string>
#include <variant>
namespace matar {
class Cpu;
namespace arm {
// https://en.cppreference.com/w/cpp/utility/variant/visit
template<class... Ts>
struct overloaded : Ts... {
using Ts::operator()...;
@@ -18,15 +9,14 @@ struct overloaded : Ts... {
template<class... Ts>
overloaded(Ts...) -> overloaded<Ts...>;
static constexpr size_t INSTRUCTION_SIZE = 4;
namespace arm {
struct BranchAndExchange {
uint8_t rn;
};
struct Branch {
bool link;
int32_t offset;
uint32_t offset;
};
struct Multiply {
@@ -90,25 +80,6 @@ struct BlockDataTransfer {
};
struct DataProcessing {
enum class OpCode {
AND = 0b0000,
EOR = 0b0001,
SUB = 0b0010,
RSB = 0b0011,
ADD = 0b0100,
ADC = 0b0101,
SBC = 0b0110,
RSC = 0b0111,
TST = 0b1000,
TEQ = 0b1001,
CMP = 0b1010,
CMN = 0b1011,
ORR = 0b1100,
MOV = 0b1101,
BIC = 0b1110,
MVN = 0b1111
};
std::variant<Shift, uint32_t> operand;
uint8_t rd;
uint8_t rn;
@@ -116,37 +87,6 @@ struct DataProcessing {
OpCode opcode;
};
constexpr auto
stringify(DataProcessing::OpCode opcode) {
#define CASE(opcode) \
case DataProcessing::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(SUB)
CASE(RSB)
CASE(ADD)
CASE(ADC)
CASE(SBC)
CASE(RSC)
CASE(TST)
CASE(TEQ)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MOV)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return "";
}
struct PsrTransfer {
enum class Type {
Mrs,
@@ -212,19 +152,14 @@ using InstructionData = std::variant<BranchAndExchange,
SoftwareInterrupt>;
struct Instruction {
Instruction(uint32_t insn);
Instruction(Condition condition, InstructionData data)
: condition(condition)
, data(data) {};
void exec(Cpu& cpu);
#ifdef DISASSEMBLER
std::string disassemble();
#endif
Condition condition;
InstructionData data;
Instruction(uint32_t insn);
Instruction(Condition condition, InstructionData data) noexcept
: condition(condition)
, data(data){};
std::string disassemble();
};
}
}

2
include/cpu/arm/meson.build
View File

@@ -1,3 +1,3 @@
headers += files(
'instruction.hh'
'instruction.hh',
)

106
include/cpu/cpu.hh
View File

@@ -2,72 +2,43 @@
#include "arm/instruction.hh"
#include "bus.hh"
#include "cpu/psr.hh"
#include "thumb/instruction.hh"
#include "psr.hh"
#include <cstdint>
#include <memory>
#ifdef GDB_DEBUG
#include <unordered_set>
#endif
namespace matar {
#ifdef GDB_DEBUG
class GdbRsp;
#endif
using std::size_t;
class Cpu {
public:
Cpu(std::shared_ptr<Bus> bus) noexcept;
Cpu(const Bus& bus);
void step();
void chg_mode(const Mode to);
void exec(arm::Instruction& instruction);
void exec(thumb::Instruction& instruction);
#ifdef GDB_DEBUG
bool breakpoint_reached() {
if (breakpoints.contains(pc - 2 * (cpsr.state() == State::Arm
? arm::INSTRUCTION_SIZE
: thumb::INSTRUCTION_SIZE))) {
return true;
}
return false;
}
#endif
private:
friend void arm::Instruction::exec(Cpu& cpu);
friend void thumb::Instruction::exec(Cpu& cpu);
static constexpr uint8_t GPR_COUNT = 16;
static constexpr uint8_t GPR_FIQ_FIRST = 8;
static constexpr uint8_t GPR_SVC_FIRST = 13;
static constexpr uint8_t GPR_ABT_FIRST = 13;
static constexpr uint8_t GPR_IRQ_FIRST = 13;
static constexpr uint8_t GPR_UND_FIRST = 13;
static constexpr uint8_t GPR_OLD_FIRST = 8;
static constexpr uint8_t GPR_FIQ_FIRST = 8;
static constexpr uint8_t GPR_SVC_FIRST = 13;
static constexpr uint8_t GPR_ABT_FIRST = 13;
static constexpr uint8_t GPR_IRQ_FIRST = 13;
static constexpr uint8_t GPR_UND_FIRST = 13;
static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
std::shared_ptr<Bus> bus;
std::array<uint32_t, GPR_COUNT> gpr = {}; // general purpose registers
std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
Psr cpsr = {}; // current program status register
Psr spsr = {}; // status program status register
static constexpr uint8_t SP_INDEX = 13;
static_assert(SP_INDEX < GPR_COUNT);
uint32_t& sp = gpr[SP_INDEX];
static constexpr uint8_t LR_INDEX = 14;
static_assert(LR_INDEX < GPR_COUNT);
uint32_t& lr = gpr[LR_INDEX];
Psr cpsr; // current program status register
Psr spsr; // status program status register
static constexpr uint8_t PC_INDEX = 15;
static_assert(PC_INDEX < GPR_COUNT);
uint32_t& pc = gpr[PC_INDEX];
bool is_flushed;
void chg_mode(const Mode to);
void exec_arm(const arm::Instruction instruction);
struct {
std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
@@ -76,8 +47,8 @@ class Cpu {
std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
// visible registers before the mode switch
std::array<uint32_t, GPR_COUNT - GPR_OLD_FIRST - 1> old;
} gpr_banked = {}; // banked general purpose registers
std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
} gpr_banked; // banked general purpose registers
struct {
Psr fiq;
@@ -85,38 +56,5 @@ class Cpu {
Psr abt;
Psr irq;
Psr und;
} spsr_banked = {}; // banked saved program status registers
void internal_cycle() { bus->internal_cycle(); }
// whether read is going to be sequential or not
CpuAccess next_access = CpuAccess::Sequential;
// raw instructions in the pipeline
std::array<uint32_t, 2> opcodes = {};
void advance_pc_arm();
void advance_pc_thumb();
template<State S>
void flush_pipeline() {
if constexpr (S == State::Arm) {
opcodes[0] = bus->read_word(pc, CpuAccess::NonSequential);
advance_pc_arm();
opcodes[1] = bus->read_word(pc, CpuAccess::Sequential);
advance_pc_arm();
} else {
opcodes[0] = bus->read_halfword(pc, CpuAccess::NonSequential);
advance_pc_thumb();
opcodes[1] = bus->read_halfword(pc, CpuAccess::Sequential);
advance_pc_thumb();
}
next_access = CpuAccess::Sequential;
}
#ifdef GDB_DEBUG
friend class GdbRsp;
std::unordered_set<uint32_t> breakpoints = {};
#endif
} spsr_banked; // banked saved program status registers
};
}

5
include/cpu/meson.build
View File

@@ -1,8 +1,7 @@
headers += files(
'alu.hh',
'cpu.hh',
'psr.hh'
'psr.hh',
'utility.hh'
)
subdir('arm')
subdir('thumb')

72
include/cpu/psr.hh
View File

@@ -1,77 +1,11 @@
#pragma once
#include "utility.hh"
#include <cstdint>
namespace matar {
enum class Mode {
/* M[4:0] in PSR */
User = 0b10000,
Fiq = 0b10001,
Irq = 0b10010,
Supervisor = 0b10011,
Abort = 0b10111,
Undefined = 0b11011,
System = 0b11111,
};
enum class State {
Arm = 0,
Thumb = 1
};
enum class Condition {
EQ = 0b0000,
NE = 0b0001,
CS = 0b0010,
CC = 0b0011,
MI = 0b0100,
PL = 0b0101,
VS = 0b0110,
VC = 0b0111,
HI = 0b1000,
LS = 0b1001,
GE = 0b1010,
LT = 0b1011,
GT = 0b1100,
LE = 0b1101,
AL = 0b1110
};
constexpr auto
stringify(Condition cond) {
#define CASE(cond) \
case Condition::cond: \
return #cond;
switch (cond) {
CASE(EQ)
CASE(NE)
CASE(CS)
CASE(CC)
CASE(MI)
CASE(PL)
CASE(VS)
CASE(VC)
CASE(HI)
CASE(LS)
CASE(GE)
CASE(LT)
CASE(GT)
CASE(LE)
case Condition::AL: {
return "";
}
}
#undef CASE
return "";
}
class Psr {
public:
Psr() = default;
// clear the reserved bits i.e, [8:27]
Psr(uint32_t raw);
uint32_t raw() const;
@@ -115,7 +49,7 @@ class Psr {
private:
static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
static constexpr uint32_t PSR_CLEAR_MODE = 0xFFFFFFE0;
uint32_t psr;
};
}

291
include/cpu/thumb/instruction.hh
View File

@@ -1,291 +0,0 @@
#pragma once
#include "cpu/alu.hh"
#include "cpu/psr.hh"
#include <cstdint>
#include <string>
#include <variant>
namespace matar {
class Cpu;
namespace thumb {
// https://en.cppreference.com/w/cpp/utility/variant/visit
template<class... Ts>
struct overloaded : Ts... {
using Ts::operator()...;
};
template<class... Ts>
overloaded(Ts...) -> overloaded<Ts...>;
static constexpr size_t INSTRUCTION_SIZE = 2;
static constexpr uint8_t LO_GPR_COUNT = 8;
struct MoveShiftedRegister {
uint8_t rd;
uint8_t rs;
uint8_t offset;
ShiftType opcode;
};
struct AddSubtract {
enum class OpCode {
ADD = 0,
SUB = 1
};
uint8_t rd;
uint8_t rs;
uint8_t offset;
OpCode opcode;
bool imm;
};
constexpr auto
stringify(AddSubtract::OpCode opcode) {
#define CASE(opcode) \
case AddSubtract::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(ADD)
CASE(SUB)
}
#undef CASE
return "";
}
struct MovCmpAddSubImmediate {
enum class OpCode {
MOV = 0b00,
CMP = 0b01,
ADD = 0b10,
SUB = 0b11
};
uint8_t offset;
uint8_t rd;
OpCode opcode;
};
constexpr auto
stringify(MovCmpAddSubImmediate::OpCode opcode) {
#define CASE(opcode) \
case MovCmpAddSubImmediate::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(MOV)
CASE(CMP)
CASE(ADD)
CASE(SUB)
}
#undef CASE
return "";
}
struct AluOperations {
enum class OpCode {
AND = 0b0000,
EOR = 0b0001,
LSL = 0b0010,
LSR = 0b0011,
ASR = 0b0100,
ADC = 0b0101,
SBC = 0b0110,
ROR = 0b0111,
TST = 0b1000,
NEG = 0b1001,
CMP = 0b1010,
CMN = 0b1011,
ORR = 0b1100,
MUL = 0b1101,
BIC = 0b1110,
MVN = 0b1111
};
uint8_t rd;
uint8_t rs;
OpCode opcode;
};
constexpr auto
stringify(AluOperations::OpCode opcode) {
#define CASE(opcode) \
case AluOperations::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(LSL)
CASE(LSR)
CASE(ASR)
CASE(ADC)
CASE(SBC)
CASE(ROR)
CASE(TST)
CASE(NEG)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MUL)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return "";
}
struct HiRegisterOperations {
enum class OpCode {
ADD = 0b00,
CMP = 0b01,
MOV = 0b10,
BX = 0b11
};
uint8_t rd;
uint8_t rs;
OpCode opcode;
};
constexpr auto
stringify(HiRegisterOperations::OpCode opcode) {
#define CASE(opcode) \
case HiRegisterOperations::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(ADD)
CASE(CMP)
CASE(MOV)
CASE(BX)
}
#undef CASE
return "";
}
struct PcRelativeLoad {
uint16_t word;
uint8_t rd;
};
struct LoadStoreRegisterOffset {
uint8_t rd;
uint8_t rb;
uint8_t ro;
bool byte;
bool load;
};
struct LoadStoreSignExtendedHalfword {
uint8_t rd;
uint8_t rb;
uint8_t ro;
bool s;
bool h;
};
struct LoadStoreImmediateOffset {
uint8_t rd;
uint8_t rb;
uint8_t offset;
bool load;
bool byte;
};
struct LoadStoreHalfword {
uint8_t rd;
uint8_t rb;
uint8_t offset;
bool load;
};
struct SpRelativeLoad {
uint16_t word;
uint8_t rd;
bool load;
};
struct LoadAddress {
uint16_t word;
uint8_t rd;
bool sp;
};
struct AddOffsetStackPointer {
int16_t word;
};
struct PushPopRegister {
uint8_t regs;
bool pclr;
bool load;
};
struct MultipleLoad {
uint8_t regs;
uint8_t rb;
bool load;
};
struct ConditionalBranch {
int32_t offset;
Condition condition;
};
struct SoftwareInterrupt {
uint8_t vector;
};
struct UnconditionalBranch {
int32_t offset;
};
struct LongBranchWithLink {
uint16_t offset;
bool low;
};
using InstructionData = std::variant<MoveShiftedRegister,
AddSubtract,
MovCmpAddSubImmediate,
AluOperations,
HiRegisterOperations,
PcRelativeLoad,
LoadStoreRegisterOffset,
LoadStoreSignExtendedHalfword,
LoadStoreImmediateOffset,
LoadStoreHalfword,
SpRelativeLoad,
LoadAddress,
AddOffsetStackPointer,
PushPopRegister,
MultipleLoad,
ConditionalBranch,
SoftwareInterrupt,
UnconditionalBranch,
LongBranchWithLink>;
struct Instruction {
Instruction(uint16_t insn);
Instruction(InstructionData data)
: data(data) {}
void exec(Cpu& cpu);
#ifdef DISASSEMBLER
std::string disassemble();
#endif
InstructionData data;
};
}
}

3
include/cpu/thumb/meson.build
View File

@@ -1,3 +0,0 @@
headers += files(
'instruction.hh'
)

99
include/cpu/utility.hh Normal file
View File

@@ -0,0 +1,99 @@
#pragma once
#include <fmt/ostream.h>
#include <ostream>
static constexpr size_t ARM_INSTRUCTION_SIZE = 4;
static constexpr size_t THUMB_INSTRUCTION_SIZE = 2;
enum class Mode {
/* M[4:0] in PSR */
User = 0b10000,
Fiq = 0b10001,
Irq = 0b10010,
Supervisor = 0b10011,
Abort = 0b10111,
Undefined = 0b11011,
System = 0b11111,
};
enum class State {
Arm = 0,
Thumb = 1
};
enum class Condition {
EQ = 0b0000,
NE = 0b0001,
CS = 0b0010,
CC = 0b0011,
MI = 0b0100,
PL = 0b0101,
VS = 0b0110,
VC = 0b0111,
HI = 0b1000,
LS = 0b1001,
GE = 0b1010,
LT = 0b1011,
GT = 0b1100,
LE = 0b1101,
AL = 0b1110
};
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const Condition cond);
template<>
struct fmt::formatter<Condition> : ostream_formatter {};
enum class OpCode {
AND = 0b0000,
EOR = 0b0001,
SUB = 0b0010,
RSB = 0b0011,
ADD = 0b0100,
ADC = 0b0101,
SBC = 0b0110,
RSC = 0b0111,
TST = 0b1000,
TEQ = 0b1001,
CMP = 0b1010,
CMN = 0b1011,
ORR = 0b1100,
MOV = 0b1101,
BIC = 0b1110,
MVN = 0b1111
};
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const OpCode cond);
template<>
struct fmt::formatter<OpCode> : ostream_formatter {};
enum class ShiftType {
LSL = 0b00,
LSR = 0b01,
ASR = 0b10,
ROR = 0b11
};
struct ShiftData {
ShiftType type;
bool immediate;
uint8_t operand;
};
struct Shift {
uint8_t rm;
ShiftData data;
};
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const ShiftType cond);
template<>
struct fmt::formatter<ShiftType> : ostream_formatter {};

4
include/header.hh
View File

@@ -3,10 +3,7 @@
#include <cstdint>
#include <string>
namespace matar {
struct Header {
static constexpr uint8_t HEADER_SIZE = 192;
enum class UniqueCode {
Old, // old games
New, // new games
@@ -45,4 +42,3 @@ struct Header {
uint32_t multiboot_entrypoint;
uint8_t slave_id;
};
}

159
include/io/display/display.hh
View File

@@ -1,159 +0,0 @@
#include "memory.hh"
#include <array>
#include <bit>
#include <cstdint>
#include <sys/types.h>
// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
namespace matar {
namespace display {
static constexpr int LCD_WIDTH = 240;
// there are 5 modes
static constexpr uint N_MODES = 6;
// there are 4 backgrounds that can be layered depending on mode
// there is also 1 object layer
static constexpr uint N_BACKGROUNDS = 4;
static constexpr uint32_t PRAM_START = 0x5000000;
static constexpr uint32_t VRAM_START = 0x6000000;
static constexpr uint32_t OAM_START = 0x7000000;
template<typename T, typename = std::enable_if_t<std::is_arithmetic_v<T>>>
struct Point {
T x;
T y;
};
struct Color {
public:
Color(uint16_t raw)
: red(raw & 0b11111)
, green(raw >> 5 & 0b11111)
, blue(raw >> 10 & 0b11111) {}
uint16_t read() const {
return (red & 0b11111) | ((green << 5) & 0b11111) |
((blue << 10) & 0b11111);
}
private:
uint8_t red;
uint8_t green;
uint8_t blue;
};
struct DisplayControl {
struct {
uint8_t mode : 3;
int : 1; // unused
bool frame_select_1 : 1;
bool hblank_free_interval : 1;
bool obj_character_vram_mapping : 1;
bool forced_blank : 1;
bool screen_display_0 : 1;
bool screen_display_1 : 1;
bool screen_display_2 : 1;
bool screen_display_3 : 1;
bool screen_display_obj : 1;
bool window_display_0 : 1;
bool window_display_1 : 1;
bool obj_window_display : 1;
} value;
uint16_t read() const { return std::bit_cast<uint16_t>(value); };
void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
};
struct DisplayStatus {
struct {
bool vblank_flag : 1;
bool hblank_flag : 1;
bool vcounter_flag : 1;
bool vblank_irq_enable : 1;
bool hblank_irq_enable : 1;
bool vcounter_irq_enable : 1;
int : 2; // unused
uint8_t vcount_setting : 8;
} value;
uint16_t read() const { return std::bit_cast<uint16_t>(value); };
void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
};
struct BackgroundControl {
struct {
uint8_t priority : 2;
uint8_t character_base_block : 2;
int : 2; // unused
bool mosaic : 1;
bool colors256 : 1;
uint8_t screen_base_block : 5;
bool bg_2_3_wraparound : 1;
uint8_t screen_size : 2;
} value;
uint16_t read() const { return std::bit_cast<uint16_t>(value); };
void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
};
struct RotationScaling {
// these are all 16 bit signed "fixed point" floats
// shifted by 8
int16_t a;
int16_t b;
int16_t c;
int16_t d;
// following points have 28 bit signed "fixed point" floats as coords
// shifted by 8
Point<int32_t> ref;
private:
Point<int32_t> internal [[maybe_unused]]
;
};
struct Display {
public:
using u16 = uint16_t;
Memory<0x400> pram;
Memory<0x18000> vram;
Memory<0x400> oam;
DisplayControl lcd_control;
DisplayStatus general_lcd_status;
u16 vertical_counter;
BackgroundControl bg_control[4];
Point<u16> bg0_offset;
Point<u16> bg1_offset;
Point<u16> bg2_offset;
Point<u16> bg3_offset;
RotationScaling bg2_rot_scale;
RotationScaling bg3_rot_scale;
u16 win0_horizontal_dimensions;
u16 win1_horizontal_dimensions;
u16 win0_vertical_dimensions;
u16 win1_vertical_dimensions;
u16 inside_win_0_1;
u16 outside_win;
u16 mosaic_size;
u16 color_special_effects_selection;
u16 alpha_blending_coefficients;
u16 brightness_coefficient;
private:
// 1 color is 16 bits in ARGB555 format
std::array<std::array<uint16_t, LCD_WIDTH>, N_BACKGROUNDS> scanline_buffers;
template<int MODE,
typename = std::enable_if_t<MODE == 3 || MODE == 4 || MODE == 5>>
void render_bitmap_mode();
template<int LAYER, typename = std::enable_if_t<LAYER >= 0 && LAYER <= 3>>
void render_text_layer();
};
}
}
// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

39
include/io/dma.hh
View File

@@ -1,39 +0,0 @@
#include <bit>
#include <cstdint>
namespace matar {
// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
struct DmaControl {
struct {
int : 4; // this is supposed to be 5 bits, however, to align the struct
// to 16 bits, we will adjust for the first LSB in the
// read/write
uint8_t dst_adjustment : 2;
uint8_t src_adjustment : 2;
bool repeat : 1;
bool transfer_32 : 1;
int : 1;
uint8_t start_timing : 2;
bool irq_enable : 1;
bool enable : 1;
} value;
uint16_t read() const { return std::bit_cast<uint16_t>(value) << 1; };
void write(uint16_t raw) {
value = std::bit_cast<decltype(value)>(static_cast<uint16_t>(raw >> 1));
};
};
struct Dma {
using u16 = uint16_t;
struct {
u16 source[2];
u16 destination[2];
u16 word_count;
DmaControl control;
} channels[4];
};
// NOLINTEND(cppcoreguidelines-avoid-c-arrays)
}

43
include/io/io.hh
View File

@@ -1,43 +0,0 @@
#pragma once
#include "display/display.hh"
#include "dma.hh"
#include "sound.hh"
#include <cstdint>
#include <memory>
namespace matar {
class Bus; // forward declaration
class IoDevices {
public:
IoDevices(std::weak_ptr<Bus>);
uint8_t read_byte(uint32_t) const;
void write_byte(uint32_t, uint8_t);
uint32_t read_word(uint32_t) const;
void write_word(uint32_t, uint32_t);
uint16_t read_halfword(uint32_t) const;
void write_halfword(uint32_t, uint16_t);
private:
struct {
using u16 = uint16_t;
bool post_boot_flag;
bool interrupt_master_enabler;
u16 interrupt_enable;
u16 interrupt_request_flags;
u16 waitstate_control;
bool low_power_mode;
} system = {};
display::Display display = {};
Sound sound = {};
Dma dma = {};
std::weak_ptr<Bus> bus;
friend class Bus;
};
}

3
include/io/meson.build
View File

@@ -1,3 +0,0 @@
headers += files(
'io.hh'
)

66
include/io/sound.hh
View File

@@ -1,66 +0,0 @@
#include <cstdint>
// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
/*
4000060h 2 R/W SOUND1CNT_L Channel 1 Sweep register (NR10)
4000062h 2 R/W SOUND1CNT_H Channel 1 Duty/Length/Envelope (NR11, NR12)
4000064h 2 R/W SOUND1CNT_X Channel 1 Frequency/Control (NR13, NR14)
4000066h - - Not used
4000068h 2 R/W SOUND2CNT_L Channel 2 Duty/Length/Envelope (NR21, NR22)
400006Ah - - Not used
400006Ch 2 R/W SOUND2CNT_H Channel 2 Frequency/Control (NR23, NR24)
400006Eh - - Not used
4000070h 2 R/W SOUND3CNT_L Channel 3 Stop/Wave RAM select (NR30)
4000072h 2 R/W SOUND3CNT_H Channel 3 Length/Volume (NR31, NR32)
4000074h 2 R/W SOUND3CNT_X Channel 3 Frequency/Control (NR33, NR34)
4000076h - - Not used
4000078h 2 R/W SOUND4CNT_L Channel 4 Length/Envelope (NR41, NR42)
400007Ah - - Not used
400007Ch 2 R/W SOUND4CNT_H Channel 4 Frequency/Control (NR43, NR44)
400007Eh - - Not used
4000080h 2 R/W SOUNDCNT_L Control Stereo/Volume/Enable (NR50, NR51)
4000082h 2 R/W SOUNDCNT_H Control Mixing/DMA Control
4000084h 2 R/W SOUNDCNT_X Control Sound on/off (NR52)
4000086h - - Not used
4000088h 2 BIOS SOUNDBIAS Sound PWM Control
400008Ah .. - - Not used
4000090h 2x10h R/W WAVE_RAM Channel 3 Wave Pattern RAM (2 banks!!)
40000A0h 4 W FIFO_A Channel A FIFO, Data 0-3
40000A4h 4 W FIFO_B Channel B FIFO, Data 0-3
*/
struct Sound {
using u16 = uint16_t;
// channel 1
u16 ch1_sweep;
u16 ch1_duty_length_env;
u16 ch1_freq_control;
// channel 2
u16 ch2_duty_length_env;
u16 ch2_freq_control;
// channel 3
u16 ch3_stop_wave_ram_select;
u16 ch3_length_volume;
u16 ch3_freq_control;
u16 ch3_wave_pattern[8];
// channel 4
u16 ch4_length_env;
u16 ch4_freq_control;
// control
u16 ctrl_stereo_volume;
u16 ctrl_mixing;
u16 ctrl_sound_on_off;
u16 pwm_control;
// fifo
u16 fifo_a[2];
u16 fifo_b[2];
};
// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

91
include/memory.hh
View File

@@ -1,60 +1,63 @@
#pragma once
#include "header.hh"
#include <array>
#include <cstddef>
#include <cstdint>
#include <vector>
// ill use [] instead of at because i dont want if (...) throw conditions for
// all accesses to improve performance (?)
// we are also not gonna perform bound checks, as i expect the user to handle
// those
namespace matar {
template<std::size_t N = 0>
class Memory {
// we can use either a vector or an array with this
using Container = std::
conditional_t<(N != 0), std::array<uint8_t, N>, std::vector<uint8_t>>;
public:
Memory() = default;
Memory(auto x)
: memory(x) {}
static constexpr size_t BIOS_SIZE = 1024 * 16;
uint8_t read_byte(std::size_t idx) const { return memory[idx]; }
Memory(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
void write_byte(std::size_t idx, uint8_t byte) { memory[idx] = byte; }
uint8_t read(size_t address) const;
void write(size_t address, uint8_t byte);
uint16_t read_halfword(std::size_t idx) const {
return memory[idx] | memory[idx + 1] << 8;
}
uint16_t read_halfword(size_t address) const;
void write_halfword(size_t address, uint16_t halfword);
void write_halfword(std::size_t idx, uint16_t halfword) {
memory[idx] = halfword & 0xFF;
memory[idx + 1] = halfword >> 8 & 0xFF;
}
uint32_t read_word(std::size_t idx) const {
return memory[idx] | memory[idx + 1] << 8 | memory[idx + 2] << 16 |
memory[idx + 3] << 24;
}
void write_word(std::size_t idx, uint32_t word) {
memory[idx] = word & 0xFF;
memory[idx + 1] = word >> 8 & 0xFF;
memory[idx + 2] = word >> 16 & 0xFF;
memory[idx + 3] = word >> 24 & 0xFF;
}
uint8_t& operator[](std::size_t idx) { return memory.at(idx); }
Container& data() { return memory; }
std::size_t size() const { return memory.size(); }
uint32_t read_word(size_t address) const;
void write_word(size_t address, uint32_t word);
private:
Container memory;
#define MEMORY_REGION(name, start, end) \
static constexpr size_t name##_START = start; \
static constexpr size_t name##_END = end;
#define DECL_MEMORY(name, ident, start, end) \
MEMORY_REGION(name, start, end) \
std::array<uint8_t, name##_END - name##_START + 1> ident;
MEMORY_REGION(BIOS, 0x00000000, 0x00003FFF)
std::array<uint8_t, BIOS_SIZE> bios;
static_assert(BIOS_END - BIOS_START + 1 == BIOS_SIZE);
// board working RAM
DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
// chip working RAM
DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
// palette RAM
DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
// video RAM
DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
// OAM OBJ attributes
DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
#undef DECL_MEMORY
MEMORY_REGION(ROM_0, 0x08000000, 0x09FFFFFF)
MEMORY_REGION(ROM_1, 0x0A000000, 0x0BFFFFFF)
MEMORY_REGION(ROM_2, 0x0C000000, 0x0DFFFFFF)
#undef MEMORY_REGION
std::vector<uint8_t> rom;
Header header;
void parse_header();
};
}

5
include/meson.build
View File

@@ -1,12 +1,9 @@
headers = files(
'memory.hh',
'bus.hh',
'header.hh',
)
inc = include_directories('.')
subdir('cpu')
subdir('util')
subdir('io')
install_headers(headers, subdir: meson.project_name(), preserve_path: true)

14
include/util/loglevel.hh
View File

@@ -1,14 +0,0 @@
#pragma once
namespace matar {
enum class LogLevel {
Off = 1 << 0,
Error = 1 << 1,
Warn = 1 << 2,
Info = 1 << 3,
Debug = 1 << 4
};
void
set_log_level(LogLevel level);
}

3
include/util/meson.build
View File

@@ -1,3 +0,0 @@
headers += files(
'loglevel.hh'
)

27
meson.build
View File

@@ -4,20 +4,33 @@ project('matar', 'cpp',
default_options : ['warning_level=3',
'werror=true',
'optimization=3',
'cpp_std=c++23',
'default_library=static'])
'cpp_std=c++20'])
lib_cpp_args = []
compiler = meson.get_compiler('cpp')
if get_option('disassembler')
lib_cpp_args += '-DDISASSEMBLER'
'''
TODO: use <print> and <format> instead of libfmt once LLVM 17 is out
if compiler.has_argument('-std=c++2c')
add_global_arguments('-std=c++2c', language: 'cpp')
elif compiler.has_argument('-std=c++23')
add_global_arguments('-std=c++23', language: 'cpp')
elif compiler.has_argument('-std=c++2b')
add_global_arguments('-std=c++2b', language: 'cpp')
elif compiler.has_argument('-std=c++20')
add_global_arguments('-std=c++20', language: 'cpp')
else
error(compiler.get_id() + ' ' + compiler.version() + 'does not meet the compiler requirements')
endif
if get_option('gdb_debug')
lib_cpp_args += '-DGDB_DEBUG'
if compiler.has_argument('-fexperimental-library')
add_global_arguments('-fexperimental-library', language: 'cpp')
else
error(compiler.get_id() + ' ' + compiler.version() + 'does not support -fexperimental-library')
endif
'''
inc = include_directories('include')
subdir('include')
subdir('src')

3
meson.options
View File

@@ -1,3 +0,0 @@
option('tests', type : 'boolean', value : true, description: 'enable tests')
option('disassembler', type: 'boolean', value: true, description: 'enable disassembler')
option('gdb_debug', type: 'boolean', value: false, description: 'enable GDB RSP server')

1
meson_options.txt Normal file
View File

@@ -0,0 +1 @@
option('tests', type : 'boolean', value : true, description: 'enable tests')

1248
nix/Cargo.lock generated
View File

File diff suppressed because it is too large Load Diff

23
nix/build.nix
View File

@@ -1,23 +0,0 @@
{ stdenv
, meson
, ninja
, pkg-config
, src ? "../."
, libraries ? [ ]
}:
stdenv.mkDerivation {
name = "matar";
version = "0.1";
inherit src;
outputs = [ "out" "dev" ];
nativeBuildInputs = [
meson
ninja
pkg-config
] ++ libraries;
enableParallelBuilding = true;
}

11
nix/default.nix
View File

@@ -1,11 +0,0 @@
{ ... }: {
imports = [
./matar.nix
./matar-clang.nix
];
perSystem = { self', pkgs, ... }: {
packages.default = self'.packages.matar-clang;
devShells.default = self'.devShells.matar-clang;
};
}

18
nix/matar-clang.nix
View File

@@ -1,18 +0,0 @@
{ ... }: {
perSystem = { pkgs, src, ... }:
let
llvm = pkgs.llvmPackages_18;
stdenv = llvm.libcxxStdenv;
libraries = with pkgs; [
(catch2_3.override { inherit stdenv; }).out
];
in
{
packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
devShells.matar-clang = pkgs.callPackage ./shell.nix {
inherit libraries stdenv;
tools = with pkgs; [ (clang-tools_18.override { enableLibcxx = true; }) ];
};
};
}

14
nix/matar.nix
View File

@@ -1,14 +0,0 @@
{ ... }: {
perSystem = { pkgs, src, ... }:
let
stdenv = pkgs.gcc14Stdenv;
libraries = with pkgs; [
(catch2_3.override { inherit stdenv; }).out
];
in
{
packages.matar = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries stdenv; };
};
}

20
nix/shell.nix
View File

@@ -1,20 +0,0 @@
{ stdenv
, mkShell
, meson
, ninja
, pkg-config
, libraries ? [ ]
, tools ? [ ]
}:
mkShell.override { inherit stdenv; } {
name = "matar";
packages = [
meson
ninja
pkg-config
] ++ libraries ++ tools;
enableParallelBuilding = true;
}

360
src/bus.cc
View File

@@ -1,365 +1,35 @@
#include "bus.hh"
#include "io/io.hh"
#include "util/crypto.hh"
#include "util/log.hh"
#include <memory>
namespace matar {
// Constants
#define MEMORY(AREA, start) \
static constexpr uint32_t AREA##_START = start; \
static constexpr uint8_t AREA##_REGION = (AREA##_START >> 24) & 0xFF;
MEMORY(BIOS, 0x0000000);
MEMORY(BOARD_WRAM, 0x2000000);
MEMORY(CHIP_WRAM, 0x3000000);
MEMORY(PRAM, display::PRAM_START);
MEMORY(VRAM, display::VRAM_START);
MEMORY(OAM, display::OAM_START);
MEMORY(ROM_0, 0x8000000);
MEMORY(ROM_1, 0xA000000);
MEMORY(ROM_2, 0xC000000);
static constexpr uint32_t IO_START = 0x4000000;
static constexpr uint32_t IO_END = 0x40003FE;
#undef MEMORY
Bus::Bus(Private,
std::array<uint8_t, BIOS_SIZE>&& bios,
std::vector<uint8_t>&& rom)
: cycle_map(init_cycle_count())
, bios(std::move(bios))
, rom(std::move(rom)) {
std::string bios_hash = crypto::sha256(this->bios.data());
static constexpr std::string_view expected_hash =
"fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
if (bios_hash != expected_hash) {
glogger.warn("BIOS hash failed to match, run at your own risk"
"\nExpected : {} "
"\nGot : {}",
expected_hash,
bios_hash);
}
parse_header();
glogger.info("Memory successfully initialised");
glogger.info("Cartridge Title: {}", header.title);
};
std::shared_ptr<Bus>
Bus::init(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom) {
auto self =
std::make_shared<Bus>(Private(), std::move(bios), std::move(rom));
self->io = std::make_unique<IoDevices>(self);
return self;
}
constexpr decltype(Bus::cycle_map)
Bus::init_cycle_count() {
/*
Region Bus Read Write Cycles
BIOS ROM 32 8/16/32 - 1/1/1
Work RAM 32K 32 8/16/32 8/16/32 1/1/1
I/O 32 8/16/32 8/16/32 1/1/1
OAM 32 8/16/32 16/32 1/1/1 *
Work RAM 256K 16 8/16/32 8/16/32 3/3/6 **
Palette RAM 16 8/16/32 16/32 1/1/2 *
VRAM 16 8/16/32 16/32 1/1/2 *
GamePak ROM 16 8/16/32 - 5/5/8 **|***
GamePak Flash 16 8/16/32 16/32 5/5/8 **|***
GamePak SRAM 8 8 8 5 **
Timing Notes:
* Plus 1 cycle if GBA accesses video memory at the same time.
** Default waitstate settings, see System Control chapter.
*** Separate timings for sequential, and non-sequential accesses.
One cycle equals approx. 59.59ns (ie. 16.78MHz clock).
*/
decltype(cycle_map) map;
map.fill({ 1, 1, 1, 1 });
/* used fill instead of this
map[BIOS_REGION] = { 1, 1, 1, 1 };
map[CHIP_WRAM_REGION] = { 1, 1, 1, 1 };
map[IO_REGION] = { 1, 1, 1, 1 };
map[OAM_REGION] = { 1, 1, 1, 1 };
*/
map[BOARD_WRAM_REGION] = { .n16 = 3, .n32 = 6, .s16 = 3, .s32 = 6 };
map[PRAM_REGION] = { .n16 = 1, .n32 = 2, .s16 = 1, .s32 = 2 };
map[VRAM_REGION] = { .n16 = 1, .n32 = 2, .s16 = 1, .s32 = 2 };
// TODO: GamePak access cycles
return map;
}
template<typename T>
T
Bus::read(uint32_t address) const {
// this is cleaned than std::enable_if
static_assert(std::is_same_v<T, uint8_t> || std::is_same_v<T, uint16_t> ||
std::is_same_v<T, uint32_t>,
"Can only read uint8_t, uin16_t or uint32_t");
constexpr int N = std::is_same_v<T, uint8_t> ? 1
: std::is_same_v<T, uint16_t> ? 2
: std::is_same_v<T, uint32_t> ? 4
: 0;
switch (address >> 24 & 0xF) {
#define MATCHES(AREA, area) \
case AREA##_REGION: { \
uint32_t i = address - AREA##_START; \
if (i > area.size() - N) \
break; \
if constexpr (std::is_same_v<T, uint8_t>) \
return area.read_byte(i); \
else if constexpr (std::is_same_v<T, uint16_t>) \
return area.read_halfword(i); \
else if constexpr (std::is_same_v<T, uint32_t>) \
return area.read_word(i); \
}
#define MATCHES_PAK(AREA, area) \
case AREA##_REGION + 1: \
MATCHES(AREA, area)
MATCHES(BIOS, bios)
MATCHES(BOARD_WRAM, board_wram)
MATCHES(CHIP_WRAM, chip_wram)
MATCHES(PRAM, io->display.pram)
MATCHES(VRAM, io->display.vram)
MATCHES(OAM, io->display.oam)
MATCHES_PAK(ROM_0, rom)
MATCHES_PAK(ROM_1, rom)
MATCHES_PAK(ROM_2, rom)
#undef MATCHES_PAK
#undef MATCHES
}
glogger.error("invalid memory region read at {:08x}", address);
if constexpr (std::is_same_v<T, uint8_t>)
return 0xFF;
else if constexpr (std::is_same_v<T, uint16_t>)
return 0xFFFF;
else if constexpr (std::is_same_v<T, uint32_t>)
return 0xFFFFFFFF;
}
template<typename T>
void
Bus::write(uint32_t address, T value) {
static_assert(std::is_same_v<T, uint8_t> || std::is_same_v<T, uint16_t> ||
std::is_same_v<T, uint32_t>,
"Can only write uint8_t, uin16_t or uint32_t");
constexpr int N = std::is_same_v<T, uint8_t> ? 1
: std::is_same_v<T, uint16_t> ? 2
: std::is_same_v<T, uint32_t> ? 4
: 0;
switch (address >> 24 & 0xF) {
#define MATCHES(AREA, area) \
case AREA##_REGION: { \
uint32_t i = address - AREA##_START; \
if (i > area.size() - N) \
break; \
if constexpr (std::is_same_v<T, uint8_t>) \
area.write_byte(i, value); \
else if constexpr (std::is_same_v<T, uint16_t>) \
area.write_halfword(i, value); \
else if constexpr (std::is_same_v<T, uint32_t>) \
area.write_word(i, value); \
return; \
}
MATCHES(BOARD_WRAM, board_wram)
MATCHES(CHIP_WRAM, chip_wram)
MATCHES(PRAM, io->display.pram)
MATCHES(VRAM, io->display.vram)
MATCHES(OAM, io->display.oam)
#undef MATCHES
}
glogger.error("invalid memory region written at {:08x}", address);
}
Bus::Bus(const Memory& memory)
: memory(std::make_shared<Memory>(memory)) {}
uint8_t
Bus::read_byte(uint32_t address) {
if (address >= IO_START && address <= IO_END)
return io->read_byte(address);
return read<uint8_t>(address);
Bus::read_byte(size_t address) {
return memory->read(address);
}
void
Bus::write_byte(uint32_t address, uint8_t byte) {
if (address >= IO_START && address <= IO_END) {
io->write_byte(address, byte);
return;
}
write<uint8_t>(address, byte);
Bus::write_byte(size_t address, uint8_t byte) {
memory->write(address, byte);
}
uint16_t
Bus::read_halfword(uint32_t address) {
if (address & 0b01)
glogger.warn("Reading a non aligned halfword address");
if (address >= IO_START && address <= IO_END)
return io->read_halfword(address);
return read<uint16_t>(address);
Bus::read_halfword(size_t address) {
return memory->read_halfword(address);
}
void
Bus::write_halfword(uint32_t address, uint16_t halfword) {
if (address & 0b01)
glogger.warn("Writing to a non aligned halfword address");
if (address >= IO_START && address <= IO_END) {
io->write_halfword(address, halfword);
return;
}
write<uint16_t>(address, halfword);
Bus::write_halfword(size_t address, uint16_t halfword) {
memory->write_halfword(address, halfword);
}
uint32_t
Bus::read_word(uint32_t address) {
if (address & 0b11)
glogger.warn("Reading a non aligned word address");
if (address >= IO_START && address <= IO_END)
return io->read_word(address);
return read<uint32_t>(address);
Bus::read_word(size_t address) {
return memory->read_word(address);
}
void
Bus::write_word(uint32_t address, uint32_t word) {
if (address & 0b11)
glogger.warn("Writing to a non aligned word address");
if (address >= IO_START && address <= IO_END) {
io->write_word(address, word);
return;
}
write<uint32_t>(address, word);
}
void
Bus::parse_header() {
if (rom.size() < header.HEADER_SIZE) {
throw std::out_of_range(
"ROM is not large enough to even have a header");
}
// entrypoint
header.entrypoint =
rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
// nintendo logo
if (rom[0x9C] != 0x21)
glogger.info("HEADER: BIOS debugger bits not set to 0");
// game info
header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
switch (rom[0xAC]) {
case 'A':
header.unique_code = Header::UniqueCode::Old;
break;
case 'B':
header.unique_code = Header::UniqueCode::New;
break;
case 'C':
header.unique_code = Header::UniqueCode::Newer;
break;
case 'F':
header.unique_code = Header::UniqueCode::Famicom;
break;
case 'K':
header.unique_code = Header::UniqueCode::YoshiKoro;
break;
case 'P':
header.unique_code = Header::UniqueCode::Ereader;
break;
case 'R':
header.unique_code = Header::UniqueCode::Warioware;
break;
case 'U':
header.unique_code = Header::UniqueCode::Boktai;
break;
case 'V':
header.unique_code = Header::UniqueCode::DrillDozer;
break;
default:
glogger.error("HEADER: invalid unique code: {}", rom[0xAC]);
}
header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
switch (rom[0xAF]) {
case 'J':
header.i18n = Header::I18n::Japan;
break;
case 'P':
header.i18n = Header::I18n::Europe;
break;
case 'F':
header.i18n = Header::I18n::French;
break;
case 'S':
header.i18n = Header::I18n::Spanish;
break;
case 'E':
header.i18n = Header::I18n::Usa;
break;
case 'D':
header.i18n = Header::I18n::German;
break;
case 'I':
header.i18n = Header::I18n::Italian;
break;
default:
glogger.error("HEADER: invalid destination/language: {}",
rom[0xAF]);
}
if (rom[0xB2] != 0x96)
glogger.error("HEADER: invalid fixed byte at 0xB2");
for (uint32_t i = 0xB5; i < 0xBC; i++) {
if (rom[i] != 0x00)
glogger.error("HEADER: invalid fixed bytes at 0xB5");
}
header.version = rom[0xBC];
// checksum
{
uint32_t i = 0xA0, chk = 0;
while (i <= 0xBC)
chk -= rom[i++];
chk -= 0x19;
chk &= 0xFF;
if (chk != rom[0xBD])
glogger.error("HEADER: checksum does not match");
}
// multiboot not required right now
}
Bus::write_word(size_t address, uint32_t word) {
memory->write_word(address, word);
}

108
src/cpu/alu.cc
View File

@@ -1,108 +0,0 @@
#include "cpu/alu.hh"
#include "util/bits.hh"
#include <bit>
namespace matar {
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry) {
uint32_t eval = 0;
switch (shift_type) {
case ShiftType::LSL:
if (amount > 0 && amount <= 32)
carry = get_bit(value, 32 - amount);
else if (amount > 32)
carry = 0;
eval = value << amount;
break;
case ShiftType::LSR:
if (amount > 0 && amount <= 32)
carry = get_bit(value, amount - 1);
else if (amount > 32)
carry = 0;
else
carry = get_bit(value, 31);
eval = value >> amount;
break;
case ShiftType::ASR:
if (amount > 0 && amount <= 32)
carry = get_bit(value, amount - 1);
else
carry = get_bit(value, 31);
return static_cast<int32_t>(value) >> amount;
break;
case ShiftType::ROR:
if (amount == 0) {
eval = (value >> 1) | (carry << 31);
carry = get_bit(value, 0);
} else {
eval = std::rotr(value, amount);
carry = get_bit(value, (amount % 32 + 31) % 32);
}
break;
}
return eval;
}
uint32_t
sub(uint32_t a, uint32_t b, bool& carry, bool& overflow) {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint32_t result = a - b;
carry = a >= b;
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result;
}
uint32_t
add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint64_t result = a + b + c;
carry = get_bit(result, 32);
overflow = s1 == s2 && s2 != get_bit(result, 31);
return result & 0xFFFFFFFF;
}
uint32_t
sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint64_t result = a - b - !c;
carry = get_bit(result, 32);
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result & 0xFFFFFFFF;
}
uint8_t
multiplier_array_cycles(uint32_t x, bool zeroes_only) {
// set zeroes_only to evaluate first condition that checks ones to false
if ((!zeroes_only && (x & 0xFFFFFF00) == 0xFFFFFF00) ||
(x & 0xFFFFFF00) == 0)
return 1;
if ((!zeroes_only && (x & 0xFFFF0000) == 0xFFFF0000) ||
(x & 0xFFFF0000) == 0)
return 2;
if ((!zeroes_only && (x & 0xFF000000) == 0xFF000000) ||
(x & 0xFF000000) == 0)
return 3;
return 4;
};
}

237
src/cpu/arm/disassembler.cc
View File

@@ -1,237 +0,0 @@
#include "cpu/arm/instruction.hh"
#include "util/bits.hh"
#include <format>
namespace matar::arm {
std::string
Instruction::disassemble() {
auto condition = stringify(this->condition);
return std::visit(
overloaded{
[condition](BranchAndExchange& data) {
return std::format("BX{} R{:d}", condition, data.rn);
},
[condition](Branch& data) {
return std::format(
"B{}{} {:#06x}",
(data.link ? "L" : ""),
condition,
static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
},
[condition](Multiply& data) {
if (data.acc) {
return std::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
condition,
(data.set ? "S" : ""),
data.rd,
data.rm,
data.rs,
data.rn);
} else {
return std::format("MUL{}{} R{:d},R{:d},R{:d}",
condition,
(data.set ? "S" : ""),
data.rd,
data.rm,
data.rs);
}
},
[condition](MultiplyLong& data) {
return std::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
(data.uns ? 'U' : 'S'),
(data.acc ? "MLAL" : "MULL"),
condition,
(data.set ? "S" : ""),
data.rdlo,
data.rdhi,
data.rm,
data.rs);
},
[](Undefined) { return std::string("UND"); },
[condition](SingleDataSwap& data) {
return std::format("SWP{}{} R{:d},R{:d},[R{:d}]",
condition,
(data.byte ? "B" : ""),
data.rd,
data.rm,
data.rn);
},
[condition](SingleDataTransfer& data) {
std::string expression;
std::string address;
if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
if (*offset == 0) {
expression = "";
} else {
expression =
std::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
}
} else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
// Shifts are always immediate in single data transfer
expression = std::format(",{}R{:d},{} #{:d}",
(data.up ? '+' : '-'),
shift->rm,
stringify(shift->data.type),
shift->data.operand);
}
return std::format(
"{}{}{}{} R{:d},[R{:d}{}]{}",
(data.load ? "LDR" : "STR"),
condition,
(data.byte ? "B" : ""),
(!data.pre && data.write ? "T" : ""),
data.rd,
data.rn,
(data.pre ? expression : ""),
(data.pre ? (data.write ? "!" : "") : expression));
},
[condition](HalfwordTransfer& data) {
std::string expression;
if (data.imm) {
if (data.offset == 0) {
expression = "";
} else {
expression = std::format(
",{}#{:d}", (data.up ? '+' : '-'), data.offset);
}
} else {
expression =
std::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
}
return std::format(
"{}{}{}{} R{:d},[R{:d}{}]{}",
(data.load ? "LDR" : "STR"),
condition,
(data.sign ? "S" : ""),
(data.half ? 'H' : 'B'),
data.rd,
data.rn,
(data.pre ? expression : ""),
(data.pre ? (data.write ? "!" : "") : expression));
},
[condition](BlockDataTransfer& data) {
std::string regs;
for (uint8_t i = 0; i < 16; i++) {
if (get_bit(data.regs, i))
std::format_to(std::back_inserter(regs), "R{:d},", i);
};
regs.pop_back();
return std::format("{}{}{}{} R{:d}{},{{{}}}{}",
(data.load ? "LDM" : "STM"),
condition,
(data.up ? 'I' : 'D'),
(data.pre ? 'B' : 'A'),
data.rn,
(data.write ? "!" : ""),
regs,
(data.s ? "^" : ""));
},
[condition](PsrTransfer& data) {
if (data.type == PsrTransfer::Type::Mrs) {
return std::format("MRS{} R{:d},{}",
condition,
data.operand,
(data.spsr ? "SPSR_all" : "CPSR_all"));
} else {
return std::format(
"MSR{} {}_{},{}{}",
condition,
(data.spsr ? "SPSR" : "CPSR"),
(data.type == PsrTransfer::Type::Msr_flg ? "flg" : "all"),
(data.imm ? '#' : 'R'),
data.operand);
}
},
[condition](DataProcessing& data) {
using OpCode = DataProcessing::OpCode;
std::string op_2;
if (const uint32_t* operand =
std::get_if<uint32_t>(&data.operand)) {
op_2 = std::format("#{:d}", *operand);
} else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
op_2 = std::format("R{:d},{} {}{:d}",
shift->rm,
stringify(shift->data.type),
(shift->data.immediate ? '#' : 'R'),
shift->data.operand);
}
switch (data.opcode) {
case OpCode::MOV:
case OpCode::MVN:
return std::format("{}{}{} R{:d},{}",
stringify(data.opcode),
condition,
(data.set ? "S" : ""),
data.rd,
op_2);
case OpCode::TST:
case OpCode::TEQ:
case OpCode::CMP:
case OpCode::CMN:
return std::format("{}{} R{:d},{}",
stringify(data.opcode),
condition,
data.rn,
op_2);
default:
return std::format("{}{}{} R{:d},R{:d},{}",
stringify(data.opcode),
condition,
(data.set ? "S" : ""),
data.rd,
data.rn,
op_2);
}
},
[condition](SoftwareInterrupt) {
return std::format("SWI{}", condition);
},
[condition](CoprocessorDataTransfer& data) {
std::string expression = std::format(",#{:d}", data.offset);
return std::format(
"{}{}{} p{:d},c{:d},[R{:d}{}]{}",
(data.load ? "LDC" : "STC"),
condition,
(data.len ? "L" : ""),
data.cpn,
data.crd,
data.rn,
(data.pre ? expression : ""),
(data.pre ? (data.write ? "!" : "") : expression));
},
[condition](CoprocessorDataOperation& data) {
return std::format("CDP{} p{},{},c{},c{},c{},{}",
condition,
data.cpn,
data.cp_opc,
data.crd,
data.crn,
data.crm,
data.cp);
},
[condition](CoprocessorRegisterTransfer& data) {
return std::format("{}{} p{},{},R{},c{},c{},{}",
(data.load ? "MRC" : "MCR"),
condition,
data.cpn,
data.cp_opc,
data.rd,
data.crn,
data.crm,
data.cp);
},
[](auto) { return std::string("unknown instruction"); } },
data);
}
}

649
src/cpu/arm/exec.cc
View File

@@ -1,54 +1,42 @@
#include "bus.hh"
#include "cpu/cpu.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar {
void
Cpu::exec(arm::Instruction& instruction) {
bool is_flushed = false;
using namespace logger;
if (!cpsr.condition(instruction.condition)) {
advance_pc_arm();
void
Cpu::exec_arm(const arm::Instruction instruction) {
auto cond = instruction.condition;
auto data = instruction.data;
if (!cpsr.condition(cond)) {
return;
}
auto pc_error = [](uint8_t r) {
if (r == PC_INDEX)
glogger.error("Using PC (R15) as operand register");
log_error("Using PC (R15) as operand register");
};
auto pc_warn = [](uint8_t r) {
if (r == PC_INDEX)
glogger.warn("Using PC (R15) as operand register");
log_warn("Using PC (R15) as operand register");
};
using namespace arm;
std::visit(
overloaded{
[this, pc_warn, &is_flushed](BranchAndExchange& data) {
/*
S -> reading instruction in step()
N -> fetch from the new address in branch
S -> last opcode fetch at +L to refill the pipeline
Total = 2S + N cycles
1S done, S+N taken care of by flush_pipeline()
*/
uint32_t addr = gpr[data.rn];
State state = static_cast<State>(get_bit(addr, 0));
[this, pc_warn](BranchAndExchange& data) {
State state = static_cast<State>(data.rn & 1);
pc_warn(data.rn);
if (state != cpsr.state())
glogger.info_bold("State changed");
// set state
cpsr.set_state(state);
// copy to PC
pc = addr;
pc = gpr[data.rn];
// ignore [1:0] bits for arm and 0 bit for thumb
rst_bit(pc, 0);
@@ -56,59 +44,32 @@ Cpu::exec(arm::Instruction& instruction) {
if (state == State::Arm)
rst_bit(pc, 1);
// PC is affected so flush the pipeline
// pc is affected so flush the pipeline
is_flushed = true;
},
[this, &is_flushed](Branch& data) {
/*
S -> reading instruction in step()
N -> fetch from the new address in branch
S -> last opcode fetch at +L to refill the pipeline
Total = 2S + N cycles
1S done, S+N taken care of by flush_pipeline()
*/
[this](Branch& data) {
if (data.link)
gpr[14] = pc - INSTRUCTION_SIZE;
gpr[14] = pc - ARM_INSTRUCTION_SIZE;
pc += data.offset;
// data.offset accounts for two instructions ahead when
// disassembling, so need to adjust
pc =
static_cast<int32_t>(pc) - 2 * ARM_INSTRUCTION_SIZE + data.offset;
// pc is affected so flush the pipeline
is_flushed = true;
},
[this, pc_error](Multiply& data) {
/*
S -> reading instruction in step()
mI -> m internal cycles
I -> only when accumulating
let v = data at rn
m = 1 if bits [32:8] of v are all zero or all one
m = 2 [32:16]
m = 3 [32:24]
m = 4 otherwise
Total = S + mI or S + (m+1)I
*/
if (data.rd == data.rm)
glogger.error("rd and rm are not distinct in {}",
typeid(data).name());
log_error("rd and rm are not distinct in {}",
typeid(data).name());
pc_error(data.rd);
pc_error(data.rd);
pc_error(data.rd);
// mI
for (int i = 0; i < multiplier_array_cycles(gpr[data.rs]); i++)
internal_cycle();
gpr[data.rd] = gpr[data.rm] * gpr[data.rs];
if (data.acc) {
gpr[data.rd] += gpr[data.rn];
// 1I
internal_cycle();
}
gpr[data.rd] =
gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
if (data.set) {
cpsr.set_z(gpr[data.rd] == 0);
@@ -117,61 +78,34 @@ Cpu::exec(arm::Instruction& instruction) {
}
},
[this, pc_error](MultiplyLong& data) {
/*
S -> reading instruction in step()
(m+1)I -> m + 1 internal cycles
I -> only when accumulating
let v = data at rs
m = 1 if bits [32:8] of v are all zeroes (or all ones if signed)
m = 2 [32:16]
m = 3 [32:24]
m = 4 otherwise
Total = S + (m+1)I or S + (m+2)I
*/
if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
data.rdlo == data.rm)
glogger.error("rdhi, rdlo and rm are not distinct in {}",
typeid(data).name());
log_error("rdhi, rdlo and rm are not distinct in {}",
typeid(data).name());
pc_error(data.rdhi);
pc_error(data.rdlo);
pc_error(data.rm);
pc_error(data.rs);
// 1I
if (data.acc)
internal_cycle();
// m+1 internal cycles
for (int i = 0;
i <= multiplier_array_cycles(gpr[data.rs], data.uns);
i++)
internal_cycle();
if (data.uns) {
auto cast = [](uint32_t x) -> uint64_t {
return static_cast<uint64_t>(x);
};
uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
(data.acc ? (cast(gpr[data.rdhi]) << 32) |
cast(gpr[data.rdlo])
: 0);
uint64_t eval =
static_cast<uint64_t>(gpr[data.rm]) *
static_cast<uint64_t>(gpr[data.rs]) +
(data.acc ? (static_cast<uint64_t>(gpr[data.rdhi]) << 32) |
static_cast<uint64_t>(gpr[data.rdlo])
: 0);
gpr[data.rdlo] = bit_range(eval, 0, 31);
gpr[data.rdhi] = bit_range(eval, 32, 63);
} else {
auto cast = [](uint32_t x) -> int64_t {
return static_cast<int64_t>(static_cast<int32_t>(x));
};
int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
(data.acc ? (cast(gpr[data.rdhi]) << 32) |
cast(gpr[data.rdlo])
: 0);
int64_t eval =
static_cast<int64_t>(gpr[data.rm]) *
static_cast<int64_t>(gpr[data.rs]) +
(data.acc ? static_cast<int64_t>(gpr[data.rdhi]) << 32 |
static_cast<int64_t>(gpr[data.rdlo])
: 0);
gpr[data.rdlo] = bit_range(eval, 0, 31);
gpr[data.rdhi] = bit_range(eval, 32, 63);
@@ -184,66 +118,31 @@ Cpu::exec(arm::Instruction& instruction) {
cpsr.set_v(0);
}
},
[](Undefined) {
// this should be 2S + N + I, should i flush the pipeline? i
// dont know. TODO: study
glogger.warn("Undefined instruction");
},
[](Undefined) { log_warn("Undefined instruction"); },
[this, pc_error](SingleDataSwap& data) {
/*
N -> reading instruction in step()
N -> unrelated read
S -> related write
I -> earlier read value is written to register
Total = S + 2N +I
*/
pc_error(data.rm);
pc_error(data.rn);
pc_error(data.rd);
if (data.byte) {
gpr[data.rd] =
bus->read_byte(gpr[data.rn], CpuAccess::NonSequential);
bus->write_byte(
gpr[data.rn], gpr[data.rm] & 0xFF, CpuAccess::Sequential);
gpr[data.rd] = bus->read_byte(gpr[data.rn]);
bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
} else {
gpr[data.rd] =
bus->read_word(gpr[data.rn], CpuAccess::NonSequential);
bus->write_word(
gpr[data.rn], gpr[data.rm], CpuAccess::Sequential);
gpr[data.rd] = bus->read_word(gpr[data.rn]);
bus->write_word(gpr[data.rn], gpr[data.rm]);
}
internal_cycle();
// last write address is unrelated to next
next_access = CpuAccess::NonSequential;
},
[this, pc_warn, pc_error, &is_flushed](SingleDataTransfer& data) {
/*
Load
====
S -> reading instruction in step()
N -> read from target
I -> stored in register
N+S -> if PC is written - taken care of by flush_pipeline()
Total = S + N + I or 2S + 2N + I
Store
=====
N -> calculating memory address
N -> write at target
Total = 2N
*/
[this, pc_warn, pc_error](SingleDataTransfer& data) {
uint32_t offset = 0;
uint32_t address = gpr[data.rn];
if (!data.pre && data.write)
glogger.warn("Write-back enabled with post-indexing in {}",
typeid(data).name());
log_warn("Write-back enabled with post-indexing in {}",
typeid(data).name());
if (data.rn == PC_INDEX && data.write)
glogger.warn("Write-back enabled with base register as PC {}",
typeid(data).name());
log_warn("Write-back enabled with base register as PC {}",
typeid(data).name());
if (data.write)
pc_warn(data.rn);
@@ -269,41 +168,35 @@ Cpu::exec(arm::Instruction& instruction) {
cpsr.set_c(carry);
}
// PC is always two instructions ahead
if (data.rn == PC_INDEX)
address -= 2 * ARM_INSTRUCTION_SIZE;
if (data.pre)
address += (data.up ? offset : -offset);
debug(address);
// load
if (data.load) {
// byte
if (data.byte)
gpr[data.rd] =
bus->read_byte(address, CpuAccess::NonSequential);
gpr[data.rd] = bus->read_byte(address);
// word
else
gpr[data.rd] =
bus->read_word(address, CpuAccess::NonSequential);
// N + S
if (data.rd == PC_INDEX)
is_flushed = true;
// I
internal_cycle();
gpr[data.rd] = bus->read_word(address);
// store
} else {
// take PC into consideration
uint32_t value = gpr[data.rd];
if (data.rd == PC_INDEX)
value += INSTRUCTION_SIZE;
address += ARM_INSTRUCTION_SIZE;
// byte
if (data.byte)
bus->write_byte(
address, value & 0xFF, CpuAccess::NonSequential);
bus->write_byte(address, gpr[data.rd] & 0xFF);
// word
else
bus->write_word(address, value, CpuAccess::NonSequential);
bus->write_word(address, gpr[data.rd]);
}
if (!data.pre)
@@ -312,49 +205,28 @@ Cpu::exec(arm::Instruction& instruction) {
if (!data.pre || data.write)
gpr[data.rn] = address;
// last read/write is unrelated, this will be overwriten if
// flushed
next_access = CpuAccess::NonSequential;
if (data.rd == PC_INDEX && data.load)
is_flushed = true;
},
[this, pc_warn, pc_error, &is_flushed](HalfwordTransfer& data) {
/*
Load
====
S -> reading instruction in step()
N -> read from target
I -> stored in register
N+S -> if PC is written - taken care of by flush_pipeline()
Total = S + N + I or 2S + 2N + I
Store
=====
N -> calculating memory address
N -> write at target
Total = 2N
*/
[this, pc_warn, pc_error](HalfwordTransfer& data) {
uint32_t address = gpr[data.rn];
uint32_t offset = 0;
if (!data.pre && data.write)
glogger.error("Write-back enabled with post-indexing in {}",
typeid(data).name());
log_error("Write-back enabled with post-indexing in {}",
typeid(data).name());
if (data.sign && !data.load)
glogger.error("Signed data found in {}", typeid(data).name());
log_error("Signed data found in {}", typeid(data).name());
if (data.write)
pc_warn(data.rn);
// offset is register number (4 bits) when not an immediate
if (!data.imm) {
if (!data.imm)
pc_error(data.offset);
offset = gpr[data.offset];
} else {
offset = data.offset;
}
if (data.pre)
address += (data.up ? offset : -offset);
address += (data.up ? data.offset : -data.offset);
// load
if (data.load) {
@@ -362,8 +234,7 @@ Cpu::exec(arm::Instruction& instruction) {
if (data.sign) {
// halfword
if (data.half) {
gpr[data.rd] =
bus->read_halfword(address, CpuAccess::NonSequential);
gpr[data.rd] = bus->read_halfword(address);
// sign extend the halfword
gpr[data.rd] =
@@ -371,8 +242,7 @@ Cpu::exec(arm::Instruction& instruction) {
// byte
} else {
gpr[data.rd] =
bus->read_byte(address, CpuAccess::NonSequential);
gpr[data.rd] = bus->read_byte(address);
// sign extend the byte
gpr[data.rd] =
@@ -380,71 +250,40 @@ Cpu::exec(arm::Instruction& instruction) {
}
// unsigned halfword
} else if (data.half) {
gpr[data.rd] =
bus->read_halfword(address, CpuAccess::NonSequential);
gpr[data.rd] = bus->read_halfword(address);
}
// I
internal_cycle();
if (data.rd == PC_INDEX)
is_flushed = true;
// store
} else {
uint32_t value = gpr[data.rd];
// take PC into consideration
if (data.rd == PC_INDEX)
value += INSTRUCTION_SIZE;
address += ARM_INSTRUCTION_SIZE;
// halfword
if (data.half)
bus->write_halfword(
address, value & 0xFFFF, CpuAccess::NonSequential);
bus->write_halfword(address, gpr[data.rd]);
}
if (!data.pre)
address += (data.up ? offset : -offset);
address += (data.up ? data.offset : -data.offset);
if (!data.pre || data.write)
gpr[data.rn] = address;
// last read/write is unrelated, this will be overwriten if
// flushed
next_access = CpuAccess::NonSequential;
if (data.rd == PC_INDEX && data.load)
is_flushed = true;
},
[this, pc_error, &is_flushed](BlockDataTransfer& data) {
/*
Load
====
S -> reading instruction in step()
N -> unrelated read from target
(n-1) S -> next n - 1 related reads from target
I -> stored in register
N+S -> if PC is written - taken care of by
flush_pipeline() Total = nS + N + I or (n+1)S + 2N + I
Store
=====
N -> calculating memory address
N -> unrelated write at target
(n-1) S -> next n - 1 related writes
Total = 2N + (n-1)S
*/
static constexpr uint8_t alignment = 4; // word
uint32_t address = gpr[data.rn];
Mode mode = cpsr.mode();
int8_t i = 0;
CpuAccess access = CpuAccess::NonSequential;
[this, pc_error](BlockDataTransfer& data) {
uint32_t address = gpr[data.rn];
Mode mode = cpsr.mode();
uint8_t alignment = 4; // word
uint8_t i = 0;
uint8_t n_regs = std::popcount(data.regs);
pc_error(data.rn);
if (cpsr.mode() == Mode::User && data.s) {
glogger.error("Bit S is set outside priviliged modes in block "
"data transfer");
log_error("Bit S is set outside priviliged modes in {}",
typeid(data).name());
}
// we just change modes to load user registers
@@ -453,88 +292,60 @@ Cpu::exec(arm::Instruction& instruction) {
chg_mode(Mode::User);
if (data.write) {
glogger.error("Write-back enable for user bank registers "
"in block data transfer");
log_error("Write-back enable for user bank registers in {}",
typeid(data).name());
}
}
// increment beforehand
// account for decrement
if (!data.up)
address -= (n_regs - 1) * alignment;
if (data.pre)
address += (data.up ? alignment : -alignment);
if (data.load) {
if (get_bit(data.regs, PC_INDEX)) {
is_flushed = true;
if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
// current mode's spsr is already loaded when it was
// switched
if (data.s)
spsr = cpsr;
spsr = cpsr;
}
if (data.up) {
for (i = 0; i < GPR_COUNT; i++) {
if (get_bit(data.regs, i)) {
gpr[i] = bus->read_word(address, access);
address += alignment;
access = CpuAccess::Sequential;
}
}
} else {
for (i = GPR_COUNT - 1; i >= 0; i--) {
if (get_bit(data.regs, i)) {
gpr[i] = bus->read_word(address, access);
address -= alignment;
access = CpuAccess::Sequential;
}
for (i = 0; i < GPR_COUNT; i++) {
if (get_bit(data.regs, i)) {
gpr[i] = bus->read_word(address);
address += alignment;
}
}
// I
internal_cycle();
} else {
if (data.up) {
for (i = 0; i < GPR_COUNT; i++) {
if (get_bit(data.regs, i)) {
bus->write_word(address, gpr[i], access);
address += alignment;
access = CpuAccess::Sequential;
}
}
} else {
for (i = GPR_COUNT - 1; i >= 0; i--) {
if (get_bit(data.regs, i)) {
bus->write_word(address, gpr[i], access);
address -= alignment;
access = CpuAccess::Sequential;
}
for (i = 0; i < GPR_COUNT; i++) {
if (get_bit(data.regs, i)) {
bus->write_word(address, gpr[i]);
address += alignment;
}
}
}
// fix increment
if (data.pre)
address += (data.up ? -alignment : alignment);
if (!data.pre)
address += (data.up ? alignment : -alignment);
// reset back to original address + offset if incremented earlier
if (data.up)
address -= n_regs * alignment;
if (!data.pre || data.write)
gpr[data.rn] = address;
if (data.load && get_bit(data.regs, PC_INDEX))
is_flushed = true;
// load back the original mode registers
chg_mode(mode);
// last read/write is unrelated, this will be overwriten if
// flushed
next_access = CpuAccess::NonSequential;
},
[this, pc_error](PsrTransfer& data) {
/*
S -> prefetched instruction in step()
Total = 1S cycle
*/
if (data.spsr && cpsr.mode() == Mode::User) {
glogger.error("Accessing SPSR in User mode in {}",
typeid(data).name());
log_error("Accessing SPSR in User mode in {}",
typeid(data).name());
}
Psr& psr = data.spsr ? spsr : cpsr;
@@ -548,50 +359,28 @@ Cpu::exec(arm::Instruction& instruction) {
pc_error(data.operand);
if (cpsr.mode() != Mode::User) {
if (!data.spsr) {
Psr tmp = Psr(gpr[data.operand]);
chg_mode(tmp.mode());
}
psr.set_all(gpr[data.operand]);
}
break;
case PsrTransfer::Type::Msr_flg:
uint32_t operand =
(data.imm ? data.operand : gpr[data.operand]);
psr.set_n(get_bit(operand, 31));
psr.set_z(get_bit(operand, 30));
psr.set_c(get_bit(operand, 29));
psr.set_v(get_bit(operand, 28));
psr.set_n(get_bit(data.operand, 31));
psr.set_z(get_bit(data.operand, 30));
psr.set_c(get_bit(data.operand, 29));
psr.set_v(get_bit(data.operand, 28));
break;
}
},
[this, pc_error, &is_flushed](DataProcessing& data) {
/*
Always
======
S -> prefetched instruction in step()
With Register specified shift
=============================
I -> internal cycle
When PC is written
==================
N -> fetch from the new address in branch
S -> last opcode fetch at +L to refill the pipeline
S+N taken care of by flush_pipeline()
Total = S or S + I or 2S + N + I or 2S + N cycles
*/
using OpCode = DataProcessing::OpCode;
[this, pc_error](DataProcessing& data) {
uint32_t op_1 = gpr[data.rn];
uint32_t op_2 = 0;
uint32_t result = 0;
bool overflow = cpsr.v();
bool carry = cpsr.c();
bool negative = cpsr.n();
bool zero = cpsr.z();
if (const uint32_t* immediate =
std::get_if<uint32_t>(&data.operand)) {
op_2 = *immediate;
@@ -613,73 +402,154 @@ Cpu::exec(arm::Instruction& instruction) {
// PC is 12 bytes ahead when shifting
if (data.rn == PC_INDEX)
op_1 += INSTRUCTION_SIZE;
// 1I when register specified shift
if (!shift->data.immediate)
internal_cycle();
op_1 += ARM_INSTRUCTION_SIZE;
}
bool overflow = cpsr.v();
bool carry = cpsr.c();
switch (data.opcode) {
case OpCode::AND:
case OpCode::TST:
case OpCode::AND: {
result = op_1 & op_2;
result = op_1 & op_2;
break;
case OpCode::EOR:
case OpCode::TEQ:
negative = get_bit(result, 31);
} break;
case OpCode::EOR: {
result = op_1 ^ op_2;
break;
case OpCode::SUB:
case OpCode::CMP:
result = sub(op_1, op_2, carry, overflow);
break;
case OpCode::RSB:
result = sub(op_2, op_1, carry, overflow);
break;
case OpCode::ADD:
case OpCode::CMN:
result = add(op_1, op_2, carry, overflow);
break;
case OpCode::ADC:
result = add(op_1, op_2, carry, overflow, carry);
break;
case OpCode::SBC:
result = sbc(op_1, op_2, carry, overflow, carry);
break;
case OpCode::RSC:
result = sbc(op_2, op_1, carry, overflow, carry);
break;
case OpCode::ORR:
negative = get_bit(result, 31);
} break;
case OpCode::SUB: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
result = op_1 - op_2;
negative = get_bit(result, 31);
carry = op_1 < op_2;
overflow = s1 != s2 && s2 == negative;
} break;
case OpCode::RSB: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
result = op_2 - op_1;
negative = get_bit(result, 31);
carry = op_2 < op_1;
overflow = s1 != s2 && s1 == negative;
} break;
case OpCode::ADD: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
// result_ is 33 bits
uint64_t result_ = op_2 + op_1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 == s2 && s1 != negative;
} break;
case OpCode::ADC: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_2 + op_1 + carry;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 == s2 && s1 != negative;
} break;
case OpCode::SBC: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_1 - op_2 + carry - 1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 != s2 && s2 == negative;
} break;
case OpCode::RSC: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_1 - op_2 + carry - 1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 != s2 && s1 == negative;
} break;
case OpCode::TST: {
result = op_1 & op_2;
negative = get_bit(result, 31);
} break;
case OpCode::TEQ: {
result = op_1 ^ op_2;
negative = get_bit(result, 31);
} break;
case OpCode::CMP: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
result = op_1 - op_2;
negative = get_bit(result, 31);
carry = op_1 < op_2;
overflow = s1 != s2 && s2 == negative;
} break;
case OpCode::CMN: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_2 + op_1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 == s2 && s1 != negative;
} break;
case OpCode::ORR: {
result = op_1 | op_2;
break;
case OpCode::MOV:
negative = get_bit(result, 31);
} break;
case OpCode::MOV: {
result = op_2;
break;
case OpCode::BIC:
negative = get_bit(result, 31);
} break;
case OpCode::BIC: {
result = op_1 & ~op_2;
break;
case OpCode::MVN:
negative = get_bit(result, 31);
} break;
case OpCode::MVN: {
result = ~op_2;
break;
negative = get_bit(result, 31);
} break;
}
auto set_conditions = [this, carry, overflow, result]() {
zero = result == 0;
debug(carry);
debug(overflow);
debug(zero);
debug(negative);
auto set_conditions = [this, carry, overflow, negative, zero]() {
cpsr.set_c(carry);
cpsr.set_v(overflow);
cpsr.set_n(get_bit(result, 31));
cpsr.set_z(result == 0);
cpsr.set_n(negative);
cpsr.set_z(zero);
};
if (data.set) {
if (data.rd == PC_INDEX) {
if (data.rd == 15) {
if (cpsr.mode() == Mode::User)
glogger.error("Running {} in User mode",
typeid(data).name());
spsr = cpsr;
log_error("Running {} in User mode",
typeid(data).name());
} else {
set_conditions();
}
@@ -690,24 +560,17 @@ Cpu::exec(arm::Instruction& instruction) {
set_conditions();
} else {
gpr[data.rd] = result;
if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
if (data.rd == 15 || data.opcode == OpCode::MVN)
is_flushed = true;
}
},
[this, &is_flushed](SoftwareInterrupt) {
[this](SoftwareInterrupt) {
chg_mode(Mode::Supervisor);
pc = 0x00;
spsr = cpsr;
is_flushed = true;
pc = 0x08;
spsr = cpsr;
},
[](auto& data) {
glogger.error("Unimplemented {} instruction", typeid(data).name());
log_error("Unimplemented {} instruction", typeid(data).name());
} },
instruction.data);
if (is_flushed)
flush_pipeline<State::Arm>();
else
advance_pc_arm();
}
data);
}

236
src/cpu/arm/instruction.cc
View File

@@ -1,7 +1,10 @@
#include "cpu/arm/instruction.hh"
#include "cpu/utility.hh"
#include "util/bits.hh"
#include <iterator>
using namespace arm;
namespace matar::arm {
Instruction::Instruction(uint32_t insn)
: condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
// Branch and exhcange
@@ -12,11 +15,13 @@ Instruction::Instruction(uint32_t insn)
// Branch
} else if ((insn & 0x0E000000) == 0x0A000000) {
bool link = get_bit(insn, 24);
int32_t offset = static_cast<int32_t>(bit_range(insn, 0, 23));
bool link = get_bit(insn, 24);
uint32_t offset = bit_range(insn, 0, 23);
// lsh 2 and sign extend the 26 bit offset to 32 bits
offset = (offset << 8) >> 6;
offset = (static_cast<int32_t>(offset) << 8) >> 6;
offset += 2 * ARM_INSTRUCTION_SIZE;
data = Branch{ .link = link, .offset = offset };
@@ -147,8 +152,6 @@ Instruction::Instruction(uint32_t insn)
// Data Processing
} else if ((insn & 0x0C000000) == 0x00000000) {
using OpCode = DataProcessing::OpCode;
uint8_t rd = bit_range(insn, 12, 15);
uint8_t rn = bit_range(insn, 16, 19);
bool set = get_bit(insn, 20);
@@ -270,4 +273,225 @@ Instruction::Instruction(uint32_t insn)
data = Undefined{};
}
}
std::string
Instruction::disassemble() {
// goddamn this is gore
// TODO: make this less ugly
return std::visit(
overloaded{
[this](BranchAndExchange& data) {
return fmt::format("BX{} R{:d}", condition, data.rn);
},
[this](Branch& data) {
return fmt::format(
"B{}{} 0x{:06X}", (data.link ? "L" : ""), condition, data.offset);
},
[this](Multiply& data) {
if (data.acc) {
return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
condition,
(data.set ? "S" : ""),
data.rd,
data.rm,
data.rs,
data.rn);
} else {
return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
condition,
(data.set ? "S" : ""),
data.rd,
data.rm,
data.rs);
}
},
[this](MultiplyLong& data) {
return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
(data.uns ? 'U' : 'S'),
(data.acc ? "MLAL" : "MULL"),
condition,
(data.set ? "S" : ""),
data.rdlo,
data.rdhi,
data.rm,
data.rs);
},
[](Undefined) { return std::string("UND"); },
[this](SingleDataSwap& data) {
return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
condition,
(data.byte ? "B" : ""),
data.rd,
data.rm,
data.rn);
},
[this](SingleDataTransfer& data) {
std::string expression;
std::string address;
if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
if (*offset == 0) {
expression = "";
} else {
expression =
fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
}
} else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
// Shifts are always immediate in single data transfer
expression = fmt::format(",{}R{:d},{} #{:d}",
(data.up ? '+' : '-'),
shift->rm,
shift->data.type,
shift->data.operand);
}
return fmt::format(
"{}{}{}{} R{:d},[R{:d}{}]{}",
(data.load ? "LDR" : "STR"),
condition,
(data.byte ? "B" : ""),
(!data.pre && data.write ? "T" : ""),
data.rd,
data.rn,
(data.pre ? expression : ""),
(data.pre ? (data.write ? "!" : "") : expression));
},
[this](HalfwordTransfer& data) {
std::string expression;
if (data.imm) {
if (data.offset == 0) {
expression = "";
} else {
expression = fmt::format(
",{}#{:d}", (data.up ? '+' : '-'), data.offset);
}
} else {
expression =
fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
}
return fmt::format(
"{}{}{}{} R{:d},[R{:d}{}]{}",
(data.load ? "LDR" : "STR"),
condition,
(data.sign ? "S" : ""),
(data.half ? 'H' : 'B'),
data.rd,
data.rn,
(data.pre ? expression : ""),
(data.pre ? (data.write ? "!" : "") : expression));
},
[this](BlockDataTransfer& data) {
std::string regs;
for (uint8_t i = 0; i < 16; i++) {
if (get_bit(data.regs, i))
fmt::format_to(std::back_inserter(regs), "R{:d},", i);
};
regs.pop_back();
return fmt::format("{}{}{}{} R{:d}{},{{{}}}{}",
(data.load ? "LDM" : "STM"),
condition,
(data.up ? 'I' : 'D'),
(data.pre ? 'B' : 'A'),
data.rn,
(data.write ? "!" : ""),
regs,
(data.s ? "^" : ""));
},
[this](PsrTransfer& data) {
if (data.type == PsrTransfer::Type::Mrs) {
return fmt::format("MRS{} R{:d},{}",
condition,
data.operand,
(data.spsr ? "SPSR_all" : "CPSR_all"));
} else {
return fmt::format(
"MSR{} {}_{},{}{}",
condition,
(data.spsr ? "SPSR" : "CPSR"),
(data.type == PsrTransfer::Type::Msr_flg ? "flg" : "all"),
(data.imm ? '#' : 'R'),
data.operand);
}
},
[this](DataProcessing& data) {
std::string op_2;
if (const uint32_t* operand =
std::get_if<uint32_t>(&data.operand)) {
op_2 = fmt::format("#{:d}", *operand);
} else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
op_2 = fmt::format("R{:d},{} {}{:d}",
shift->rm,
shift->data.type,
(shift->data.immediate ? '#' : 'R'),
shift->data.operand);
}
switch (data.opcode) {
case OpCode::MOV:
case OpCode::MVN:
return fmt::format("{}{}{} R{:d},{}",
data.opcode,
condition,
(data.set ? "S" : ""),
data.rd,
op_2);
case OpCode::TST:
case OpCode::TEQ:
case OpCode::CMP:
case OpCode::CMN:
return fmt::format(
"{}{} R{:d},{}", data.opcode, condition, data.rn, op_2);
default:
return fmt::format("{}{}{} R{:d},R{:d},{}",
data.opcode,
condition,
(data.set ? "S" : ""),
data.rd,
data.rn,
op_2);
}
},
[this](SoftwareInterrupt) { return fmt::format("SWI{}", condition); },
[this](CoprocessorDataTransfer& data) {
std::string expression = fmt::format(",#{:d}", data.offset);
return fmt::format(
"{}{}{} p{:d},c{:d},[R{:d}{}]{}",
(data.load ? "LDC" : "STC"),
condition,
(data.len ? "L" : ""),
data.cpn,
data.crd,
data.rn,
(data.pre ? expression : ""),
(data.pre ? (data.write ? "!" : "") : expression));
},
[this](CoprocessorDataOperation& data) {
return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
condition,
data.cpn,
data.cp_opc,
data.crd,
data.crn,
data.crm,
data.cp);
},
[this](CoprocessorRegisterTransfer& data) {
return fmt::format("{}{} p{},{},R{},c{},c{},{}",
(data.load ? "MRC" : "MCR"),
condition,
data.cpn,
data.cp_opc,
data.rd,
data.crn,
data.crm,
data.cp);
},
[](auto) { return std::string("unknown instruction"); } },
data);
}

4
src/cpu/arm/meson.build
View File

@@ -2,7 +2,3 @@ lib_sources += files(
'instruction.cc',
'exec.cc'
)
if get_option('disassembler')
lib_sources += files('disassembler.cc')
endif

104
src/cpu/cpu.cc
View File

@@ -1,20 +1,29 @@
#include "cpu/cpu.hh"
#include "cpu/arm/instruction.hh"
#include "cpu/thumb/instruction.hh"
#include "cpu/utility.hh"
#include "util/bits.hh"
#include "util/log.hh"
#include <algorithm>
#include <cstdio>
namespace matar {
Cpu::Cpu(std::shared_ptr<Bus> bus) noexcept
: bus(bus) {
using namespace logger;
Cpu::Cpu(const Bus& bus)
: bus(std::make_shared<Bus>(bus))
, gpr({ 0 })
, cpsr(0)
, spsr(0)
, is_flushed(false)
, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
, spsr_banked({ 0, 0, 0, 0, 0 }) {
cpsr.set_mode(Mode::Supervisor);
cpsr.set_irq_disabled(true);
cpsr.set_fiq_disabled(true);
cpsr.set_state(State::Arm);
glogger.info("CPU successfully initialised");
log_info("CPU successfully initialised");
// PC always points to two instructions ahead
flush_pipeline<State::Arm>();
// PC - 2 is the instruction being executed
pc += 2 * ARM_INSTRUCTION_SIZE;
}
/* change modes */
@@ -29,16 +38,13 @@ Cpu::chg_mode(const Mode to) {
* concatenate views */
#define STORE_BANKED(mode, MODE) \
std::copy(gpr.begin() + GPR_##MODE##_FIRST, \
gpr.end() - 1, \
gpr.begin() + gpr.size() - 1, \
gpr_banked.mode.begin())
switch (from) {
case Mode::Fiq:
STORE_BANKED(fiq, FIQ);
spsr_banked.fiq = spsr;
std::copy(gpr_banked.old.begin(),
gpr_banked.old.end() - 2, // dont copy R13 and R14
gpr.begin() + GPR_OLD_FIRST);
break;
case Mode::Supervisor:
@@ -63,15 +69,10 @@ Cpu::chg_mode(const Mode to) {
case Mode::User:
case Mode::System:
// we only take care of r13 and r14, because FIQ takes care of the
// rest
gpr_banked.old[5] = gpr[13];
gpr_banked.old[6] = gpr[14];
STORE_BANKED(old, SYS_USR);
break;
}
#undef STORE_BANKED
#define RESTORE_BANKED(mode, MODE) \
std::copy(gpr_banked.mode.begin(), \
gpr_banked.mode.end(), \
@@ -81,9 +82,6 @@ Cpu::chg_mode(const Mode to) {
case Mode::Fiq:
RESTORE_BANKED(fiq, FIQ);
spsr = spsr_banked.fiq;
std::copy(gpr.begin() + GPR_FIQ_FIRST,
gpr.end() - 2, // dont copy R13 and R14
gpr_banked.old.begin());
break;
case Mode::Supervisor:
@@ -108,65 +106,39 @@ Cpu::chg_mode(const Mode to) {
case Mode::User:
case Mode::System:
gpr[13] = gpr_banked.old[5];
gpr[14] = gpr_banked.old[6];
STORE_BANKED(old, SYS_USR);
break;
}
#undef RESTORE_BANKED
cpsr.set_mode(to);
glogger.info_bold("Mode changed from {:b} to {:b}",
static_cast<uint32_t>(from),
static_cast<uint32_t>(to));
}
void
Cpu::step() {
// halfword align
rst_bit(pc, 0);
// Current instruction is two instructions behind PC
uint32_t cur_pc = pc - 2 * ARM_INSTRUCTION_SIZE;
if (cpsr.state() == State::Arm) {
// word align
rst_bit(pc, 1);
debug(cur_pc);
uint32_t x = bus->read_word(cur_pc);
arm::Instruction instruction(x);
log_info("{:#034b}", x);
arm::Instruction instruction(opcodes[0]);
exec_arm(instruction);
opcodes[0] = opcodes[1];
opcodes[1] = bus->read_word(pc, next_access);
log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
#ifdef DISASSEMBLER
glogger.info("0x{:08X} : {}",
pc - 2 * arm::INSTRUCTION_SIZE,
instruction.disassemble());
#endif
exec(instruction);
} else {
thumb::Instruction instruction(opcodes[0]);
opcodes[0] = opcodes[1];
opcodes[1] = bus->read_halfword(pc, next_access);
#ifdef DISASSEMBLER
glogger.info("0x{:08X} : {}",
pc - 2 * thumb::INSTRUCTION_SIZE,
instruction.disassemble());
#endif
exec(instruction);
if (is_flushed) {
// if flushed, do not increment the PC, instead set it to two
// instructions ahead to account for flushed "fetch" and "decode"
// instructions
pc += 2 * ARM_INSTRUCTION_SIZE;
is_flushed = false;
} else {
// if not flushed continue like normal
pc += ARM_INSTRUCTION_SIZE;
}
}
}
void
Cpu::advance_pc_arm() {
rst_bit(pc, 0);
rst_bit(pc, 1);
pc += arm::INSTRUCTION_SIZE;
};
void
Cpu::advance_pc_thumb() {
rst_bit(pc, 0);
pc += thumb::INSTRUCTION_SIZE;
}
}

3
src/cpu/meson.build
View File

@@ -1,8 +1,7 @@
lib_sources += files(
'cpu.cc',
'psr.cc',
'alu.cc'
'utility.cc'
)
subdir('arm')
subdir('thumb')

9
src/cpu/psr.cc
View File

@@ -1,7 +1,7 @@
#include "cpu/psr.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar {
Psr::Psr(uint32_t raw)
: psr(raw & PSR_CLEAR_RESERVED) {}
@@ -12,17 +12,17 @@ Psr::raw() const {
void
Psr::set_all(uint32_t raw) {
psr = raw;
psr = raw & ~PSR_CLEAR_RESERVED;
}
Mode
Psr::mode() const {
return static_cast<Mode>(psr & 0b11111);
return static_cast<Mode>(psr & ~PSR_CLEAR_MODE);
}
void
Psr::set_mode(Mode mode) {
psr &= 0b00000;
psr &= PSR_CLEAR_MODE;
psr |= static_cast<uint32_t>(mode);
}
@@ -95,4 +95,3 @@ Psr::condition(Condition cond) const {
return false;
}
}

155
src/cpu/thumb/disassembler.cc
View File

@@ -1,155 +0,0 @@
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include <format>
namespace matar::thumb {
std::string
Instruction::disassemble() {
return std::visit(
overloaded{
[](MoveShiftedRegister& data) {
return std::format("{} R{:d},R{:d},#{:d}",
stringify(data.opcode),
data.rd,
data.rs,
data.offset);
},
[](AddSubtract& data) {
return std::format("{} R{:d},R{:d},{}{:d}",
stringify(data.opcode),
data.rd,
data.rs,
(data.imm ? '#' : 'R'),
data.offset);
},
[](MovCmpAddSubImmediate& data) {
return std::format(
"{} R{:d},#{:d}", stringify(data.opcode), data.rd, data.offset);
},
[](AluOperations& data) {
return std::format(
"{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
},
[](HiRegisterOperations& data) {
if (data.opcode == HiRegisterOperations::OpCode::BX) {
return std::format("{} R{:d}", stringify(data.opcode), data.rs);
}
return std::format(
"{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
},
[](PcRelativeLoad& data) {
return std::format("LDR R{:d},[PC,#{:d}]", data.rd, data.word);
},
[](LoadStoreRegisterOffset& data) {
return std::format("{}{} R{:d},[R{:d},R{:d}]",
(data.load ? "LDR" : "STR"),
(data.byte ? "B" : ""),
data.rd,
data.rb,
data.ro);
},
[](LoadStoreSignExtendedHalfword& data) {
if (!data.s && !data.h) {
return std::format(
"STRH R{:d},[R{:d},R{:d}]", data.rd, data.rb, data.ro);
}
return std::format("{}{} R{:d},[R{:d},R{:d}]",
(data.s ? "LDS" : "LDR"),
(data.h ? 'H' : 'B'),
data.rd,
data.rb,
data.ro);
},
[](LoadStoreImmediateOffset& data) {
return std::format("{}{} R{:d},[R{:d},#{:d}]",
(data.load ? "LDR" : "STR"),
(data.byte ? "B" : ""),
data.rd,
data.rb,
data.offset);
},
[](LoadStoreHalfword& data) {
return std::format("{} R{:d},[R{:d},#{:d}]",
(data.load ? "LDRH" : "STRH"),
data.rd,
data.rb,
data.offset);
},
[](SpRelativeLoad& data) {
return std::format("{} R{:d},[SP,#{:d}]",
(data.load ? "LDR" : "STR"),
data.rd,
data.word);
},
[](LoadAddress& data) {
return std::format("ADD R{:d},{},#{:d}",
data.rd,
(data.sp ? "SP" : "PC"),
data.word);
},
[](AddOffsetStackPointer& data) {
return std::format("ADD SP,#{:d}", data.word);
},
[](PushPopRegister& data) {
std::string regs;
for (uint8_t i = 0; i < 16; i++) {
if (get_bit(data.regs, i))
std::format_to(std::back_inserter(regs), "R{:d},", i);
};
if (data.load) {
if (data.pclr)
regs += "PC";
else
regs.pop_back();
return std::format("POP {{{}}}", regs);
} else {
if (data.pclr)
regs += "LR";
else
regs.pop_back();
return std::format("PUSH {{{}}}", regs);
}
},
[](MultipleLoad& data) {
std::string regs;
for (uint8_t i = 0; i < 16; i++) {
if (get_bit(data.regs, i))
std::format_to(std::back_inserter(regs), "R{:d},", i);
};
regs.pop_back();
return std::format(
"{} R{}!,{{{}}}", (data.load ? "LDMIA" : "STMIA"), data.rb, regs);
},
[](SoftwareInterrupt& data) {
return std::format("SWI {:d}", data.vector);
},
[](ConditionalBranch& data) {
return std::format(
"B{} #{:d}",
stringify(data.condition),
static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
},
[](UnconditionalBranch& data) {
return std::format(
"B #{:d}",
static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
},
[](LongBranchWithLink& data) {
// duh this manual be empty for H = 0
return std::format(
"BL{} #{:d}", (data.low ? "" : "H"), data.offset);
},
[](auto) { return std::string("unknown instruction"); } },
data);
}
}

612
src/cpu/thumb/exec.cc
View File

@@ -1,612 +0,0 @@
#include "bus.hh"
#include "cpu/alu.hh"
#include "cpu/cpu.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar {
void
Cpu::exec(thumb::Instruction& instruction) {
bool is_flushed = false;
dbg(pc);
auto set_cc = [this](bool c, bool v, bool n, bool z) {
cpsr.set_c(c);
cpsr.set_v(v);
cpsr.set_n(n);
cpsr.set_z(z);
};
using namespace thumb;
std::visit(
overloaded{
[this, set_cc](MoveShiftedRegister& data) {
/*
S -> prefetched instruction in step()
Total = S cycle
*/
if (data.opcode == ShiftType::ROR)
glogger.error("Invalid opcode in {}", typeid(data).name());
bool carry = cpsr.c();
uint32_t shifted =
eval_shift(data.opcode, gpr[data.rs], data.offset, carry);
gpr[data.rd] = shifted;
set_cc(carry, cpsr.v(), get_bit(shifted, 31), shifted == 0);
},
[this, set_cc](AddSubtract& data) {
/*
S -> prefetched instruction in step()
Total = S cycle
*/
uint32_t offset =
data.imm ? static_cast<uint32_t>(static_cast<int8_t>(data.offset))
: gpr[data.offset];
uint32_t result = 0;
bool carry = cpsr.c();
bool overflow = cpsr.v();
switch (data.opcode) {
case AddSubtract::OpCode::ADD:
result = add(gpr[data.rs], offset, carry, overflow);
break;
case AddSubtract::OpCode::SUB:
result = sub(gpr[data.rs], offset, carry, overflow);
break;
}
gpr[data.rd] = result;
set_cc(carry, overflow, get_bit(result, 31), result == 0);
},
[this, set_cc](MovCmpAddSubImmediate& data) {
/*
S -> prefetched instruction in step()
Total = S cycle
*/
uint32_t result = 0;
bool carry = cpsr.c();
bool overflow = cpsr.v();
switch (data.opcode) {
case MovCmpAddSubImmediate::OpCode::MOV:
result = data.offset;
carry = 0;
break;
case MovCmpAddSubImmediate::OpCode::ADD:
result = add(gpr[data.rd], data.offset, carry, overflow);
break;
case MovCmpAddSubImmediate::OpCode::SUB:
case MovCmpAddSubImmediate::OpCode::CMP:
result = sub(gpr[data.rd], data.offset, carry, overflow);
break;
}
set_cc(carry, overflow, get_bit(result, 31), result == 0);
if (data.opcode != MovCmpAddSubImmediate::OpCode::CMP)
gpr[data.rd] = result;
},
[this, set_cc](AluOperations& data) {
/*
Data Processing
===============
S -> prefetched instruction in step()
I -> only when register specified shift
Total = S or S + I cycles
Multiply
========
S -> reading instruction in step()
mI -> m internal cycles
let v = data at rn
m = 1 if bits [32:8] of v are all zero or all one
m = 2 [32:16]
m = 3 [32:24]
m = 4 otherwise
Total = S + mI cycles
*/
uint32_t op_1 = gpr[data.rd];
uint32_t op_2 = gpr[data.rs];
uint32_t result = 0;
bool carry = cpsr.c();
bool overflow = cpsr.v();
switch (data.opcode) {
case AluOperations::OpCode::AND:
case AluOperations::OpCode::TST:
result = op_1 & op_2;
break;
case AluOperations::OpCode::EOR:
result = op_1 ^ op_2;
break;
case AluOperations::OpCode::LSL:
result = eval_shift(ShiftType::LSL, op_1, op_2, carry);
internal_cycle();
break;
case AluOperations::OpCode::LSR:
result = eval_shift(ShiftType::LSR, op_1, op_2, carry);
internal_cycle();
break;
case AluOperations::OpCode::ASR:
result = eval_shift(ShiftType::ASR, op_1, op_2, carry);
internal_cycle();
break;
case AluOperations::OpCode::ADC:
result = add(op_1, op_2, carry, overflow, carry);
break;
case AluOperations::OpCode::SBC:
result = sbc(op_1, op_2, carry, overflow, carry);
break;
case AluOperations::OpCode::ROR:
result = eval_shift(ShiftType::ROR, op_1, op_2, carry);
internal_cycle();
break;
case AluOperations::OpCode::NEG:
result = -op_2;
break;
case AluOperations::OpCode::CMP:
result = sub(op_1, op_2, carry, overflow);
break;
case AluOperations::OpCode::CMN:
result = add(op_1, op_2, carry, overflow);
break;
case AluOperations::OpCode::ORR:
result = op_1 | op_2;
break;
case AluOperations::OpCode::MUL:
result = op_1 * op_2;
// mI cycles
for (int i = 0; i < multiplier_array_cycles(op_2); i++)
internal_cycle();
break;
case AluOperations::OpCode::BIC:
result = op_1 & ~op_2;
break;
case AluOperations::OpCode::MVN:
result = ~op_2;
break;
}
if (data.opcode != AluOperations::OpCode::TST &&
data.opcode != AluOperations::OpCode::CMP &&
data.opcode != AluOperations::OpCode::CMN)
gpr[data.rd] = result;
set_cc(carry, overflow, get_bit(result, 31), result == 0);
},
[this, set_cc, &is_flushed](HiRegisterOperations& data) {
/*
Always
======
S -> prefetched instruction in step()
When PC is written
==================
N -> fetch from the new address in branch
S -> last opcode fetch at +L to refill the pipeline
S+N taken care of by flush_pipeline()
Total = S or 2S + N cycles
*/
uint32_t op_1 = gpr[data.rd];
uint32_t op_2 = gpr[data.rs];
bool carry = cpsr.c();
bool overflow = cpsr.v();
// PC is already current + 4, so dont need to do that
if (data.rd == PC_INDEX)
rst_bit(op_1, 0);
if (data.rs == PC_INDEX)
rst_bit(op_2, 0);
switch (data.opcode) {
case HiRegisterOperations::OpCode::ADD: {
gpr[data.rd] = add(op_1, op_2, carry, overflow);
if (data.rd == PC_INDEX)
is_flushed = true;
} break;
case HiRegisterOperations::OpCode::CMP: {
uint32_t result = sub(op_1, op_2, carry, overflow);
set_cc(carry, overflow, get_bit(result, 31), result == 0);
} break;
case HiRegisterOperations::OpCode::MOV: {
gpr[data.rd] = op_2;
if (data.rd == PC_INDEX)
is_flushed = true;
} break;
case HiRegisterOperations::OpCode::BX: {
State state = static_cast<State>(get_bit(op_2, 0));
if (state != cpsr.state())
glogger.info_bold("State changed");
// set state
cpsr.set_state(state);
// copy to PC
pc = op_2;
// ignore [1:0] bits for arm and 0 bit for thumb
rst_bit(pc, 0);
if (state == State::Arm)
rst_bit(pc, 1);
// pc is affected so flush the pipeline
is_flushed = true;
} break;
}
},
[this](PcRelativeLoad& data) {
/*
S -> reading instruction in step()
N -> read from target
I -> stored in register
Total = S + N + I cycles
*/
uint32_t pc_ = pc;
rst_bit(pc_, 0);
rst_bit(pc_, 1);
gpr[data.rd] =
bus->read_word(pc_ + data.word, CpuAccess::NonSequential);
internal_cycle();
// last read is unrelated
next_access = CpuAccess::NonSequential;
},
[this](LoadStoreRegisterOffset& data) {
/*
Load
====
S -> reading instruction in step()
N -> read from target
I -> stored in register
Total = S + N + I
Store
=====
N -> calculating memory address
N -> write at target
Total = 2N
*/
uint32_t address = gpr[data.rb] + gpr[data.ro];
if (data.load) {
if (data.byte) {
gpr[data.rd] =
bus->read_byte(address, CpuAccess::NonSequential);
} else {
gpr[data.rd] =
bus->read_word(address, CpuAccess::NonSequential);
}
internal_cycle();
} else {
if (data.byte) {
bus->write_byte(
address, gpr[data.rd] & 0xFF, CpuAccess::NonSequential);
} else {
bus->write_word(
address, gpr[data.rd], CpuAccess::NonSequential);
}
}
// last read/write is unrelated
next_access = CpuAccess::NonSequential;
},
[this](LoadStoreSignExtendedHalfword& data) {
// Same cycles as above
uint32_t address = gpr[data.rb] + gpr[data.ro];
switch (data.s << 1 | data.h) {
case 0b00:
bus->write_halfword(
address, gpr[data.rd] & 0xFFFF, CpuAccess::NonSequential);
break;
case 0b01:
gpr[data.rd] =
bus->read_halfword(address, CpuAccess::NonSequential);
internal_cycle();
break;
case 0b10:
// sign extend and load the byte
gpr[data.rd] = (static_cast<int32_t>(bus->read_byte(
address, CpuAccess::NonSequential))
<< 24) >>
24;
internal_cycle();
break;
case 0b11:
// sign extend the halfword
gpr[data.rd] = (static_cast<int32_t>(bus->read_halfword(
address, CpuAccess::NonSequential))
<< 16) >>
16;
internal_cycle();
break;
// unreachable
default: {
}
}
// last read/write is unrelated
next_access = CpuAccess::NonSequential;
},
[this](LoadStoreImmediateOffset& data) {
// Same cycles as above
uint32_t address = gpr[data.rb] + data.offset;
dbg(address);
if (data.load) {
if (data.byte) {
gpr[data.rd] =
bus->read_byte(address, CpuAccess::NonSequential);
} else {
gpr[data.rd] =
bus->read_word(address, CpuAccess::NonSequential);
}
internal_cycle();
} else {
if (data.byte) {
bus->write_byte(
address, gpr[data.rd] & 0xFF, CpuAccess::NonSequential);
} else {
bus->write_word(
address, gpr[data.rd], CpuAccess::NonSequential);
}
}
// last read/write is unrelated
next_access = CpuAccess::NonSequential;
},
[this](LoadStoreHalfword& data) {
// Same cycles as above
uint32_t address = gpr[data.rb] + data.offset;
if (data.load) {
gpr[data.rd] =
bus->read_halfword(address, CpuAccess::NonSequential);
internal_cycle();
} else {
bus->write_halfword(
address, gpr[data.rd] & 0xFFFF, CpuAccess::NonSequential);
}
// last read/write is unrelated
next_access = CpuAccess::NonSequential;
},
[this](SpRelativeLoad& data) {
// Same cycles as above
uint32_t address = sp + data.word;
if (data.load) {
gpr[data.rd] = bus->read_word(address, CpuAccess::Sequential);
internal_cycle();
} else {
bus->write_word(address, gpr[data.rd], CpuAccess::Sequential);
}
// last read/write is unrelated
next_access = CpuAccess::NonSequential;
},
[this](LoadAddress& data) {
// 1S cycle in step()
if (data.sp) {
gpr[data.rd] = sp + data.word;
} else {
// PC is already current + 4, so dont need to do that
// force bit 1 to 0
gpr[data.rd] = (pc & ~(1 << 1)) + data.word;
}
},
[this](AddOffsetStackPointer& data) {
// 1S cycle in step()
sp += data.word;
},
[this, &is_flushed](PushPopRegister& data) {
/*
Load
====
S -> reading instruction in step()
N -> unrelated read from target
(n-1) S -> next n - 1 related reads from target
I -> stored in register
N+S -> if PC is written - taken care of by flush_pipeline()
S -> if PC, memory read for PC write
Total = nS + N + I or (n+2)S + 2N + I
Store
=====
N -> calculating memory address
N -> if LR, memory read for PC write
N/S -> unrelated write at target
(n-1) S -> next n - 1 related writes
Total = 2N + nS or 2N + (n-1)S
*/
static constexpr uint8_t alignment = 4;
CpuAccess access = CpuAccess::NonSequential;
if (data.load) {
for (uint8_t i = 0; i < 8; i++) {
if (get_bit(data.regs, i)) {
gpr[i] = bus->read_word(sp, access);
sp += alignment;
access = CpuAccess::Sequential;
}
}
if (data.pclr) {
pc = bus->read_word(sp, access);
sp += alignment;
is_flushed = true;
}
// I
internal_cycle();
} else {
if (data.pclr) {
sp -= alignment;
bus->write_word(sp, lr, access);
access = CpuAccess::Sequential;
}
for (int8_t i = 7; i >= 0; i--) {
if (get_bit(data.regs, i)) {
sp -= alignment;
bus->write_word(sp, gpr[i], access);
access = CpuAccess::Sequential;
}
}
}
// last read/write is unrelated
next_access = CpuAccess::NonSequential;
},
[this](MultipleLoad& data) {
/*
Load
====
S -> reading instruction in step()
N -> unrelated read from target
(n-1) S -> next n - 1 related reads from target
I -> stored in register
Total = nS + N + I
Store
=====
N -> calculating memory address
N -> unrelated write at target
(n-1) S -> next n - 1 related writes
Total = 2N + (n-1)S
*/
static constexpr uint8_t alignment = 4;
uint32_t rb = gpr[data.rb];
CpuAccess access = CpuAccess::NonSequential;
if (data.load) {
for (uint8_t i = 0; i < 8; i++) {
if (get_bit(data.regs, i)) {
gpr[i] = bus->read_word(rb, access);
rb += alignment;
access = CpuAccess::Sequential;
}
}
internal_cycle();
} else {
for (uint8_t i = 0; i < 8; i++) {
if (get_bit(data.regs, i)) {
bus->write_word(rb, gpr[i], access);
rb += alignment;
access = CpuAccess::Sequential;
}
}
}
gpr[data.rb] = rb;
// last read/write is unrelated
next_access = CpuAccess::NonSequential;
},
[this, &is_flushed](ConditionalBranch& data) {
/*
S -> reading instruction in step()
N+S -> if condition is true, branch and refill pipeline
Total = S or 2S + N
*/
if (data.condition == Condition::AL)
glogger.warn("Condition 1110 (AL) is undefined");
if (!cpsr.condition(data.condition))
return;
pc += data.offset;
is_flushed = true;
},
[this, &is_flushed](SoftwareInterrupt& data) {
/*
S -> reading instruction in step()
N+S -> refill pipeline
Total = 2S + N
*/
// next instruction is one instruction behind PC
lr = pc - INSTRUCTION_SIZE;
spsr = cpsr;
pc = data.vector;
cpsr.set_state(State::Arm);
chg_mode(Mode::Supervisor);
is_flushed = true;
},
[this, &is_flushed](UnconditionalBranch& data) {
/*
S -> reading instruction in step()
N+S -> branch and refill pipeline
Total = 2S + N
*/
pc += data.offset;
is_flushed = true;
},
[this, &is_flushed](LongBranchWithLink& data) {
/*
S -> prefetched instruction in step()
N -> fetch from the new address in branch
S -> last opcode fetch at +L to refill the pipeline
Total = 2S + N cycles
1S done, S+N taken care of by flush_pipeline()
*/
// 12 bit integer
int32_t offset = data.offset;
if (data.low) {
uint32_t old_pc = pc;
offset <<= 1;
pc = lr + offset;
lr = (old_pc - INSTRUCTION_SIZE) | 1;
is_flushed = true;
} else {
// 12 + 11 = 23 bit
offset <<= 12;
// sign extend
offset = (offset << 9) >> 9;
lr = pc + offset;
}
},
[](auto& data) {
glogger.error("Unknown thumb format : {}", typeid(data).name());
} },
instruction.data);
if (is_flushed)
flush_pipeline<State::Thumb>();
else
advance_pc_thumb();
}
}

211
src/cpu/thumb/instruction.cc
View File

@@ -1,211 +0,0 @@
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar::thumb {
Instruction::Instruction(uint16_t insn) {
// Format 2: Add/Subtract
if ((insn & 0xF800) == 0x1800) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rs = bit_range(insn, 3, 5);
uint8_t offset = bit_range(insn, 6, 8);
AddSubtract::OpCode opcode =
static_cast<AddSubtract::OpCode>(get_bit(insn, 9));
bool imm = get_bit(insn, 10);
data = AddSubtract{
.rd = rd, .rs = rs, .offset = offset, .opcode = opcode, .imm = imm
};
// Format 1: Move Shifted Register
} else if ((insn & 0xE000) == 0x0000) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rs = bit_range(insn, 3, 5);
uint8_t offset = bit_range(insn, 6, 10);
ShiftType opcode = static_cast<ShiftType>(bit_range(insn, 11, 12));
data = MoveShiftedRegister{
.rd = rd, .rs = rs, .offset = offset, .opcode = opcode
};
// Format 3: Move/compare/add/subtract immediate
} else if ((insn & 0xE000) == 0x2000) {
uint8_t offset = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
MovCmpAddSubImmediate::OpCode opcode =
static_cast<MovCmpAddSubImmediate::OpCode>(bit_range(insn, 11, 12));
data =
MovCmpAddSubImmediate{ .offset = offset, .rd = rd, .opcode = opcode };
// Format 4: ALU operations
} else if ((insn & 0xFC00) == 0x4000) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rs = bit_range(insn, 3, 5);
AluOperations::OpCode opcode =
static_cast<AluOperations::OpCode>(bit_range(insn, 6, 9));
data = AluOperations{ .rd = rd, .rs = rs, .opcode = opcode };
// Format 5: Hi register operations/branch exchange
} else if ((insn & 0xFC00) == 0x4400) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rs = bit_range(insn, 3, 5);
bool hi_2 = get_bit(insn, 6);
bool hi_1 = get_bit(insn, 7);
HiRegisterOperations::OpCode opcode =
static_cast<HiRegisterOperations::OpCode>(bit_range(insn, 8, 9));
if (opcode == HiRegisterOperations::OpCode::BX && hi_1)
glogger.warn("H1 set with BX");
rd += (hi_1 ? LO_GPR_COUNT : 0);
rs += (hi_2 ? LO_GPR_COUNT : 0);
data = HiRegisterOperations{ .rd = rd, .rs = rs, .opcode = opcode };
// Format 6: PC-relative load
} else if ((insn & 0xF800) == 0x4800) {
uint16_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
data =
PcRelativeLoad{ .word = static_cast<uint16_t>(word << 2), .rd = rd };
// Format 7: Load/store with register offset
} else if ((insn & 0xF200) == 0x5000) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rb = bit_range(insn, 3, 5);
uint8_t ro = bit_range(insn, 6, 8);
bool byte = get_bit(insn, 10);
bool load = get_bit(insn, 11);
data = LoadStoreRegisterOffset{
.rd = rd, .rb = rb, .ro = ro, .byte = byte, .load = load
};
// Format 8: Load/store sign-extended byte/halfword
} else if ((insn & 0xF200) == 0x5200) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rb = bit_range(insn, 3, 5);
uint8_t ro = bit_range(insn, 6, 8);
bool s = get_bit(insn, 10);
bool h = get_bit(insn, 11);
data = LoadStoreSignExtendedHalfword{
.rd = rd, .rb = rb, .ro = ro, .s = s, .h = h
};
// Format 9: Load/store with immediate offset
} else if ((insn & 0xE000) == 0x6000) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rb = bit_range(insn, 3, 5);
uint8_t offset = bit_range(insn, 6, 10);
bool load = get_bit(insn, 11);
bool byte = get_bit(insn, 12);
if (!byte)
offset <<= 2;
data = LoadStoreImmediateOffset{
.rd = rd, .rb = rb, .offset = offset, .load = load, .byte = byte
};
// Format 10: Load/store halfword
} else if ((insn & 0xF000) == 0x8000) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rb = bit_range(insn, 3, 5);
uint8_t offset = bit_range(insn, 6, 10);
bool load = get_bit(insn, 11);
offset <<= 1;
data = LoadStoreHalfword{
.rd = rd, .rb = rb, .offset = offset, .load = load
};
// Format 11: SP-relative load/store
} else if ((insn & 0xF000) == 0x9000) {
uint16_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
bool load = get_bit(insn, 11);
word <<= 2;
data = SpRelativeLoad{ .word = word, .rd = rd, .load = load };
// Format 12: Load address
} else if ((insn & 0xF000) == 0xA000) {
uint16_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
bool sp = get_bit(insn, 11);
word <<= 2;
data = LoadAddress{ .word = word, .rd = rd, .sp = sp };
// Format 13: Add offset to stack pointer
} else if ((insn & 0xFF00) == 0xB000) {
int16_t word = static_cast<int16_t>(bit_range(insn, 0, 6));
bool sign = get_bit(insn, 7);
word <<= 2;
word = static_cast<int16_t>(word * (sign ? -1 : 1));
data = AddOffsetStackPointer{
.word = word,
};
// Format 14: Push/pop registers
} else if ((insn & 0xF600) == 0xB400) {
uint8_t regs = bit_range(insn, 0, 7);
bool pclr = get_bit(insn, 8);
bool load = get_bit(insn, 11);
data = PushPopRegister{ .regs = regs, .pclr = pclr, .load = load };
// Format 15: Multiple load/store
} else if ((insn & 0xF000) == 0xC000) {
uint8_t regs = bit_range(insn, 0, 7);
uint8_t rb = bit_range(insn, 8, 10);
bool load = get_bit(insn, 11);
data = MultipleLoad{ .regs = regs, .rb = rb, .load = load };
// Format 17: Software interrupt
} else if ((insn & 0xFF00) == 0xDF00) {
uint8_t vector = bit_range(insn, 0, 7);
data = SoftwareInterrupt{ .vector = vector };
// Format 16: Conditional branch
} else if ((insn & 0xF000) == 0xD000) {
int32_t offset = bit_range(insn, 0, 7);
Condition condition = static_cast<Condition>(bit_range(insn, 8, 11));
offset <<= 1;
// sign extend the 9 bit integer
offset = (offset << 23) >> 23;
data = ConditionalBranch{ .offset = offset, .condition = condition };
// Format 18: Unconditional branch
} else if ((insn & 0xF800) == 0xE000) {
int32_t offset = bit_range(insn, 0, 10);
offset <<= 1;
// sign extend the 12 bit integer
offset = (offset << 20) >> 20;
data = UnconditionalBranch{ .offset = offset };
// Format 19: Long branch with link
} else if ((insn & 0xF000) == 0xF000) {
uint16_t offset = bit_range(insn, 0, 10);
bool low = get_bit(insn, 11);
data = LongBranchWithLink{ .offset = offset, .low = low };
}
}
}

8
src/cpu/thumb/meson.build
View File

@@ -1,8 +0,0 @@
lib_sources += files(
'instruction.cc',
'exec.cc'
)
if get_option('disassembler')
lib_sources += files('disassembler.cc')
endif

137
src/cpu/utility.cc Normal file
View File

@@ -0,0 +1,137 @@
#include "cpu/utility.hh"
#include "util/bits.hh"
#include <bit>
std::ostream&
operator<<(std::ostream& os, const Condition cond) {
#define CASE(cond) \
case Condition::cond: \
os << #cond; \
break;
switch (cond) {
CASE(EQ)
CASE(NE)
CASE(CS)
CASE(CC)
CASE(MI)
CASE(PL)
CASE(VS)
CASE(VC)
CASE(HI)
CASE(LS)
CASE(GE)
CASE(LT)
CASE(GT)
CASE(LE)
case Condition::AL: {
// empty
}
}
#undef CASE
return os;
}
std::ostream&
operator<<(std::ostream& os, const OpCode opcode) {
#define CASE(opcode) \
case OpCode::opcode: \
os << #opcode; \
break;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(SUB)
CASE(RSB)
CASE(ADD)
CASE(ADC)
CASE(SBC)
CASE(RSC)
CASE(TST)
CASE(TEQ)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MOV)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return os;
}
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
uint32_t eval = 0;
switch (shift_type) {
case ShiftType::LSL:
if (amount > 0 && amount <= 32)
carry = get_bit(value, 32 - amount);
else if (amount > 32)
carry = 0;
eval = value << amount;
break;
case ShiftType::LSR:
if (amount > 0 && amount <= 32)
carry = get_bit(value, amount - 1);
else if (amount > 32)
carry = 0;
else
carry = get_bit(value, 31);
eval = value >> amount;
break;
case ShiftType::ASR:
if (amount > 0 && amount <= 32)
carry = get_bit(value, amount - 1);
else
carry = get_bit(value, 31);
return static_cast<int32_t>(value) >> amount;
break;
case ShiftType::ROR:
if (amount == 0) {
bool old_carry = carry;
carry = get_bit(value, 0);
eval = (value >> 1) | (old_carry << 31);
} else {
carry = get_bit(value, (amount % 32 + 31) % 32);
eval = std::rotr(value, amount);
}
break;
}
return eval;
}
std::ostream&
operator<<(std::ostream& os, const ShiftType shift_type) {
#define CASE(type) \
case ShiftType::type: \
os << #type; \
break;
switch (shift_type) {
CASE(LSL)
CASE(LSR)
CASE(ASR)
CASE(ROR)
}
#undef CASE
return os;
}

487
src/gdb_rsp.cc
View File

@@ -1,487 +0,0 @@
#include "gdb_rsp.hh"
#include "util/log.hh"
#include <csignal>
#include <numeric>
#include <regex>
#include <stdexcept>
#include <string>
namespace matar {
template<typename... Args>
static inline constexpr void
gdb_log(const std::format_string<Args...>& fmt, Args&&... args) {
glogger.debug("GDB: {}", std::format(fmt, std::forward<Args>(args)...));
}
static inline void
append_le(std::string& str, uint32_t value) {
// little endian only
str += std::format("{:02x}", value & 0xFF);
str += std::format("{:02x}", value >> 8 & 0xFF);
str += std::format("{:02x}", value >> 16 & 0xFF);
str += std::format("{:02x}", value >> 24 & 0xFF);
}
static inline std::string
be_to_le(std::string str) {
if (str.length() != 8)
throw std::out_of_range("string is supposed to be 8 bytes");
std::string current;
for (int i = 7; i >= 0; i -= 2) {
current += str[i - 1];
current += str[i];
}
return current;
}
GdbRsp::GdbRsp(std::shared_ptr<Cpu> cpu, uint port)
: cpu(cpu) {
server.start(port);
}
void
GdbRsp::start() {
server.run();
attach();
// attaching is not enough, we continue, until the last GDB communication
// happens for ARMv4t i.e, fetching of the CPSR
std::string msg;
while (msg != "$p19") {
msg = receive();
step(msg); // 25th (0x19) register is cpsr
}
}
void
GdbRsp::attach() {
while (!attached) {
step();
}
}
void
GdbRsp::satisfy_client() {
while (server.client_waiting() && attached) {
step();
}
}
void
GdbRsp::step() {
std::string msg = receive();
step(msg);
}
void
GdbRsp::step(std::string msg) {
switch (msg[0]) {
case '+':
break;
case '-':
break;
case '\x03':
gdb_log("ctrl+c interrupt received");
cmd_halted();
break;
case '$': {
acknowledge();
switch (msg[1]) {
case '?':
cmd_halted();
break;
case 'g':
cmd_read_registers();
break;
case 'G':
cmd_write_registers(msg);
break;
case 'p':
cmd_read_register(msg);
break;
case 'P':
cmd_write_register(msg);
break;
case 'm':
cmd_read_memory(msg);
break;
case 'M':
cmd_write_memory(msg);
break;
case 'z':
cmd_rm_breakpoint(msg);
break;
case 'Z':
cmd_add_breakpoint(msg);
break;
case 'c':
cmd_continue();
break;
case 'D':
cmd_detach();
break;
case 'Q':
if (msg == "$QStartNoAckMode")
ack_mode = true;
send_ok();
break;
case 'q':
if (msg.starts_with("$qSupported")) {
cmd_supported(msg);
break;
} else if (msg == "$qAttached") {
cmd_attached();
break;
}
[[fallthrough]];
default:
gdb_log("unknown command");
send_empty();
}
break;
}
default:
gdb_log("unknown message received");
}
}
std::string
GdbRsp::receive() {
std::string msg = server.receive(1);
char ch = msg[0];
uint checksum = 0;
if (ch == '$') {
while ((ch = server.receive(1)[0]) != '#') {
checksum += static_cast<uint>(ch);
msg += ch;
if (msg.length() > MAX_MSG_LEN) {
throw std::logic_error("GDB: received message is too long");
}
}
if (std::stoul(server.receive(2), nullptr, 16) != (checksum & 0xFF)) {
gdb_log("{}", msg);
throw std::logic_error("GDB: bad message checksum");
}
}
gdb_log("received message \"{}\"", msg);
return msg;
}
std::string
GdbRsp::make_packet(std::string raw) {
uint checksum = std::accumulate(raw.begin(), raw.end(), 0);
return std::format("${}#{:02x}", raw, checksum & 0xFF);
}
void
GdbRsp::acknowledge() {
if (ack_mode)
server.send("+");
}
void
GdbRsp::send_empty() {
server.send(make_packet(""));
}
void
GdbRsp::send_ok() {
acknowledge();
server.send(make_packet("OK"));
}
void
GdbRsp::notify_breakpoint_reached() {
gdb_log("reached breakpoint, sending signal");
server.send(make_packet(std::format("S{:02x}", SIGTRAP)));
}
void
GdbRsp::cmd_attached() {
attached = true;
gdb_log("server is now attached");
server.send(make_packet("1"));
}
void
GdbRsp::cmd_supported(std::string msg) {
std::string response;
if (msg.find("hwbreak+;") != std::string::npos)
response += "hwbreak+;";
// no acknowledgement mode
response += "QStartNoAckMode+";
gdb_log("sending response for qSupported");
server.send(make_packet(response));
}
void
GdbRsp::cmd_halted() {
gdb_log("sending reason for upcoming halt");
server.send(make_packet(std::format("S{:02x}", SIGTRAP)));
}
void
GdbRsp::cmd_read_registers() {
std::string response;
for (int i = 0; i < cpu->GPR_COUNT - 1; i++)
append_le(response, cpu->gpr[i]);
// for some reason this PC needs to be the address of executing instruction
// i.e, two instructions behind actual PC
append_le(response,
cpu->pc - 2 * (cpu->cpsr.state() == State::Arm
? arm::INSTRUCTION_SIZE
: thumb::INSTRUCTION_SIZE));
gdb_log("sending register values");
server.send(make_packet(response));
}
void
GdbRsp::cmd_write_registers(std::string msg) {
static std::regex rgx("\\$G([0-9A-Fa-f]+)");
std::smatch sm;
regex_match(msg, sm, rgx);
if (sm.size() != 2 || sm[1].str().size() != 16 * 8) {
gdb_log("invalid arguments to write registers");
send_empty();
return;
}
try {
std::string values = sm[1].str();
for (uint i = 0, j = 0; i < values.length() - 8; i += 8, j++) {
cpu->gpr[i] = std::stoul(sm[i + 1].str(), nullptr, 16);
cpu->gpr[j] =
std::stoul(be_to_le(values.substr(i, 8)), nullptr, 16);
}
gdb_log("register values written");
send_ok();
} catch (const std::exception& e) {
gdb_log("{}", e.what());
send_empty();
}
}
void
GdbRsp::cmd_read_register(std::string msg) {
std::string response;
try {
uint reg = std::stoul(msg.substr(2), nullptr, 16);
// 25th register is CPSR in gdb ARM
if (reg == 25)
append_le(response, cpu->cpsr.raw());
else if (reg < cpu->GPR_COUNT)
append_le(response, cpu->gpr[reg]);
else
response += "xxxxxxxx";
gdb_log("sending single register value");
server.send(make_packet(response));
} catch (const std::exception& e) {
gdb_log("{}", e.what());
send_empty();
}
}
void
GdbRsp::cmd_write_register(std::string msg) {
static std::regex rgx("\\$P([0-9A-Fa-f]+)\\=([0-9A-Fa-f]+)");
std::smatch sm;
regex_match(msg, sm, rgx);
if (sm.size() != 3 && sm[2].str().length() != 8) {
gdb_log("invalid arguments to write single register");
send_empty();
return;
}
try {
uint reg = std::stoul(sm[1].str(), nullptr, 16);
uint32_t value = std::stoul(be_to_le(sm[2].str()), nullptr, 16);
dbg(value);
if (reg == 25)
cpu->cpsr.set_all(value);
else if (reg < cpu->GPR_COUNT)
cpu->gpr[reg] = value;
gdb_log("single register value written");
send_ok();
} catch (const std::exception& e) {
gdb_log("{}", e.what());
send_empty();
}
}
void
GdbRsp::cmd_read_memory(std::string msg) {
std::string response;
static std::regex rgx("\\$m([0-9A-Fa-f]+),([0-9A-Fa-f]+)");
std::smatch sm;
regex_match(msg, sm, rgx);
if (sm.size() != 3) {
gdb_log("invalid arguments to read memory");
send_empty();
return;
}
uint32_t address = 0, length = 0;
try {
address = std::stoul(sm[1].str(), nullptr, 16);
length = std::stoul(sm[2].str(), nullptr, 16);
} catch (const std::exception& e) {
gdb_log("{}", e.what());
send_empty();
return;
}
for (uint i = 0; i < length; i++) {
response += std::format("{:02x}", cpu->bus->read_byte(address + i));
}
gdb_log("sending memory values values");
server.send(make_packet(response));
}
void
GdbRsp::cmd_write_memory(std::string msg) {
static std::regex rgx("\\$M([0-9A-Fa-f]+),([0-9A-Fa-f]+):([0-9A-Fa-f]+)");
std::smatch sm;
regex_match(msg, sm, rgx);
if (sm.size() != 4) {
gdb_log("invalid arguments to write memory");
send_empty();
return;
}
try {
uint32_t address = std::stoul(sm[1].str(), nullptr, 16);
uint32_t length = std::stoul(sm[2].str(), nullptr, 16);
std::string values = sm[3].str();
for (uint i = 0, j = 0; i < length && j < values.size(); i++, j += 2) {
cpu->bus->write_byte(
address + i, std::stoul(values.substr(j, 2), nullptr, 16) & 0xFF);
}
gdb_log("register values written");
send_ok();
} catch (const std::exception& e) {
gdb_log("{}", e.what());
send_empty();
}
}
void
GdbRsp::cmd_rm_breakpoint(std::string msg) {
static std::regex rgx("\\$z(0|1),([0-9A-Fa-f]+),(2|3|4)");
std::smatch sm;
regex_match(msg, sm, rgx);
if (sm.size() != 4) {
gdb_log("invalid arguments to remove breakpoint");
send_empty();
return;
}
if (sm[1].str() != "0" && sm[0].str() != "1") {
gdb_log("unrecognized breakpoint type encountered");
send_empty();
return;
}
if (sm[3].str() != "3" && sm[3].str() != "4") {
gdb_log("only 32 bit breakpoints supported");
send_empty();
return;
}
try {
uint32_t address = std::stoul(sm[2].str(), nullptr, 16);
cpu->breakpoints.erase(address);
gdb_log("breakpoint {:#08x} removed", address);
send_ok();
} catch (const std::exception& e) {
gdb_log("{}", e.what());
send_empty();
}
}
void
GdbRsp::cmd_add_breakpoint(std::string msg) {
static std::regex rgx("\\$Z(0|1),([0-9A-Fa-f]+),(2|3|4)");
std::smatch sm;
regex_match(msg, sm, rgx);
dbg(sm.size());
dbg(sm[0].str());
if (sm.size() != 4) {
gdb_log("invalid arguments to add breakpoint");
send_empty();
return;
}
if (sm[1].str() != "0" && sm[0].str() != "1") {
gdb_log("unrecognized breakpoint type encountered");
send_empty();
return;
}
if (sm[3].str() != "3" && sm[3].str() != "4") {
gdb_log("only 32 bit breakpoints supported");
send_empty();
return;
}
try {
uint32_t address = std::stoul(sm[2].str(), nullptr, 16);
cpu->breakpoints.insert(address);
gdb_log("breakpoint {:#08x} added", address);
send_ok();
} catch (const std::exception& e) {
gdb_log("{}", e.what());
send_empty();
}
}
void
GdbRsp::cmd_detach() {
attached = false;
gdb_log("detached");
send_ok();
}
void
GdbRsp::cmd_continue() {
// what to do?
gdb_log("cpu continued");
send_ok();
}
}

47
src/gdb_rsp.hh
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@@ -1,47 +0,0 @@
#include "cpu/cpu.hh"
#include "util/tcp_server.hh"
namespace matar {
class GdbRsp {
public:
GdbRsp(std::shared_ptr<Cpu> cpu, uint port);
~GdbRsp() = default;
void start();
void attach();
void satisfy_client();
void step();
void step(std::string msg);
void notify_breakpoint_reached();
inline bool is_attached() { return attached; }
private:
bool attached = false;
std::shared_ptr<Cpu> cpu;
net::TcpServer server;
std::string receive();
std::string make_packet(std::string raw);
bool ack_mode = true;
void acknowledge();
void send_empty();
void send_ok();
// Commands
void cmd_attached();
void cmd_supported(std::string msg);
void cmd_halted();
void cmd_read_registers();
void cmd_write_registers(std::string msg);
void cmd_read_register(std::string msg);
void cmd_write_register(std::string msg);
void cmd_read_memory(std::string msg);
void cmd_write_memory(std::string msg);
void cmd_rm_breakpoint(std::string msg);
void cmd_add_breakpoint(std::string msg);
void cmd_detach();
void cmd_continue();
static constexpr uint MAX_MSG_LEN = 4096;
};
}

23
src/io/display/display.cc
View File

@@ -1,23 +0,0 @@
#include "io/display/display.hh"
namespace matar {
namespace display {
/*
static constexpr uint LCD_HEIGHT = 160;
static constexpr uint LCD_WIDTH = 240;
static constexpr uint BLANK = 68;
static constexpr uint PIXEL_CYCLES = 4; // 4
static constexpr uint HDRAW_CYCLES = LCD_WIDTH * PIXEL_CYCLES + 46; // 1006
static constexpr uint HBLANK_CYCLES = BLANK * PIXEL_CYCLES - 46; // 226
static constexpr uint HREFRESH_CYCLES = HDRAW_CYCLES + HBLANK_CYCLES; // 1232
static constexpr uint VDRAW_CYCLES = LCD_HEIGHT * HREFRESH_CYCLES; // 197120
static constexpr uint VBLANK_CYCLES = BLANK * HREFRESH_CYCLES; // 83776
static constexpr uint VREFRESH_CYCLES = VDRAW_CYCLES + VBLANK_CYCLES; // 280896
*/
void
Display::mode_3() {}
}
}

3
src/io/display/meson.build
View File

@@ -1,3 +0,0 @@
lib_sources += files(
'display.cc'
)

51
src/io/display/render.cc
View File

@@ -1,51 +0,0 @@
#include "io/display/display.hh"
namespace matar {
namespace display {
struct TextScreen {
uint16_t tile_number : 10;
bool mirror_horizontal : 1;
bool mirror_vertical : 1;
uint8_t palette_number : 4;
};
// if 16th bit is set, this will denote the transparent color in rgb555 format
static constexpr uint16_t TRANSPARENT_RGB555 = 0x8000;
template<int MODE, typename>
void
Display::render_bitmap_mode() {
static constexpr std::size_t VIEWPORT_WIDTH = MODE == 5 ? 160 : 240;
for (int x = 0; x < LCD_WIDTH; x++) {
// pixel to texel for x
// shift by 8 cuz both ref.x and a are fixed point floats shifted by 8
int32_t x_ = (bg2_rot_scale.ref.x + x * bg2_rot_scale.a) >> 8;
int32_t y_ = (bg2_rot_scale.ref.y + x * bg2_rot_scale.c) >> 8;
// ignore handling area overflow for bitmap modes
// i am not sure how well this will turn out
std::size_t idx = y_ * VIEWPORT_WIDTH + x_;
// mode 3 and 5 takes 2 bytes per pixel
if constexpr (MODE != 4)
idx *= 2;
// offset
if constexpr (MODE != 3) {
std::size_t offset =
lcd_control.value.frame_select_1 ? 0xA000 : 0x0000;
idx += offset;
}
// read two bytes
if constexpr (MODE == 4)
scanline_buffers[2][x] = pram.read_halfword(vram.read_byte(idx));
else
scanline_buffers[2][x] = vram.read_halfword(idx);
}
}
}
}

419
src/io/io.cc
View File

@@ -1,419 +0,0 @@
#include "io/io.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar {
#define ADDR static constexpr uint32_t
// lcd
ADDR DISPCNT = 0x4000000;
ADDR DISPSTAT = 0x4000004;
ADDR VCOUNT = 0x4000006;
ADDR BG0CNT = 0x4000008;
ADDR BG1CNT = 0x400000A;
ADDR BG2CNT = 0x400000C;
ADDR BG3CNT = 0x400000E;
ADDR BG0HOFS = 0x4000010;
ADDR BG0VOFS = 0x4000012;
ADDR BG1HOFS = 0x4000014;
ADDR BG1VOFS = 0x4000016;
ADDR BG2HOFS = 0x4000018;
ADDR BG2VOFS = 0x400001A;
ADDR BG3HOFS = 0x400001C;
ADDR BG3VOFS = 0x400001E;
ADDR BG2PA = 0x4000020;
ADDR BG2PB = 0x4000022;
ADDR BG2PC = 0x4000024;
ADDR BG2PD = 0x4000026;
ADDR BG2X_L = 0x4000028;
ADDR BG2X_H = 0x400002A;
ADDR BG2Y_L = 0x400002C;
ADDR BG2Y_H = 0x400002E;
ADDR BG3PA = 0x4000030;
ADDR BG3PB = 0x4000032;
ADDR BG3PC = 0x4000034;
ADDR BG3PD = 0x4000036;
ADDR BG3X_L = 0x4000038;
ADDR BG3X_H = 0x400003A;
ADDR BG3Y_L = 0x400003C;
ADDR BG3Y_H = 0x400003E;
ADDR WIN0H = 0x4000040;
ADDR WIN1H = 0x4000042;
ADDR WIN0V = 0x4000044;
ADDR WIN1V = 0x4000046;
ADDR WININ = 0x4000048;
ADDR WINOUT = 0x400004A;
ADDR MOSAIC = 0x400004C;
ADDR BLDCNT = 0x4000050;
ADDR BLDALPHA = 0x4000052;
ADDR BLDY = 0x4000054;
// sound
ADDR SOUND1CNT_L = 0x4000060;
ADDR SOUND1CNT_H = 0x4000062;
ADDR SOUND1CNT_X = 0x4000064;
ADDR SOUND2CNT_L = 0x4000068;
ADDR SOUND2CNT_H = 0x400006C;
ADDR SOUND3CNT_L = 0x4000070;
ADDR SOUND3CNT_H = 0x4000072;
ADDR SOUND3CNT_X = 0x4000074;
ADDR SOUND4CNT_L = 0x4000078;
ADDR SOUND4CNT_H = 0x400007C;
ADDR SOUNDCNT_L = 0x4000080;
ADDR SOUNDCNT_H = 0x4000082;
ADDR SOUNDCNT_X = 0x4000084;
ADDR SOUNDBIAS = 0x4000088;
ADDR WAVE_RAM0_L = 0x4000090;
ADDR WAVE_RAM0_H = 0x4000092;
ADDR WAVE_RAM1_L = 0x4000094;
ADDR WAVE_RAM1_H = 0x4000096;
ADDR WAVE_RAM2_L = 0x4000098;
ADDR WAVE_RAM2_H = 0x400009A;
ADDR WAVE_RAM3_L = 0x400009C;
ADDR WAVE_RAM3_H = 0x400009E;
ADDR FIFO_A_L = 0x40000A0;
ADDR FIFO_A_H = 0x40000A2;
ADDR FIFO_B_L = 0x40000A4;
ADDR FIFO_B_H = 0x40000A6;
// dma
ADDR DMA0SAD = 0x40000B0;
ADDR DMA0DAD = 0x40000B4;
ADDR DMA0CNT_L = 0x40000B8;
ADDR DMA0CNT_H = 0x40000BA;
ADDR DMA1SAD = 0x40000BC;
ADDR DMA1DAD = 0x40000C0;
ADDR DMA1CNT_L = 0x40000C4;
ADDR DMA1CNT_H = 0x40000C6;
ADDR DMA2SAD = 0x40000C8;
ADDR DMA2DAD = 0x40000CC;
ADDR DMA2CNT_L = 0x40000D0;
ADDR DMA2CNT_H = 0x40000D2;
ADDR DMA3SAD = 0x40000D4;
ADDR DMA3DAD = 0x40000D8;
ADDR DMA3CNT_L = 0x40000DC;
ADDR DMA3CNT_H = 0x40000DE;
// system
ADDR POSTFLG = 0x4000300;
ADDR IME = 0x4000208;
ADDR IE = 0x4000200;
ADDR IF = 0x4000202;
ADDR WAITCNT = 0x4000204;
ADDR HALTCNT = 0x4000301;
#undef ADDR
IoDevices::IoDevices(std::weak_ptr<Bus> bus)
: bus(bus) {}
uint8_t
IoDevices::read_byte(uint32_t address) const {
uint16_t halfword = read_halfword(address & ~1);
if (address & 1)
halfword >>= 8;
return halfword & 0xFF;
}
void
IoDevices::write_byte(uint32_t address, uint8_t byte) {
uint16_t halfword = read_halfword(address & ~1);
if (address & 1)
write_halfword(address & ~1,
(static_cast<uint16_t>(byte) << 8) | (halfword & 0xFF));
else
write_halfword(address & ~1,
(static_cast<uint16_t>(byte) | (halfword & 0xFF00)));
}
uint32_t
IoDevices::read_word(uint32_t address) const {
return read_halfword(address) | read_halfword(address + 2) << 16;
}
void
IoDevices::write_word(uint32_t address, uint32_t word) {
write_halfword(address, word & 0xFFFF);
write_halfword(address + 2, (word >> 16) & 0xFFFF);
}
uint16_t
IoDevices::read_halfword(uint32_t address) const {
switch (address) {
#define READ(name, var) \
case name: \
return var;
// lcd
case DISPCNT:
return display.lcd_control.read();
case DISPSTAT:
return display.general_lcd_status.read();
case BG0CNT:
return display.bg_control[0].read();
case BG1CNT:
return display.bg_control[1].read();
case BG2CNT:
return display.bg_control[2].read();
case BG3CNT:
return display.bg_control[3].read();
READ(VCOUNT, display.vertical_counter)
READ(WININ, display.inside_win_0_1)
READ(WINOUT, display.outside_win)
READ(BLDCNT, display.color_special_effects_selection)
READ(BLDALPHA, display.alpha_blending_coefficients)
// sound
READ(SOUND1CNT_L, sound.ch1_sweep)
READ(SOUND1CNT_H, sound.ch1_duty_length_env)
READ(SOUND1CNT_X, sound.ch1_freq_control)
READ(SOUND2CNT_L, sound.ch2_duty_length_env)
READ(SOUND2CNT_H, sound.ch2_freq_control)
READ(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
READ(SOUND3CNT_H, sound.ch3_length_volume)
READ(SOUND3CNT_X, sound.ch3_freq_control)
READ(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
READ(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
READ(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
READ(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
READ(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
READ(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
READ(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
READ(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
READ(SOUND4CNT_L, sound.ch4_length_env);
READ(SOUND4CNT_H, sound.ch4_freq_control);
READ(SOUNDCNT_L, sound.ctrl_stereo_volume);
READ(SOUNDCNT_H, sound.ctrl_mixing);
READ(SOUNDCNT_X, sound.ctrl_sound_on_off);
READ(SOUNDBIAS, sound.pwm_control);
// dma
case DMA0CNT_H:
return dma.channels[0].control.read();
case DMA1CNT_H:
return dma.channels[1].control.read();
case DMA2CNT_H:
return dma.channels[2].control.read();
case DMA3CNT_H:
return dma.channels[3].control.read();
READ(DMA0SAD, dma.channels[0].source[0]);
READ(DMA0SAD + 2, dma.channels[0].source[1]);
READ(DMA0DAD, dma.channels[0].destination[0]);
READ(DMA0DAD + 2, dma.channels[0].destination[1]);
READ(DMA0CNT_L, dma.channels[0].word_count);
READ(DMA1SAD, dma.channels[1].source[0]);
READ(DMA1SAD + 2, dma.channels[1].source[1]);
READ(DMA1DAD, dma.channels[1].destination[0]);
READ(DMA1DAD + 2, dma.channels[1].destination[1]);
READ(DMA1CNT_L, dma.channels[1].word_count);
READ(DMA2SAD, dma.channels[2].source[0]);
READ(DMA2SAD + 2, dma.channels[2].source[1]);
READ(DMA2DAD, dma.channels[2].destination[0]);
READ(DMA2DAD + 2, dma.channels[2].destination[1]);
READ(DMA2CNT_L, dma.channels[2].word_count);
READ(DMA3SAD, dma.channels[3].source[0]);
READ(DMA3SAD + 2, dma.channels[3].source[1]);
READ(DMA3DAD, dma.channels[3].destination[0]);
READ(DMA3DAD + 2, dma.channels[3].destination[1]);
READ(DMA3CNT_L, dma.channels[3].word_count);
// system
READ(POSTFLG, system.post_boot_flag)
READ(IME, system.interrupt_master_enabler)
READ(IE, system.interrupt_enable);
READ(IF, system.interrupt_request_flags);
READ(WAITCNT, system.waitstate_control);
#undef READ
default:
glogger.warn("Unused IO address read at 0x{:08X}", address);
}
return 0xFF;
}
void
IoDevices::write_halfword(uint32_t address, uint16_t halfword) {
// set lower 16 bits for reference points (BG 2/3)
auto ref_low = [](uint32_t original, uint16_t low) {
return static_cast<int32_t>((original & 0xFFFF0000) | low);
};
// set upper 12 bits for reference points (BG 2/3)
// and sign extend
auto ref_high = [](uint32_t original, uint16_t high) {
return static_cast<int32_t>(
((((high & 0xFFF) << 16) | (original & 0xFFFF)) << 4) >> 4);
};
switch (address) {
#define WRITE(name, var) \
case name: \
var = halfword; \
break;
#define WRITE_2(name, var, val) \
case name: \
var = val; \
break;
// lcd
case DISPCNT:
display.lcd_control.write(halfword);
break;
case DISPSTAT:
display.general_lcd_status.write(halfword);
break;
case BG0CNT:
display.bg_control[0].write(halfword);
break;
case BG1CNT:
display.bg_control[1].write(halfword);
break;
case BG2CNT:
display.bg_control[2].write(halfword);
break;
case BG3CNT:
display.bg_control[3].write(halfword);
break;
WRITE(BG0HOFS, display.bg0_offset.x)
WRITE(BG0VOFS, display.bg0_offset.y)
WRITE(BG1HOFS, display.bg1_offset.x)
WRITE(BG1VOFS, display.bg1_offset.y)
WRITE(BG2HOFS, display.bg2_offset.x)
WRITE(BG2VOFS, display.bg2_offset.y)
WRITE(BG3HOFS, display.bg3_offset.x)
WRITE(BG3VOFS, display.bg3_offset.y)
WRITE(BG2PA, display.bg2_rot_scale.a)
WRITE(BG2PB, display.bg2_rot_scale.b)
WRITE(BG2PC, display.bg2_rot_scale.c)
WRITE(BG2PD, display.bg2_rot_scale.d)
WRITE_2(BG2X_L,
display.bg2_rot_scale.ref.x,
ref_low(display.bg2_rot_scale.ref.x, halfword));
WRITE_2(BG2X_H,
display.bg2_rot_scale.ref.x,
ref_high(display.bg2_rot_scale.ref.x, halfword));
WRITE_2(BG2Y_L,
display.bg2_rot_scale.ref.y,
ref_low(display.bg2_rot_scale.ref.y, halfword));
WRITE_2(BG2Y_H,
display.bg2_rot_scale.ref.y,
ref_high(display.bg2_rot_scale.ref.y, halfword));
WRITE(BG3PA, display.bg3_rot_scale.a)
WRITE(BG3PB, display.bg3_rot_scale.b)
WRITE(BG3PC, display.bg3_rot_scale.c)
WRITE(BG3PD, display.bg3_rot_scale.d)
WRITE_2(BG3X_L,
display.bg3_rot_scale.ref.x,
ref_low(display.bg3_rot_scale.ref.x, halfword));
WRITE_2(BG3X_H,
display.bg3_rot_scale.ref.x,
ref_high(display.bg3_rot_scale.ref.x, halfword));
WRITE_2(BG3Y_L,
display.bg3_rot_scale.ref.y,
ref_low(display.bg3_rot_scale.ref.y, halfword));
WRITE_2(BG3Y_H,
display.bg3_rot_scale.ref.y,
ref_high(display.bg3_rot_scale.ref.y, halfword));
WRITE(WIN0H, display.win0_horizontal_dimensions)
WRITE(WIN1H, display.win1_horizontal_dimensions)
WRITE(WIN0V, display.win0_vertical_dimensions)
WRITE(WIN1V, display.win1_vertical_dimensions)
WRITE(WININ, display.inside_win_0_1)
WRITE(WINOUT, display.outside_win)
WRITE(MOSAIC, display.mosaic_size)
WRITE(BLDCNT, display.color_special_effects_selection)
WRITE(BLDALPHA, display.alpha_blending_coefficients)
WRITE(BLDY, display.brightness_coefficient)
// sound
WRITE(SOUND1CNT_L, sound.ch1_sweep)
WRITE(SOUND1CNT_H, sound.ch1_duty_length_env)
WRITE(SOUND1CNT_X, sound.ch1_freq_control)
WRITE(SOUND2CNT_L, sound.ch2_duty_length_env)
WRITE(SOUND2CNT_H, sound.ch2_freq_control)
WRITE(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
WRITE(SOUND3CNT_H, sound.ch3_length_volume)
WRITE(SOUND3CNT_X, sound.ch3_freq_control)
WRITE(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
WRITE(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
WRITE(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
WRITE(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
WRITE(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
WRITE(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
WRITE(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
WRITE(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
WRITE(SOUND4CNT_L, sound.ch4_length_env);
WRITE(SOUND4CNT_H, sound.ch4_freq_control);
WRITE(SOUNDCNT_L, sound.ctrl_stereo_volume);
WRITE(SOUNDCNT_H, sound.ctrl_mixing);
WRITE(SOUNDCNT_X, sound.ctrl_sound_on_off);
WRITE(SOUNDBIAS, sound.pwm_control);
WRITE(FIFO_A_L, sound.fifo_a[0]);
WRITE(FIFO_A_H, sound.fifo_a[1]);
WRITE(FIFO_B_L, sound.fifo_b[0]);
WRITE(FIFO_B_H, sound.fifo_b[1]);
// dma
case DMA0CNT_H:
dma.channels[0].control.write(halfword);
break;
case DMA1CNT_H:
dma.channels[1].control.write(halfword);
break;
case DMA2CNT_H:
dma.channels[2].control.write(halfword);
break;
case DMA3CNT_H:
dma.channels[3].control.write(halfword);
break;
WRITE(DMA0SAD, dma.channels[0].source[0]);
WRITE(DMA0SAD + 2, dma.channels[0].source[1]);
WRITE(DMA0DAD, dma.channels[0].destination[0]);
WRITE(DMA0DAD + 2, dma.channels[0].destination[1]);
WRITE(DMA0CNT_L, dma.channels[0].word_count);
WRITE(DMA1SAD, dma.channels[1].source[0]);
WRITE(DMA1SAD + 2, dma.channels[1].source[1]);
WRITE(DMA1DAD, dma.channels[1].destination[0]);
WRITE(DMA1DAD + 2, dma.channels[1].destination[1]);
WRITE(DMA1CNT_L, dma.channels[1].word_count);
WRITE(DMA2SAD, dma.channels[2].source[0]);
WRITE(DMA2SAD + 2, dma.channels[2].source[1]);
WRITE(DMA2DAD, dma.channels[2].destination[0]);
WRITE(DMA2DAD + 2, dma.channels[2].destination[1]);
WRITE(DMA2CNT_L, dma.channels[2].word_count);
WRITE(DMA3SAD, dma.channels[3].source[0]);
WRITE(DMA3SAD + 2, dma.channels[3].source[1]);
WRITE(DMA3DAD, dma.channels[3].destination[0]);
WRITE(DMA3DAD + 2, dma.channels[3].destination[1]);
WRITE(DMA3CNT_L, dma.channels[3].word_count);
// system
WRITE_2(POSTFLG, system.post_boot_flag, halfword & 1)
WRITE_2(IME, system.interrupt_master_enabler, halfword & 1)
WRITE(IE, system.interrupt_enable);
WRITE(IF, system.interrupt_request_flags);
WRITE(WAITCNT, system.waitstate_control);
WRITE_2(HALTCNT, system.low_power_mode, get_bit(halfword, 7));
#undef WRITE
#undef WRITE_2
default:
glogger.warn("Unused IO address written at 0x{:08X}", address);
}
return;
}
}

3
src/io/meson.build
View File

@@ -1,3 +0,0 @@
lib_sources += files(
'io.cc'
)

234
src/memory.cc Normal file
View File

@@ -0,0 +1,234 @@
#include "memory.hh"
#include "header.hh"
#include "util/bits.hh"
#include "util/log.hh"
#include "util/utils.hh"
#include <bitset>
#include <stdexcept>
using namespace logger;
Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
std::vector<uint8_t>&& rom)
: bios(std::move(bios))
, board_wram({ 0 })
, chip_wram({ 0 })
, palette_ram({ 0 })
, vram({ 0 })
, oam_obj_attr({ 0 })
, rom(std::move(rom)) {
std::string bios_hash = crypto::sha256(this->bios);
static constexpr std::string_view expected_hash =
"fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
if (bios_hash != expected_hash) {
log_warn("BIOS hash failed to match, run at your own risk"
"\nExpected : {} "
"\nGot : {}",
expected_hash,
bios_hash);
}
parse_header();
log_info("Memory successfully initialised");
log_info("Cartridge Title: {}", header.title);
};
#define MATCHES(area) address >= area##_START&& address <= area##_END
uint8_t
Memory::read(size_t address) const {
if (MATCHES(BIOS)) {
return bios[address];
} else if (MATCHES(BOARD_WRAM)) {
return board_wram[address - BOARD_WRAM_START];
} else if (MATCHES(CHIP_WRAM)) {
return chip_wram[address - CHIP_WRAM_START];
} else if (MATCHES(PALETTE_RAM)) {
return palette_ram[address - PALETTE_RAM_START];
} else if (MATCHES(VRAM)) {
return vram[address - VRAM_START];
} else if (MATCHES(OAM_OBJ_ATTR)) {
return oam_obj_attr[address - OAM_OBJ_ATTR_START];
} else if (MATCHES(ROM_0)) {
return rom[address - ROM_0_START];
} else if (MATCHES(ROM_1)) {
return rom[address - ROM_1_START];
} else if (MATCHES(ROM_2)) {
return rom[address - ROM_2_START];
} else {
log_error("Invalid memory region accessed");
return 0xFF;
}
}
void
Memory::write(size_t address, uint8_t byte) {
if (MATCHES(BIOS)) {
bios[address] = byte;
} else if (MATCHES(BOARD_WRAM)) {
board_wram[address - BOARD_WRAM_START] = byte;
} else if (MATCHES(CHIP_WRAM)) {
chip_wram[address - CHIP_WRAM_START] = byte;
} else if (MATCHES(PALETTE_RAM)) {
palette_ram[address - PALETTE_RAM_START] = byte;
} else if (MATCHES(VRAM)) {
vram[address - VRAM_START] = byte;
} else if (MATCHES(OAM_OBJ_ATTR)) {
oam_obj_attr[address - OAM_OBJ_ATTR_START] = byte;
} else if (MATCHES(ROM_0)) {
rom[address - ROM_0_START] = byte;
} else if (MATCHES(ROM_1)) {
rom[address - ROM_1_START] = byte;
} else if (MATCHES(ROM_2)) {
rom[address - ROM_2_START] = byte;
} else {
log_error("Invalid memory region accessed");
}
}
#undef MATCHES
uint16_t
Memory::read_halfword(size_t address) const {
if (address & 0b01)
log_warn("Reading a non aligned halfword address");
return read(address) | read(address + 1) << 8;
}
void
Memory::write_halfword(size_t address, uint16_t halfword) {
if (address & 0b01)
log_warn("Writing to a non aligned halfword address");
write(address, halfword & 0xFF);
write(address + 1, halfword >> 8 & 0xFF);
}
uint32_t
Memory::read_word(size_t address) const {
if (address & 0b11)
log_warn("Reading a non aligned word address");
return read(address) | read(address + 1) << 8 | read(address + 2) << 16 |
read(address + 3) << 24;
}
void
Memory::write_word(size_t address, uint32_t word) {
if (address & 0b11)
log_warn("Writing to a non aligned word address");
write(address, word & 0xFF);
write(address + 1, word >> 8 & 0xFF);
write(address + 2, word >> 16 & 0xFF);
write(address + 3, word >> 24 & 0xFF);
}
void
Memory::parse_header() {
if (rom.size() < 192) {
throw std::out_of_range(
"ROM is not large enough to even have a header");
}
// entrypoint
header.entrypoint =
rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
// nintendo logo
if (rom[0x9C] != 0x21)
log_info("HEADER: BIOS debugger bits not set to 0");
// game info
header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
switch (rom[0xAC]) {
case 'A':
header.unique_code = Header::UniqueCode::Old;
break;
case 'B':
header.unique_code = Header::UniqueCode::New;
break;
case 'C':
header.unique_code = Header::UniqueCode::Newer;
break;
case 'F':
header.unique_code = Header::UniqueCode::Famicom;
break;
case 'K':
header.unique_code = Header::UniqueCode::YoshiKoro;
break;
case 'P':
header.unique_code = Header::UniqueCode::Ereader;
break;
case 'R':
header.unique_code = Header::UniqueCode::Warioware;
break;
case 'U':
header.unique_code = Header::UniqueCode::Boktai;
break;
case 'V':
header.unique_code = Header::UniqueCode::DrillDozer;
break;
default:
log_error("HEADER: invalid unique code: {}", rom[0xAC]);
}
header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
switch (rom[0xAF]) {
case 'J':
header.i18n = Header::I18n::Japan;
break;
case 'P':
header.i18n = Header::I18n::Europe;
break;
case 'F':
header.i18n = Header::I18n::French;
break;
case 'S':
header.i18n = Header::I18n::Spanish;
break;
case 'E':
header.i18n = Header::I18n::Usa;
break;
case 'D':
header.i18n = Header::I18n::German;
break;
case 'I':
header.i18n = Header::I18n::Italian;
break;
default:
log_error("HEADER: invalid destination/language: {}", rom[0xAF]);
}
if (rom[0xB2] != 0x96)
log_error("HEADER: invalid fixed byte at 0xB2");
for (size_t i = 0xB5; i < 0xBC; i++) {
if (rom[i] != 0x00)
log_error("HEADER: invalid fixed bytes at 0xB5");
}
header.version = rom[0xBC];
// checksum
{
size_t i = 0xA0, chk = 0;
while (i <= 0xBC)
chk -= rom[i++];
chk -= 0x19;
chk &= 0xFF;
if (chk != rom[0xBD])
log_error("HEADER: checksum does not match");
}
// multiboot not required right now
}

14
src/meson.build
View File

@@ -1,21 +1,17 @@
lib_sources = files(
'bus.cc',
'memory.cc',
'bus.cc'
)
if get_option('gdb_debug')
lib_sources += files('gdb_rsp.cc')
endif
subdir('util')
subdir('cpu')
subdir('io')
fmt = dependency('fmt', version : '>=10.1.0')
lib = library(
meson.project_name(),
lib_sources,
dependencies: [fmt],
include_directories: inc,
install: true,
cpp_args: lib_cpp_args
install: true
)
import('pkgconfig').generate(lib)

10
src/util/bits.hh
View File

@@ -14,19 +14,19 @@ get_bit(Int num, size_t n) {
template<std::integral Int>
inline void
set_bit(Int& num, size_t n) {
num |= (static_cast<Int>(1) << n);
num |= (1 << n);
}
template<std::integral Int>
inline void
rst_bit(Int& num, size_t n) {
num &= ~(static_cast<Int>(1) << n);
num &= ~(1 << n);
}
template<std::integral Int>
inline void
chg_bit(Int& num, size_t n, bool x) {
num = (num & ~(static_cast<Int>(1) << n)) | (static_cast<Int>(x) << n);
num = (num & ~(1 << n)) | (x << n);
}
/// read range of bits from start to end inclusive
@@ -35,6 +35,6 @@ inline Int
bit_range(Int num, size_t start, size_t end) {
// NOTE: we do not require -1 if it is a signed integral
Int left =
std::numeric_limits<Int>::digits - (!std::is_signed<Int>::value) - end;
return static_cast<Int>(num << left) >> (left + start);
std::numeric_limits<Int>::digits - (std::is_unsigned<Int>::value) - end;
return num << left >> (left + start);
}

8
src/util/log.cc
View File

@@ -1,8 +0,0 @@
#include "log.hh"
logging::Logger glogger = logging::Logger();
void
matar::set_log_level(LogLevel level) {
glogger.set_level(level);
}

131
src/util/log.hh
View File

@@ -1,91 +1,58 @@
#pragma once
#include "util/loglevel.hh"
#include <print>
#include <fmt/ostream.h>
#include <iostream>
namespace logging {
using fmt::print;
using std::clog;
namespace logger {
namespace ansi {
static constexpr auto RED = "\033[31m";
static constexpr auto YELLOW = "\033[33m";
static constexpr auto MAGENTA = "\033[35m";
static constexpr auto WHITE = "\033[37m";
static constexpr auto BOLD = "\033[1m";
static constexpr auto RESET = "\033[0m";
static constexpr std::string_view RED = "\033[31m";
static constexpr std::string_view YELLOW = "\033[33m";
static constexpr std::string_view MAGENTA = "\033[35m";
static constexpr std::string_view WHITE = "\033[37m";
static constexpr std::string_view BOLD = "\033[1m";
static constexpr std::string_view RESET = "\033[0m";
}
using std::print;
class Logger {
using LogLevel = matar::LogLevel;
public:
Logger(LogLevel level = LogLevel::Debug, FILE* stream = stdout)
: level(0)
, stream(stream) {
set_level(level);
}
template<typename... Args>
void log(const std::format_string<Args...>& fmt, Args&&... args) {
std::println(stream, fmt, std::forward<Args>(args)...);
}
template<typename... Args>
void debug(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Debug)) {
print(stream, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
log(fmt, std::forward<Args>(args)...);
print(stream, ansi::RESET);
}
}
template<typename... Args>
void info(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Info)) {
print(stream, "{}[INFO] ", ansi::WHITE);
log(fmt, std::forward<Args>(args)...);
print(stream, ansi::RESET);
}
}
template<typename... Args>
void info_bold(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Info)) {
print(stream, "{}{}[INFO] ", ansi::WHITE, ansi::BOLD);
log(fmt, std::forward<Args>(args)...);
print(stream, ansi::RESET);
}
}
template<typename... Args>
void warn(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Warn)) {
print(stream, "{}[WARN] ", ansi::YELLOW);
log(fmt, std::forward<Args>(args)...);
print(stream, ansi::RESET);
}
}
template<typename... Args>
void error(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Error)) {
print(stream, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
log(fmt, std::forward<Args>(args)...);
print(stream, ansi::RESET);
}
}
void set_level(LogLevel level) {
this->level = (static_cast<uint8_t>(level) << 1) - 1;
}
void set_stream(FILE* stream) { this->stream = stream; }
private:
uint8_t level;
FILE* stream;
};
template<typename... Args>
inline void
log_raw(const fmt::format_string<Args...>& fmt, Args&&... args) {
fmt::println(clog, fmt, std::forward<Args>(args)...);
}
extern logging::Logger glogger;
template<typename... Args>
inline void
log_debug(const fmt::format_string<Args...>& fmt, Args&&... args) {
print(clog, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
log_raw(fmt, std::forward<Args>(args)...);
print(clog, ansi::RESET);
}
#define dbg(x) glogger.debug("{} = {}", #x, x);
template<typename... Args>
inline void
log_info(const fmt::format_string<Args...>& fmt, Args&&... args) {
print(clog, "{}[INFO] ", ansi::WHITE);
log_raw(fmt, std::forward<Args>(args)...);
print(clog, ansi::RESET);
}
template<typename... Args>
inline void
log_warn(const fmt::format_string<Args...>& fmt, Args&&... args) {
print(clog, "{}[WARN] ", ansi::YELLOW);
log_raw(fmt, std::forward<Args>(args)...);
print(clog, ansi::RESET);
}
template<typename... Args>
inline void
log_error(const fmt::format_string<Args...>& fmt, Args&&... args) {
print(clog, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
log_raw(fmt, std::forward<Args>(args)...);
print(clog, ansi::RESET);
}
}
#define debug(value) logger::log_debug("{} = {}", #value, value)

8
src/util/meson.build
View File

@@ -1,8 +0,0 @@
lib_sources += files(
'log.cc',
'tcp_server.cc'
)
if get_option('gdb_debug')
lib_sources += files('tcp_server.cc')
endif

89
src/util/tcp_server.cc
View File

@@ -1,89 +0,0 @@
#include "tcp_server.hh"
#include <netinet/tcp.h>
#include <cstring>
#include <format>
#include <sys/ioctl.h>
#include <unistd.h>
namespace net {
TcpServer::TcpServer()
: server_fd(0)
, client_fd(0) {}
TcpServer::~TcpServer() {
close(server_fd);
close(client_fd);
}
bool
TcpServer::client_waiting() {
int count = 0;
ioctl(client_fd, FIONREAD, &count);
return static_cast<bool>(count);
}
void
TcpServer::run() {
socklen_t cli_addr_size = sizeof(client_addr);
client_fd = ::accept(
server_fd, reinterpret_cast<sockaddr*>(&client_addr), &cli_addr_size);
if (client_fd == -1)
throw std::runtime_error("accept failed");
}
void
TcpServer::start(uint port) {
int opts = 0;
server_fd = socket(PF_INET, SOCK_STREAM, 0);
if (server_fd == -1) {
throw std::runtime_error("creating socket failed");
}
int option = 1;
opts +=
setsockopt(server_fd, SOL_SOCKET, SO_REUSEADDR, &option, sizeof(option));
opts +=
setsockopt(server_fd, IPPROTO_TCP, TCP_NODELAY, &option, sizeof(option));
if (opts != 0) {
throw std::runtime_error("failed to set socket opts");
}
std::memset(&server_addr, 0, sizeof(server_addr));
server_addr.sin_family = PF_INET;
server_addr.sin_addr.s_addr = htonl(INADDR_ANY);
server_addr.sin_port = htons(port);
if (::bind(server_fd,
reinterpret_cast<sockaddr*>(&server_addr),
sizeof(server_addr)) == -1) {
throw std::runtime_error("binding socket failed");
}
if (::listen(server_fd, 1) == -1) {
throw std::runtime_error("listening failed");
}
}
void
TcpServer::send(std::string msg) {
if (::send(client_fd, msg.data(), msg.length(), 0) == -1) {
throw std::runtime_error(
std::format("failed to send message: {}\n", strerror(errno)));
}
}
std::string
TcpServer::receive(uint length) {
ssize_t num_bytes = recv(client_fd, msg, length, 0);
msg[num_bytes] = '\0';
if (num_bytes < 0) {
throw std::runtime_error(
std::format("failed to receive messages: {}\n", strerror(errno)));
}
return std::string(msg);
}
}

28
src/util/tcp_server.hh
View File

@@ -1,28 +0,0 @@
#pragma once
#include <netinet/in.h>
#include <string>
namespace net {
class TcpServer {
public:
TcpServer();
~TcpServer();
void run();
void start(uint port);
void send(std::string msg);
std::string receive(uint length);
std::string receive_all() { return receive(MAX_PACKET_SIZE); };
bool client_waiting();
private:
static constexpr uint MAX_PACKET_SIZE = 4096;
char msg[MAX_PACKET_SIZE];
int server_fd;
int client_fd;
sockaddr_in server_addr;
sockaddr_in client_addr;
};
}

4
src/util/crypto.hh → src/util/utils.hh
View File

@@ -2,7 +2,7 @@
#include <array>
#include <bit>
#include <format>
#include <fmt/core.h>
#include <string>
// Why I wrote this myself? I do not know
@@ -110,7 +110,7 @@ sha256(std::array<uint8_t, N>& data) {
for (j = 0; j < 8; j++)
for (i = 0; i < 4; i++)
std::format_to(std::back_inserter(string),
fmt::format_to(std::back_inserter(string),
"{:02x}",
((h[j] >> (24 - i * 8)) & 0xFF));

128
tests/bus.cc
View File

@@ -1,128 +0,0 @@
#include "bus.hh"
#include <catch2/catch_test_macros.hpp>
#define TAG "[bus]"
using namespace matar;
class BusFixture {
public:
BusFixture()
: bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
std::vector<uint8_t>(Header::HEADER_SIZE))) {}
protected:
std::shared_ptr<Bus> bus;
};
TEST_CASE("bios", TAG) {
std::array<uint8_t, Bus::BIOS_SIZE> bios = { 0 };
// populate bios
bios[0] = 0xAC;
bios[0x3FFF] = 0x48;
bios[0x2A56] = 0x10;
auto bus =
Bus::init(std::move(bios), std::vector<uint8_t>(Header::HEADER_SIZE));
CHECK(bus->read_byte(0) == 0xAC);
CHECK(bus->read_byte(0x3FFF) == 0x48);
CHECK(bus->read_byte(0x2A56) == 0x10);
}
TEST_CASE_METHOD(BusFixture, "board wram", TAG) {
bus->write_byte(0x2000000, 0xAC);
CHECK(bus->read_byte(0x2000000) == 0xAC);
bus->write_byte(0x203FFFF, 0x48);
CHECK(bus->read_byte(0x203FFFF) == 0x48);
bus->write_byte(0x2022A56, 0x10);
CHECK(bus->read_byte(0x2022A56) == 0x10);
}
TEST_CASE_METHOD(BusFixture, "chip wram", TAG) {
bus->write_byte(0x3000000, 0xAC);
CHECK(bus->read_byte(0x3000000) == 0xAC);
bus->write_byte(0x3007FFF, 0x48);
CHECK(bus->read_byte(0x3007FFF) == 0x48);
bus->write_byte(0x3002A56, 0x10);
CHECK(bus->read_byte(0x3002A56) == 0x10);
}
TEST_CASE_METHOD(BusFixture, "palette ram", TAG) {
bus->write_byte(0x5000000, 0xAC);
CHECK(bus->read_byte(0x5000000) == 0xAC);
bus->write_byte(0x50003FF, 0x48);
CHECK(bus->read_byte(0x50003FF) == 0x48);
bus->write_byte(0x5000156, 0x10);
CHECK(bus->read_byte(0x5000156) == 0x10);
}
TEST_CASE_METHOD(BusFixture, "video ram", TAG) {
bus->write_byte(0x6000000, 0xAC);
CHECK(bus->read_byte(0x6000000) == 0xAC);
bus->write_byte(0x6017FFF, 0x48);
CHECK(bus->read_byte(0x6017FFF) == 0x48);
bus->write_byte(0x6012A56, 0x10);
CHECK(bus->read_byte(0x6012A56) == 0x10);
}
TEST_CASE_METHOD(BusFixture, "oam obj ram", TAG) {
bus->write_byte(0x7000000, 0xAC);
CHECK(bus->read_byte(0x7000000) == 0xAC);
bus->write_byte(0x70003FF, 0x48);
CHECK(bus->read_byte(0x70003FF) == 0x48);
bus->write_byte(0x7000156, 0x10);
CHECK(bus->read_byte(0x7000156) == 0x10);
}
TEST_CASE("rom", TAG) {
std::vector<uint8_t> rom(32 * 1024 * 1024, 0);
// populate rom
rom[0] = 0xAC;
rom[0x1FFFFFF] = 0x48;
rom[0x0EF0256] = 0x10;
// 32 megabyte ROM
auto bus = Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(), std::move(rom));
SECTION("ROM1") {
CHECK(bus->read_byte(0x8000000) == 0xAC);
CHECK(bus->read_byte(0x9FFFFFF) == 0x48);
CHECK(bus->read_byte(0x8EF0256) == 0x10);
}
SECTION("ROM2") {
CHECK(bus->read_byte(0xA000000) == 0xAC);
CHECK(bus->read_byte(0xBFFFFFF) == 0x48);
CHECK(bus->read_byte(0xAEF0256) == 0x10);
}
SECTION("ROM3") {
CHECK(bus->read_byte(0xC000000) == 0xAC);
CHECK(bus->read_byte(0xDFFFFFF) == 0x48);
CHECK(bus->read_byte(0xCEF0256) == 0x10);
}
}
TEST_CASE_METHOD(BusFixture, "internal cycle", TAG) {
uint32_t cycles = bus->get_cycles();
bus->internal_cycle();
bus->internal_cycle();
CHECK(bus->get_cycles() == cycles + 2);
}
#undef TAG

1305
tests/cpu/arm/exec.cc
View File

File diff suppressed because it is too large Load Diff

365
tests/cpu/arm/instruction.cc
View File

@@ -1,9 +1,9 @@
#include "cpu/arm/instruction.hh"
#include "cpu/utility.hh"
#include <catch2/catch_test_macros.hpp>
#define TAG "[arm][disassembly]"
#define TAG "disassembler"
using namespace matar;
using namespace arm;
TEST_CASE("Branch and Exchange", TAG) {
@@ -12,13 +12,11 @@ TEST_CASE("Branch and Exchange", TAG) {
BranchAndExchange* bx = nullptr;
REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
CHECK(instruction.condition == Condition::GT);
REQUIRE(instruction.condition == Condition::GT);
CHECK(bx->rn == 10);
REQUIRE(bx->rn == 10);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "BXGT R10");
#endif
REQUIRE(instruction.disassemble() == "BXGT R10");
}
TEST_CASE("Branch", TAG) {
@@ -27,21 +25,18 @@ TEST_CASE("Branch", TAG) {
Branch* b = nullptr;
REQUIRE((b = std::get_if<Branch>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
// last 24 bits = 8748995
// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
CHECK(b->offset == static_cast<int32_t>(0xfe15ff0c));
CHECK(b->link == true);
// Also +8 since PC is two instructions ahead
REQUIRE(b->offset == 0xFE15FF14);
REQUIRE(b->link == true);
#ifdef DISASSEMBLER
// take prefetch into account
// offset + 8 = 0xfe15ff0c + 8 = -0x1ea00e4 + 8
CHECK(instruction.disassemble() == "BL -0x1ea00ec");
REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
b->link = false;
CHECK(instruction.disassemble() == "B -0x1ea00ec");
#endif
REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
}
TEST_CASE("Multiply", TAG) {
@@ -50,22 +45,20 @@ TEST_CASE("Multiply", TAG) {
Multiply* mul = nullptr;
REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
CHECK(instruction.condition == Condition::EQ);
REQUIRE(instruction.condition == Condition::EQ);
CHECK(mul->rm == 0);
CHECK(mul->rs == 15);
CHECK(mul->rn == 14);
CHECK(mul->rd == 10);
CHECK(mul->acc == true);
CHECK(mul->set == true);
REQUIRE(mul->rm == 0);
REQUIRE(mul->rs == 15);
REQUIRE(mul->rn == 14);
REQUIRE(mul->rd == 10);
REQUIRE(mul->acc == true);
REQUIRE(mul->set == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
mul->acc = false;
mul->set = false;
CHECK(instruction.disassemble() == "MULEQ R10,R0,R15");
#endif
REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
}
TEST_CASE("Multiply Long", TAG) {
@@ -74,26 +67,24 @@ TEST_CASE("Multiply Long", TAG) {
MultiplyLong* mull = nullptr;
REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
CHECK(instruction.condition == Condition::NE);
REQUIRE(instruction.condition == Condition::NE);
CHECK(mull->rm == 2);
CHECK(mull->rs == 6);
CHECK(mull->rdlo == 7);
CHECK(mull->rdhi == 14);
CHECK(mull->acc == false);
CHECK(mull->set == true);
CHECK(mull->uns == true);
REQUIRE(mull->rm == 2);
REQUIRE(mull->rs == 6);
REQUIRE(mull->rdlo == 7);
REQUIRE(mull->rdhi == 14);
REQUIRE(mull->acc == false);
REQUIRE(mull->set == true);
REQUIRE(mull->uns == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
REQUIRE(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
mull->acc = true;
CHECK(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
REQUIRE(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
mull->uns = false;
mull->set = false;
CHECK(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
#endif
REQUIRE(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
}
TEST_CASE("Undefined", TAG) {
@@ -102,11 +93,8 @@ TEST_CASE("Undefined", TAG) {
uint32_t raw = 0b11100111101000101010111100010110;
Instruction instruction(raw);
CHECK(instruction.condition == Condition::AL);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "UND");
#endif
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(instruction.disassemble() == "UND");
}
TEST_CASE("Single Data Swap", TAG) {
@@ -115,19 +103,17 @@ TEST_CASE("Single Data Swap", TAG) {
SingleDataSwap* swp = nullptr;
REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
CHECK(instruction.condition == Condition::GE);
REQUIRE(instruction.condition == Condition::GE);
CHECK(swp->rm == 6);
CHECK(swp->rd == 5);
CHECK(swp->rn == 9);
CHECK(swp->byte == false);
REQUIRE(swp->rm == 6);
REQUIRE(swp->rd == 5);
REQUIRE(swp->rn == 9);
REQUIRE(swp->byte == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "SWPGE R5,R6,[R9]");
REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
swp->byte = true;
CHECK(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
#endif
REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
}
TEST_CASE("Single Data Transfer", TAG) {
@@ -137,38 +123,36 @@ TEST_CASE("Single Data Transfer", TAG) {
Shift* shift = nullptr;
REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
CHECK(shift->rm == 6);
CHECK(shift->data.immediate == true);
CHECK(shift->data.type == ShiftType::LSL);
CHECK(shift->data.operand == 30);
CHECK(ldr->rd == 10);
CHECK(ldr->rn == 2);
CHECK(ldr->load == false);
CHECK(ldr->write == true);
CHECK(ldr->byte == false);
CHECK(ldr->up == true);
CHECK(ldr->pre == true);
REQUIRE(shift->rm == 6);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::LSL);
REQUIRE(shift->data.operand == 30);
REQUIRE(ldr->rd == 10);
REQUIRE(ldr->rn == 2);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->byte == false);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
#ifdef DISASSEMBLER
ldr->load = true;
ldr->byte = true;
ldr->write = false;
shift->data.type = ShiftType::ROR;
CHECK(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
ldr->up = false;
ldr->pre = false;
CHECK(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
ldr->offset = static_cast<uint16_t>(9023);
CHECK(instruction.disassemble() == "LDRB R10,[R2],-#9023");
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
ldr->pre = true;
CHECK(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
#endif
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
}
TEST_CASE("Halfword Transfer", TAG) {
@@ -177,40 +161,38 @@ TEST_CASE("Halfword Transfer", TAG) {
HalfwordTransfer* ldr = nullptr;
REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::CC);
REQUIRE(instruction.condition == Condition::CC);
// offset is not immediate
CHECK(ldr->imm == 0);
REQUIRE(ldr->imm == 0);
// hence this offset is a register number (rm)
CHECK(ldr->offset == 6);
CHECK(ldr->half == true);
CHECK(ldr->sign == false);
CHECK(ldr->rd == 2);
CHECK(ldr->rn == 15);
CHECK(ldr->load == false);
CHECK(ldr->write == true);
CHECK(ldr->up == true);
CHECK(ldr->pre == true);
REQUIRE(ldr->offset == 6);
REQUIRE(ldr->half == true);
REQUIRE(ldr->sign == false);
REQUIRE(ldr->rd == 2);
REQUIRE(ldr->rn == 15);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
ldr->pre = false;
ldr->load = true;
ldr->sign = true;
ldr->up = false;
CHECK(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
ldr->half = false;
CHECK(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
ldr->load = false;
// not a register anymore
ldr->imm = 1;
ldr->offset = 90;
CHECK(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
#endif
REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
}
TEST_CASE("Block Data Transfer", TAG) {
@@ -219,7 +201,7 @@ TEST_CASE("Block Data Transfer", TAG) {
BlockDataTransfer* ldm = nullptr;
REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::LS);
REQUIRE(instruction.condition == Condition::LS);
{
uint16_t regs = 0;
@@ -231,24 +213,23 @@ TEST_CASE("Block Data Transfer", TAG) {
regs |= 1 << 8;
regs |= 1 << 14;
CHECK(ldm->regs == regs);
REQUIRE(ldm->regs == regs);
}
CHECK(ldm->rn == 7);
CHECK(ldm->load == true);
CHECK(ldm->write == false);
CHECK(ldm->s == true);
CHECK(ldm->up == false);
CHECK(ldm->pre == true);
REQUIRE(ldm->rn == 7);
REQUIRE(ldm->load == true);
REQUIRE(ldm->write == false);
REQUIRE(ldm->s == true);
REQUIRE(ldm->up == false);
REQUIRE(ldm->pre == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
ldm->write = true;
ldm->s = false;
ldm->up = true;
CHECK(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
ldm->regs &= ~(1 << 6);
ldm->regs &= ~(1 << 3);
@@ -256,8 +237,7 @@ TEST_CASE("Block Data Transfer", TAG) {
ldm->load = false;
ldm->pre = false;
CHECK(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
#endif
REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
}
TEST_CASE("PSR Transfer", TAG) {
@@ -269,16 +249,14 @@ TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* mrs = nullptr;
REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::MI);
REQUIRE(instruction.condition == Condition::MI);
CHECK(mrs->type == PsrTransfer::Type::Mrs);
REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
// Operand is a register in the case of MRS (PSR -> Register)
CHECK(mrs->operand == 10);
CHECK(mrs->spsr == true);
REQUIRE(mrs->operand == 10);
REQUIRE(mrs->spsr == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "MRSMI R10,SPSR_all");
#endif
REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
}
SECTION("MSR") {
@@ -287,16 +265,14 @@ TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* msr = nullptr;
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(msr->type == PsrTransfer::Type::Msr);
REQUIRE(msr->type == PsrTransfer::Type::Msr);
// Operand is a register in the case of MSR (Register -> PSR)
CHECK(msr->operand == 8);
CHECK(msr->spsr == false);
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "MSR CPSR_all,R8");
#endif
REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
}
SECTION("MSR_flg with register operand") {
@@ -304,16 +280,14 @@ TEST_CASE("PSR Transfer", TAG) {
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::VS);
REQUIRE(instruction.condition == Condition::VS);
CHECK(msr->type == PsrTransfer::Type::Msr_flg);
CHECK(msr->imm == 0);
CHECK(msr->operand == 8);
CHECK(msr->spsr == false);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 0);
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "MSRVS CPSR_flg,R8");
#endif
REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
}
SECTION("MSR_flg with immediate operand") {
@@ -321,107 +295,101 @@ TEST_CASE("PSR Transfer", TAG) {
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(msr->type == PsrTransfer::Type::Msr_flg);
CHECK(msr->imm == 1);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 1);
// 104 (32 bits) rotated by 2 * 7
CHECK(msr->operand == 27262976);
CHECK(msr->spsr == true);
REQUIRE(msr->operand == 27262976);
REQUIRE(msr->spsr == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "MSR SPSR_flg,#27262976");
#endif
REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
}
}
TEST_CASE("Data Processing", TAG) {
using OpCode = DataProcessing::OpCode;
uint32_t raw = 0b11100000000111100111101101100001;
Instruction instruction(raw);
DataProcessing* alu = nullptr;
Shift* shift = nullptr;
REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
// operand 2 is a shifted register
REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
CHECK(shift->rm == 1);
CHECK(shift->data.immediate == true);
CHECK(shift->data.type == ShiftType::ROR);
CHECK(shift->data.operand == 22);
REQUIRE(shift->rm == 1);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::ROR);
REQUIRE(shift->data.operand == 22);
CHECK(alu->rd == 7);
CHECK(alu->rn == 14);
CHECK(alu->set == true);
CHECK(alu->opcode == OpCode::AND);
REQUIRE(alu->rd == 7);
REQUIRE(alu->rn == 14);
REQUIRE(alu->set == true);
REQUIRE(alu->opcode == OpCode::AND);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
shift->data.immediate = false;
shift->data.operand = 2;
alu->set = false;
CHECK(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
alu->operand = static_cast<uint32_t>(3300012);
CHECK(instruction.disassemble() == "AND R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
SECTION("set-only operations") {
alu->set = true;
alu->opcode = OpCode::TST;
CHECK(instruction.disassemble() == "TST R14,#3300012");
REQUIRE(instruction.disassemble() == "TST R14,#3300012");
alu->opcode = OpCode::TEQ;
CHECK(instruction.disassemble() == "TEQ R14,#3300012");
REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
alu->opcode = OpCode::CMP;
CHECK(instruction.disassemble() == "CMP R14,#3300012");
REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
alu->opcode = OpCode::CMN;
CHECK(instruction.disassemble() == "CMN R14,#3300012");
REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
}
SECTION("destination operations") {
alu->opcode = OpCode::EOR;
CHECK(instruction.disassemble() == "EOR R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
alu->opcode = OpCode::SUB;
CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::RSB;
CHECK(instruction.disassemble() == "RSB R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
alu->opcode = OpCode::SUB;
CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::ADC;
CHECK(instruction.disassemble() == "ADC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
alu->opcode = OpCode::SBC;
CHECK(instruction.disassemble() == "SBC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
alu->opcode = OpCode::RSC;
CHECK(instruction.disassemble() == "RSC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
alu->opcode = OpCode::ORR;
CHECK(instruction.disassemble() == "ORR R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
alu->opcode = OpCode::MOV;
CHECK(instruction.disassemble() == "MOV R7,#3300012");
REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
alu->opcode = OpCode::BIC;
CHECK(instruction.disassemble() == "BIC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
alu->opcode = OpCode::MVN;
CHECK(instruction.disassemble() == "MVN R7,#3300012");
REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
}
#endif
}
TEST_CASE("Coprocessor Data Transfer", TAG) {
@@ -430,28 +398,26 @@ TEST_CASE("Coprocessor Data Transfer", TAG) {
CoprocessorDataTransfer* ldc = nullptr;
REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::GE);
REQUIRE(instruction.condition == Condition::GE);
CHECK(ldc->offset == 70);
CHECK(ldc->cpn == 1);
CHECK(ldc->crd == 15);
CHECK(ldc->rn == 5);
CHECK(ldc->load == false);
CHECK(ldc->write == true);
CHECK(ldc->len == false);
CHECK(ldc->up == true);
CHECK(ldc->pre == true);
REQUIRE(ldc->offset == 70);
REQUIRE(ldc->cpn == 1);
REQUIRE(ldc->crd == 15);
REQUIRE(ldc->rn == 5);
REQUIRE(ldc->load == false);
REQUIRE(ldc->write == true);
REQUIRE(ldc->len == false);
REQUIRE(ldc->up == true);
REQUIRE(ldc->pre == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
ldc->load = true;
ldc->pre = false;
ldc->write = false;
ldc->len = true;
CHECK(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
#endif
REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
}
TEST_CASE("Coprocessor Operand Operation", TAG) {
@@ -460,18 +426,16 @@ TEST_CASE("Coprocessor Operand Operation", TAG) {
CoprocessorDataOperation* cdp = nullptr;
REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(cdp->crm == 6);
CHECK(cdp->cp == 2);
CHECK(cdp->cpn == 1);
CHECK(cdp->crd == 15);
CHECK(cdp->crn == 5);
CHECK(cdp->cp_opc == 10);
REQUIRE(cdp->crm == 6);
REQUIRE(cdp->cp == 2);
REQUIRE(cdp->cpn == 1);
REQUIRE(cdp->crd == 15);
REQUIRE(cdp->crn == 5);
REQUIRE(cdp->cp_opc == 10);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
#endif
REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
}
TEST_CASE("Coprocessor Register Transfer", TAG) {
@@ -481,30 +445,25 @@ TEST_CASE("Coprocessor Register Transfer", TAG) {
REQUIRE(
(mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(mrc->crm == 6);
CHECK(mrc->cp == 2);
CHECK(mrc->cpn == 1);
CHECK(mrc->rd == 15);
CHECK(mrc->crn == 5);
CHECK(mrc->load == false);
CHECK(mrc->cp_opc == 5);
REQUIRE(mrc->crm == 6);
REQUIRE(mrc->cp == 2);
REQUIRE(mrc->cpn == 1);
REQUIRE(mrc->rd == 15);
REQUIRE(mrc->crn == 5);
REQUIRE(mrc->load == false);
REQUIRE(mrc->cp_opc == 5);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
#endif
REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
}
TEST_CASE("Software Interrupt", TAG) {
uint32_t raw = 0b00001111101010101010101010101010;
Instruction instruction(raw);
CHECK(instruction.condition == Condition::EQ);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "SWIEQ");
#endif
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(instruction.disassemble() == "SWIEQ");
}
#undef TAG

99
tests/cpu/cpu-fixture.cc
View File

@@ -1,99 +0,0 @@
#include "cpu-fixture.hh"
Psr
CpuFixture::psr(bool spsr) {
uint32_t pc = getr(15);
Psr psr(0);
Cpu tmp = cpu;
arm::Instruction instruction(
Condition::AL,
arm::PsrTransfer{ .operand = 0,
.spsr = spsr,
.type = arm::PsrTransfer::Type::Mrs,
.imm = false });
tmp.exec(instruction);
psr.set_all(getr_(0, tmp));
// reset pc
setr(15, pc);
return psr;
}
void
CpuFixture::set_psr(Psr psr, bool spsr) {
uint32_t pc = getr(15);
uint32_t old = getr(0);
setr(0, psr.raw());
arm::Instruction instruction(
Condition::AL,
arm::PsrTransfer{ .operand = 0,
.spsr = spsr,
.type = arm::PsrTransfer::Type::Msr,
.imm = false });
cpu.exec(instruction);
setr(0, old);
// reset PC
setr(15, pc);
}
// We need these workarounds to just use the public API and not private
// fields. Assuming that these work correctly is necessary. Besides, all that
// matters is that the public API is correct.
uint32_t
CpuFixture::getr_(uint8_t r, Cpu tmp) {
uint32_t addr = 0x02000000;
uint32_t word = bus->read_word(addr);
uint32_t ret = 0xFFFFFFFF;
uint8_t base = r ? 0 : 1;
// set R0/R1 = addr
arm::Instruction zero(
Condition::AL,
arm::DataProcessing{ .operand = addr,
.rd = base,
.rn = 0,
.set = false,
.opcode = arm::DataProcessing::OpCode::MOV });
// get register
arm::Instruction get(
Condition::AL,
arm::SingleDataTransfer{ .offset = static_cast<uint16_t>(0),
.rd = r,
.rn = base,
.load = false,
.write = false,
.byte = false,
.up = true,
.pre = true });
tmp.exec(zero);
tmp.exec(get);
ret = bus->read_word(addr);
bus->write_word(addr, word);
return ret - (r == 15 ? 4 : 0); // +4 for rd = 15 in str
}
void
CpuFixture::setr_(uint8_t r, uint32_t value, Cpu& cpu) {
// set register
arm::Instruction set(
Condition::AL,
arm::DataProcessing{
.operand = (r == 15 ? value - 8 : value), // account for pipeline flush
.rd = r,
.rn = 0,
.set = false,
.opcode = arm::DataProcessing::OpCode::MOV });
cpu.exec(set);
}

71
tests/cpu/cpu-fixture.hh
View File

@@ -1,71 +0,0 @@
#include "cpu/cpu.hh"
using namespace matar;
class CpuFixture {
public:
CpuFixture()
: bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
std::vector<uint8_t>(Header::HEADER_SIZE)))
, cpu(bus) {}
protected:
void exec(arm::InstructionData data, Condition condition = Condition::AL) {
// hack to account for one fetch cycle
bus->internal_cycle();
arm::Instruction instruction(condition, data);
cpu.exec(instruction);
}
void exec(thumb::InstructionData data) {
// hack to account for one fetch cycle
bus->internal_cycle();
thumb::Instruction instruction(data);
cpu.exec(instruction);
}
void reset(uint32_t value = 0) { setr(15, value + 8); }
uint32_t getr(uint8_t r) {
uint32_t pc = 0;
if (r != 15)
pc = getr_(15, cpu);
uint32_t ret = getr_(r, cpu);
if (r == 15)
pc = ret;
// undo PC advance
setr_(15, pc, cpu);
return ret;
}
void setr(uint8_t r, uint32_t value) {
uint32_t pc = getr_(15, cpu);
setr_(r, value, cpu);
// undo PC advance when r != 15
// when r is 15, setr_ takes account of pipeline flush
if (r != 15)
setr_(15, pc, cpu);
}
Psr psr(bool spsr = false);
void set_psr(Psr psr, bool spsr = false);
std::shared_ptr<Bus> bus;
Cpu cpu;
private:
// hack to get a register
uint32_t getr_(uint8_t r, Cpu tmp);
// hack to set a register
void setr_(uint8_t r, uint32_t value, Cpu& cpu);
};

0
tests/cpu/cpu.cc Normal file
View File

467
tests/cpu/instruction.cc Normal file
View File

@@ -0,0 +1,467 @@
#include "cpu/arm/instruction.hh"
#include "cpu/utility.hh"
#include <catch2/catch_test_macros.hpp>
[[maybe_unused]] static constexpr auto TAG = "disassembler";
using namespace arm;
TEST_CASE("Branch and Exchange", TAG) {
uint32_t raw = 0b11000001001011111111111100011010;
Instruction instruction(raw);
BranchAndExchange* bx = nullptr;
REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GT);
REQUIRE(bx->rn == 10);
REQUIRE(instruction.disassemble() == "BXGT R10");
}
TEST_CASE("Branch", TAG) {
uint32_t raw = 0b11101011100001010111111111000011;
Instruction instruction(raw);
Branch* b = nullptr;
REQUIRE((b = std::get_if<Branch>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
// last 24 bits = 8748995
// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
// Also +8 since PC is two instructions ahead
REQUIRE(b->offset == 0xFE15FF14);
REQUIRE(b->link == true);
REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
b->link = false;
REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
}
TEST_CASE("Multiply", TAG) {
uint32_t raw = 0b00000000001110101110111110010000;
Instruction instruction(raw);
Multiply* mul = nullptr;
REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(mul->rm == 0);
REQUIRE(mul->rs == 15);
REQUIRE(mul->rn == 14);
REQUIRE(mul->rd == 10);
REQUIRE(mul->acc == true);
REQUIRE(mul->set == true);
REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
mul->acc = false;
mul->set = false;
REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
}
TEST_CASE("Multiply Long", TAG) {
uint32_t raw = 0b00010000100111100111011010010010;
Instruction instruction(raw);
MultiplyLong* mull = nullptr;
REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
REQUIRE(instruction.condition == Condition::NE);
REQUIRE(mull->rm == 2);
REQUIRE(mull->rs == 6);
REQUIRE(mull->rdlo == 7);
REQUIRE(mull->rdhi == 14);
REQUIRE(mull->acc == false);
REQUIRE(mull->set == true);
REQUIRE(mull->uns == false);
REQUIRE(instruction.disassemble() == "SMULLNES R7,R14,R2,R6");
mull->acc = true;
REQUIRE(instruction.disassemble() == "SMLALNES R7,R14,R2,R6");
mull->uns = true;
mull->set = false;
REQUIRE(instruction.disassemble() == "UMLALNE R7,R14,R2,R6");
}
TEST_CASE("Undefined", TAG) {
// notice how this is the same as single data transfer except the shift
// is now a register based shift
uint32_t raw = 0b11100111101000101010111100010110;
Instruction instruction(raw);
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(instruction.disassemble() == "UND");
}
TEST_CASE("Single Data Swap", TAG) {
uint32_t raw = 0b10100001000010010101000010010110;
Instruction instruction(raw);
SingleDataSwap* swp = nullptr;
REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GE);
REQUIRE(swp->rm == 6);
REQUIRE(swp->rd == 5);
REQUIRE(swp->rn == 9);
REQUIRE(swp->byte == false);
REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
swp->byte = true;
REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
}
TEST_CASE("Single Data Transfer", TAG) {
uint32_t raw = 0b11100111101000101010111100000110;
Instruction instruction(raw);
SingleDataTransfer* ldr = nullptr;
Shift* shift = nullptr;
REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
REQUIRE(shift->rm == 6);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::LSL);
REQUIRE(shift->data.operand == 30);
REQUIRE(ldr->rd == 10);
REQUIRE(ldr->rn == 2);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->byte == false);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
ldr->load = true;
ldr->byte = true;
ldr->write = false;
shift->data.type = ShiftType::ROR;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
ldr->up = false;
ldr->pre = false;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
ldr->offset = static_cast<uint16_t>(9023);
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
ldr->pre = true;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
}
TEST_CASE("Halfword Transfer", TAG) {
uint32_t raw = 0b00110001101011110010000010110110;
Instruction instruction(raw);
HalfwordTransfer* ldr = nullptr;
REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::CC);
// offset is not immediate
REQUIRE(ldr->imm == 0);
// hence this offset is a register number (rm)
REQUIRE(ldr->offset == 6);
REQUIRE(ldr->half == true);
REQUIRE(ldr->sign == false);
REQUIRE(ldr->rd == 2);
REQUIRE(ldr->rn == 15);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
ldr->pre = false;
ldr->load = true;
ldr->sign = true;
ldr->up = false;
REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
ldr->half = false;
REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
ldr->load = false;
// not a register anymore
ldr->imm = 1;
ldr->offset = 90;
REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
}
TEST_CASE("Block Data Transfer", TAG) {
uint32_t raw = 0b10011001010101110100000101101101;
Instruction instruction(raw);
BlockDataTransfer* ldm = nullptr;
REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::LS);
{
uint16_t regs = 0;
regs |= 1 << 0;
regs |= 1 << 2;
regs |= 1 << 3;
regs |= 1 << 5;
regs |= 1 << 6;
regs |= 1 << 8;
regs |= 1 << 14;
REQUIRE(ldm->regs == regs);
}
REQUIRE(ldm->rn == 7);
REQUIRE(ldm->load == true);
REQUIRE(ldm->write == false);
REQUIRE(ldm->s == true);
REQUIRE(ldm->up == false);
REQUIRE(ldm->pre == true);
REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
ldm->write = true;
ldm->s = false;
ldm->up = true;
REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
ldm->regs &= ~(1 << 6);
ldm->regs &= ~(1 << 3);
ldm->regs &= ~(1 << 8);
ldm->load = false;
ldm->pre = false;
REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
}
TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* msr = nullptr;
SECTION("MRS") {
uint32_t raw = 0b01000001010011111010000000000000;
Instruction instruction(raw);
PsrTransfer* mrs = nullptr;
REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::MI);
REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
// Operand is a register in the case of MRS (PSR -> Register)
REQUIRE(mrs->operand == 10);
REQUIRE(mrs->spsr == true);
REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
}
SECTION("MSR") {
uint32_t raw = 0b11100001001010011111000000001000;
Instruction instruction(raw);
PsrTransfer* msr = nullptr;
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(msr->type == PsrTransfer::Type::Msr);
// Operand is a register in the case of MSR (Register -> PSR)
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
}
SECTION("MSR_flg with register operand") {
uint32_t raw = 0b01100001001010001111000000001000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::VS);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 0);
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
}
SECTION("MSR_flg with immediate operand") {
uint32_t raw = 0b11100011011010001111011101101000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 1);
// 104 (32 bits) rotated by 2 * 7
REQUIRE(msr->operand == 27262976);
REQUIRE(msr->spsr == true);
REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
}
}
TEST_CASE("Data Processing", TAG) {
uint32_t raw = 0b11100010000111100111101101100001;
Instruction instruction(raw);
DataProcessing* alu = nullptr;
Shift* shift = nullptr;
REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
// operand 2 is a shifted register
REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
REQUIRE(shift->rm == 1);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::ROR);
REQUIRE(shift->data.operand == 22);
REQUIRE(alu->rd == 7);
REQUIRE(alu->rn == 14);
REQUIRE(alu->set == true);
REQUIRE(alu->opcode == OpCode::AND);
REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
shift->data.immediate = false;
shift->data.operand = 2;
alu->set = false;
REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
alu->operand = static_cast<uint32_t>(3300012);
REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
SECTION("set-only operations") {
alu->set = true;
alu->opcode = OpCode::TST;
REQUIRE(instruction.disassemble() == "TST R14,#3300012");
alu->opcode = OpCode::TEQ;
REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
alu->opcode = OpCode::CMP;
REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
alu->opcode = OpCode::CMN;
REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
}
SECTION("destination operations") {
alu->opcode = OpCode::EOR;
REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
alu->opcode = OpCode::SUB;
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::RSB;
REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
alu->opcode = OpCode::SUB;
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::ADC;
REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
alu->opcode = OpCode::SBC;
REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
alu->opcode = OpCode::RSC;
REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
alu->opcode = OpCode::ORR;
REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
alu->opcode = OpCode::MOV;
REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
alu->opcode = OpCode::BIC;
REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
alu->opcode = OpCode::MVN;
REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
}
}
TEST_CASE("Coprocessor Data Transfer", TAG) {
uint32_t raw = 0b10101101101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataTransfer* ldc = nullptr;
REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GE);
REQUIRE(ldc->offset == 70);
REQUIRE(ldc->cpn == 1);
REQUIRE(ldc->crd == 15);
REQUIRE(ldc->rn == 5);
REQUIRE(ldc->load == false);
REQUIRE(ldc->write == true);
REQUIRE(ldc->len == false);
REQUIRE(ldc->up == true);
REQUIRE(ldc->pre == true);
REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
ldc->load = true;
ldc->pre = false;
ldc->write = false;
ldc->len = true;
REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
}
TEST_CASE("Coprocessor Operand Operation", TAG) {
uint32_t raw = 0b11101110101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataOperation* cdp = nullptr;
REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(cdp->crm == 6);
REQUIRE(cdp->cp == 2);
REQUIRE(cdp->cpn == 1);
REQUIRE(cdp->crd == 15);
REQUIRE(cdp->crn == 5);
REQUIRE(cdp->cp_opc == 10);
REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
}
TEST_CASE("Coprocessor Register Transfer", TAG) {
uint32_t raw = 0b11101110101001011111000101010110;
Instruction instruction(raw);
CoprocessorRegisterTransfer* mrc = nullptr;
REQUIRE(
(mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(mrc->crm == 6);
REQUIRE(mrc->cp == 2);
REQUIRE(mrc->cpn == 1);
REQUIRE(mrc->rd == 15);
REQUIRE(mrc->crn == 5);
REQUIRE(mrc->load == false);
REQUIRE(mrc->cp_opc == 5);
REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
}
TEST_CASE("Software Interrupt", TAG) {
uint32_t raw = 0b00001111101010101010101010101010;
Instruction instruction(raw);
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(instruction.disassemble() == "SWIEQ");
}

5
tests/cpu/meson.build
View File

@@ -1,6 +1 @@
tests_sources += files(
'cpu-fixture.cc'
)
subdir('arm')
subdir('thumb')

1139
tests/cpu/thumb/exec.cc
View File

File diff suppressed because it is too large Load Diff

467
tests/cpu/thumb/instruction.cc
View File

@@ -1,467 +0,0 @@
#include "cpu/thumb/instruction.hh"
#include <catch2/catch_test_macros.hpp>
#define TAG "[thumb][disassembly]"
using namespace matar;
using namespace thumb;
TEST_CASE("Move Shifted Register", TAG) {
uint16_t raw = 0b0001001101100011;
Instruction instruction(raw);
MoveShiftedRegister* lsl = nullptr;
REQUIRE((lsl = std::get_if<MoveShiftedRegister>(&instruction.data)));
CHECK(lsl->rd == 3);
CHECK(lsl->rs == 4);
CHECK(lsl->offset == 13);
CHECK(lsl->opcode == ShiftType::ASR);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ASR R3,R4,#13");
lsl->opcode = ShiftType::LSR;
CHECK(instruction.disassemble() == "LSR R3,R4,#13");
lsl->opcode = ShiftType::LSL;
CHECK(instruction.disassemble() == "LSL R3,R4,#13");
#endif
}
TEST_CASE("Add/Subtract", TAG) {
uint16_t raw = 0b0001111101001111;
Instruction instruction(raw);
AddSubtract* add = nullptr;
REQUIRE((add = std::get_if<AddSubtract>(&instruction.data)));
CHECK(add->rd == 7);
CHECK(add->rs == 1);
CHECK(add->offset == 5);
CHECK(add->opcode == AddSubtract::OpCode::SUB);
CHECK(add->imm == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "SUB R7,R1,#5");
add->imm = false;
CHECK(instruction.disassemble() == "SUB R7,R1,R5");
add->opcode = AddSubtract::OpCode::ADD;
CHECK(instruction.disassemble() == "ADD R7,R1,R5");
#endif
}
TEST_CASE("Move/Compare/Add/Subtract Immediate", TAG) {
uint16_t raw = 0b0010111001011011;
Instruction instruction(raw);
MovCmpAddSubImmediate* mov = nullptr;
REQUIRE((mov = std::get_if<MovCmpAddSubImmediate>(&instruction.data)));
CHECK(mov->offset == 91);
CHECK(mov->rd == 6);
CHECK(mov->opcode == MovCmpAddSubImmediate::OpCode::CMP);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "CMP R6,#91");
mov->opcode = MovCmpAddSubImmediate::OpCode::ADD;
CHECK(instruction.disassemble() == "ADD R6,#91");
mov->opcode = MovCmpAddSubImmediate::OpCode::SUB;
CHECK(instruction.disassemble() == "SUB R6,#91");
mov->opcode = MovCmpAddSubImmediate::OpCode::MOV;
CHECK(instruction.disassemble() == "MOV R6,#91");
#endif
}
TEST_CASE("ALU Operations", TAG) {
uint16_t raw = 0b0100000110011111;
Instruction instruction(raw);
AluOperations* alu = nullptr;
REQUIRE((alu = std::get_if<AluOperations>(&instruction.data)));
CHECK(alu->rd == 7);
CHECK(alu->rs == 3);
CHECK(alu->opcode == AluOperations::OpCode::SBC);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "SBC R7,R3");
#define OPCODE(op) \
alu->opcode = AluOperations::OpCode::op; \
CHECK(instruction.disassemble() == #op " R7,R3");
OPCODE(AND)
OPCODE(EOR)
OPCODE(LSL)
OPCODE(LSR)
OPCODE(ASR)
OPCODE(ADC)
OPCODE(SBC)
OPCODE(ROR)
OPCODE(TST)
OPCODE(NEG)
OPCODE(CMP)
OPCODE(CMN)
OPCODE(ORR)
OPCODE(MUL)
OPCODE(BIC)
OPCODE(MVN)
#undef OPCODE
#endif
}
TEST_CASE("Hi Register Operations/Branch Exchange", TAG) {
HiRegisterOperations* hi = nullptr;
uint16_t raw = 0b0100011000011010;
SECTION("both lo") {
Instruction instruction(raw);
REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
CHECK(hi->rd == 2);
CHECK(hi->rs == 3);
}
SECTION("hi rd") {
raw |= 1 << 7;
Instruction instruction(raw);
REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
CHECK(hi->rd == 10);
CHECK(hi->rs == 3);
}
SECTION("hi rs") {
raw |= 1 << 6;
Instruction instruction(raw);
REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
CHECK(hi->rd == 2);
CHECK(hi->rs == 11);
}
if (hi)
CHECK(hi->opcode == HiRegisterOperations::OpCode::MOV);
SECTION("both hi") {
raw |= 1 << 6;
raw |= 1 << 7;
Instruction instruction(raw);
REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
CHECK(hi->rd == 10);
CHECK(hi->rs == 11);
CHECK(hi->opcode == HiRegisterOperations::OpCode::MOV);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "MOV R10,R11");
hi->opcode = HiRegisterOperations::OpCode::ADD;
CHECK(instruction.disassemble() == "ADD R10,R11");
hi->opcode = HiRegisterOperations::OpCode::CMP;
CHECK(instruction.disassemble() == "CMP R10,R11");
hi->opcode = HiRegisterOperations::OpCode::BX;
CHECK(instruction.disassemble() == "BX R11");
#endif
}
}
TEST_CASE("PC Relative Load", TAG) {
uint16_t raw = 0b0100101011100110;
Instruction instruction(raw);
PcRelativeLoad* ldr = nullptr;
REQUIRE((ldr = std::get_if<PcRelativeLoad>(&instruction.data)));
// 230 << 2
CHECK(ldr->word == 920);
CHECK(ldr->rd == 2);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "LDR R2,[PC,#920]");
#endif
}
TEST_CASE("Load/Store with Register Offset", TAG) {
uint16_t raw = 0b0101000110011101;
Instruction instruction(raw);
LoadStoreRegisterOffset* ldr = nullptr;
REQUIRE((ldr = std::get_if<LoadStoreRegisterOffset>(&instruction.data)));
CHECK(ldr->rd == 5);
CHECK(ldr->rb == 3);
CHECK(ldr->ro == 6);
CHECK(ldr->byte == false);
CHECK(ldr->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STR R5,[R3,R6]");
ldr->byte = true;
CHECK(instruction.disassemble() == "STRB R5,[R3,R6]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDRB R5,[R3,R6]");
ldr->byte = false;
CHECK(instruction.disassemble() == "LDR R5,[R3,R6]");
#endif
}
TEST_CASE("Load/Store Sign-Extended Byte/Halfword", TAG) {
uint16_t raw = 0b0101001110011101;
Instruction instruction(raw);
LoadStoreSignExtendedHalfword* ldr = nullptr;
REQUIRE(
(ldr = std::get_if<LoadStoreSignExtendedHalfword>(&instruction.data)));
CHECK(ldr->rd == 5);
CHECK(ldr->rb == 3);
CHECK(ldr->ro == 6);
CHECK(ldr->s == false);
CHECK(ldr->h == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STRH R5,[R3,R6]");
ldr->h = true;
CHECK(instruction.disassemble() == "LDRH R5,[R3,R6]");
ldr->s = true;
CHECK(instruction.disassemble() == "LDSH R5,[R3,R6]");
ldr->h = false;
CHECK(instruction.disassemble() == "LDSB R5,[R3,R6]");
#endif
}
TEST_CASE("Load/Store with Immediate Offset", TAG) {
uint16_t raw = 0b0110010110011101;
Instruction instruction(raw);
LoadStoreImmediateOffset* ldr = nullptr;
REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
CHECK(ldr->rd == 5);
CHECK(ldr->rb == 3);
// 22 << 4 when byte == false
CHECK(ldr->offset == 88);
CHECK(ldr->byte == false);
CHECK(ldr->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STR R5,[R3,#88]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDR R5,[R3,#88]");
#endif
// byte
raw = 0b0111010110011101;
instruction = Instruction(raw);
INFO(instruction.data.index());
REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
CHECK(ldr->byte == true);
CHECK(ldr->offset == 22);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STRB R5,[R3,#22]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDRB R5,[R3,#22]");
#endif
}
TEST_CASE("Load/Store Halfword", TAG) {
uint16_t raw = 0b1000011010011101;
Instruction instruction(raw);
LoadStoreHalfword* ldr = nullptr;
REQUIRE((ldr = std::get_if<LoadStoreHalfword>(&instruction.data)));
CHECK(ldr->rd == 5);
CHECK(ldr->rb == 3);
// 26 << 1
CHECK(ldr->offset == 52);
CHECK(ldr->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STRH R5,[R3,#52]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDRH R5,[R3,#52]");
#endif
}
TEST_CASE("SP-Relative Load/Store", TAG) {
uint16_t raw = 0b1001010010011101;
Instruction instruction(raw);
SpRelativeLoad* ldr = nullptr;
REQUIRE((ldr = std::get_if<SpRelativeLoad>(&instruction.data)));
CHECK(ldr->rd == 4);
// 157 << 2
CHECK(ldr->word == 628);
CHECK(ldr->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STR R4,[SP,#628]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDR R4,[SP,#628]");
#endif
}
TEST_CASE("Load Adress", TAG) {
uint16_t raw = 0b1010000110001111;
Instruction instruction(raw);
LoadAddress* add = nullptr;
REQUIRE((add = std::get_if<LoadAddress>(&instruction.data)));
// 143 << 2
CHECK(add->word == 572);
CHECK(add->rd == 1);
CHECK(add->sp == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ADD R1,PC,#572");
add->sp = true;
CHECK(instruction.disassemble() == "ADD R1,SP,#572");
#endif
}
TEST_CASE("Add Offset to Stack Pointer", TAG) {
uint16_t raw = 0b1011000000100101;
Instruction instruction(raw);
AddOffsetStackPointer* add = nullptr;
REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
// 37 << 2
CHECK(add->word == 148);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ADD SP,#148");
#endif
raw = 0b1011000010100101;
instruction = Instruction(raw);
REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
CHECK(add->word == -148);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ADD SP,#-148");
#endif
}
TEST_CASE("Push/Pop Registers", TAG) {
uint16_t raw = 0b1011010000110101;
Instruction instruction(raw);
PushPopRegister* push = nullptr;
REQUIRE((push = std::get_if<PushPopRegister>(&instruction.data)));
CHECK(push->regs == 53);
CHECK(push->pclr == false);
CHECK(push->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "PUSH {R0,R2,R4,R5}");
push->pclr = true;
CHECK(instruction.disassemble() == "PUSH {R0,R2,R4,R5,LR}");
push->load = true;
CHECK(instruction.disassemble() == "POP {R0,R2,R4,R5,PC}");
push->pclr = false;
CHECK(instruction.disassemble() == "POP {R0,R2,R4,R5}");
#endif
}
TEST_CASE("Multiple Load/Store", TAG) {
uint16_t raw = 0b1100011001100101;
Instruction instruction(raw);
MultipleLoad* ldm = nullptr;
REQUIRE((ldm = std::get_if<MultipleLoad>(&instruction.data)));
CHECK(ldm->regs == 101);
CHECK(ldm->rb == 6);
CHECK(ldm->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STMIA R6!,{R0,R2,R5,R6}");
ldm->load = true;
CHECK(instruction.disassemble() == "LDMIA R6!,{R0,R2,R5,R6}");
#endif
}
TEST_CASE("Conditional Branch", TAG) {
uint16_t raw = 0b1101100110110100;
Instruction instruction(raw);
ConditionalBranch* b = nullptr;
REQUIRE((b = std::get_if<ConditionalBranch>(&instruction.data)));
// (-76 << 1)
CHECK(b->offset == -152);
CHECK(b->condition == Condition::LS);
#ifdef DISASSEMBLER
// take prefetch into account
// offset + 4 = -152 + 4
CHECK(instruction.disassemble() == "BLS #-148");
#endif
}
TEST_CASE("SoftwareInterrupt") {
uint16_t raw = 0b1101111100110011;
Instruction instruction(raw);
SoftwareInterrupt* swi = nullptr;
REQUIRE((swi = std::get_if<SoftwareInterrupt>(&instruction.data)));
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "SWI 51");
#endif
}
TEST_CASE("Unconditional Branch") {
uint16_t raw = 0b1110011100110011;
Instruction instruction(raw);
UnconditionalBranch* b = nullptr;
REQUIRE((b = std::get_if<UnconditionalBranch>(&instruction.data)));
// (2147483443 << 1)
REQUIRE(b->offset == -410);
#ifdef DISASSEMBLER
// take prefetch into account
// offset + 4 = -410 + 4
CHECK(instruction.disassemble() == "B #-406");
#endif
}
TEST_CASE("Long Branch with link") {
uint16_t raw = 0b1111110011101100;
Instruction instruction(raw);
LongBranchWithLink* bl = nullptr;
REQUIRE((bl = std::get_if<LongBranchWithLink>(&instruction.data)));
// 1260 << 1
CHECK(bl->offset == 1260);
CHECK(bl->low == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "BL #1260");
bl->low = false;
CHECK(instruction.disassemble() == "BLH #1260");
#endif
}
#undef TAG

4
tests/cpu/thumb/meson.build
View File

@@ -1,4 +0,0 @@
tests_sources += files(
'instruction.cc',
'exec.cc'
)

8
tests/main.cc
View File

@@ -1,8 +0,0 @@
#include "util/loglevel.hh"
#include <catch2/catch_session.hpp>
int
main(int argc, char* argv[]) {
matar::set_log_level(matar::LogLevel::Off);
return Catch::Session().run(argc, argv);
}

19
tests/meson.build
View File

@@ -2,27 +2,18 @@ tests_deps = [
lib
]
src = include_directories('../src')
tests_sources = files(
'main.cc',
'bus.cc'
)
tests_cpp_args = lib_cpp_args
tests_sources = files()
subdir('cpu')
subdir('util')
catch2 = dependency('catch2', version: '>=3.4.0', static: true)
catch2 = dependency('catch2-with-main', version: '>=3.4.0', static: true)
catch2_tests = executable(
'matar_tests',
meson.project_name() + '_tests',
tests_sources,
dependencies: catch2,
link_with: tests_deps,
include_directories: [inc, src],
build_by_default: false,
cpp_args: tests_cpp_args
include_directories: inc,
build_by_default: false
)
test('catch2 tests', catch2_tests)

108
tests/util/bits.cc
View File

@@ -1,108 +0,0 @@
#include "util/bits.hh"
#include <catch2/catch_test_macros.hpp>
#define TAG "[util][bits]"
TEST_CASE("8 bits", TAG) {
uint8_t num = 45;
CHECK(get_bit(num, 0));
CHECK(!get_bit(num, 1));
CHECK(get_bit(num, 5));
CHECK(!get_bit(num, 6));
CHECK(!get_bit(num, 7));
set_bit(num, 6);
CHECK(get_bit(num, 6));
rst_bit(num, 6);
CHECK(!get_bit(num, 6));
chg_bit(num, 5, false);
CHECK(!get_bit(num, 5));
chg_bit(num, 5, true);
CHECK(get_bit(num, 5));
// 0b0110
CHECK(bit_range(num, 1, 4) == 6);
}
TEST_CASE("16 bits", TAG) {
uint16_t num = 34587;
CHECK(get_bit(num, 0));
CHECK(get_bit(num, 1));
CHECK(!get_bit(num, 5));
CHECK(!get_bit(num, 14));
CHECK(get_bit(num, 15));
set_bit(num, 14);
CHECK(get_bit(num, 14));
rst_bit(num, 14);
CHECK(!get_bit(num, 14));
chg_bit(num, 5, true);
CHECK(get_bit(num, 5));
// num = 45
chg_bit(num, 5, false);
CHECK(!get_bit(num, 5));
// 0b1000110
CHECK(bit_range(num, 2, 8) == 70);
}
TEST_CASE("32 bits", TAG) {
uint32_t num = 3194142523;
CHECK(get_bit(num, 0));
CHECK(get_bit(num, 1));
CHECK(get_bit(num, 12));
CHECK(get_bit(num, 29));
CHECK(!get_bit(num, 30));
CHECK(get_bit(num, 31));
set_bit(num, 30);
CHECK(get_bit(num, 30));
rst_bit(num, 30);
CHECK(!get_bit(num, 30));
chg_bit(num, 12, false);
CHECK(!get_bit(num, 12));
chg_bit(num, 12, true);
CHECK(get_bit(num, 12));
// 0b10011000101011111100111
CHECK(bit_range(num, 3, 25) == 5003239);
}
TEST_CASE("64 bits", TAG) {
uint64_t num = 58943208889991935;
CHECK(get_bit(num, 0));
CHECK(get_bit(num, 1));
CHECK(!get_bit(num, 10));
CHECK(get_bit(num, 55));
CHECK(!get_bit(num, 60));
set_bit(num, 63);
CHECK(get_bit(num, 63));
rst_bit(num, 63);
CHECK(!get_bit(num, 63));
chg_bit(num, 10, true);
CHECK(get_bit(num, 10));
chg_bit(num, 10, false);
CHECK(!get_bit(num, 10));
// 0b011010001
CHECK(bit_range(num, 39, 47) == 209);
}
#undef TAG

23
tests/util/crypto.cc
View File

@@ -1,23 +0,0 @@
#include "util/crypto.hh"
#include <catch2/catch_test_macros.hpp>
#define TAG "[util][crypto]"
TEST_CASE("sha256 matar", TAG) {
std::array<uint8_t, 5> data = { 'm', 'a', 't', 'a', 'r' };
CHECK(crypto::sha256(data) ==
"3b02a908fd5743c0e868675bb6ae77d2a62b3b5f7637413238e2a1e0e94b6a53");
}
TEST_CASE("sha256 forgis", TAG) {
std::array<uint8_t, 32> data = { 'i', ' ', 'p', 'u', 't', ' ', 't', 'h',
'e', ' ', 'n', 'e', 'w', ' ', 'f', 'o',
'r', 'g', 'i', 's', ' ', 'o', 'n', ' ',
't', 'h', 'e', ' ', 'j', 'e', 'e', 'p' };
CHECK(crypto::sha256(data) ==
"cfddca2ce2673f355518cbe2df2a8522693c54723a469e8b36a4f68b90d2b759");
}
#undef TAG

4
tests/util/meson.build
View File

@@ -1,4 +0,0 @@
tests_sources += files(
'bits.cc',
'crypto.cc'
)