natto1784/matar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Compare commits

base: natto1784:build-system
Branches Tags
natto1784:master natto1784:thumb natto1784:tests natto1784:build-system natto1784:test-public-api
..
compare: natto1784:test-public-api
Branches Tags
natto1784:master natto1784:thumb natto1784:tests natto1784:build-system natto1784:test-public-api

1 Commits
build-syst ... test-publi

Author SHA1 Message Date
Amneesh Singh
b918b75f27 tests: add some exec tests 
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
 2023-09-18 08:05:21 +05:30
40 changed files with 1423 additions and 1953 deletions
Expand all files Collapse all files

2
.envrc
View File

@@ -1 +1 @@
use flake .#matar-clang
use flake

36
.github/workflows/clang.yml vendored
View File

@@ -1,36 +0,0 @@
name: matar-clang
on: [push, pull_request, workflow_dispatch]
env:
BUILDDIR: build
jobs:
build:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v3
- uses: cachix/install-nix-action@v20
with:
extra_nix_config: |
auto-optimise-store = true
experimental-features = nix-command flakes
- uses: cachix/cachix-action@v12
with:
name: pain
authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
- name: setup
run: nix develop .#matar-clang -c meson setup $BUILDDIR
- name: fmt
run: nix develop .#matar-clang -c ninja clang-format-check -C $BUILDDIR
- name: lint
run: nix develop .#matar-clang -c ninja clang-tidy -C $BUILDDIR
- name: tests
run: nix develop .#matar-clang -c ninja test -C $BUILDDIR
- name: build
run: nix develop .#matar-clang -c ninja -C $BUILDDIR

19
.github/workflows/gcc.yml → .github/workflows/main.yml vendored
View File

@@ -1,4 +1,4 @@
name: matar-gcc
name: matar
on: [push, pull_request, workflow_dispatch]
env:
@@ -14,17 +14,18 @@ jobs:
extra_nix_config: |
auto-optimise-store = true
experimental-features = nix-command flakes
- uses: cachix/cachix-action@v12
with:
name: pain
authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
- name: setup
run: nix develop .#matar -c meson setup $BUILDDIR
run: nix develop -c meson setup $BUILDDIR
- name: fmt
run: nix develop -c ninja clang-format-check -C $BUILDDIR
- name: lint
run: nix develop -c ninja clang-tidy -C $BUILDDIR
- name: tests
run: nix develop .#matar -c ninja test -C $BUILDDIR
run: nix develop -c ninja test -C $BUILDDIR
- name: build
run: nix develop .#matar -c ninja -C $BUILDDIR
run: nix develop -c ninja -C $BUILDDIR

12
apps/target/main.cc
View File

@@ -15,7 +15,7 @@
int
main(int argc, const char* argv[]) {
std::vector<uint8_t> rom;
std::array<uint8_t, matar::Memory::BIOS_SIZE> bios = { 0 };
std::array<uint8_t, Memory::BIOS_SIZE> bios = { 0 };
auto usage = [argv]() {
std::cerr << "Usage: " << argv[0] << " <file> [-b <bios>]" << std::endl;
@@ -65,7 +65,7 @@ main(int argc, const char* argv[]) {
ifile.seekg(0, std::ios::end);
bios_size = ifile.tellg();
if (bios_size != matar::Memory::BIOS_SIZE) {
if (bios_size != Memory::BIOS_SIZE) {
throw std::ios::failure("BIOS file has invalid size",
std::error_code());
}
@@ -85,12 +85,12 @@ main(int argc, const char* argv[]) {
std::flush(std::cout);
try {
matar::Memory memory(std::move(bios), std::move(rom));
matar::Bus bus(memory);
matar::Cpu cpu(bus);
Memory memory(std::move(bios), std::move(rom));
Bus bus(memory);
Cpu cpu(bus);
while (true) {
cpu.step();
sleep(2);
sleep(1);
}
} catch (const std::exception& e) {
std::cerr << "Exception: " << e.what() << std::endl;

2
apps/target/meson.build
View File

@@ -7,7 +7,7 @@ target_sources = files(
)
executable(
'matar',
meson.project_name(),
target_sources,
link_with: target_deps,
include_directories: inc,

45
flake.lock generated
View File

@@ -1,60 +1,23 @@
{
"nodes": {
"flake-parts": {
"inputs": {
"nixpkgs-lib": "nixpkgs-lib"
},
"locked": {
"lastModified": 1693611461,
"narHash": "sha256-aPODl8vAgGQ0ZYFIRisxYG5MOGSkIczvu2Cd8Gb9+1Y=",
"owner": "hercules-ci",
"repo": "flake-parts",
"rev": "7f53fdb7bdc5bb237da7fefef12d099e4fd611ca",
"type": "github"
},
"original": {
"owner": "hercules-ci",
"repo": "flake-parts",
"type": "github"
}
},
"nixpkgs": {
"locked": {
"lastModified": 1695318763,
"narHash": "sha256-FHVPDRP2AfvsxAdc+AsgFJevMz5VBmnZglFUMlxBkcY=",
"lastModified": 1694911158,
"narHash": "sha256-5WENkcO8O5SuA5pozpVppLGByWfHVv/1wOWgB2+TfV4=",
"owner": "nixos",
"repo": "nixpkgs",
"rev": "e12483116b3b51a185a33a272bf351e357ba9a99",
"rev": "46423a1a750594236673c1d741def4e93cf5a8f7",
"type": "github"
},
"original": {
"owner": "nixos",
"ref": "nixpkgs-unstable",
"repo": "nixpkgs",
"type": "github"
}
},
"nixpkgs-lib": {
"locked": {
"dir": "lib",
"lastModified": 1693471703,
"narHash": "sha256-0l03ZBL8P1P6z8MaSDS/MvuU8E75rVxe5eE1N6gxeTo=",
"owner": "NixOS",
"repo": "nixpkgs",
"rev": "3e52e76b70d5508f3cec70b882a29199f4d1ee85",
"type": "github"
},
"original": {
"dir": "lib",
"owner": "NixOS",
"ref": "nixos-unstable",
"ref": "master",
"repo": "nixpkgs",
"type": "github"
}
},
"root": {
"inputs": {
"flake-parts": "flake-parts",
"nixpkgs": "nixpkgs"
}
}

73
flake.nix
View File

@@ -2,39 +2,80 @@
description = "matar";
inputs = {
nixpkgs.url = github:nixos/nixpkgs/nixpkgs-unstable;
flake-parts.url = github:hercules-ci/flake-parts;
nixpkgs.url = github:nixos/nixpkgs/master;
};
outputs = inputs@{ self, nixpkgs, flake-parts }:
flake-parts.lib.mkFlake { inherit inputs; } {
outputs = { self, nixpkgs }:
let
systems = [
"x86_64-linux"
"aarch64-linux"
];
imports = [
./nix
];
perSystem = { self', system, ... }:
eachSystem = with nixpkgs.lib; f: foldAttrs mergeAttrs { }
(map (s: mapAttrs (_: v: { ${s} = v; }) (f s)) systems);
in
eachSystem (system:
let
pkgs = import nixpkgs { inherit system; };
# aliases
llvm = pkgs.llvmPackages_16;
stdenv = llvm.libcxxStdenv;
# TODO: this is ugly
#dependencies
nativeBuildInputs = with pkgs;
[
meson
ninja
# libraries
pkg-config
cmake
((pkgs.fmt.override {
inherit stdenv;
enableShared = false;
}).overrideAttrs (oa: {
cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
})).dev
(catch2_3.override { inherit stdenv; }).out
];
in
rec {
packages = rec {
inherit (llvm) libcxxabi;
matar = stdenv.mkDerivation rec {
name = "matar";
version = "0.1";
src = pkgs.lib.sourceFilesBySuffices ./. [
".hh"
".cc"
".build"
"meson_options.txt"
];
in
rec {
_module.args = {
inherit src pkgs;
outputs = [ "out" "dev" ];
inherit nativeBuildInputs;
enableParallelBuilding = true;
};
default = matar;
};
devShells = rec {
matar = pkgs.mkShell.override { inherit stdenv; } {
name = "matar";
packages = nativeBuildInputs ++ (with pkgs; [
# lsp
clang-tools_16
]);
};
default = matar;
};
formatter = pkgs.nixpkgs-fmt;
};
};
});
}

2
include/bus.hh
View File

@@ -3,7 +3,6 @@
#include "memory.hh"
#include <memory>
namespace matar {
class Bus {
public:
Bus(const Memory& memory);
@@ -20,4 +19,3 @@ class Bus {
private:
std::shared_ptr<Memory> memory;
};
}

39
src/cpu/arm/instruction.hh → include/cpu/arm/instruction.hh
View File

@@ -1,13 +1,7 @@
#pragma once
#include "cpu/alu.hh"
#include "cpu/psr.hh"
#include "cpu/utility.hh"
#include <cstdint>
#include <fmt/ostream.h>
#include <variant>
namespace matar {
namespace arm {
template<class... Ts>
struct overloaded : Ts... {
using Ts::operator()...;
@@ -15,8 +9,7 @@ struct overloaded : Ts... {
template<class... Ts>
overloaded(Ts...) -> overloaded<Ts...>;
static constexpr size_t INSTRUCTION_SIZE = 4;
namespace arm {
struct BranchAndExchange {
uint8_t rn;
};
@@ -87,25 +80,6 @@ struct BlockDataTransfer {
};
struct DataProcessing {
enum class OpCode {
AND = 0b0000,
EOR = 0b0001,
SUB = 0b0010,
RSB = 0b0011,
ADD = 0b0100,
ADC = 0b0101,
SBC = 0b0110,
RSC = 0b0111,
TST = 0b1000,
TEQ = 0b1001,
CMP = 0b1010,
CMN = 0b1011,
ORR = 0b1100,
MOV = 0b1101,
BIC = 0b1110,
MVN = 0b1111
};
std::variant<Shift, uint32_t> operand;
uint8_t rd;
uint8_t rn;
@@ -188,13 +162,4 @@ struct Instruction {
std::string disassemble();
};
std::ostream&
operator<<(std::ostream& os, const DataProcessing::OpCode cond);
}
}
namespace fmt {
template<>
struct formatter<matar::arm::DataProcessing::OpCode> : ostream_formatter {};
}

3
include/cpu/arm/meson.build Normal file
View File

@@ -0,0 +1,3 @@
headers += files(
'instruction.hh',
)

65
include/cpu/cpu.hh
View File

@@ -1,21 +1,60 @@
#include "bus.hh"
#pragma once
namespace matar {
class CpuImpl;
#include "arm/instruction.hh"
#include "bus.hh"
#include "psr.hh"
#include <cstdint>
using std::size_t;
class Cpu {
public:
Cpu(const Bus& bus) noexcept;
Cpu(const Cpu&) = delete;
Cpu(Cpu&&) = delete;
Cpu& operator=(const Cpu&) = delete;
Cpu& operator=(Cpu&&) = delete;
~Cpu();
Cpu(const Bus& bus);
void step();
private:
std::unique_ptr<CpuImpl> impl;
static constexpr uint8_t GPR_COUNT = 16;
static constexpr uint8_t GPR_FIQ_FIRST = 8;
static constexpr uint8_t GPR_SVC_FIRST = 13;
static constexpr uint8_t GPR_ABT_FIRST = 13;
static constexpr uint8_t GPR_IRQ_FIRST = 13;
static constexpr uint8_t GPR_UND_FIRST = 13;
static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
std::shared_ptr<Bus> bus;
std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
Psr cpsr; // current program status register
Psr spsr; // status program status register
static constexpr uint8_t PC_INDEX = 15;
static_assert(PC_INDEX < GPR_COUNT);
uint32_t& pc = gpr[PC_INDEX];
bool is_flushed;
void chg_mode(const Mode to);
void exec_arm(const arm::Instruction instruction);
struct {
std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
// visible registers before the mode switch
std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
} gpr_banked; // banked general purpose registers
struct {
Psr fiq;
Psr svc;
Psr abt;
Psr irq;
Psr und;
} spsr_banked; // banked saved program status registers
};
}

4
include/cpu/meson.build
View File

@@ -1,3 +1,7 @@
headers += files(
'cpu.hh',
'psr.hh',
'utility.hh'
)
subdir('arm')

47
src/cpu/psr.hh → include/cpu/psr.hh
View File

@@ -1,42 +1,7 @@
#pragma once
#include "utility.hh"
#include <cstdint>
#include <fmt/ostream.h>
namespace matar {
enum class Mode {
/* M[4:0] in PSR */
User = 0b10000,
Fiq = 0b10001,
Irq = 0b10010,
Supervisor = 0b10011,
Abort = 0b10111,
Undefined = 0b11011,
System = 0b11111,
};
enum class State {
Arm = 0,
Thumb = 1
};
enum class Condition {
EQ = 0b0000,
NE = 0b0001,
CS = 0b0010,
CC = 0b0011,
MI = 0b0100,
PL = 0b0101,
VS = 0b0110,
VC = 0b0111,
HI = 0b1000,
LS = 0b1001,
GE = 0b1010,
LT = 0b1011,
GT = 0b1100,
LE = 0b1101,
AL = 0b1110
};
class Psr {
public:
@@ -88,13 +53,3 @@ class Psr {
uint32_t psr;
};
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const Condition cond);
}
namespace fmt {
template<>
struct formatter<matar::Condition> : ostream_formatter {};
}

99
include/cpu/utility.hh Normal file
View File

@@ -0,0 +1,99 @@
#pragma once
#include <fmt/ostream.h>
#include <ostream>
static constexpr size_t ARM_INSTRUCTION_SIZE = 4;
static constexpr size_t THUMB_INSTRUCTION_SIZE = 2;
enum class Mode {
/* M[4:0] in PSR */
User = 0b10000,
Fiq = 0b10001,
Irq = 0b10010,
Supervisor = 0b10011,
Abort = 0b10111,
Undefined = 0b11011,
System = 0b11111,
};
enum class State {
Arm = 0,
Thumb = 1
};
enum class Condition {
EQ = 0b0000,
NE = 0b0001,
CS = 0b0010,
CC = 0b0011,
MI = 0b0100,
PL = 0b0101,
VS = 0b0110,
VC = 0b0111,
HI = 0b1000,
LS = 0b1001,
GE = 0b1010,
LT = 0b1011,
GT = 0b1100,
LE = 0b1101,
AL = 0b1110
};
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const Condition cond);
template<>
struct fmt::formatter<Condition> : ostream_formatter {};
enum class OpCode {
AND = 0b0000,
EOR = 0b0001,
SUB = 0b0010,
RSB = 0b0011,
ADD = 0b0100,
ADC = 0b0101,
SBC = 0b0110,
RSC = 0b0111,
TST = 0b1000,
TEQ = 0b1001,
CMP = 0b1010,
CMN = 0b1011,
ORR = 0b1100,
MOV = 0b1101,
BIC = 0b1110,
MVN = 0b1111
};
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const OpCode cond);
template<>
struct fmt::formatter<OpCode> : ostream_formatter {};
enum class ShiftType {
LSL = 0b00,
LSR = 0b01,
ASR = 0b10,
ROR = 0b11
};
struct ShiftData {
ShiftType type;
bool immediate;
uint8_t operand;
};
struct Shift {
uint8_t rm;
ShiftData data;
};
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const ShiftType cond);
template<>
struct fmt::formatter<ShiftType> : ostream_formatter {};

4
include/header.hh
View File

@@ -3,10 +3,7 @@
#include <cstdint>
#include <string>
namespace matar {
struct Header {
static constexpr uint8_t HEADER_SIZE = 192;
enum class UniqueCode {
Old, // old games
New, // new games
@@ -45,4 +42,3 @@ struct Header {
uint32_t multiboot_entrypoint;
uint8_t slave_id;
};
}

4
include/memory.hh
View File

@@ -4,10 +4,8 @@
#include <array>
#include <cstddef>
#include <cstdint>
#include <unordered_map>
#include <vector>
namespace matar {
class Memory {
public:
static constexpr size_t BIOS_SIZE = 1024 * 16;
@@ -59,9 +57,7 @@ class Memory {
#undef MEMORY_REGION
std::unordered_map<size_t, uint8_t> invalid_mem;
std::vector<uint8_t> rom;
Header header;
void parse_header();
};
}

2
include/meson.build
View File

@@ -4,8 +4,6 @@ headers = files(
'header.hh',
)
inc = include_directories('.')
subdir('cpu')
install_headers(headers, subdir: meson.project_name(), preserve_path: true)

2
meson.build
View File

@@ -30,6 +30,8 @@ else
endif
'''
inc = include_directories('include')
subdir('include')
subdir('src')
subdir('apps')

23
nix/build.nix
View File

@@ -1,23 +0,0 @@
{ stdenv
, meson
, ninja
, pkg-config
, src ? "../."
, libraries ? [ ]
}:
stdenv.mkDerivation {
name = "matar";
version = "0.1";
inherit src;
outputs = [ "out" "dev" ];
nativeBuildInputs = [
meson
ninja
pkg-config
] ++ libraries;
enableParallelBuilding = true;
}

11
nix/default.nix
View File

@@ -1,11 +0,0 @@
{ ... }: {
imports = [
./matar.nix
./matar-clang.nix
];
perSystem = { self', pkgs, ... }: {
packages.default = self'.packages.matar-clang;
devShells.default = self'.devShells.matar-clang;
};
}

25
nix/matar-clang.nix
View File

@@ -1,25 +0,0 @@
{ ... }: {
perSystem = { pkgs, src, ... }:
let
llvm = pkgs.llvmPackages_16;
stdenv = llvm.libcxxStdenv;
libraries = with pkgs; [
((pkgs.fmt.override {
inherit stdenv;
enableShared = false;
}).overrideAttrs (oa: {
cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
})).dev
(catch2_3.override { inherit stdenv; }).out
];
in
{
packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
devShells.matar-clang = pkgs.callPackage ./shell.nix {
inherit libraries stdenv;
tools = with pkgs; [ clang-tools_16 ];
};
};
}

13
nix/matar.nix
View File

@@ -1,13 +0,0 @@
{ ... }: {
perSystem = { pkgs, src, ... }:
let
libraries = with pkgs; [
(pkgs.fmt.override { enableShared = false; }).dev
catch2_3.out
];
in
{
packages.matar = pkgs.callPackage ./build.nix { inherit src libraries; };
devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries; };
};
}

20
nix/shell.nix
View File

@@ -1,20 +0,0 @@
{ stdenv
, mkShell
, meson
, ninja
, pkg-config
, libraries ? [ ]
, tools ? [ ]
}:
mkShell.override { inherit stdenv; } {
name = "matar";
packages = [
meson
ninja
pkg-config
] ++ libraries ++ tools;
enableParallelBuilding = true;
}

2
src/bus.cc
View File

@@ -1,7 +1,6 @@
#include "bus.hh"
#include <memory>
namespace matar {
Bus::Bus(const Memory& memory)
: memory(std::make_shared<Memory>(memory)) {}
@@ -34,4 +33,3 @@ void
Bus::write_word(size_t address, uint32_t word) {
memory->write_word(address, word);
}
}

35
src/cpu/alu.hh
View File

@@ -1,35 +0,0 @@
#pragma once
#include <cstdint>
#include <fmt/ostream.h>
namespace matar {
enum class ShiftType {
LSL = 0b00,
LSR = 0b01,
ASR = 0b10,
ROR = 0b11
};
struct ShiftData {
ShiftType type;
bool immediate;
uint8_t operand;
};
struct Shift {
uint8_t rm;
ShiftData data;
};
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const ShiftType cond);
}
namespace fmt {
template<>
struct formatter<matar::ShiftType> : ostream_formatter {};
}

295
src/cpu/arm/exec.cc
View File

@@ -1,16 +1,14 @@
#include "cpu/cpu-impl.hh"
#include "cpu/cpu.hh"
#include "util/bits.hh"
#include "util/log.hh"
using namespace logger;
namespace matar {
void
CpuImpl::exec_arm(const arm::Instruction instruction) {
Condition cond = instruction.condition;
arm::InstructionData data = instruction.data;
Cpu::exec_arm(const arm::Instruction instruction) {
auto cond = instruction.condition;
auto data = instruction.data;
debug(cpsr.condition(cond));
if (!cpsr.condition(cond)) {
return;
}
@@ -51,11 +49,12 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
},
[this](Branch& data) {
if (data.link)
gpr[14] = pc - INSTRUCTION_SIZE;
gpr[14] = pc - ARM_INSTRUCTION_SIZE;
// data.offset accounts for two instructions ahead when
// disassembling, so need to adjust
pc = static_cast<int32_t>(pc) - 2 * INSTRUCTION_SIZE + data.offset;
pc =
static_cast<int32_t>(pc) - 2 * ARM_INSTRUCTION_SIZE + data.offset;
// pc is affected so flush the pipeline
is_flushed = true;
@@ -90,26 +89,22 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
pc_error(data.rs);
if (data.uns) {
auto cast = [](uint32_t x) -> uint64_t {
return static_cast<uint64_t>(x);
};
uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
(data.acc ? (cast(gpr[data.rdhi]) << 32) |
cast(gpr[data.rdlo])
uint64_t eval =
static_cast<uint64_t>(gpr[data.rm]) *
static_cast<uint64_t>(gpr[data.rs]) +
(data.acc ? (static_cast<uint64_t>(gpr[data.rdhi]) << 32) |
static_cast<uint64_t>(gpr[data.rdlo])
: 0);
gpr[data.rdlo] = bit_range(eval, 0, 31);
gpr[data.rdhi] = bit_range(eval, 32, 63);
} else {
auto cast = [](uint32_t x) -> int64_t {
return static_cast<int64_t>(static_cast<int32_t>(x));
};
int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
(data.acc ? (cast(gpr[data.rdhi]) << 32) |
cast(gpr[data.rdlo])
int64_t eval =
static_cast<int64_t>(gpr[data.rm]) *
static_cast<int64_t>(gpr[data.rs]) +
(data.acc ? static_cast<int64_t>(gpr[data.rdhi]) << 32 |
static_cast<int64_t>(gpr[data.rdlo])
: 0);
gpr[data.rdlo] = bit_range(eval, 0, 31);
@@ -175,11 +170,13 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
// PC is always two instructions ahead
if (data.rn == PC_INDEX)
address -= 2 * INSTRUCTION_SIZE;
address -= 2 * ARM_INSTRUCTION_SIZE;
if (data.pre)
address += (data.up ? offset : -offset);
debug(address);
// load
if (data.load) {
// byte
@@ -192,7 +189,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
} else {
// take PC into consideration
if (data.rd == PC_INDEX)
address += INSTRUCTION_SIZE;
address += ARM_INSTRUCTION_SIZE;
// byte
if (data.byte)
@@ -213,7 +210,6 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
},
[this, pc_warn, pc_error](HalfwordTransfer& data) {
uint32_t address = gpr[data.rn];
uint32_t offset = 0;
if (!data.pre && data.write)
log_error("Write-back enabled with post-indexing in {}",
@@ -226,19 +222,11 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
pc_warn(data.rn);
// offset is register number (4 bits) when not an immediate
if (!data.imm) {
if (!data.imm)
pc_error(data.offset);
offset = gpr[data.offset];
} else {
offset = data.offset;
}
// PC is always two instructions ahead
if (data.rn == PC_INDEX)
address -= 2 * INSTRUCTION_SIZE;
if (data.pre)
address += (data.up ? offset : -offset);
address += (data.up ? data.offset : -data.offset);
// load
if (data.load) {
@@ -268,7 +256,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
} else {
// take PC into consideration
if (data.rd == PC_INDEX)
address += INSTRUCTION_SIZE;
address += ARM_INSTRUCTION_SIZE;
// halfword
if (data.half)
@@ -276,7 +264,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
}
if (!data.pre)
address += (data.up ? offset : -offset);
address += (data.up ? data.offset : -data.offset);
if (!data.pre || data.write)
gpr[data.rn] = address;
@@ -344,8 +332,6 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
// reset back to original address + offset if incremented earlier
if (data.up)
address -= n_regs * alignment;
else
address -= alignment;
if (!data.pre || data.write)
gpr[data.rn] = address;
@@ -377,23 +363,24 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
}
break;
case PsrTransfer::Type::Msr_flg:
uint32_t operand =
(data.imm ? data.operand : gpr[data.operand]);
psr.set_n(get_bit(operand, 31));
psr.set_z(get_bit(operand, 30));
psr.set_c(get_bit(operand, 29));
psr.set_v(get_bit(operand, 28));
psr.set_n(get_bit(data.operand, 31));
psr.set_z(get_bit(data.operand, 30));
psr.set_c(get_bit(data.operand, 29));
psr.set_v(get_bit(data.operand, 28));
break;
}
},
[this, pc_error](DataProcessing& data) {
using OpCode = DataProcessing::OpCode;
uint32_t op_1 = gpr[data.rn];
uint32_t op_2 = 0;
uint32_t result = 0;
bool overflow = cpsr.v();
bool carry = cpsr.c();
bool negative = cpsr.n();
bool zero = cpsr.z();
if (const uint32_t* immediate =
std::get_if<uint32_t>(&data.operand)) {
op_2 = *immediate;
@@ -415,107 +402,154 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
// PC is 12 bytes ahead when shifting
if (data.rn == PC_INDEX)
op_1 += INSTRUCTION_SIZE;
op_1 += ARM_INSTRUCTION_SIZE;
}
bool overflow = cpsr.v();
bool carry = cpsr.c();
auto sub = [&carry, &overflow](uint32_t a, uint32_t b) -> uint32_t {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint32_t result = a - b;
carry = b <= a;
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result;
};
auto add = [&carry, &overflow](
uint32_t a, uint32_t b, bool c = 0) -> uint32_t {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
// 33 bits
uint64_t result_ = a + b + c;
uint32_t result = result_ & 0xFFFFFFFF;
carry = get_bit(result_, 32);
overflow = s1 == s2 && s2 != get_bit(result, 31);
return result;
};
auto sbc = [&carry,
&overflow](uint32_t a, uint32_t b, bool c) -> uint32_t {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint64_t result_ = a - b + c - 1;
uint32_t result = result_ & 0xFFFFFFFF;
carry = get_bit(result_, 32);
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result;
};
switch (data.opcode) {
case OpCode::AND:
case OpCode::TST:
case OpCode::AND: {
result = op_1 & op_2;
result = op_1 & op_2;
break;
case OpCode::EOR:
case OpCode::TEQ:
negative = get_bit(result, 31);
} break;
case OpCode::EOR: {
result = op_1 ^ op_2;
break;
case OpCode::SUB:
case OpCode::CMP:
result = sub(op_1, op_2);
break;
case OpCode::RSB:
result = sub(op_2, op_1);
break;
case OpCode::ADD:
case OpCode::CMN:
result = add(op_1, op_2);
break;
case OpCode::ADC:
result = add(op_1, op_2, carry);
break;
case OpCode::SBC:
result = sbc(op_1, op_2, carry);
break;
case OpCode::RSC:
result = sbc(op_2, op_1, carry);
break;
case OpCode::ORR:
negative = get_bit(result, 31);
} break;
case OpCode::SUB: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
result = op_1 - op_2;
negative = get_bit(result, 31);
carry = op_1 < op_2;
overflow = s1 != s2 && s2 == negative;
} break;
case OpCode::RSB: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
result = op_2 - op_1;
negative = get_bit(result, 31);
carry = op_2 < op_1;
overflow = s1 != s2 && s1 == negative;
} break;
case OpCode::ADD: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
// result_ is 33 bits
uint64_t result_ = op_2 + op_1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 == s2 && s1 != negative;
} break;
case OpCode::ADC: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_2 + op_1 + carry;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 == s2 && s1 != negative;
} break;
case OpCode::SBC: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_1 - op_2 + carry - 1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 != s2 && s2 == negative;
} break;
case OpCode::RSC: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_1 - op_2 + carry - 1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 != s2 && s1 == negative;
} break;
case OpCode::TST: {
result = op_1 & op_2;
negative = get_bit(result, 31);
} break;
case OpCode::TEQ: {
result = op_1 ^ op_2;
negative = get_bit(result, 31);
} break;
case OpCode::CMP: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
result = op_1 - op_2;
negative = get_bit(result, 31);
carry = op_1 < op_2;
overflow = s1 != s2 && s2 == negative;
} break;
case OpCode::CMN: {
bool s1 = get_bit(op_1, 31);
bool s2 = get_bit(op_2, 31);
uint64_t result_ = op_2 + op_1;
result = result_ & 0xFFFFFFFF;
negative = get_bit(result, 31);
carry = get_bit(result_, 32);
overflow = s1 == s2 && s1 != negative;
} break;
case OpCode::ORR: {
result = op_1 | op_2;
break;
case OpCode::MOV:
negative = get_bit(result, 31);
} break;
case OpCode::MOV: {
result = op_2;
break;
case OpCode::BIC:
negative = get_bit(result, 31);
} break;
case OpCode::BIC: {
result = op_1 & ~op_2;
break;
case OpCode::MVN:
negative = get_bit(result, 31);
} break;
case OpCode::MVN: {
result = ~op_2;
break;
negative = get_bit(result, 31);
} break;
}
auto set_conditions = [this, carry, overflow, result]() {
zero = result == 0;
debug(carry);
debug(overflow);
debug(zero);
debug(negative);
auto set_conditions = [this, carry, overflow, negative, zero]() {
cpsr.set_c(carry);
cpsr.set_v(overflow);
cpsr.set_n(get_bit(result, 31));
cpsr.set_z(result == 0);
cpsr.set_n(negative);
cpsr.set_z(zero);
};
if (data.set) {
if (data.rd == PC_INDEX) {
if (data.rd == 15) {
if (cpsr.mode() == Mode::User)
log_error("Running {} in User mode",
typeid(data).name());
spsr = cpsr;
} else {
set_conditions();
}
@@ -526,7 +560,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
set_conditions();
} else {
gpr[data.rd] = result;
if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
if (data.rd == 15 || data.opcode == OpCode::MVN)
is_flushed = true;
}
},
@@ -540,4 +574,3 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
} },
data);
}
}

46
src/cpu/arm/instruction.cc
View File

@@ -1,9 +1,9 @@
#include "instruction.hh"
#include "cpu/arm/instruction.hh"
#include "cpu/utility.hh"
#include "util/bits.hh"
#include <iterator>
namespace matar {
namespace arm {
using namespace arm;
Instruction::Instruction(uint32_t insn)
: condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
@@ -21,7 +21,7 @@ Instruction::Instruction(uint32_t insn)
// lsh 2 and sign extend the 26 bit offset to 32 bits
offset = (static_cast<int32_t>(offset) << 8) >> 6;
offset += 2 * INSTRUCTION_SIZE;
offset += 2 * ARM_INSTRUCTION_SIZE;
data = Branch{ .link = link, .offset = offset };
@@ -152,8 +152,6 @@ Instruction::Instruction(uint32_t insn)
// Data Processing
} else if ((insn & 0x0C000000) == 0x00000000) {
using OpCode = DataProcessing::OpCode;
uint8_t rd = bit_range(insn, 12, 15);
uint8_t rn = bit_range(insn, 16, 19);
bool set = get_bit(insn, 20);
@@ -421,8 +419,6 @@ Instruction::disassemble() {
}
},
[this](DataProcessing& data) {
using OpCode = DataProcessing::OpCode;
std::string op_2;
if (const uint32_t* operand =
@@ -499,37 +495,3 @@ Instruction::disassemble() {
[](auto) { return std::string("unknown instruction"); } },
data);
}
std::ostream&
operator<<(std::ostream& os, const DataProcessing::OpCode opcode) {
#define CASE(opcode) \
case DataProcessing::OpCode::opcode: \
os << #opcode; \
break;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(SUB)
CASE(RSB)
CASE(ADD)
CASE(ADC)
CASE(SBC)
CASE(RSC)
CASE(TST)
CASE(TEQ)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MOV)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return os;
}
}
}

145
src/cpu/cpu-impl.cc
View File

@@ -1,145 +0,0 @@
#include "cpu-impl.hh"
#include "util/bits.hh"
#include "util/log.hh"
#include <algorithm>
#include <cstdio>
using namespace logger;
namespace matar {
CpuImpl::CpuImpl(const Bus& bus) noexcept
: bus(std::make_shared<Bus>(bus))
, gpr({ 0 })
, cpsr(0)
, spsr(0)
, is_flushed(false)
, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
, spsr_banked({ 0, 0, 0, 0, 0 }) {
cpsr.set_mode(Mode::Supervisor);
cpsr.set_irq_disabled(true);
cpsr.set_fiq_disabled(true);
cpsr.set_state(State::Arm);
log_info("CPU successfully initialised");
// PC always points to two instructions ahead
// PC - 2 is the instruction being executed
pc += 2 * arm::INSTRUCTION_SIZE;
}
/* change modes */
void
CpuImpl::chg_mode(const Mode to) {
Mode from = cpsr.mode();
if (from == to)
return;
/* TODO: replace visible registers with view once I understand how to
* concatenate views */
#define STORE_BANKED(mode, MODE) \
std::copy(gpr.begin() + GPR_##MODE##_FIRST, \
gpr.begin() + gpr.size() - 1, \
gpr_banked.mode.begin())
switch (from) {
case Mode::Fiq:
STORE_BANKED(fiq, FIQ);
spsr_banked.fiq = spsr;
break;
case Mode::Supervisor:
STORE_BANKED(svc, SVC);
spsr_banked.svc = spsr;
break;
case Mode::Abort:
STORE_BANKED(abt, ABT);
spsr_banked.abt = spsr;
break;
case Mode::Irq:
STORE_BANKED(irq, IRQ);
spsr_banked.irq = spsr;
break;
case Mode::Undefined:
STORE_BANKED(und, UND);
spsr_banked.und = spsr;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#define RESTORE_BANKED(mode, MODE) \
std::copy(gpr_banked.mode.begin(), \
gpr_banked.mode.end(), \
gpr.begin() + GPR_##MODE##_FIRST)
switch (to) {
case Mode::Fiq:
RESTORE_BANKED(fiq, FIQ);
spsr = spsr_banked.fiq;
break;
case Mode::Supervisor:
RESTORE_BANKED(svc, SVC);
spsr = spsr_banked.svc;
break;
case Mode::Abort:
RESTORE_BANKED(abt, ABT);
spsr = spsr_banked.abt;
break;
case Mode::Irq:
RESTORE_BANKED(irq, IRQ);
spsr = spsr_banked.irq;
break;
case Mode::Undefined:
RESTORE_BANKED(und, UND);
spsr = spsr_banked.und;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#undef RESTORE_BANKED
cpsr.set_mode(to);
}
void
CpuImpl::step() {
// Current instruction is two instructions behind PC
uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
if (cpsr.state() == State::Arm) {
debug(cur_pc);
uint32_t x = bus->read_word(cur_pc);
arm::Instruction instruction(x);
log_info("{:#034b}", x);
exec_arm(instruction);
log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
if (is_flushed) {
// if flushed, do not increment the PC, instead set it to two
// instructions ahead to account for flushed "fetch" and "decode"
// instructions
pc += 2 * arm::INSTRUCTION_SIZE;
is_flushed = false;
} else {
// if not flushed continue like normal
pc += arm::INSTRUCTION_SIZE;
}
}
}
}

59
src/cpu/cpu-impl.hh
View File

@@ -1,59 +0,0 @@
#pragma once
#include "bus.hh"
#include "cpu/arm/instruction.hh"
#include "cpu/psr.hh"
#include <cstdint>
namespace matar {
class CpuImpl {
public:
CpuImpl(const Bus& bus) noexcept;
void step();
void chg_mode(const Mode to);
void exec_arm(const arm::Instruction instruction);
static constexpr uint8_t GPR_COUNT = 16;
static constexpr uint8_t GPR_FIQ_FIRST = 8;
static constexpr uint8_t GPR_SVC_FIRST = 13;
static constexpr uint8_t GPR_ABT_FIRST = 13;
static constexpr uint8_t GPR_IRQ_FIRST = 13;
static constexpr uint8_t GPR_UND_FIRST = 13;
static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
std::shared_ptr<Bus> bus;
std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
Psr cpsr; // current program status register
Psr spsr; // status program status register
static constexpr uint8_t PC_INDEX = 15;
static_assert(PC_INDEX < GPR_COUNT);
uint32_t& pc = gpr[PC_INDEX];
bool is_flushed;
struct {
std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
// visible registers before the mode switch
std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
} gpr_banked; // banked general purpose registers
struct {
Psr fiq;
Psr svc;
Psr abt;
Psr irq;
Psr und;
} spsr_banked; // banked saved program status registers
};
}

144
src/cpu/cpu.cc
View File

@@ -1,14 +1,144 @@
#include "cpu/cpu.hh"
#include "cpu-impl.hh"
#include "cpu/utility.hh"
#include "util/bits.hh"
#include "util/log.hh"
#include <algorithm>
#include <cstdio>
namespace matar {
Cpu::Cpu(const Bus& bus) noexcept
: impl(std::make_unique<CpuImpl>(bus)){};
using namespace logger;
Cpu::~Cpu() = default;
Cpu::Cpu(const Bus& bus)
: bus(std::make_shared<Bus>(bus))
, gpr({ 0 })
, cpsr(0)
, spsr(0)
, is_flushed(false)
, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
, spsr_banked({ 0, 0, 0, 0, 0 }) {
cpsr.set_mode(Mode::Supervisor);
cpsr.set_irq_disabled(true);
cpsr.set_fiq_disabled(true);
cpsr.set_state(State::Arm);
log_info("CPU successfully initialised");
// PC always points to two instructions ahead
// PC - 2 is the instruction being executed
pc += 2 * ARM_INSTRUCTION_SIZE;
}
/* change modes */
void
Cpu::chg_mode(const Mode to) {
Mode from = cpsr.mode();
if (from == to)
return;
/* TODO: replace visible registers with view once I understand how to
* concatenate views */
#define STORE_BANKED(mode, MODE) \
std::copy(gpr.begin() + GPR_##MODE##_FIRST, \
gpr.begin() + gpr.size() - 1, \
gpr_banked.mode.begin())
switch (from) {
case Mode::Fiq:
STORE_BANKED(fiq, FIQ);
spsr_banked.fiq = spsr;
break;
case Mode::Supervisor:
STORE_BANKED(svc, SVC);
spsr_banked.svc = spsr;
break;
case Mode::Abort:
STORE_BANKED(abt, ABT);
spsr_banked.abt = spsr;
break;
case Mode::Irq:
STORE_BANKED(irq, IRQ);
spsr_banked.irq = spsr;
break;
case Mode::Undefined:
STORE_BANKED(und, UND);
spsr_banked.und = spsr;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#define RESTORE_BANKED(mode, MODE) \
std::copy(gpr_banked.mode.begin(), \
gpr_banked.mode.end(), \
gpr.begin() + GPR_##MODE##_FIRST)
switch (to) {
case Mode::Fiq:
RESTORE_BANKED(fiq, FIQ);
spsr = spsr_banked.fiq;
break;
case Mode::Supervisor:
RESTORE_BANKED(svc, SVC);
spsr = spsr_banked.svc;
break;
case Mode::Abort:
RESTORE_BANKED(abt, ABT);
spsr = spsr_banked.abt;
break;
case Mode::Irq:
RESTORE_BANKED(irq, IRQ);
spsr = spsr_banked.irq;
break;
case Mode::Undefined:
RESTORE_BANKED(und, UND);
spsr = spsr_banked.und;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#undef RESTORE_BANKED
cpsr.set_mode(to);
}
void
Cpu::step() {
impl->step();
};
// Current instruction is two instructions behind PC
uint32_t cur_pc = pc - 2 * ARM_INSTRUCTION_SIZE;
if (cpsr.state() == State::Arm) {
debug(cur_pc);
uint32_t x = bus->read_word(cur_pc);
arm::Instruction instruction(x);
log_info("{:#034b}", x);
exec_arm(instruction);
log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
if (is_flushed) {
// if flushed, do not increment the PC, instead set it to two
// instructions ahead to account for flushed "fetch" and "decode"
// instructions
pc += 2 * ARM_INSTRUCTION_SIZE;
is_flushed = false;
} else {
// if not flushed continue like normal
pc += ARM_INSTRUCTION_SIZE;
}
}
}

3
src/cpu/meson.build
View File

@@ -1,8 +1,7 @@
lib_sources += files(
'cpu-impl.cc',
'cpu.cc',
'psr.cc',
'alu.cc'
'utility.cc'
)
subdir('arm')

39
src/cpu/psr.cc
View File

@@ -1,8 +1,7 @@
#include "psr.hh"
#include "cpu/psr.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar {
Psr::Psr(uint32_t raw)
: psr(raw & PSR_CLEAR_RESERVED) {}
@@ -91,42 +90,8 @@ Psr::condition(Condition cond) const {
case Condition::LE:
return z() || (n() != v());
case Condition::AL:
return true && state() == State::Arm;
return true;
}
return false;
}
std::ostream&
operator<<(std::ostream& os, const Condition cond) {
#define CASE(cond) \
case Condition::cond: \
os << #cond; \
break;
switch (cond) {
CASE(EQ)
CASE(NE)
CASE(CS)
CASE(CC)
CASE(MI)
CASE(PL)
CASE(VS)
CASE(VC)
CASE(HI)
CASE(LS)
CASE(GE)
CASE(LT)
CASE(GT)
CASE(LE)
case Condition::AL: {
// empty
}
}
#undef CASE
return os;
}
}

76
src/cpu/alu.cc → src/cpu/utility.cc
View File

@@ -1,7 +1,72 @@
#include "alu.hh"
#include "cpu/utility.hh"
#include "util/bits.hh"
#include <bit>
std::ostream&
operator<<(std::ostream& os, const Condition cond) {
#define CASE(cond) \
case Condition::cond: \
os << #cond; \
break;
switch (cond) {
CASE(EQ)
CASE(NE)
CASE(CS)
CASE(CC)
CASE(MI)
CASE(PL)
CASE(VS)
CASE(VC)
CASE(HI)
CASE(LS)
CASE(GE)
CASE(LT)
CASE(GT)
CASE(LE)
case Condition::AL: {
// empty
}
}
#undef CASE
return os;
}
std::ostream&
operator<<(std::ostream& os, const OpCode opcode) {
#define CASE(opcode) \
case OpCode::opcode: \
os << #opcode; \
break;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(SUB)
CASE(RSB)
CASE(ADD)
CASE(ADC)
CASE(SBC)
CASE(RSC)
CASE(TST)
CASE(TEQ)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MOV)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return os;
}
namespace matar {
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
uint32_t eval = 0;
@@ -37,11 +102,13 @@ eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
break;
case ShiftType::ROR:
if (amount == 0) {
eval = (value >> 1) | (carry << 31);
bool old_carry = carry;
carry = get_bit(value, 0);
eval = (value >> 1) | (old_carry << 31);
} else {
eval = std::rotr(value, amount);
carry = get_bit(value, (amount % 32 + 31) % 32);
eval = std::rotr(value, amount);
}
break;
}
@@ -68,4 +135,3 @@ operator<<(std::ostream& os, const ShiftType shift_type) {
return os;
}
}

4
src/memory.cc
View File

@@ -8,7 +8,6 @@
using namespace logger;
namespace matar {
Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
std::vector<uint8_t>&& rom)
: bios(std::move(bios))
@@ -131,7 +130,7 @@ Memory::write_word(size_t address, uint32_t word) {
void
Memory::parse_header() {
if (rom.size() < header.HEADER_SIZE) {
if (rom.size() < 192) {
throw std::out_of_range(
"ROM is not large enough to even have a header");
}
@@ -233,4 +232,3 @@ Memory::parse_header() {
// multiboot not required right now
}
}

13
src/meson.build
View File

@@ -5,22 +5,13 @@ lib_sources = files(
subdir('cpu')
lib_cpp_args = [ ]
fmt = dependency('fmt', version : '>=10.1.0', static: true)
if not fmt.found()
fmt = dependency('fmt', version : '>=10.1.0', static: false)
lib_cpp_args += 'DFMT_HEADER_ONLY'
endif
fmt = dependency('fmt', version : '>=10.1.0')
lib = library(
meson.project_name(),
lib_sources,
dependencies: [fmt],
include_directories: inc,
install: true,
cpp_args: lib_cpp_args
install: true
)
import('pkgconfig').generate(lib)

1146
tests/cpu/arm/exec.cc
View File

File diff suppressed because it is too large Load Diff

322
tests/cpu/arm/instruction.cc
View File

@@ -1,9 +1,9 @@
#include "cpu/arm/instruction.hh"
#include "cpu/utility.hh"
#include <catch2/catch_test_macros.hpp>
#define TAG "disassembler"
using namespace matar;
using namespace arm;
TEST_CASE("Branch and Exchange", TAG) {
@@ -12,11 +12,11 @@ TEST_CASE("Branch and Exchange", TAG) {
BranchAndExchange* bx = nullptr;
REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
CHECK(instruction.condition == Condition::GT);
REQUIRE(instruction.condition == Condition::GT);
CHECK(bx->rn == 10);
REQUIRE(bx->rn == 10);
CHECK(instruction.disassemble() == "BXGT R10");
REQUIRE(instruction.disassemble() == "BXGT R10");
}
TEST_CASE("Branch", TAG) {
@@ -25,18 +25,18 @@ TEST_CASE("Branch", TAG) {
Branch* b = nullptr;
REQUIRE((b = std::get_if<Branch>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
// last 24 bits = 8748995
// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
// Also +8 since PC is two instructions ahead
CHECK(b->offset == 0xFE15FF14);
CHECK(b->link == true);
REQUIRE(b->offset == 0xFE15FF14);
REQUIRE(b->link == true);
CHECK(instruction.disassemble() == "BL 0xFE15FF14");
REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
b->link = false;
CHECK(instruction.disassemble() == "B 0xFE15FF14");
REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
}
TEST_CASE("Multiply", TAG) {
@@ -45,20 +45,20 @@ TEST_CASE("Multiply", TAG) {
Multiply* mul = nullptr;
REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
CHECK(instruction.condition == Condition::EQ);
REQUIRE(instruction.condition == Condition::EQ);
CHECK(mul->rm == 0);
CHECK(mul->rs == 15);
CHECK(mul->rn == 14);
CHECK(mul->rd == 10);
CHECK(mul->acc == true);
CHECK(mul->set == true);
REQUIRE(mul->rm == 0);
REQUIRE(mul->rs == 15);
REQUIRE(mul->rn == 14);
REQUIRE(mul->rd == 10);
REQUIRE(mul->acc == true);
REQUIRE(mul->set == true);
CHECK(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
mul->acc = false;
mul->set = false;
CHECK(instruction.disassemble() == "MULEQ R10,R0,R15");
REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
}
TEST_CASE("Multiply Long", TAG) {
@@ -67,24 +67,24 @@ TEST_CASE("Multiply Long", TAG) {
MultiplyLong* mull = nullptr;
REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
CHECK(instruction.condition == Condition::NE);
REQUIRE(instruction.condition == Condition::NE);
CHECK(mull->rm == 2);
CHECK(mull->rs == 6);
CHECK(mull->rdlo == 7);
CHECK(mull->rdhi == 14);
CHECK(mull->acc == false);
CHECK(mull->set == true);
CHECK(mull->uns == true);
REQUIRE(mull->rm == 2);
REQUIRE(mull->rs == 6);
REQUIRE(mull->rdlo == 7);
REQUIRE(mull->rdhi == 14);
REQUIRE(mull->acc == false);
REQUIRE(mull->set == true);
REQUIRE(mull->uns == true);
CHECK(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
REQUIRE(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
mull->acc = true;
CHECK(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
REQUIRE(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
mull->uns = false;
mull->set = false;
CHECK(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
REQUIRE(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
}
TEST_CASE("Undefined", TAG) {
@@ -93,8 +93,8 @@ TEST_CASE("Undefined", TAG) {
uint32_t raw = 0b11100111101000101010111100010110;
Instruction instruction(raw);
CHECK(instruction.condition == Condition::AL);
CHECK(instruction.disassemble() == "UND");
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(instruction.disassemble() == "UND");
}
TEST_CASE("Single Data Swap", TAG) {
@@ -103,17 +103,17 @@ TEST_CASE("Single Data Swap", TAG) {
SingleDataSwap* swp = nullptr;
REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
CHECK(instruction.condition == Condition::GE);
REQUIRE(instruction.condition == Condition::GE);
CHECK(swp->rm == 6);
CHECK(swp->rd == 5);
CHECK(swp->rn == 9);
CHECK(swp->byte == false);
REQUIRE(swp->rm == 6);
REQUIRE(swp->rd == 5);
REQUIRE(swp->rn == 9);
REQUIRE(swp->byte == false);
CHECK(instruction.disassemble() == "SWPGE R5,R6,[R9]");
REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
swp->byte = true;
CHECK(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
}
TEST_CASE("Single Data Transfer", TAG) {
@@ -123,36 +123,36 @@ TEST_CASE("Single Data Transfer", TAG) {
Shift* shift = nullptr;
REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
CHECK(shift->rm == 6);
CHECK(shift->data.immediate == true);
CHECK(shift->data.type == ShiftType::LSL);
CHECK(shift->data.operand == 30);
CHECK(ldr->rd == 10);
CHECK(ldr->rn == 2);
CHECK(ldr->load == false);
CHECK(ldr->write == true);
CHECK(ldr->byte == false);
CHECK(ldr->up == true);
CHECK(ldr->pre == true);
REQUIRE(shift->rm == 6);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::LSL);
REQUIRE(shift->data.operand == 30);
REQUIRE(ldr->rd == 10);
REQUIRE(ldr->rn == 2);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->byte == false);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
ldr->load = true;
ldr->byte = true;
ldr->write = false;
shift->data.type = ShiftType::ROR;
CHECK(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
ldr->up = false;
ldr->pre = false;
CHECK(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
ldr->offset = static_cast<uint16_t>(9023);
CHECK(instruction.disassemble() == "LDRB R10,[R2],-#9023");
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
ldr->pre = true;
CHECK(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
}
TEST_CASE("Halfword Transfer", TAG) {
@@ -161,38 +161,38 @@ TEST_CASE("Halfword Transfer", TAG) {
HalfwordTransfer* ldr = nullptr;
REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::CC);
REQUIRE(instruction.condition == Condition::CC);
// offset is not immediate
CHECK(ldr->imm == 0);
REQUIRE(ldr->imm == 0);
// hence this offset is a register number (rm)
CHECK(ldr->offset == 6);
CHECK(ldr->half == true);
CHECK(ldr->sign == false);
CHECK(ldr->rd == 2);
CHECK(ldr->rn == 15);
CHECK(ldr->load == false);
CHECK(ldr->write == true);
CHECK(ldr->up == true);
CHECK(ldr->pre == true);
REQUIRE(ldr->offset == 6);
REQUIRE(ldr->half == true);
REQUIRE(ldr->sign == false);
REQUIRE(ldr->rd == 2);
REQUIRE(ldr->rn == 15);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
CHECK(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
ldr->pre = false;
ldr->load = true;
ldr->sign = true;
ldr->up = false;
CHECK(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
ldr->half = false;
CHECK(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
ldr->load = false;
// not a register anymore
ldr->imm = 1;
ldr->offset = 90;
CHECK(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
}
TEST_CASE("Block Data Transfer", TAG) {
@@ -201,7 +201,7 @@ TEST_CASE("Block Data Transfer", TAG) {
BlockDataTransfer* ldm = nullptr;
REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::LS);
REQUIRE(instruction.condition == Condition::LS);
{
uint16_t regs = 0;
@@ -213,23 +213,23 @@ TEST_CASE("Block Data Transfer", TAG) {
regs |= 1 << 8;
regs |= 1 << 14;
CHECK(ldm->regs == regs);
REQUIRE(ldm->regs == regs);
}
CHECK(ldm->rn == 7);
CHECK(ldm->load == true);
CHECK(ldm->write == false);
CHECK(ldm->s == true);
CHECK(ldm->up == false);
CHECK(ldm->pre == true);
REQUIRE(ldm->rn == 7);
REQUIRE(ldm->load == true);
REQUIRE(ldm->write == false);
REQUIRE(ldm->s == true);
REQUIRE(ldm->up == false);
REQUIRE(ldm->pre == true);
CHECK(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
ldm->write = true;
ldm->s = false;
ldm->up = true;
CHECK(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
ldm->regs &= ~(1 << 6);
ldm->regs &= ~(1 << 3);
@@ -237,7 +237,7 @@ TEST_CASE("Block Data Transfer", TAG) {
ldm->load = false;
ldm->pre = false;
CHECK(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
}
TEST_CASE("PSR Transfer", TAG) {
@@ -249,14 +249,14 @@ TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* mrs = nullptr;
REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::MI);
REQUIRE(instruction.condition == Condition::MI);
CHECK(mrs->type == PsrTransfer::Type::Mrs);
REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
// Operand is a register in the case of MRS (PSR -> Register)
CHECK(mrs->operand == 10);
CHECK(mrs->spsr == true);
REQUIRE(mrs->operand == 10);
REQUIRE(mrs->spsr == true);
CHECK(instruction.disassemble() == "MRSMI R10,SPSR_all");
REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
}
SECTION("MSR") {
@@ -265,14 +265,14 @@ TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* msr = nullptr;
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(msr->type == PsrTransfer::Type::Msr);
REQUIRE(msr->type == PsrTransfer::Type::Msr);
// Operand is a register in the case of MSR (Register -> PSR)
CHECK(msr->operand == 8);
CHECK(msr->spsr == false);
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
CHECK(instruction.disassemble() == "MSR CPSR_all,R8");
REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
}
SECTION("MSR_flg with register operand") {
@@ -280,14 +280,14 @@ TEST_CASE("PSR Transfer", TAG) {
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::VS);
REQUIRE(instruction.condition == Condition::VS);
CHECK(msr->type == PsrTransfer::Type::Msr_flg);
CHECK(msr->imm == 0);
CHECK(msr->operand == 8);
CHECK(msr->spsr == false);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 0);
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
CHECK(instruction.disassemble() == "MSRVS CPSR_flg,R8");
REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
}
SECTION("MSR_flg with immediate operand") {
@@ -295,102 +295,100 @@ TEST_CASE("PSR Transfer", TAG) {
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(msr->type == PsrTransfer::Type::Msr_flg);
CHECK(msr->imm == 1);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 1);
// 104 (32 bits) rotated by 2 * 7
CHECK(msr->operand == 27262976);
CHECK(msr->spsr == true);
REQUIRE(msr->operand == 27262976);
REQUIRE(msr->spsr == true);
CHECK(instruction.disassemble() == "MSR SPSR_flg,#27262976");
REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
}
}
TEST_CASE("Data Processing", TAG) {
using OpCode = DataProcessing::OpCode;
uint32_t raw = 0b11100000000111100111101101100001;
Instruction instruction(raw);
DataProcessing* alu = nullptr;
Shift* shift = nullptr;
REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
// operand 2 is a shifted register
REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
CHECK(shift->rm == 1);
CHECK(shift->data.immediate == true);
CHECK(shift->data.type == ShiftType::ROR);
CHECK(shift->data.operand == 22);
REQUIRE(shift->rm == 1);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::ROR);
REQUIRE(shift->data.operand == 22);
CHECK(alu->rd == 7);
CHECK(alu->rn == 14);
CHECK(alu->set == true);
CHECK(alu->opcode == OpCode::AND);
REQUIRE(alu->rd == 7);
REQUIRE(alu->rn == 14);
REQUIRE(alu->set == true);
REQUIRE(alu->opcode == OpCode::AND);
CHECK(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
shift->data.immediate = false;
shift->data.operand = 2;
alu->set = false;
CHECK(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
alu->operand = static_cast<uint32_t>(3300012);
CHECK(instruction.disassemble() == "AND R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
SECTION("set-only operations") {
alu->set = true;
alu->opcode = OpCode::TST;
CHECK(instruction.disassemble() == "TST R14,#3300012");
REQUIRE(instruction.disassemble() == "TST R14,#3300012");
alu->opcode = OpCode::TEQ;
CHECK(instruction.disassemble() == "TEQ R14,#3300012");
REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
alu->opcode = OpCode::CMP;
CHECK(instruction.disassemble() == "CMP R14,#3300012");
REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
alu->opcode = OpCode::CMN;
CHECK(instruction.disassemble() == "CMN R14,#3300012");
REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
}
SECTION("destination operations") {
alu->opcode = OpCode::EOR;
CHECK(instruction.disassemble() == "EOR R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
alu->opcode = OpCode::SUB;
CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::RSB;
CHECK(instruction.disassemble() == "RSB R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
alu->opcode = OpCode::SUB;
CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::ADC;
CHECK(instruction.disassemble() == "ADC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
alu->opcode = OpCode::SBC;
CHECK(instruction.disassemble() == "SBC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
alu->opcode = OpCode::RSC;
CHECK(instruction.disassemble() == "RSC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
alu->opcode = OpCode::ORR;
CHECK(instruction.disassemble() == "ORR R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
alu->opcode = OpCode::MOV;
CHECK(instruction.disassemble() == "MOV R7,#3300012");
REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
alu->opcode = OpCode::BIC;
CHECK(instruction.disassemble() == "BIC R7,R14,#3300012");
REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
alu->opcode = OpCode::MVN;
CHECK(instruction.disassemble() == "MVN R7,#3300012");
REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
}
}
@@ -400,26 +398,26 @@ TEST_CASE("Coprocessor Data Transfer", TAG) {
CoprocessorDataTransfer* ldc = nullptr;
REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::GE);
REQUIRE(instruction.condition == Condition::GE);
CHECK(ldc->offset == 70);
CHECK(ldc->cpn == 1);
CHECK(ldc->crd == 15);
CHECK(ldc->rn == 5);
CHECK(ldc->load == false);
CHECK(ldc->write == true);
CHECK(ldc->len == false);
CHECK(ldc->up == true);
CHECK(ldc->pre == true);
REQUIRE(ldc->offset == 70);
REQUIRE(ldc->cpn == 1);
REQUIRE(ldc->crd == 15);
REQUIRE(ldc->rn == 5);
REQUIRE(ldc->load == false);
REQUIRE(ldc->write == true);
REQUIRE(ldc->len == false);
REQUIRE(ldc->up == true);
REQUIRE(ldc->pre == true);
CHECK(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
ldc->load = true;
ldc->pre = false;
ldc->write = false;
ldc->len = true;
CHECK(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
}
TEST_CASE("Coprocessor Operand Operation", TAG) {
@@ -428,16 +426,16 @@ TEST_CASE("Coprocessor Operand Operation", TAG) {
CoprocessorDataOperation* cdp = nullptr;
REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(cdp->crm == 6);
CHECK(cdp->cp == 2);
CHECK(cdp->cpn == 1);
CHECK(cdp->crd == 15);
CHECK(cdp->crn == 5);
CHECK(cdp->cp_opc == 10);
REQUIRE(cdp->crm == 6);
REQUIRE(cdp->cp == 2);
REQUIRE(cdp->cpn == 1);
REQUIRE(cdp->crd == 15);
REQUIRE(cdp->crn == 5);
REQUIRE(cdp->cp_opc == 10);
CHECK(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
}
TEST_CASE("Coprocessor Register Transfer", TAG) {
@@ -447,25 +445,25 @@ TEST_CASE("Coprocessor Register Transfer", TAG) {
REQUIRE(
(mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE(instruction.condition == Condition::AL);
CHECK(mrc->crm == 6);
CHECK(mrc->cp == 2);
CHECK(mrc->cpn == 1);
CHECK(mrc->rd == 15);
CHECK(mrc->crn == 5);
CHECK(mrc->load == false);
CHECK(mrc->cp_opc == 5);
REQUIRE(mrc->crm == 6);
REQUIRE(mrc->cp == 2);
REQUIRE(mrc->cpn == 1);
REQUIRE(mrc->rd == 15);
REQUIRE(mrc->crn == 5);
REQUIRE(mrc->load == false);
REQUIRE(mrc->cp_opc == 5);
CHECK(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
}
TEST_CASE("Software Interrupt", TAG) {
uint32_t raw = 0b00001111101010101010101010101010;
Instruction instruction(raw);
CHECK(instruction.condition == Condition::EQ);
CHECK(instruction.disassemble() == "SWIEQ");
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(instruction.disassemble() == "SWIEQ");
}
#undef TAG

0
tests/cpu/cpu.cc Normal file
View File

467
tests/cpu/instruction.cc Normal file
View File

@@ -0,0 +1,467 @@
#include "cpu/arm/instruction.hh"
#include "cpu/utility.hh"
#include <catch2/catch_test_macros.hpp>
[[maybe_unused]] static constexpr auto TAG = "disassembler";
using namespace arm;
TEST_CASE("Branch and Exchange", TAG) {
uint32_t raw = 0b11000001001011111111111100011010;
Instruction instruction(raw);
BranchAndExchange* bx = nullptr;
REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GT);
REQUIRE(bx->rn == 10);
REQUIRE(instruction.disassemble() == "BXGT R10");
}
TEST_CASE("Branch", TAG) {
uint32_t raw = 0b11101011100001010111111111000011;
Instruction instruction(raw);
Branch* b = nullptr;
REQUIRE((b = std::get_if<Branch>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
// last 24 bits = 8748995
// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
// Also +8 since PC is two instructions ahead
REQUIRE(b->offset == 0xFE15FF14);
REQUIRE(b->link == true);
REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
b->link = false;
REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
}
TEST_CASE("Multiply", TAG) {
uint32_t raw = 0b00000000001110101110111110010000;
Instruction instruction(raw);
Multiply* mul = nullptr;
REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(mul->rm == 0);
REQUIRE(mul->rs == 15);
REQUIRE(mul->rn == 14);
REQUIRE(mul->rd == 10);
REQUIRE(mul->acc == true);
REQUIRE(mul->set == true);
REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
mul->acc = false;
mul->set = false;
REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
}
TEST_CASE("Multiply Long", TAG) {
uint32_t raw = 0b00010000100111100111011010010010;
Instruction instruction(raw);
MultiplyLong* mull = nullptr;
REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
REQUIRE(instruction.condition == Condition::NE);
REQUIRE(mull->rm == 2);
REQUIRE(mull->rs == 6);
REQUIRE(mull->rdlo == 7);
REQUIRE(mull->rdhi == 14);
REQUIRE(mull->acc == false);
REQUIRE(mull->set == true);
REQUIRE(mull->uns == false);
REQUIRE(instruction.disassemble() == "SMULLNES R7,R14,R2,R6");
mull->acc = true;
REQUIRE(instruction.disassemble() == "SMLALNES R7,R14,R2,R6");
mull->uns = true;
mull->set = false;
REQUIRE(instruction.disassemble() == "UMLALNE R7,R14,R2,R6");
}
TEST_CASE("Undefined", TAG) {
// notice how this is the same as single data transfer except the shift
// is now a register based shift
uint32_t raw = 0b11100111101000101010111100010110;
Instruction instruction(raw);
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(instruction.disassemble() == "UND");
}
TEST_CASE("Single Data Swap", TAG) {
uint32_t raw = 0b10100001000010010101000010010110;
Instruction instruction(raw);
SingleDataSwap* swp = nullptr;
REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GE);
REQUIRE(swp->rm == 6);
REQUIRE(swp->rd == 5);
REQUIRE(swp->rn == 9);
REQUIRE(swp->byte == false);
REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
swp->byte = true;
REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
}
TEST_CASE("Single Data Transfer", TAG) {
uint32_t raw = 0b11100111101000101010111100000110;
Instruction instruction(raw);
SingleDataTransfer* ldr = nullptr;
Shift* shift = nullptr;
REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
REQUIRE(shift->rm == 6);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::LSL);
REQUIRE(shift->data.operand == 30);
REQUIRE(ldr->rd == 10);
REQUIRE(ldr->rn == 2);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->byte == false);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
ldr->load = true;
ldr->byte = true;
ldr->write = false;
shift->data.type = ShiftType::ROR;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
ldr->up = false;
ldr->pre = false;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
ldr->offset = static_cast<uint16_t>(9023);
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
ldr->pre = true;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
}
TEST_CASE("Halfword Transfer", TAG) {
uint32_t raw = 0b00110001101011110010000010110110;
Instruction instruction(raw);
HalfwordTransfer* ldr = nullptr;
REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::CC);
// offset is not immediate
REQUIRE(ldr->imm == 0);
// hence this offset is a register number (rm)
REQUIRE(ldr->offset == 6);
REQUIRE(ldr->half == true);
REQUIRE(ldr->sign == false);
REQUIRE(ldr->rd == 2);
REQUIRE(ldr->rn == 15);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
ldr->pre = false;
ldr->load = true;
ldr->sign = true;
ldr->up = false;
REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
ldr->half = false;
REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
ldr->load = false;
// not a register anymore
ldr->imm = 1;
ldr->offset = 90;
REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
}
TEST_CASE("Block Data Transfer", TAG) {
uint32_t raw = 0b10011001010101110100000101101101;
Instruction instruction(raw);
BlockDataTransfer* ldm = nullptr;
REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::LS);
{
uint16_t regs = 0;
regs |= 1 << 0;
regs |= 1 << 2;
regs |= 1 << 3;
regs |= 1 << 5;
regs |= 1 << 6;
regs |= 1 << 8;
regs |= 1 << 14;
REQUIRE(ldm->regs == regs);
}
REQUIRE(ldm->rn == 7);
REQUIRE(ldm->load == true);
REQUIRE(ldm->write == false);
REQUIRE(ldm->s == true);
REQUIRE(ldm->up == false);
REQUIRE(ldm->pre == true);
REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
ldm->write = true;
ldm->s = false;
ldm->up = true;
REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
ldm->regs &= ~(1 << 6);
ldm->regs &= ~(1 << 3);
ldm->regs &= ~(1 << 8);
ldm->load = false;
ldm->pre = false;
REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
}
TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* msr = nullptr;
SECTION("MRS") {
uint32_t raw = 0b01000001010011111010000000000000;
Instruction instruction(raw);
PsrTransfer* mrs = nullptr;
REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::MI);
REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
// Operand is a register in the case of MRS (PSR -> Register)
REQUIRE(mrs->operand == 10);
REQUIRE(mrs->spsr == true);
REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
}
SECTION("MSR") {
uint32_t raw = 0b11100001001010011111000000001000;
Instruction instruction(raw);
PsrTransfer* msr = nullptr;
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(msr->type == PsrTransfer::Type::Msr);
// Operand is a register in the case of MSR (Register -> PSR)
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
}
SECTION("MSR_flg with register operand") {
uint32_t raw = 0b01100001001010001111000000001000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::VS);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 0);
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
}
SECTION("MSR_flg with immediate operand") {
uint32_t raw = 0b11100011011010001111011101101000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 1);
// 104 (32 bits) rotated by 2 * 7
REQUIRE(msr->operand == 27262976);
REQUIRE(msr->spsr == true);
REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
}
}
TEST_CASE("Data Processing", TAG) {
uint32_t raw = 0b11100010000111100111101101100001;
Instruction instruction(raw);
DataProcessing* alu = nullptr;
Shift* shift = nullptr;
REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
// operand 2 is a shifted register
REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
REQUIRE(shift->rm == 1);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::ROR);
REQUIRE(shift->data.operand == 22);
REQUIRE(alu->rd == 7);
REQUIRE(alu->rn == 14);
REQUIRE(alu->set == true);
REQUIRE(alu->opcode == OpCode::AND);
REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
shift->data.immediate = false;
shift->data.operand = 2;
alu->set = false;
REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
alu->operand = static_cast<uint32_t>(3300012);
REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
SECTION("set-only operations") {
alu->set = true;
alu->opcode = OpCode::TST;
REQUIRE(instruction.disassemble() == "TST R14,#3300012");
alu->opcode = OpCode::TEQ;
REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
alu->opcode = OpCode::CMP;
REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
alu->opcode = OpCode::CMN;
REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
}
SECTION("destination operations") {
alu->opcode = OpCode::EOR;
REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
alu->opcode = OpCode::SUB;
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::RSB;
REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
alu->opcode = OpCode::SUB;
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::ADC;
REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
alu->opcode = OpCode::SBC;
REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
alu->opcode = OpCode::RSC;
REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
alu->opcode = OpCode::ORR;
REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
alu->opcode = OpCode::MOV;
REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
alu->opcode = OpCode::BIC;
REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
alu->opcode = OpCode::MVN;
REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
}
}
TEST_CASE("Coprocessor Data Transfer", TAG) {
uint32_t raw = 0b10101101101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataTransfer* ldc = nullptr;
REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GE);
REQUIRE(ldc->offset == 70);
REQUIRE(ldc->cpn == 1);
REQUIRE(ldc->crd == 15);
REQUIRE(ldc->rn == 5);
REQUIRE(ldc->load == false);
REQUIRE(ldc->write == true);
REQUIRE(ldc->len == false);
REQUIRE(ldc->up == true);
REQUIRE(ldc->pre == true);
REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
ldc->load = true;
ldc->pre = false;
ldc->write = false;
ldc->len = true;
REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
}
TEST_CASE("Coprocessor Operand Operation", TAG) {
uint32_t raw = 0b11101110101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataOperation* cdp = nullptr;
REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(cdp->crm == 6);
REQUIRE(cdp->cp == 2);
REQUIRE(cdp->cpn == 1);
REQUIRE(cdp->crd == 15);
REQUIRE(cdp->crn == 5);
REQUIRE(cdp->cp_opc == 10);
REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
}
TEST_CASE("Coprocessor Register Transfer", TAG) {
uint32_t raw = 0b11101110101001011111000101010110;
Instruction instruction(raw);
CoprocessorRegisterTransfer* mrc = nullptr;
REQUIRE(
(mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(mrc->crm == 6);
REQUIRE(mrc->cp == 2);
REQUIRE(mrc->cpn == 1);
REQUIRE(mrc->rd == 15);
REQUIRE(mrc->crn == 5);
REQUIRE(mrc->load == false);
REQUIRE(mrc->cp_opc == 5);
REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
}
TEST_CASE("Software Interrupt", TAG) {
uint32_t raw = 0b00001111101010101010101010101010;
Instruction instruction(raw);
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(instruction.disassemble() == "SWIEQ");
}

8
tests/meson.build
View File

@@ -2,20 +2,18 @@ tests_deps = [
lib
]
src = include_directories('../src')
tests_sources = files()
subdir('cpu')
catch2 = dependency('catch2-with-main', version: '>=3.4.0', static: true)
catch2_tests = executable(
'matar_tests',
meson.project_name() + '_tests',
tests_sources,
dependencies: catch2,
link_with: tests_deps,
include_directories: [inc, src],
build_by_default: false,
include_directories: inc,
build_by_default: false
)
test('catch2 tests', catch2_tests)