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comeback(?)

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Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2024-06-11 22:46:48 +05:30
parent 174008f60c
commit 028c80f6cb
17 changed files with 97 additions and 129 deletions
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1
src/cpu/alu.cc
View File

@@ -1,5 +1,6 @@
#include "cpu/alu.hh"
#include "util/bits.hh"
#include <bit>
namespace matar {
uint32_t

54
src/cpu/arm/disassembler.cc
View File

@@ -1,5 +1,7 @@
#include "cpu/arm/instruction.hh"
#include "util/bits.hh"
#include <format>
#include <string>
namespace matar::arm {
std::string
@@ -9,15 +11,15 @@ Instruction::disassemble() {
return std::visit(
overloaded{
[condition](BranchAndExchange& data) {
return fmt::format("BX{} R{:d}", condition, data.rn);
return std::format("BX{} R{:d}", condition, data.rn);
},
[condition](Branch& data) {
return fmt::format(
return std::format(
"B{}{} 0x{:06X}", (data.link ? "L" : ""), condition, data.offset);
},
[condition](Multiply& data) {
if (data.acc) {
return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
return std::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
condition,
(data.set ? "S" : ""),
data.rd,
@@ -25,7 +27,7 @@ Instruction::disassemble() {
data.rs,
data.rn);
} else {
return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
return std::format("MUL{}{} R{:d},R{:d},R{:d}",
condition,
(data.set ? "S" : ""),
data.rd,
@@ -34,7 +36,7 @@ Instruction::disassemble() {
}
},
[condition](MultiplyLong& data) {
return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
return std::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
(data.uns ? 'U' : 'S'),
(data.acc ? "MLAL" : "MULL"),
condition,
@@ -46,7 +48,7 @@ Instruction::disassemble() {
},
[](Undefined) { return std::string("UND"); },
[condition](SingleDataSwap& data) {
return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
return std::format("SWP{}{} R{:d},R{:d},[R{:d}]",
condition,
(data.byte ? "B" : ""),
data.rd,
@@ -62,18 +64,18 @@ Instruction::disassemble() {
expression = "";
} else {
expression =
fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
std::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
}
} else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
// Shifts are always immediate in single data transfer
expression = fmt::format(",{}R{:d},{} #{:d}",
expression = std::format(",{}R{:d},{} #{:d}",
(data.up ? '+' : '-'),
shift->rm,
stringify(shift->data.type),
shift->data.operand);
}
return fmt::format(
return std::format(
"{}{}{}{} R{:d},[R{:d}{}]{}",
(data.load ? "LDR" : "STR"),
condition,
@@ -91,15 +93,15 @@ Instruction::disassemble() {
if (data.offset == 0) {
expression = "";
} else {
expression = fmt::format(
expression = std::format(
",{}#{:d}", (data.up ? '+' : '-'), data.offset);
}
} else {
expression =
fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
std::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
}
return fmt::format(
return std::format(
"{}{}{}{} R{:d},[R{:d}{}]{}",
(data.load ? "LDR" : "STR"),
condition,
@@ -115,12 +117,12 @@ Instruction::disassemble() {
for (uint8_t i = 0; i < 16; i++) {
if (get_bit(data.regs, i))
fmt::format_to(std::back_inserter(regs), "R{:d},", i);
std::format_to(std::back_inserter(regs), "R{:d},", i);
};
regs.pop_back();
return fmt::format("{}{}{}{} R{:d}{},{{{}}}{}",
return std::format("{}{}{}{} R{:d}{},{{{}}}{}",
(data.load ? "LDM" : "STM"),
condition,
(data.up ? 'I' : 'D'),
@@ -132,12 +134,12 @@ Instruction::disassemble() {
},
[condition](PsrTransfer& data) {
if (data.type == PsrTransfer::Type::Mrs) {
return fmt::format("MRS{} R{:d},{}",
return std::format("MRS{} R{:d},{}",
condition,
data.operand,
(data.spsr ? "SPSR_all" : "CPSR_all"));
} else {
return fmt::format(
return std::format(
"MSR{} {}_{},{}{}",
condition,
(data.spsr ? "SPSR" : "CPSR"),
@@ -153,9 +155,9 @@ Instruction::disassemble() {
if (const uint32_t* operand =
std::get_if<uint32_t>(&data.operand)) {
op_2 = fmt::format("#{:d}", *operand);
op_2 = std::format("#{:d}", *operand);
} else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
op_2 = fmt::format("R{:d},{} {}{:d}",
op_2 = std::format("R{:d},{} {}{:d}",
shift->rm,
stringify(shift->data.type),
(shift->data.immediate ? '#' : 'R'),
@@ -165,7 +167,7 @@ Instruction::disassemble() {
switch (data.opcode) {
case OpCode::MOV:
case OpCode::MVN:
return fmt::format("{}{}{} R{:d},{}",
return std::format("{}{}{} R{:d},{}",
stringify(data.opcode),
condition,
(data.set ? "S" : ""),
@@ -175,13 +177,13 @@ Instruction::disassemble() {
case OpCode::TEQ:
case OpCode::CMP:
case OpCode::CMN:
return fmt::format("{}{} R{:d},{}",
return std::format("{}{} R{:d},{}",
stringify(data.opcode),
condition,
data.rn,
op_2);
default:
return fmt::format("{}{}{} R{:d},R{:d},{}",
return std::format("{}{}{} R{:d},R{:d},{}",
stringify(data.opcode),
condition,
(data.set ? "S" : ""),
@@ -191,11 +193,11 @@ Instruction::disassemble() {
}
},
[condition](SoftwareInterrupt) {
return fmt::format("SWI{}", condition);
return std::format("SWI{}", condition);
},
[condition](CoprocessorDataTransfer& data) {
std::string expression = fmt::format(",#{:d}", data.offset);
return fmt::format(
std::string expression = std::format(",#{:d}", data.offset);
return std::format(
"{}{}{} p{:d},c{:d},[R{:d}{}]{}",
(data.load ? "LDC" : "STC"),
condition,
@@ -207,7 +209,7 @@ Instruction::disassemble() {
(data.pre ? (data.write ? "!" : "") : expression));
},
[condition](CoprocessorDataOperation& data) {
return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
return std::format("CDP{} p{},{},c{},c{},c{},{}",
condition,
data.cpn,
data.cp_opc,
@@ -217,7 +219,7 @@ Instruction::disassemble() {
data.cp);
},
[condition](CoprocessorRegisterTransfer& data) {
return fmt::format("{}{} p{},{},R{},c{},c{},{}",
return std::format("{}{} p{},{},R{},c{},c{},{}",
(data.load ? "MRC" : "MCR"),
condition,
data.cpn,

49
src/cpu/thumb/disassembler.cc
View File

@@ -1,5 +1,6 @@
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include <format>
namespace matar::thumb {
std::string
@@ -7,14 +8,14 @@ Instruction::disassemble(uint32_t pc) {
return std::visit(
overloaded{
[](MoveShiftedRegister& data) {
return fmt::format("{} R{:d},R{:d},#{:d}",
return std::format("{} R{:d},R{:d},#{:d}",
stringify(data.opcode),
data.rd,
data.rs,
data.offset);
},
[](AddSubtract& data) {
return fmt::format("{} R{:d},R{:d},{}{:d}",
return std::format("{} R{:d},R{:d},{}{:d}",
stringify(data.opcode),
data.rd,
data.rs,
@@ -22,27 +23,27 @@ Instruction::disassemble(uint32_t pc) {
data.offset);
},
[](MovCmpAddSubImmediate& data) {
return fmt::format(
return std::format(
"{} R{:d},#{:d}", stringify(data.opcode), data.rd, data.offset);
},
[](AluOperations& data) {
return fmt::format(
return std::format(
"{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
},
[](HiRegisterOperations& data) {
if (data.opcode == HiRegisterOperations::OpCode::BX) {
return fmt::format("{} R{:d}", stringify(data.opcode), data.rs);
return std::format("{} R{:d}", stringify(data.opcode), data.rs);
}
return fmt::format(
return std::format(
"{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
},
[](PcRelativeLoad& data) {
return fmt::format("LDR R{:d},[PC,#{:d}]", data.rd, data.word);
return std::format("LDR R{:d},[PC,#{:d}]", data.rd, data.word);
},
[](LoadStoreRegisterOffset& data) {
return fmt::format("{}{} R{:d},[R{:d},R{:d}]",
return std::format("{}{} R{:d},[R{:d},R{:d}]",
(data.load ? "LDR" : "STR"),
(data.byte ? "B" : ""),
data.rd,
@@ -51,11 +52,11 @@ Instruction::disassemble(uint32_t pc) {
},
[](LoadStoreSignExtendedHalfword& data) {
if (!data.s && !data.h) {
return fmt::format(
return std::format(
"STRH R{:d},[R{:d},R{:d}]", data.rd, data.rb, data.ro);
}
return fmt::format("{}{} R{:d},[R{:d},R{:d}]",
return std::format("{}{} R{:d},[R{:d},R{:d}]",
(data.s ? "LDS" : "LDR"),
(data.h ? 'H' : 'B'),
data.rd,
@@ -63,7 +64,7 @@ Instruction::disassemble(uint32_t pc) {
data.ro);
},
[](LoadStoreImmediateOffset& data) {
return fmt::format("{}{} R{:d},[R{:d},#{:d}]",
return std::format("{}{} R{:d},[R{:d},#{:d}]",
(data.load ? "LDR" : "STR"),
(data.byte ? "B" : ""),
data.rd,
@@ -71,33 +72,33 @@ Instruction::disassemble(uint32_t pc) {
data.offset);
},
[](LoadStoreHalfword& data) {
return fmt::format("{} R{:d},[R{:d},#{:d}]",
return std::format("{} R{:d},[R{:d},#{:d}]",
(data.load ? "LDRH" : "STRH"),
data.rd,
data.rb,
data.offset);
},
[](SpRelativeLoad& data) {
return fmt::format("{} R{:d},[SP,#{:d}]",
return std::format("{} R{:d},[SP,#{:d}]",
(data.load ? "LDR" : "STR"),
data.rd,
data.word);
},
[](LoadAddress& data) {
return fmt::format("ADD R{:d},{},#{:d}",
return std::format("ADD R{:d},{},#{:d}",
data.rd,
(data.sp ? "SP" : "PC"),
data.word);
},
[](AddOffsetStackPointer& data) {
return fmt::format("ADD SP,#{:d}", data.word);
return std::format("ADD SP,#{:d}", data.word);
},
[](PushPopRegister& data) {
std::string regs;
for (uint8_t i = 0; i < 16; i++) {
if (get_bit(data.regs, i))
fmt::format_to(std::back_inserter(regs), "R{:d},", i);
std::format_to(std::back_inserter(regs), "R{:d},", i);
};
if (data.load) {
@@ -106,14 +107,14 @@ Instruction::disassemble(uint32_t pc) {
else
regs.pop_back();
return fmt::format("POP {{{}}}", regs);
return std::format("POP {{{}}}", regs);
} else {
if (data.pclr)
regs += "LR";
else
regs.pop_back();
return fmt::format("PUSH {{{}}}", regs);
return std::format("PUSH {{{}}}", regs);
}
},
[](MultipleLoad& data) {
@@ -121,31 +122,31 @@ Instruction::disassemble(uint32_t pc) {
for (uint8_t i = 0; i < 16; i++) {
if (get_bit(data.regs, i))
fmt::format_to(std::back_inserter(regs), "R{:d},", i);
std::format_to(std::back_inserter(regs), "R{:d},", i);
};
regs.pop_back();
return fmt::format(
return std::format(
"{} R{}!,{{{}}}", (data.load ? "LDMIA" : "STMIA"), data.rb, regs);
},
[](SoftwareInterrupt& data) {
return fmt::format("SWI {:d}", data.vector);
return std::format("SWI {:d}", data.vector);
},
[pc](ConditionalBranch& data) {
return fmt::format(
return std::format(
"B{} #{:d}",
stringify(data.condition),
static_cast<int32_t>(data.offset + pc + 2 * INSTRUCTION_SIZE));
},
[pc](UnconditionalBranch& data) {
return fmt::format(
return std::format(
"B #{:d}",
static_cast<int32_t>(data.offset + pc + 2 * INSTRUCTION_SIZE));
},
[](LongBranchWithLink& data) {
// duh this manual be empty for H = 0
return fmt::format(
return std::format(
"BL{} #{:d}", (data.high ? "H" : ""), data.offset);
},
[](auto) { return std::string("unknown instruction"); } },

7
src/meson.build
View File

@@ -8,12 +8,6 @@ subdir('cpu')
lib_cpp_args = []
fmt = dependency('fmt', version : '>=10.1.0', static: true)
if not fmt.found()
fmt = dependency('fmt', version : '>=10.1.0', static: false)
lib_cpp_args += '-DFMT_HEADER_ONLY'
endif
if get_option('disassembler')
lib_cpp_args += '-DDISASSEMBLER'
endif
@@ -21,7 +15,6 @@ endif
lib = library(
meson.project_name(),
lib_sources,
dependencies: [fmt],
include_directories: inc,
install: true,
cpp_args: lib_cpp_args

2
src/util/bits.hh
View File

@@ -35,6 +35,6 @@ inline Int
bit_range(Int num, size_t start, size_t end) {
// NOTE: we do not require -1 if it is a signed integral
Int left =
std::numeric_limits<Int>::digits - (std::is_unsigned<Int>::value) - end;
std::numeric_limits<Int>::digits - (!std::is_signed<Int>::value) - end;
return static_cast<Int>(num << left) >> (left + start);
}

4
src/util/crypto.hh
View File

@@ -2,7 +2,7 @@
#include <array>
#include <bit>
#include <fmt/core.h>
#include <format>
#include <string>
// Why I wrote this myself? I do not know
@@ -110,7 +110,7 @@ sha256(std::array<uint8_t, N>& data) {
for (j = 0; j < 8; j++)
for (i = 0; i < 4; i++)
fmt::format_to(std::back_inserter(string),
std::format_to(std::back_inserter(string),
"{:02x}",
((h[j] >> (24 - i * 8)) & 0xFF));

17
src/util/log.hh
View File

@@ -1,8 +1,7 @@
#pragma once
#include "util/loglevel.hh"
#include <fmt/ostream.h>
#include <iostream>
#include <print>
namespace logging {
namespace ansi {
@@ -14,7 +13,7 @@ static constexpr auto BOLD = "\033[1m";
static constexpr auto RESET = "\033[0m";
}
using fmt::print;
using std::print;
class Logger {
using LogLevel = matar::LogLevel;
@@ -27,12 +26,12 @@ class Logger {
}
template<typename... Args>
void log(const fmt::format_string<Args...>& fmt, Args&&... args) {
fmt::println(stream, fmt, std::forward<Args>(args)...);
void log(const std::format_string<Args...>& fmt, Args&&... args) {
std::println(stream, fmt, std::forward<Args>(args)...);
}
template<typename... Args>
void debug(const fmt::format_string<Args...>& fmt, Args&&... args) {
void debug(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Debug)) {
print(stream, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
log(fmt, std::forward<Args>(args)...);
@@ -41,7 +40,7 @@ class Logger {
}
template<typename... Args>
void info(const fmt::format_string<Args...>& fmt, Args&&... args) {
void info(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Info)) {
print(stream, "{}[INFO] ", ansi::WHITE);
log(fmt, std::forward<Args>(args)...);
@@ -50,7 +49,7 @@ class Logger {
}
template<typename... Args>
void warn(const fmt::format_string<Args...>& fmt, Args&&... args) {
void warn(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Warn)) {
print(stream, "{}[WARN] ", ansi::YELLOW);
log(fmt, std::forward<Args>(args)...);
@@ -59,7 +58,7 @@ class Logger {
}
template<typename... Args>
void error(const fmt::format_string<Args...>& fmt, Args&&... args) {
void error(const std::format_string<Args...>& fmt, Args&&... args) {
if (level & static_cast<uint8_t>(LogLevel::Error)) {
print(stream, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
log(fmt, std::forward<Args>(args)...);