Amneesh Singh
1c96f418eb
So, I ended up moving exec methods from Instruction to Cpu for encapsulating cycle emulation, and this has caused me lots of pain since I had to rewrite a shit ton of tests which are not even useful or comprehensible, i do no know why i put myself through this Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
468 lines
12 KiB
C++
468 lines
12 KiB
C++
#include "cpu/thumb/instruction.hh"
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#include <catch2/catch_test_macros.hpp>
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#define TAG "[thumb][disassembly]"
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using namespace matar;
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using namespace thumb;
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TEST_CASE("Move Shifted Register", TAG) {
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uint16_t raw = 0b0001001101100011;
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Instruction instruction(raw);
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MoveShiftedRegister* lsl = nullptr;
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REQUIRE((lsl = std::get_if<MoveShiftedRegister>(&instruction.data)));
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CHECK(lsl->rd == 3);
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CHECK(lsl->rs == 4);
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CHECK(lsl->offset == 13);
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CHECK(lsl->opcode == ShiftType::ASR);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "ASR R3,R4,#13");
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lsl->opcode = ShiftType::LSR;
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CHECK(instruction.disassemble() == "LSR R3,R4,#13");
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lsl->opcode = ShiftType::LSL;
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CHECK(instruction.disassemble() == "LSL R3,R4,#13");
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#endif
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}
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TEST_CASE("Add/Subtract", TAG) {
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uint16_t raw = 0b0001111101001111;
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Instruction instruction(raw);
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AddSubtract* add = nullptr;
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REQUIRE((add = std::get_if<AddSubtract>(&instruction.data)));
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CHECK(add->rd == 7);
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CHECK(add->rs == 1);
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CHECK(add->offset == 5);
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CHECK(add->opcode == AddSubtract::OpCode::SUB);
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CHECK(add->imm == true);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "SUB R7,R1,#5");
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add->imm = false;
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CHECK(instruction.disassemble() == "SUB R7,R1,R5");
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add->opcode = AddSubtract::OpCode::ADD;
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CHECK(instruction.disassemble() == "ADD R7,R1,R5");
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#endif
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}
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TEST_CASE("Move/Compare/Add/Subtract Immediate", TAG) {
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uint16_t raw = 0b0010111001011011;
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Instruction instruction(raw);
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MovCmpAddSubImmediate* mov = nullptr;
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REQUIRE((mov = std::get_if<MovCmpAddSubImmediate>(&instruction.data)));
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CHECK(mov->offset == 91);
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CHECK(mov->rd == 6);
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CHECK(mov->opcode == MovCmpAddSubImmediate::OpCode::CMP);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "CMP R6,#91");
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mov->opcode = MovCmpAddSubImmediate::OpCode::ADD;
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CHECK(instruction.disassemble() == "ADD R6,#91");
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mov->opcode = MovCmpAddSubImmediate::OpCode::SUB;
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CHECK(instruction.disassemble() == "SUB R6,#91");
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mov->opcode = MovCmpAddSubImmediate::OpCode::MOV;
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CHECK(instruction.disassemble() == "MOV R6,#91");
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#endif
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}
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TEST_CASE("ALU Operations", TAG) {
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uint16_t raw = 0b0100000110011111;
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Instruction instruction(raw);
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AluOperations* alu = nullptr;
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REQUIRE((alu = std::get_if<AluOperations>(&instruction.data)));
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CHECK(alu->rd == 7);
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CHECK(alu->rs == 3);
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CHECK(alu->opcode == AluOperations::OpCode::SBC);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "SBC R7,R3");
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#define OPCODE(op) \
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alu->opcode = AluOperations::OpCode::op; \
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CHECK(instruction.disassemble() == #op " R7,R3");
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OPCODE(AND)
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OPCODE(EOR)
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OPCODE(LSL)
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OPCODE(LSR)
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OPCODE(ASR)
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OPCODE(ADC)
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OPCODE(SBC)
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OPCODE(ROR)
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OPCODE(TST)
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OPCODE(NEG)
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OPCODE(CMP)
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OPCODE(CMN)
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OPCODE(ORR)
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OPCODE(MUL)
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OPCODE(BIC)
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OPCODE(MVN)
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#undef OPCODE
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#endif
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}
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TEST_CASE("Hi Register Operations/Branch Exchange", TAG) {
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HiRegisterOperations* hi = nullptr;
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uint16_t raw = 0b0100011000011010;
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SECTION("both lo") {
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Instruction instruction(raw);
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REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
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CHECK(hi->rd == 2);
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CHECK(hi->rs == 3);
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}
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SECTION("hi rd") {
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raw |= 1 << 7;
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Instruction instruction(raw);
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REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
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CHECK(hi->rd == 10);
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CHECK(hi->rs == 3);
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}
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SECTION("hi rs") {
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raw |= 1 << 6;
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Instruction instruction(raw);
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REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
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CHECK(hi->rd == 2);
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CHECK(hi->rs == 11);
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}
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if (hi)
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CHECK(hi->opcode == HiRegisterOperations::OpCode::MOV);
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SECTION("both hi") {
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raw |= 1 << 6;
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raw |= 1 << 7;
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Instruction instruction(raw);
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REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
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CHECK(hi->rd == 10);
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CHECK(hi->rs == 11);
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CHECK(hi->opcode == HiRegisterOperations::OpCode::MOV);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "MOV R10,R11");
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hi->opcode = HiRegisterOperations::OpCode::ADD;
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CHECK(instruction.disassemble() == "ADD R10,R11");
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hi->opcode = HiRegisterOperations::OpCode::CMP;
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CHECK(instruction.disassemble() == "CMP R10,R11");
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hi->opcode = HiRegisterOperations::OpCode::BX;
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CHECK(instruction.disassemble() == "BX R11");
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#endif
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}
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}
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TEST_CASE("PC Relative Load", TAG) {
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uint16_t raw = 0b0100101011100110;
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Instruction instruction(raw);
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PcRelativeLoad* ldr = nullptr;
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REQUIRE((ldr = std::get_if<PcRelativeLoad>(&instruction.data)));
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// 230 << 2
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CHECK(ldr->word == 920);
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CHECK(ldr->rd == 2);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "LDR R2,[PC,#920]");
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#endif
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}
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TEST_CASE("Load/Store with Register Offset", TAG) {
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uint16_t raw = 0b0101000110011101;
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Instruction instruction(raw);
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LoadStoreRegisterOffset* ldr = nullptr;
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REQUIRE((ldr = std::get_if<LoadStoreRegisterOffset>(&instruction.data)));
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CHECK(ldr->rd == 5);
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CHECK(ldr->rb == 3);
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CHECK(ldr->ro == 6);
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CHECK(ldr->byte == false);
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CHECK(ldr->load == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "STR R5,[R3,R6]");
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ldr->byte = true;
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CHECK(instruction.disassemble() == "STRB R5,[R3,R6]");
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ldr->load = true;
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CHECK(instruction.disassemble() == "LDRB R5,[R3,R6]");
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ldr->byte = false;
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CHECK(instruction.disassemble() == "LDR R5,[R3,R6]");
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#endif
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}
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TEST_CASE("Load/Store Sign-Extended Byte/Halfword", TAG) {
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uint16_t raw = 0b0101001110011101;
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Instruction instruction(raw);
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LoadStoreSignExtendedHalfword* ldr = nullptr;
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REQUIRE(
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(ldr = std::get_if<LoadStoreSignExtendedHalfword>(&instruction.data)));
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CHECK(ldr->rd == 5);
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CHECK(ldr->rb == 3);
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CHECK(ldr->ro == 6);
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CHECK(ldr->s == false);
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CHECK(ldr->h == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "STRH R5,[R3,R6]");
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ldr->h = true;
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CHECK(instruction.disassemble() == "LDRH R5,[R3,R6]");
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ldr->s = true;
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CHECK(instruction.disassemble() == "LDSH R5,[R3,R6]");
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ldr->h = false;
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CHECK(instruction.disassemble() == "LDSB R5,[R3,R6]");
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#endif
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}
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TEST_CASE("Load/Store with Immediate Offset", TAG) {
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uint16_t raw = 0b0110010110011101;
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Instruction instruction(raw);
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LoadStoreImmediateOffset* ldr = nullptr;
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REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
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CHECK(ldr->rd == 5);
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CHECK(ldr->rb == 3);
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// 22 << 4 when byte == false
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CHECK(ldr->offset == 88);
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CHECK(ldr->byte == false);
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CHECK(ldr->load == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "STR R5,[R3,#88]");
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ldr->load = true;
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CHECK(instruction.disassemble() == "LDR R5,[R3,#88]");
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#endif
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// byte
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raw = 0b0111010110011101;
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instruction = Instruction(raw);
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INFO(instruction.data.index());
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REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
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CHECK(ldr->byte == true);
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CHECK(ldr->offset == 22);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "STRB R5,[R3,#22]");
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ldr->load = true;
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CHECK(instruction.disassemble() == "LDRB R5,[R3,#22]");
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#endif
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}
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TEST_CASE("Load/Store Halfword", TAG) {
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uint16_t raw = 0b1000011010011101;
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Instruction instruction(raw);
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LoadStoreHalfword* ldr = nullptr;
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REQUIRE((ldr = std::get_if<LoadStoreHalfword>(&instruction.data)));
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CHECK(ldr->rd == 5);
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CHECK(ldr->rb == 3);
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// 26 << 1
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CHECK(ldr->offset == 52);
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CHECK(ldr->load == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "STRH R5,[R3,#52]");
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ldr->load = true;
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CHECK(instruction.disassemble() == "LDRH R5,[R3,#52]");
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#endif
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}
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TEST_CASE("SP-Relative Load/Store", TAG) {
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uint16_t raw = 0b1001010010011101;
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Instruction instruction(raw);
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SpRelativeLoad* ldr = nullptr;
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REQUIRE((ldr = std::get_if<SpRelativeLoad>(&instruction.data)));
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CHECK(ldr->rd == 4);
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// 157 << 2
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CHECK(ldr->word == 628);
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CHECK(ldr->load == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "STR R4,[SP,#628]");
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ldr->load = true;
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CHECK(instruction.disassemble() == "LDR R4,[SP,#628]");
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#endif
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}
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TEST_CASE("Load Adress", TAG) {
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uint16_t raw = 0b1010000110001111;
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Instruction instruction(raw);
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LoadAddress* add = nullptr;
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REQUIRE((add = std::get_if<LoadAddress>(&instruction.data)));
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// 143 << 2
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CHECK(add->word == 572);
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CHECK(add->rd == 1);
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CHECK(add->sp == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "ADD R1,PC,#572");
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add->sp = true;
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CHECK(instruction.disassemble() == "ADD R1,SP,#572");
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#endif
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}
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TEST_CASE("Add Offset to Stack Pointer", TAG) {
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uint16_t raw = 0b1011000000100101;
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Instruction instruction(raw);
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AddOffsetStackPointer* add = nullptr;
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REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
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// 37 << 2
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CHECK(add->word == 148);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "ADD SP,#148");
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#endif
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raw = 0b1011000010100101;
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instruction = Instruction(raw);
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REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
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CHECK(add->word == -148);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "ADD SP,#-148");
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#endif
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}
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TEST_CASE("Push/Pop Registers", TAG) {
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uint16_t raw = 0b1011010000110101;
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Instruction instruction(raw);
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PushPopRegister* push = nullptr;
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REQUIRE((push = std::get_if<PushPopRegister>(&instruction.data)));
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CHECK(push->regs == 53);
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CHECK(push->pclr == false);
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CHECK(push->load == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "PUSH {R0,R2,R4,R5}");
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push->pclr = true;
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CHECK(instruction.disassemble() == "PUSH {R0,R2,R4,R5,LR}");
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push->load = true;
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CHECK(instruction.disassemble() == "POP {R0,R2,R4,R5,PC}");
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push->pclr = false;
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CHECK(instruction.disassemble() == "POP {R0,R2,R4,R5}");
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#endif
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}
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TEST_CASE("Multiple Load/Store", TAG) {
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uint16_t raw = 0b1100011001100101;
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Instruction instruction(raw);
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MultipleLoad* ldm = nullptr;
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REQUIRE((ldm = std::get_if<MultipleLoad>(&instruction.data)));
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CHECK(ldm->regs == 101);
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CHECK(ldm->rb == 6);
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CHECK(ldm->load == false);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "STMIA R6!,{R0,R2,R5,R6}");
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ldm->load = true;
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CHECK(instruction.disassemble() == "LDMIA R6!,{R0,R2,R5,R6}");
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#endif
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}
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TEST_CASE("Conditional Branch", TAG) {
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uint16_t raw = 0b1101100110110100;
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Instruction instruction(raw);
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ConditionalBranch* b = nullptr;
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REQUIRE((b = std::get_if<ConditionalBranch>(&instruction.data)));
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// (-76 << 1)
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CHECK(b->offset == -152);
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CHECK(b->condition == Condition::LS);
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#ifdef DISASSEMBLER
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// take prefetch into account
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// offset + 4 = -152 + 4
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CHECK(instruction.disassemble() == "BLS #-148");
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#endif
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}
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TEST_CASE("SoftwareInterrupt") {
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uint16_t raw = 0b1101111100110011;
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Instruction instruction(raw);
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SoftwareInterrupt* swi = nullptr;
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REQUIRE((swi = std::get_if<SoftwareInterrupt>(&instruction.data)));
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "SWI 51");
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#endif
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}
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TEST_CASE("Unconditional Branch") {
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uint16_t raw = 0b1110011100110011;
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Instruction instruction(raw);
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UnconditionalBranch* b = nullptr;
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REQUIRE((b = std::get_if<UnconditionalBranch>(&instruction.data)));
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// (2147483443 << 1)
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REQUIRE(b->offset == -410);
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#ifdef DISASSEMBLER
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// take prefetch into account
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// offset + 4 = -410 + 4
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CHECK(instruction.disassemble() == "B #-406");
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#endif
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}
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TEST_CASE("Long Branch with link") {
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uint16_t raw = 0b1111110011101100;
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Instruction instruction(raw);
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LongBranchWithLink* bl = nullptr;
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REQUIRE((bl = std::get_if<LongBranchWithLink>(&instruction.data)));
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// 1260 << 1
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CHECK(bl->offset == 1260);
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CHECK(bl->low == true);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "BL #1260");
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bl->low = false;
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CHECK(instruction.disassemble() == "BLH #1260");
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#endif
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}
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#undef TAG
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