Amneesh Singh
1c96f418eb
So, I ended up moving exec methods from Instruction to Cpu for encapsulating cycle emulation, and this has caused me lots of pain since I had to rewrite a shit ton of tests which are not even useful or comprehensible, i do no know why i put myself through this Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
1140 lines
29 KiB
C++
1140 lines
29 KiB
C++
#include "cpu/cpu-fixture.hh"
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#include "cpu/thumb/instruction.hh"
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#include <catch2/catch_test_macros.hpp>
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using namespace matar;
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#define TAG "[thumb][execution]"
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using namespace thumb;
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TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
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InstructionData data = MoveShiftedRegister{
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.rd = 3, .rs = 5, .offset = 15, .opcode = ShiftType::LSL
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};
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MoveShiftedRegister* move = std::get_if<MoveShiftedRegister>(&data);
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SECTION("LSL") {
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setr(3, 0);
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setr(5, 6687);
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// LSL
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(3) == 219119616);
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setr(5, 0);
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// zero
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exec(data);
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CHECK(getr(3) == 0);
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CHECK(psr().z());
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}
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SECTION("LSR") {
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move->opcode = ShiftType::LSR;
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setr(5, -1827489745);
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// LSR
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(3) == 75301);
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CHECK(!psr().n());
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setr(5, 4444);
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// zero flag
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exec(data);
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CHECK(getr(3) == 0);
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CHECK(psr().z());
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}
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SECTION("ASR") {
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setr(5, -1827489745);
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move->opcode = ShiftType::ASR;
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// ASR
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(psr().n());
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CHECK(getr(3) == 4294911525);
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setr(5, 500);
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// zero flag
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exec(data);
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CHECK(getr(3) == 0);
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CHECK(psr().z());
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Add/Subtract", TAG) {
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InstructionData data = AddSubtract{ .rd = 5,
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.rs = 2,
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.offset = 7,
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.opcode = AddSubtract::OpCode::ADD,
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.imm = false };
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AddSubtract* add = std::get_if<AddSubtract>(&data);
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setr(2, 378427891);
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setr(7, -666666);
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SECTION("ADD") {
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// register
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(5) == 377761225);
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add->imm = true;
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setr(2, (1u << 31) - 1);
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// immediate and overflow
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exec(data);
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CHECK(getr(5) == 2147483654);
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CHECK(psr().v());
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setr(2, -7);
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// zero
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exec(data);
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CHECK(getr(5) == 0);
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CHECK(psr().z());
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}
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add->imm = true;
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SECTION("SUB") {
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add->opcode = AddSubtract::OpCode::SUB;
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setr(2, -((1u << 31) - 1));
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add->offset = 4;
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(5) == 2147483645);
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CHECK(psr().v());
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setr(2, ~0u);
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add->offset = -4;
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// carry
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exec(data);
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CHECK(getr(5) == 3);
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CHECK(psr().c());
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setr(2, 0);
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add->offset = 0;
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// zero
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exec(data);
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CHECK(getr(5) == 0);
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CHECK(psr().z());
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
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InstructionData data = MovCmpAddSubImmediate{
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.offset = 251, .rd = 5, .opcode = MovCmpAddSubImmediate::OpCode::MOV
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};
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MovCmpAddSubImmediate* move = std::get_if<MovCmpAddSubImmediate>(&data);
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SECTION("MOV") {
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(5) == 251);
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move->offset = 0;
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// zero
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exec(data);
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CHECK(getr(5) == 0);
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CHECK(psr().z());
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}
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SECTION("CMP") {
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setr(5, 251);
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move->opcode = MovCmpAddSubImmediate::OpCode::CMP;
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CHECK(!psr().z());
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(5) == 251);
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CHECK(psr().z());
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// overflow
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setr(5, -((1u << 31) - 1));
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CHECK(!psr().v());
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exec(data);
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CHECK(getr(5) == 2147483649);
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CHECK(psr().v());
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}
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SECTION("ADD") {
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move->opcode = MovCmpAddSubImmediate::OpCode::ADD;
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setr(5, (1u << 31) - 1);
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// immediate and overflow
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(5) == 2147483898);
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CHECK(psr().v());
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setr(5, -251);
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// zero
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exec(data);
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CHECK(getr(5) == 0);
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CHECK(psr().z());
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}
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SECTION("SUB") {
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// same as CMP but loaded
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setr(5, 251);
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move->opcode = MovCmpAddSubImmediate::OpCode::SUB;
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CHECK(!psr().z());
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(5) == 0);
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CHECK(psr().z());
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// overflow
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setr(5, -((1u << 31) - 1));
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CHECK(!psr().v());
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exec(data);
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CHECK(getr(5) == 2147483398);
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CHECK(psr().v());
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}
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}
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TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
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InstructionData data =
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AluOperations{ .rd = 1, .rs = 3, .opcode = AluOperations::OpCode::AND };
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AluOperations* alu = std::get_if<AluOperations>(&data);
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setr(1, 328940001);
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setr(3, -991);
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SECTION("AND") {
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uint32_t cycles = bus->get_cycles();
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// 328940001 & -991
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(1) == 328939553);
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CHECK(!psr().n());
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setr(3, 0);
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CHECK(!psr().z());
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("EOR") {
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alu->opcode = AluOperations::OpCode::EOR;
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// 328940001 ^ -991
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exec(data);
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CHECK(getr(1) == 3966027200);
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CHECK(psr().n());
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setr(3, 3966027200);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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CHECK(!psr().n());
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}
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SECTION("LSL") {
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setr(3, 3);
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alu->opcode = AluOperations::OpCode::LSL;
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uint32_t cycles = bus->get_cycles();
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// 328940001 << 3
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exec(data);
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CHECK(bus->get_cycles() == cycles + 2); // 1S + 1I (shift)
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CHECK(getr(1) == 2631520008);
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CHECK(psr().n());
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setr(1, 0);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("LSR") {
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alu->opcode = AluOperations::OpCode::LSR;
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setr(3, 991);
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// 328940001 >> 991
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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setr(1, -83885328);
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setr(3, 5);
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// -83885328 >> 5
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exec(data);
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CHECK(getr(1) == 131596311);
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CHECK(!psr().z());
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CHECK(!psr().n());
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}
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SECTION("ASR") {
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alu->opcode = AluOperations::OpCode::ASR;
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setr(3, 991);
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// 328940001 >> 991
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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setr(1, -83885328);
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setr(3, 5);
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// -83885328 >> 5
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exec(data);
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CHECK(getr(1) == 4292345879);
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CHECK(!psr().z());
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CHECK(psr().n());
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}
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SECTION("ADC") {
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alu->opcode = AluOperations::OpCode::ADC;
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setr(3, (1u << 31) - 1);
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Psr cpsr = psr();
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cpsr.set_c(true);
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set_psr(cpsr);
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// 2147483647 + 328940001 + 1
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exec(data);
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CHECK(getr(1) == 2476423649);
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CHECK(psr().v());
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CHECK(psr().n());
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CHECK(!psr().c());
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setr(3, -328940001);
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setr(1, 328940001);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("SBC") {
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alu->opcode = AluOperations::OpCode::SBC;
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setr(3, -((1u << 31) - 1));
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Psr cpsr = psr();
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cpsr.set_c(false);
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set_psr(cpsr);
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// 328940001 - -2147483647 - 1
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exec(data);
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CHECK(getr(1) == 2476423647);
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CHECK(psr().v());
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CHECK(psr().n());
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CHECK(!psr().c());
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setr(1, -34892);
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setr(3, -34893);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("ROR") {
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setr(3, 993);
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alu->opcode = AluOperations::OpCode::ROR;
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// 328940001 ROR 993
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exec(data);
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CHECK(getr(1) == 2311953648);
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CHECK(psr().n());
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CHECK(psr().c());
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setr(1, 0);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("TST") {
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alu->opcode = AluOperations::OpCode::TST;
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// 328940001 & -991
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exec(data);
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// no change
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CHECK(getr(1) == 328940001);
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setr(3, 0);
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CHECK(!psr().z());
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// zero
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exec(data);
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CHECK(getr(1) == 328940001);
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CHECK(psr().z());
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}
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SECTION("NEG") {
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alu->opcode = AluOperations::OpCode::NEG;
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// -(-991)
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exec(data);
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CHECK(getr(1) == 991);
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setr(3, 0);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("CMP") {
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alu->opcode = AluOperations::OpCode::CMP;
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setr(3, -((1u << 31) - 1));
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// 328940001 - -2147483647
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exec(data);
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// no change
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CHECK(getr(1) == 328940001);
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CHECK(psr().v());
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CHECK(psr().n());
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CHECK(!psr().c());
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setr(1, -34892);
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setr(3, -34892);
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// zero
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exec(data);
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// no change (-34892)
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CHECK(getr(1) == 4294932404);
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CHECK(psr().z());
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}
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SECTION("CMN") {
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alu->opcode = AluOperations::OpCode::CMN;
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setr(3, (1u << 31) - 1);
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// 2147483647 + 328940001
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exec(data);
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CHECK(getr(1) == 328940001);
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CHECK(psr().v());
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CHECK(psr().n());
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CHECK(!psr().c());
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setr(3, -328940001);
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setr(1, 328940001);
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// zero
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exec(data);
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CHECK(getr(1) == 328940001);
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CHECK(psr().z());
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}
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SECTION("ORR") {
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alu->opcode = AluOperations::OpCode::ORR;
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// 328940001 | -991
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exec(data);
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CHECK(getr(1) == 4294966753);
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CHECK(psr().n());
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setr(1, 0);
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setr(3, 0);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("MUL") {
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alu->opcode = AluOperations::OpCode::MUL;
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uint32_t cycles = bus->get_cycles();
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// 328940001 * -991 (lower 32 bits) (-325979540991 & 0xFFFFFFFF)
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exec(data);
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CHECK(bus->get_cycles() == cycles + 3); // S + mI (m = 2 for -991)
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CHECK(getr(1) == 437973505);
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setr(3, 0);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("BIC") {
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alu->opcode = AluOperations::OpCode::BIC;
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// 328940001 & ~ -991
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exec(data);
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CHECK(getr(1) == 448);
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CHECK(!psr().n());
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setr(3, ~0u);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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SECTION("MVN") {
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alu->opcode = AluOperations::OpCode::MVN;
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//~ -991
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exec(data);
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CHECK(getr(1) == 990);
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CHECK(!psr().n());
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setr(3, 24358);
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// negative
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exec(data);
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CHECK(getr(1) == 4294942937);
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CHECK(psr().n());
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setr(3, ~0u);
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// zero
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exec(data);
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CHECK(getr(1) == 0);
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CHECK(psr().z());
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
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InstructionData data = HiRegisterOperations{
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.rd = 5, .rs = 15, .opcode = HiRegisterOperations::OpCode::ADD
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};
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HiRegisterOperations* hi = std::get_if<HiRegisterOperations>(&data);
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setr(15, 3452948948);
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setr(5, 958656720);
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SECTION("ADD") {
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uint32_t cycles = bus->get_cycles();
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exec(data);
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CHECK(bus->get_cycles() == cycles + 1); // 1S
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CHECK(getr(5) == 116638372);
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// hi + hi
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hi->rd = 14;
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hi->rs = 15;
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setr(14, 42589);
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exec(data);
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CHECK(getr(14) == 3452991537);
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}
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SECTION("CMP") {
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hi->opcode = HiRegisterOperations::OpCode::CMP;
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exec(data);
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// no change
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CHECK(getr(5) == 958656720);
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CHECK(!psr().n());
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CHECK(!psr().c());
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CHECK(!psr().v());
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CHECK(!psr().z());
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setr(15, 958656720);
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// zero
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exec(data);
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// no change
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CHECK(getr(5) == 958656720);
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CHECK(psr().z());
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}
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SECTION("MOV") {
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hi->opcode = HiRegisterOperations::OpCode::MOV;
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exec(data);
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CHECK(getr(5) == 3452948948);
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}
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SECTION("BX") {
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hi->opcode = HiRegisterOperations::OpCode::BX;
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hi->rs = 10;
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SECTION("Arm") {
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setr(10, 2189988);
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|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // 2S + N cycles
|
|
|
|
// +4 for pipeline flush
|
|
CHECK(getr(15) == 2189988 + 4);
|
|
// switched to arm
|
|
CHECK(psr().state() == State::Arm);
|
|
}
|
|
|
|
SECTION("Thumb") {
|
|
setr(10, 2189989);
|
|
exec(data);
|
|
|
|
// +4 for pipeline flush
|
|
CHECK(getr(15) == 2189988 + 4);
|
|
|
|
// switched to thumb
|
|
CHECK(psr().state() == State::Thumb);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "PC Relative Load", TAG) {
|
|
InstructionData data = PcRelativeLoad{ .word = 0x578, .rd = 0 };
|
|
|
|
setr(15, 0x3003FD5);
|
|
// resetting bit 0 for 0x3003FD5, we get 0x3003FD4
|
|
// 0x3003FD4 + 0x578
|
|
bus->write_word(0x300454C, 489753492);
|
|
|
|
CHECK(getr(0) == 0);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
|
|
CHECK(getr(0) == 489753492);
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Load/Store with Register Offset", TAG) {
|
|
InstructionData data = LoadStoreRegisterOffset{
|
|
.rd = 3, .rb = 0, .ro = 7, .byte = false, .load = false
|
|
};
|
|
LoadStoreRegisterOffset* load = std::get_if<LoadStoreRegisterOffset>(&data);
|
|
|
|
setr(7, 0x3003000);
|
|
setr(0, 0x332);
|
|
setr(3, 389524259);
|
|
|
|
SECTION("store") {
|
|
// 0x3003000 + 0x332
|
|
CHECK(bus->read_word(0x3003332) == 0);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
|
|
|
|
CHECK(bus->read_word(0x3003332) == 389524259);
|
|
|
|
// byte
|
|
load->byte = true;
|
|
bus->write_word(0x3003332, 0);
|
|
exec(data);
|
|
CHECK(bus->read_word(0x3003332) == 35);
|
|
}
|
|
|
|
SECTION("load") {
|
|
load->load = true;
|
|
bus->write_word(0x3003332, 11123489);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
|
|
CHECK(getr(3) == 11123489);
|
|
|
|
// byte
|
|
load->byte = true;
|
|
exec(data);
|
|
CHECK(getr(3) == 33);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Load/Store Sign Extended Byte/Halfword", TAG) {
|
|
InstructionData data = LoadStoreSignExtendedHalfword{
|
|
.rd = 3, .rb = 0, .ro = 7, .s = false, .h = false
|
|
};
|
|
LoadStoreSignExtendedHalfword* load =
|
|
std::get_if<LoadStoreSignExtendedHalfword>(&data);
|
|
|
|
setr(7, 0x3003000);
|
|
setr(0, 0x332);
|
|
setr(3, 389524259);
|
|
|
|
SECTION("SH = 00") {
|
|
// 0x3003000 + 0x332
|
|
CHECK(bus->read_word(0x3003332) == 0);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
|
|
CHECK(bus->read_word(0x3003332) == 43811);
|
|
}
|
|
|
|
SECTION("SH = 01") {
|
|
load->h = true;
|
|
bus->write_word(0x3003332, 11123489);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
CHECK(getr(3) == 47905);
|
|
}
|
|
|
|
SECTION("SH = 10") {
|
|
load->s = true;
|
|
bus->write_word(0x3003332, 34521594);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
// sign extended 250 byte (0xFA)
|
|
CHECK(getr(3) == 4294967290);
|
|
}
|
|
|
|
SECTION("SH = 11") {
|
|
load->s = true;
|
|
load->h = true;
|
|
bus->write_word(0x3003332, 11123489);
|
|
// sign extended 47905 halfword (0xBB21)
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
CHECK(getr(3) == 4294949665);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Load/Store with Immediate Offset", TAG) {
|
|
InstructionData data = LoadStoreImmediateOffset{
|
|
.rd = 3, .rb = 0, .offset = 0x6E, .load = false, .byte = false
|
|
};
|
|
LoadStoreImmediateOffset* load =
|
|
std::get_if<LoadStoreImmediateOffset>(&data);
|
|
|
|
setr(0, 0x300666A);
|
|
setr(3, 389524259);
|
|
|
|
SECTION("store") {
|
|
// 0x30066A + 0x6E
|
|
CHECK(bus->read_word(0x30066D8) == 0);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
|
|
CHECK(bus->read_word(0x30066D8) == 389524259);
|
|
|
|
// byte
|
|
load->byte = true;
|
|
bus->write_word(0x30066D8, 0);
|
|
exec(data);
|
|
CHECK(bus->read_word(0x30066D8) == 35);
|
|
}
|
|
|
|
SECTION("load") {
|
|
load->load = true;
|
|
bus->write_word(0x30066D8, 11123489);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
CHECK(getr(3) == 11123489);
|
|
|
|
// byte
|
|
load->byte = true;
|
|
exec(data);
|
|
CHECK(getr(3) == 33);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Load/Store Halfword", TAG) {
|
|
InstructionData data =
|
|
LoadStoreHalfword{ .rd = 3, .rb = 0, .offset = 0x6E, .load = false };
|
|
LoadStoreHalfword* load = std::get_if<LoadStoreHalfword>(&data);
|
|
|
|
setr(0, 0x300666A);
|
|
setr(3, 389524259);
|
|
|
|
SECTION("store") {
|
|
// 0x300666A + 0x6E
|
|
CHECK(bus->read_word(0x30066D8) == 0);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
|
|
CHECK(bus->read_word(0x30066D8) == 43811);
|
|
}
|
|
|
|
SECTION("load") {
|
|
load->load = true;
|
|
bus->write_word(0x30066D8, 11123489);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
CHECK(getr(3) == 47905);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "SP Relative Load", TAG) {
|
|
InstructionData data =
|
|
SpRelativeLoad{ .word = 0x328, .rd = 1, .load = false };
|
|
SpRelativeLoad* load = std::get_if<SpRelativeLoad>(&data);
|
|
|
|
setr(1, 2349505744);
|
|
// sp
|
|
setr(13, 0x3004A8A);
|
|
|
|
SECTION("store") {
|
|
// 0x3004A8A + 0x328
|
|
CHECK(bus->read_word(0x3004DB2) == 0);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
|
|
CHECK(bus->read_word(0x3004DB2) == 2349505744);
|
|
}
|
|
|
|
SECTION("load") {
|
|
load->load = true;
|
|
bus->write_word(0x3004DB2, 11123489);
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
|
|
CHECK(getr(1) == 11123489);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Load Address", TAG) {
|
|
InstructionData data = LoadAddress{ .word = 808, .rd = 1, .sp = false };
|
|
LoadAddress* load = std::get_if<LoadAddress>(&data);
|
|
|
|
// pc
|
|
setr(15, 336485);
|
|
// sp
|
|
setr(13, 69879977);
|
|
|
|
SECTION("PC") {
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 1); // 1S
|
|
// word align 337293
|
|
CHECK(getr(1) == 337292);
|
|
}
|
|
|
|
SECTION("SP") {
|
|
load->sp = true;
|
|
exec(data);
|
|
CHECK(getr(1) == 69880785);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Add Offset to Stack Pointer", TAG) {
|
|
InstructionData data = AddOffsetStackPointer{ .word = 473 };
|
|
AddOffsetStackPointer* add = std::get_if<AddOffsetStackPointer>(&data);
|
|
|
|
// sp
|
|
setr(13, 69879977);
|
|
|
|
SECTION("positive") {
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 1); // 1S
|
|
CHECK(getr(13) == 69880450);
|
|
}
|
|
|
|
SECTION("negative") {
|
|
add->word = -473;
|
|
exec(data);
|
|
CHECK(getr(13) == 69879504);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
|
|
InstructionData data =
|
|
PushPopRegister{ .regs = 0b11010011, .pclr = false, .load = false };
|
|
PushPopRegister* push = std::get_if<PushPopRegister>(&data);
|
|
|
|
static constexpr uint8_t alignment = 4;
|
|
static constexpr uint32_t address = 0x30015AC;
|
|
|
|
// registers = 0, 1, 4, 6, 7
|
|
SECTION("push (store)") {
|
|
|
|
// populate registers
|
|
setr(0, 237164);
|
|
setr(1, 679785111);
|
|
setr(4, 905895898);
|
|
setr(6, 131313333);
|
|
setr(7, 131);
|
|
|
|
auto checker = [this]() {
|
|
// address
|
|
CHECK(bus->read_word(address) == 237164);
|
|
CHECK(bus->read_word(address + alignment) == 679785111);
|
|
CHECK(bus->read_word(address + alignment * 2) == 905895898);
|
|
CHECK(bus->read_word(address + alignment * 3) == 131313333);
|
|
CHECK(bus->read_word(address + alignment * 4) == 131);
|
|
};
|
|
|
|
// set stack pointer to top of stack
|
|
setr(13, address + alignment * 5);
|
|
|
|
SECTION("without LR") {
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 6); // 2N + (n-1)S, n = 5
|
|
checker();
|
|
CHECK(getr(13) == address);
|
|
}
|
|
|
|
SECTION("with LR") {
|
|
push->pclr = true;
|
|
// populate lr
|
|
setr(14, 999304);
|
|
// add another word on stack (top + 4)
|
|
setr(13, address + alignment * 6);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 7); // 2N + nS, n = 5
|
|
|
|
CHECK(bus->read_word(address + alignment * 5) == 999304);
|
|
checker();
|
|
CHECK(getr(13) == address);
|
|
}
|
|
}
|
|
|
|
SECTION("pop (load)") {
|
|
push->load = true;
|
|
|
|
// populate memory
|
|
bus->write_word(address, 237164);
|
|
bus->write_word(address + alignment, 679785111);
|
|
bus->write_word(address + alignment * 2, 905895898);
|
|
bus->write_word(address + alignment * 3, 131313333);
|
|
bus->write_word(address + alignment * 4, 131);
|
|
|
|
auto checker = [this]() {
|
|
CHECK(getr(0) == 237164);
|
|
CHECK(getr(1) == 679785111);
|
|
CHECK(getr(2) == 0);
|
|
CHECK(getr(3) == 0);
|
|
CHECK(getr(4) == 905895898);
|
|
CHECK(getr(5) == 0);
|
|
CHECK(getr(6) == 131313333);
|
|
CHECK(getr(7) == 131);
|
|
|
|
for (uint8_t i = 0; i < 8; i++) {
|
|
setr(i, 0);
|
|
}
|
|
};
|
|
|
|
// set stack pointer to bottom of stack
|
|
setr(13, address);
|
|
|
|
SECTION("without PC") {
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 7); // nS + N + I, n = 5
|
|
checker();
|
|
CHECK(getr(13) == address + alignment * 5);
|
|
}
|
|
|
|
SECTION("with PC") {
|
|
push->pclr = true;
|
|
// populate next address
|
|
bus->write_word(address + alignment * 5, 93333912);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 10); //(n+2)S + 2N + I, n = 5
|
|
|
|
// +4 for flushed pipeline
|
|
CHECK(getr(15) == 93333912 + 4);
|
|
checker();
|
|
CHECK(getr(13) == address + alignment * 6);
|
|
}
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Multiple Load/Store", TAG) {
|
|
InstructionData data =
|
|
MultipleLoad{ .regs = 0b11010101, .rb = 2, .load = false };
|
|
MultipleLoad* push = std::get_if<MultipleLoad>(&data);
|
|
// registers = 0, 1, 4, 6, 7
|
|
|
|
static constexpr uint8_t alignment = 4;
|
|
static constexpr uint32_t address = 0x30015AC;
|
|
|
|
SECTION("store") {
|
|
|
|
// populate registers
|
|
setr(0, 237164);
|
|
setr(4, 905895898);
|
|
setr(6, 131313333);
|
|
setr(7, 131);
|
|
|
|
// base
|
|
setr(2, address);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 6); //(n-1)S + 2N, n = 5
|
|
|
|
CHECK(bus->read_word(address) == 237164);
|
|
CHECK(bus->read_word(address + alignment) == address);
|
|
CHECK(bus->read_word(address + alignment * 2) == 905895898);
|
|
CHECK(bus->read_word(address + alignment * 3) == 131313333);
|
|
CHECK(bus->read_word(address + alignment * 4) == 131);
|
|
|
|
// write back
|
|
CHECK(getr(2) == address + alignment * 5);
|
|
}
|
|
|
|
SECTION("load") {
|
|
push->load = true;
|
|
|
|
// populate memory
|
|
bus->write_word(address, 237164);
|
|
bus->write_word(address + alignment, 679785111);
|
|
bus->write_word(address + alignment * 2, 905895898);
|
|
bus->write_word(address + alignment * 3, 131313333);
|
|
bus->write_word(address + alignment * 4, 131);
|
|
|
|
// base
|
|
setr(2, address);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 7); // nS + N + 1, n = 5
|
|
|
|
CHECK(getr(0) == 237164);
|
|
CHECK(getr(1) == 0);
|
|
CHECK(getr(2) == address + alignment * 5); // write back
|
|
CHECK(getr(3) == 0);
|
|
CHECK(getr(4) == 905895898);
|
|
CHECK(getr(5) == 0);
|
|
CHECK(getr(6) == 131313333);
|
|
CHECK(getr(7) == 131);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Conditional Branch", TAG) {
|
|
InstructionData data =
|
|
ConditionalBranch{ .offset = -192, .condition = Condition::EQ };
|
|
ConditionalBranch* branch = std::get_if<ConditionalBranch>(&data);
|
|
|
|
Psr cpsr = psr();
|
|
cpsr.set_state(State::Thumb);
|
|
|
|
setr(15, 4589344);
|
|
|
|
SECTION("z") {
|
|
uint32_t cycles = bus->get_cycles();
|
|
// condition is false
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 1); // 1S
|
|
|
|
// +2 for pc advance
|
|
CHECK(getr(15) == 4589344 + 2);
|
|
|
|
cpsr.set_z(true);
|
|
set_psr(cpsr);
|
|
cycles = bus->get_cycles();
|
|
// condition is true
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
|
|
// +4 for pipeline flush
|
|
CHECK(getr(15) == 4589156);
|
|
}
|
|
|
|
SECTION("c") {
|
|
branch->condition = Condition::CS;
|
|
// condition is false
|
|
exec(data);
|
|
|
|
// +2 for pc advance
|
|
CHECK(getr(15) == 4589346);
|
|
|
|
cpsr.set_c(true);
|
|
set_psr(cpsr);
|
|
// condition is true
|
|
exec(data);
|
|
// +4 for pipeline flush
|
|
CHECK(getr(15) == 4589156);
|
|
}
|
|
|
|
SECTION("n") {
|
|
branch->condition = Condition::MI;
|
|
// condition is false
|
|
exec(data);
|
|
|
|
// +2 for pc advance
|
|
CHECK(getr(15) == 4589346);
|
|
|
|
cpsr.set_n(true);
|
|
set_psr(cpsr);
|
|
// condition is true
|
|
exec(data);
|
|
// +4 for pipeline flush
|
|
CHECK(getr(15) == 4589156);
|
|
}
|
|
|
|
SECTION("v") {
|
|
branch->condition = Condition::VS;
|
|
// condition is false
|
|
exec(data);
|
|
|
|
// +2 for pc advance
|
|
CHECK(getr(15) == 4589346);
|
|
|
|
cpsr.set_v(true);
|
|
set_psr(cpsr);
|
|
// condition is true
|
|
exec(data);
|
|
// +4 for pipeline flush
|
|
CHECK(getr(15) == 4589156);
|
|
}
|
|
}
|
|
|
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TEST_CASE_METHOD(CpuFixture, "Software Interrupt", TAG) {
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InstructionData data = SoftwareInterrupt{ .vector = 32 };
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|
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setr(15, 4492);
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|
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uint32_t cycles = bus->get_cycles();
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// condition is true
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|
exec(data);
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CHECK(bus->get_cycles() == cycles + 3); // 2S + N
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|
|
|
CHECK(psr().raw() == psr(true).raw());
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|
CHECK(getr(14) == 4490);
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|
// +4 for flushed pipeline
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|
CHECK(getr(15) == 36);
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|
CHECK(psr().state() == State::Arm);
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|
CHECK(psr().mode() == Mode::Supervisor);
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|
}
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|
|
|
TEST_CASE_METHOD(CpuFixture, "Unconditional Branch", TAG) {
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|
InstructionData data = UnconditionalBranch{ .offset = -920 };
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|
|
|
setr(15, 4589344);
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|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
|
|
|
|
// +4 for flushed pipeline
|
|
CHECK(getr(15) == 4588428);
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Long Branch With Link", TAG) {
|
|
InstructionData data =
|
|
LongBranchWithLink{ .offset = 0b10010111110, .low = false };
|
|
LongBranchWithLink* branch = std::get_if<LongBranchWithLink>(&data);
|
|
|
|
// high
|
|
setr(15, 4589344);
|
|
|
|
uint32_t cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 1); // 1S
|
|
|
|
CHECK(getr(14) == 1173280);
|
|
|
|
// low
|
|
branch->low = true;
|
|
|
|
cycles = bus->get_cycles();
|
|
exec(data);
|
|
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
|
|
|
|
// +2 for advancing thumb, then -2 to get the next instruciton of current
|
|
// executing instruction, then set bit 0
|
|
CHECK(getr(14) == 4589343);
|
|
// 1175712 + 4 for flushed pipeline
|
|
CHECK(getr(15) == 1175712);
|
|
}
|