Amneesh Singh
9397140473
also fix bus' shared pointer in cpu TODO: put cpu in bus not the other way around Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
1078 lines
27 KiB
C++
1078 lines
27 KiB
C++
#include "cpu/arm/instruction.hh"
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#include "cpu/cpu-fixture.hh"
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#include "util/bits.hh"
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#include <catch2/catch_test_macros.hpp>
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#include <cstdint>
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using namespace matar;
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#define TAG "[arm][execution]"
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using namespace arm;
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TEST_CASE_METHOD(CpuFixture, "Branch and Exchange", TAG) {
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InstructionData data = BranchAndExchange{ .rn = 3 };
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setr(3, 342800);
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exec(data);
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CHECK(getr(15) == 342800);
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}
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TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
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InstructionData data = Branch{ .link = false, .offset = 3489748 };
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Branch* branch = std::get_if<Branch>(&data);
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// set PC to 48
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setr(15, 48);
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exec(data);
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// 48 + offset
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CHECK(getr(15) == 3489796);
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CHECK(getr(14) == 0);
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// with link
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reset();
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setr(15, 48);
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branch->link = true;
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exec(data);
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// 48 + offset
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CHECK(getr(15) == 3489796);
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// pc was set to 48
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CHECK(getr(14) == 48 - INSTRUCTION_SIZE);
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}
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TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
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InstructionData data = Multiply{
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.rm = 10, .rs = 11, .rn = 3, .rd = 5, .set = false, .acc = false
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};
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Multiply* multiply = std::get_if<Multiply>(&data);
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setr(10, 234912349);
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setr(11, 124897);
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setr(3, 99999);
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{
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uint32_t result = 234912349ull * 124897ull & 0xFFFFFFFF;
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exec(data);
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CHECK(getr(5) == result);
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}
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// with accumulate
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{
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uint32_t result = (234912349ull * 124897ull + 99999ull) & 0xFFFFFFFF;
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multiply->acc = true;
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exec(data);
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CHECK(getr(5) == result);
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}
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// with set
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{
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uint32_t result = (234912349ull * 124897ull + 99999ull) & 0xFFFFFFFF;
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multiply->set = true;
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exec(data);
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CHECK(getr(5) == result);
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CHECK(psr().n() == get_bit(result, 31));
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}
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// with set and zero
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{
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setr(10, 0);
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setr(3, 0);
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exec(data);
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CHECK(getr(5) == 0);
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CHECK(psr().n() == false);
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CHECK(psr().z() == true);
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
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InstructionData data = MultiplyLong{ .rm = 10,
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.rs = 11,
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.rdlo = 3,
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.rdhi = 5,
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.set = false,
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.acc = false,
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.uns = true };
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MultiplyLong* multiply_long = std::get_if<MultiplyLong>(&data);
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setr(10, 234912349);
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setr(11, 124897);
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// unsigned
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{
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uint64_t result = 234912349ull * 124897ull;
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exec(data);
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CHECK(getr(3) == bit_range(result, 0, 31));
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CHECK(getr(5) == bit_range(result, 32, 63));
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}
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// signed
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{
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int64_t result = 234912349ll * -124897ll;
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setr(11, getr(11) * -1);
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multiply_long->uns = false;
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exec(data);
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CHECK(getr(3) == static_cast<uint32_t>(bit_range(result, 0, 31)));
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CHECK(getr(5) == static_cast<uint32_t>(bit_range(result, 32, 63)));
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}
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// accumulate
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{
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setr(3, 99999);
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setr(5, -444333391);
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int64_t result =
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234912349ll * -124897ll + (99999ll | -444333391ll << 32);
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multiply_long->acc = true;
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exec(data);
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CHECK(getr(3) == static_cast<uint32_t>(bit_range(result, 0, 31)));
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CHECK(getr(5) == static_cast<uint32_t>(bit_range(result, 32, 63)));
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}
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// set
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{
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setr(3, 99999);
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setr(5, -444333391);
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int64_t result =
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234912349ll * -124897ll + (99999ll | -444333391ll << 32);
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multiply_long->set = true;
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exec(data);
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CHECK(getr(3) == static_cast<uint32_t>(bit_range(result, 0, 31)));
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CHECK(getr(5) == static_cast<uint32_t>(bit_range(result, 32, 63)));
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CHECK(psr().n() == true);
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CHECK(psr().z() == false);
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}
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// zero
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{
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setr(10, 0);
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setr(5, 0);
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setr(3, 0);
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exec(data);
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CHECK(getr(3) == 0);
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CHECK(getr(5) == 0);
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CHECK(psr().n() == false);
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CHECK(psr().z() == true);
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Single Data Swap", TAG) {
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InstructionData data =
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SingleDataSwap{ .rm = 3, .rd = 4, .rn = 9, .byte = false };
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SingleDataSwap* swap = std::get_if<SingleDataSwap>(&data);
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setr(9, 0x3003FED);
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setr(3, 94235087);
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setr(3, -259039045);
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bus->write_word(getr(9), 3241011111);
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SECTION("word") {
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exec(data);
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CHECK(getr(4) == 3241011111);
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CHECK(bus->read_word(getr(9)) == static_cast<uint32_t>(-259039045));
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}
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SECTION("byte") {
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swap->byte = true;
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exec(data);
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CHECK(getr(4) == (3241011111 & 0xFF));
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CHECK(bus->read_byte(getr(9)) ==
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static_cast<uint8_t>(-259039045 & 0xFF));
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
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InstructionData data =
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SingleDataTransfer{ .offset = Shift{ .rm = 3,
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.data =
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ShiftData{
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.type = ShiftType::ROR,
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.immediate = true,
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.operand = 29,
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} },
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.rd = 5,
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.rn = 7,
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.load = true,
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.write = false,
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.byte = false,
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.up = true,
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.pre = true };
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SingleDataTransfer* data_transfer = std::get_if<SingleDataTransfer>(&data);
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setr(3, 0x63C);
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setr(7, 0x3000004);
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setr(5, -911111);
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// shifted register (immediate)
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{
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// 0x31E + 0x3000004
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bus->write_word(0x30031E4, 95995);
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exec(data);
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CHECK(getr(5) == 95995);
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setr(5, 0);
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}
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// shifted register (register)
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{
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data_transfer->offset = Shift{ .rm = 3,
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.data = ShiftData{
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.type = ShiftType::LSL,
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.immediate = false,
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.operand = 12,
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} };
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setr(12, 2);
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// 6384 + 0x3000004
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bus->write_word(0x30018F4, 3948123487);
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exec(data);
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CHECK(getr(5) == 3948123487);
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}
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// immediate
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{
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data_transfer->offset = static_cast<uint16_t>(0xDA1);
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// 0xDA1 + 0x3000004
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bus->write_word(0x3000DA5, 68795467);
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exec(data);
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CHECK(getr(5) == 68795467);
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}
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// down
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{
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setr(7, 0x3005E0D);
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data_transfer->up = false;
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// 0x3005E0D - 0xDA1
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bus->write_word(0x300506C, 5949595);
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exec(data);
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CHECK(getr(5) == 5949595);
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// no write back
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CHECK(getr(7) == 0x3005E0D);
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}
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// write
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{
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data_transfer->write = true;
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// 0x3005E0D - 0xDA1
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bus->write_word(0x300506C, 967844);
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exec(data);
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CHECK(getr(5) == 967844);
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// 0x3005E0D - 0xDA1
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CHECK(getr(7) == 0x300506C);
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}
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// post
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{
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data_transfer->write = false;
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data_transfer->pre = false;
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bus->write_word(0x300506C, 61119);
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exec(data);
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CHECK(getr(5) == 61119);
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// 0x300506C - 0xDA1
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CHECK(getr(7) == 0x30042CB);
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}
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// store
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{
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data_transfer->load = false;
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exec(data);
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CHECK(bus->read_word(0x30042CB) == 61119);
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// 0x30042CB - 0xDA1
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CHECK(getr(7) == 0x300352A);
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}
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// r15 as rn
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{
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data_transfer->rn = 15;
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setr(15, 0x300352A);
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exec(data);
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CHECK(bus->read_word(0x300352A) == 61119);
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// 0x300352A - 0xDA1
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CHECK(getr(15) == 0x3002789);
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// cleanup
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data_transfer->rn = 7;
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}
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// r15 as rd
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{
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data_transfer->rd = 15;
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setr(15, 444444);
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exec(data);
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CHECK(bus->read_word(0x300352A + INSTRUCTION_SIZE) == 444444);
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// 0x300352A - 0xDA1
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CHECK(getr(7) == 0x3002789 + INSTRUCTION_SIZE);
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// cleanup
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data_transfer->rd = 5;
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setr(7, getr(7) - INSTRUCTION_SIZE);
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}
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// byte
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{
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data_transfer->byte = true;
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setr(5, 458267584);
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exec(data);
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CHECK(bus->read_word(0x3002789) == (458267584 & 0xFF));
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// 0x3002789 - 0xDA1
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CHECK(getr(7) == 0x30019E8);
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
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InstructionData data = HalfwordTransfer{ .offset = 12,
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.half = true,
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.sign = false,
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.rd = 11,
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.rn = 10,
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.load = true,
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.write = false,
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.imm = false,
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.up = true,
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.pre = true };
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HalfwordTransfer* hw_transfer = std::get_if<HalfwordTransfer>(&data);
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setr(12, 0x384);
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setr(11, 459058287);
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setr(10, 0x300611E);
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// register offset
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{
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// 0x300611E + 0x384
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bus->write_word(0x30064A2, 3948123487);
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exec(data);
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CHECK(getr(11) == (3948123487 & 0xFFFF));
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}
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// immediate offset
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{
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hw_transfer->imm = true;
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hw_transfer->offset = 0xA7;
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// 0x300611E + 0xA7
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bus->write_word(0x30061C5, 594633302);
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exec(data);
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CHECK(getr(11) == (594633302 & 0xFFFF));
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}
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// down
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{
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hw_transfer->up = false;
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// 0x300611E - 0xA7
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bus->write_word(0x3006077, 222221);
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exec(data);
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CHECK(getr(11) == (222221 & 0xFFFF));
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// no write back
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CHECK(getr(10) == 0x300611E);
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}
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// write
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{
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hw_transfer->write = true;
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// 0x300611E - 0xA7
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bus->write_word(0x3006077, 100000005);
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exec(data);
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CHECK(getr(11) == (100000005 & 0xFFFF));
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CHECK(getr(10) == 0x3006077);
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}
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// post
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{
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hw_transfer->pre = false;
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hw_transfer->write = false;
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bus->write_word(0x3006077, 6111909);
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exec(data);
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CHECK(getr(11) == (6111909 & 0xFFFF));
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// 0x3006077 - 0xA7
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CHECK(getr(10) == 0x3005FD0);
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}
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// store
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{
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hw_transfer->load = false;
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exec(data);
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CHECK(bus->read_halfword(0x3005FD0) == (6111909 & 0xFFFF));
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// 0x3005FD0 - 0xA7
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CHECK(getr(10) == 0x3005F29);
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}
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// r15 as rn
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{
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hw_transfer->rn = 15;
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setr(15, 0x3005F29);
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exec(data);
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CHECK(bus->read_halfword(0x3005F29 - 2 * INSTRUCTION_SIZE) ==
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(6111909 & 0xFFFF));
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// 0x3005F29 - 0xA7
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CHECK(getr(15) == 0x3005E82 - 2 * INSTRUCTION_SIZE);
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// cleanup
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hw_transfer->rn = 10;
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}
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// r15 as rd
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{
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hw_transfer->rd = 15;
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setr(15, 224);
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exec(data);
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CHECK(bus->read_halfword(0x3005F29 + INSTRUCTION_SIZE) == 224);
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// 0x3005F29 - 0xA7
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CHECK(getr(10) == 0x3005E82 + INSTRUCTION_SIZE);
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// cleanup
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hw_transfer->rd = 11;
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setr(10, getr(10) - INSTRUCTION_SIZE);
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}
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// signed halfword
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{
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hw_transfer->load = true;
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hw_transfer->sign = true;
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bus->write_halfword(0x3005E82, -12345);
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exec(data);
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CHECK(getr(11) == static_cast<uint32_t>(-12345));
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// 0x3005E82 - 0xA7
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CHECK(getr(10) == 0x3005DDB);
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}
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// signed byte
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{
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hw_transfer->half = false;
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bus->write_byte(0x3005DDB, -56);
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exec(data);
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CHECK(getr(11) == static_cast<uint32_t>(-56));
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// 0x3005DDB - 0xA7
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CHECK(getr(10) == 0x3005D34);
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}
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}
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TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
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InstructionData data = BlockDataTransfer{ .regs = 0b1010100111000001,
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.rn = 10,
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.load = true,
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.write = false,
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.s = false,
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.up = true,
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.pre = true };
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BlockDataTransfer* block_transfer = std::get_if<BlockDataTransfer>(&data);
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static constexpr uint8_t alignment = 4;
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// load
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SECTION("load") {
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static constexpr uint32_t address = 0x3000D78;
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// populate memory
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bus->write_word(address, 38947234);
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bus->write_word(address + alignment, 237164);
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bus->write_word(address + alignment * 2, 679785111);
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bus->write_word(address + alignment * 3, 905895898);
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bus->write_word(address + alignment * 4, 131313333);
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bus->write_word(address + alignment * 5, 131);
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bus->write_word(address + alignment * 6, 989231);
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bus->write_word(address + alignment * 7, 6);
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auto checker = [this](uint32_t rnval = 0) {
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CHECK(getr(0) == 237164);
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CHECK(getr(1) == 0);
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CHECK(getr(2) == 0);
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CHECK(getr(3) == 0);
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CHECK(getr(4) == 0);
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CHECK(getr(5) == 0);
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CHECK(getr(6) == 679785111);
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CHECK(getr(7) == 905895898);
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CHECK(getr(8) == 131313333);
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CHECK(getr(9) == 0);
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CHECK(getr(10) == rnval);
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CHECK(getr(11) == 131);
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CHECK(getr(12) == 0);
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CHECK(getr(13) == 989231);
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CHECK(getr(14) == 0);
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CHECK(getr(15) == 6);
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for (uint8_t i = 0; i < 16; i++) {
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setr(i, 0);
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}
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};
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setr(10, address);
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exec(data);
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checker(address);
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// with write
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setr(10, address);
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block_transfer->write = true;
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exec(data);
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checker(address + 7 * alignment);
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// decrement
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block_transfer->write = false;
|
|
block_transfer->up = false;
|
|
// adjust rn
|
|
setr(10, address + alignment * 8);
|
|
exec(data);
|
|
checker(address + alignment * 8);
|
|
|
|
// with write
|
|
setr(10, address + alignment * 8);
|
|
block_transfer->write = true;
|
|
exec(data);
|
|
checker(address + alignment);
|
|
|
|
// post increment
|
|
block_transfer->write = false;
|
|
block_transfer->up = true;
|
|
block_transfer->pre = false;
|
|
// adjust rn
|
|
setr(10, address + alignment);
|
|
exec(data);
|
|
checker(address + alignment * 8);
|
|
|
|
// post decrement
|
|
block_transfer->up = false;
|
|
// adjust rn
|
|
setr(10, address + alignment * 7);
|
|
exec(data);
|
|
checker(address);
|
|
|
|
// with s bit
|
|
cpu.chg_mode(Mode::Fiq);
|
|
block_transfer->s = true;
|
|
CHECK(psr().raw() != psr(true).raw());
|
|
exec(data);
|
|
CHECK(psr().raw() == psr(true).raw());
|
|
}
|
|
|
|
// store
|
|
SECTION("store") {
|
|
static constexpr uint32_t address = 0x30015A8;
|
|
|
|
block_transfer->load = false;
|
|
|
|
// populate registers
|
|
setr(0, 237164);
|
|
setr(6, 679785111);
|
|
setr(7, 905895898);
|
|
setr(8, 131313333);
|
|
setr(11, 131);
|
|
setr(13, 989231);
|
|
setr(15, 6);
|
|
|
|
auto checker = [this]() {
|
|
CHECK(bus->read_word(address + alignment) == 237164);
|
|
CHECK(bus->read_word(address + alignment * 2) == 679785111);
|
|
CHECK(bus->read_word(address + alignment * 3) == 905895898);
|
|
CHECK(bus->read_word(address + alignment * 4) == 131313333);
|
|
CHECK(bus->read_word(address + alignment * 5) == 131);
|
|
CHECK(bus->read_word(address + alignment * 6) == 989231);
|
|
CHECK(bus->read_word(address + alignment * 7) == 6);
|
|
|
|
for (uint8_t i = 1; i < 8; i++)
|
|
bus->write_word(address + alignment * i, 0);
|
|
};
|
|
|
|
setr(10, address); // base
|
|
exec(data);
|
|
checker();
|
|
|
|
// decrement
|
|
block_transfer->write = false;
|
|
block_transfer->up = false;
|
|
// adjust rn
|
|
setr(10, address + alignment * 8);
|
|
exec(data);
|
|
checker();
|
|
|
|
// post increment
|
|
block_transfer->up = true;
|
|
block_transfer->pre = false;
|
|
// adjust rn
|
|
setr(10, address + alignment);
|
|
exec(data);
|
|
checker();
|
|
|
|
// post decrement
|
|
block_transfer->up = false;
|
|
// adjust rn
|
|
setr(10, address + alignment * 7);
|
|
exec(data);
|
|
checker();
|
|
|
|
// with s bit
|
|
cpu.chg_mode(Mode::Fiq);
|
|
block_transfer->s = true;
|
|
exec(data);
|
|
// User's R13 is different (unset at this point)
|
|
CHECK(bus->read_word(address + alignment * 6) == 0);
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
|
|
InstructionData data = PsrTransfer{
|
|
.operand = 12,
|
|
.spsr = false,
|
|
.type = PsrTransfer::Type::Mrs,
|
|
.imm = false,
|
|
};
|
|
PsrTransfer* psr_transfer = std::get_if<PsrTransfer>(&data);
|
|
|
|
SECTION("MRS") {
|
|
setr(12, 12389398);
|
|
|
|
CHECK(psr().raw() != getr(12));
|
|
exec(data);
|
|
CHECK(psr().raw() == getr(12));
|
|
|
|
psr_transfer->spsr = true;
|
|
// with SPSR
|
|
CHECK(psr(true).raw() != getr(12));
|
|
exec(data);
|
|
CHECK(psr(true).raw() == getr(12));
|
|
}
|
|
|
|
// MSR
|
|
SECTION("MSR") {
|
|
psr_transfer->type = PsrTransfer::Type::Msr;
|
|
// go to the reserved bits
|
|
setr(12, 16556u << 8);
|
|
|
|
CHECK(psr().raw() != getr(12));
|
|
exec(data);
|
|
CHECK(psr().raw() == getr(12));
|
|
|
|
psr_transfer->spsr = true;
|
|
// with SPSR
|
|
CHECK(psr(true).raw() != getr(12));
|
|
exec(data);
|
|
CHECK(psr(true).raw() == getr(12));
|
|
}
|
|
|
|
// MSR_flg
|
|
SECTION("MSR_flg") {
|
|
psr_transfer->type = PsrTransfer::Type::Msr_flg;
|
|
|
|
setr(12, 1490352945);
|
|
// go to the reserved bits
|
|
|
|
exec(data);
|
|
CHECK(psr().n() == get_bit(1490352945, 31));
|
|
CHECK(psr().z() == get_bit(1490352945, 30));
|
|
CHECK(psr().c() == get_bit(1490352945, 29));
|
|
CHECK(psr().v() == get_bit(1490352945, 28));
|
|
|
|
// with SPSR and immediate operand
|
|
psr_transfer->operand = 99333394;
|
|
psr_transfer->imm = true;
|
|
psr_transfer->spsr = true;
|
|
exec(data);
|
|
CHECK(psr(true).n() == get_bit(9933394, 31));
|
|
CHECK(psr(true).z() == get_bit(9933394, 30));
|
|
CHECK(psr(true).c() == get_bit(9933394, 29));
|
|
CHECK(psr(true).v() == get_bit(9933394, 28));
|
|
}
|
|
}
|
|
|
|
TEST_CASE_METHOD(CpuFixture, "Data Processing", TAG) {
|
|
using OpCode = DataProcessing::OpCode;
|
|
|
|
InstructionData data =
|
|
DataProcessing{ .operand = Shift{ .rm = 3,
|
|
.data =
|
|
ShiftData{
|
|
.type = ShiftType::ROR,
|
|
.immediate = true,
|
|
.operand = 29,
|
|
} },
|
|
.rd = 5,
|
|
.rn = 7,
|
|
.set = true,
|
|
.opcode = OpCode::AND };
|
|
DataProcessing* processing = std::get_if<DataProcessing>(&data);
|
|
|
|
// operand 1
|
|
setr(7, -28717);
|
|
|
|
// AND with shifted register (imediate)
|
|
{
|
|
// rm
|
|
setr(3, 1596);
|
|
exec(data);
|
|
// -28717 & 12768
|
|
CHECK(getr(5) == 448);
|
|
}
|
|
|
|
// AND with shifted register (register)
|
|
{
|
|
processing->operand = Shift{ .rm = 3,
|
|
.data = ShiftData{
|
|
.type = ShiftType::LSL,
|
|
.immediate = false,
|
|
.operand = 12,
|
|
} };
|
|
// rm
|
|
setr(3, 1596);
|
|
// rs
|
|
setr(12, 2);
|
|
exec(data);
|
|
// -28717 & 6384
|
|
CHECK(getr(5) == 2256);
|
|
}
|
|
|
|
// same as above but with rn (oprerand 1) = 15
|
|
{
|
|
processing->rn = 15;
|
|
setr(15, -2871);
|
|
exec(data);
|
|
|
|
// (-2871 + INSTRUCTION_SIZE) & 6384
|
|
CHECK(getr(5) == ((-2871 + INSTRUCTION_SIZE) & 6384));
|
|
|
|
// cleanup
|
|
processing->rn = 7;
|
|
}
|
|
|
|
auto reset_flags = [this]() {
|
|
Psr cpsr = psr();
|
|
cpsr.set_n(false);
|
|
cpsr.set_z(false);
|
|
cpsr.set_v(false);
|
|
cpsr.set_c(false);
|
|
set_psr(cpsr);
|
|
};
|
|
|
|
auto flags = [this, reset_flags](bool n, bool z, bool v, bool c) {
|
|
CHECK(psr().n() == n);
|
|
CHECK(psr().z() == z);
|
|
CHECK(psr().v() == v);
|
|
CHECK(psr().c() == c);
|
|
reset_flags();
|
|
};
|
|
|
|
// immediate operand
|
|
processing->operand = static_cast<uint32_t>(54924809);
|
|
// rs
|
|
setr(12, 2);
|
|
setr(5, 0);
|
|
reset_flags();
|
|
|
|
SECTION("AND (with condition check)") {
|
|
Psr cpsr = psr();
|
|
|
|
processing->opcode = OpCode::AND;
|
|
|
|
exec(data, Condition::EQ);
|
|
|
|
// condition is false
|
|
CHECK(getr(5) == 0);
|
|
|
|
cpsr.set_z(true);
|
|
set_psr(cpsr);
|
|
exec(data, Condition::EQ);
|
|
exec(data, Condition::EQ);
|
|
|
|
// -28717 & 54924809
|
|
// condition is true now
|
|
CHECK(getr(5) == 54920705);
|
|
|
|
// check set flags
|
|
flags(false, false, false, false);
|
|
}
|
|
|
|
// TST with immediate operand
|
|
SECTION("TST") {
|
|
processing->opcode = OpCode::TST;
|
|
|
|
exec(data);
|
|
|
|
// -28717 & 54924809
|
|
CHECK(getr(5) == 0);
|
|
|
|
// check set flags
|
|
flags(false, false, false, false);
|
|
}
|
|
|
|
SECTION("EOR (with condition check)") {
|
|
Psr cpsr = psr();
|
|
|
|
processing->opcode = OpCode::EOR;
|
|
|
|
cpsr.set_c(true);
|
|
set_psr(cpsr);
|
|
exec(data, Condition::CC);
|
|
|
|
// condition fails
|
|
CHECK(getr(5) == 0);
|
|
|
|
cpsr = psr();
|
|
cpsr.set_c(false);
|
|
set_psr(cpsr);
|
|
exec(data, Condition::CC);
|
|
|
|
// -28717 ^ 54924809
|
|
// condition is true now
|
|
CHECK(getr(5) == 4240021978);
|
|
|
|
// check set flags
|
|
flags(true, false, false, false);
|
|
|
|
// check zero flag
|
|
processing->operand = static_cast<uint32_t>(-28717);
|
|
exec(data);
|
|
|
|
// -28717 ^ -28717
|
|
CHECK(getr(5) == 0);
|
|
|
|
// check set flags
|
|
flags(false, true, false, false);
|
|
}
|
|
|
|
SECTION("TEQ") {
|
|
processing->opcode = OpCode::TEQ;
|
|
|
|
exec(data);
|
|
|
|
// -28717 ^ 54924809
|
|
CHECK(getr(5) == 0);
|
|
|
|
// check set flags
|
|
flags(true, false, false, false);
|
|
}
|
|
|
|
SECTION("SUB") {
|
|
processing->opcode = OpCode::SUB;
|
|
exec(data);
|
|
|
|
// -28717 - 54924809
|
|
CHECK(getr(5) == static_cast<uint32_t>(-54953526));
|
|
|
|
// check set flags
|
|
flags(true, false, false, true);
|
|
|
|
// check zero flag
|
|
processing->operand = static_cast<uint32_t>(-28717);
|
|
exec(data);
|
|
|
|
// -28717 - (-28717)
|
|
CHECK(getr(5) == 0);
|
|
|
|
// check set flags
|
|
flags(false, true, false, true);
|
|
}
|
|
|
|
SECTION("CMP") {
|
|
processing->opcode = OpCode::CMP;
|
|
|
|
exec(data);
|
|
|
|
// -28717 - 54924809
|
|
CHECK(getr(5) == 0);
|
|
|
|
// check set flags
|
|
flags(true, false, false, true);
|
|
}
|
|
|
|
SECTION("RSB") {
|
|
processing->opcode = OpCode::RSB;
|
|
exec(data);
|
|
|
|
// +28717 + 54924809
|
|
CHECK(getr(5) == 54953526);
|
|
|
|
// check set flags
|
|
flags(false, false, false, false);
|
|
}
|
|
|
|
SECTION("ADD") {
|
|
processing->opcode = OpCode::ADD;
|
|
exec(data);
|
|
|
|
// -28717 + 54924809
|
|
CHECK(getr(5) == 54896092);
|
|
|
|
// check set flags
|
|
flags(false, false, false, false);
|
|
|
|
// test zero flag
|
|
processing->operand = static_cast<uint32_t>(28717);
|
|
exec(data);
|
|
|
|
// -28717 + 28717
|
|
CHECK(getr(5) == 0);
|
|
|
|
// check set flags
|
|
flags(false, true, false, false);
|
|
|
|
// test overflow flag
|
|
processing->operand = static_cast<uint32_t>((1u << 31) - 1);
|
|
setr(7, (1u << 31) - 1);
|
|
|
|
exec(data);
|
|
|
|
CHECK(getr(5) == (1ull << 32) - 2);
|
|
|
|
// check set flags
|
|
flags(true, false, true, false);
|
|
}
|
|
|
|
SECTION("CMN") {
|
|
processing->opcode = OpCode::CMN;
|
|
|
|
exec(data);
|
|
|
|
// -28717 + 54924809
|
|
CHECK(getr(5) == 0);
|
|
|
|
// check set flags
|
|
flags(false, false, false, false);
|
|
}
|
|
|
|
SECTION("ADC") {
|
|
Psr cpsr = psr();
|
|
processing->opcode = OpCode::ADC;
|
|
|
|
cpsr.set_c(true);
|
|
set_psr(cpsr);
|
|
exec(data);
|
|
|
|
// -28717 + 54924809 + carry
|
|
CHECK(getr(5) == 54896093);
|
|
|
|
// check set flags
|
|
flags(false, false, false, false);
|
|
}
|
|
|
|
SECTION("SBC") {
|
|
Psr cpsr = psr();
|
|
processing->opcode = OpCode::SBC;
|
|
|
|
cpsr.set_c(false);
|
|
set_psr(cpsr);
|
|
exec(data);
|
|
|
|
// -28717 - 54924809 + carry - 1
|
|
CHECK(getr(5) == static_cast<uint32_t>(-54953527));
|
|
|
|
// check set flags
|
|
flags(true, false, false, false);
|
|
}
|
|
|
|
SECTION("RSC") {
|
|
Psr cpsr = psr();
|
|
processing->opcode = OpCode::RSC;
|
|
|
|
cpsr.set_c(false);
|
|
set_psr(cpsr);
|
|
exec(data);
|
|
|
|
// +28717 +54924809 + carry - 1
|
|
CHECK(getr(5) == 54953525);
|
|
|
|
// check set flags
|
|
flags(false, false, false, false);
|
|
}
|
|
|
|
SECTION("ORR") {
|
|
processing->opcode = OpCode::ORR;
|
|
exec(data);
|
|
|
|
// -28717 | 54924809
|
|
CHECK(getr(5) == static_cast<uint32_t>(-24613));
|
|
|
|
// check set flags
|
|
flags(true, false, false, false);
|
|
}
|
|
|
|
SECTION("BIC") {
|
|
processing->opcode = OpCode::BIC;
|
|
exec(data);
|
|
|
|
// -28717 & ~54924809
|
|
CHECK(getr(5) == static_cast<uint32_t>(-54949422));
|
|
|
|
// check set flags
|
|
flags(true, false, false, false);
|
|
}
|
|
|
|
SECTION("MVN") {
|
|
processing->opcode = OpCode::MVN;
|
|
exec(data);
|
|
|
|
// ~54924809
|
|
CHECK(getr(5) == static_cast<uint32_t>(-54924810));
|
|
|
|
// check set flags
|
|
flags(true, false, false, false);
|
|
}
|
|
|
|
SECTION("R15 as destination") {
|
|
processing->opcode = OpCode::MVN;
|
|
processing->rd = 15;
|
|
setr(15, 0);
|
|
CHECK(psr(true).raw() != psr().raw());
|
|
exec(data);
|
|
|
|
// ~54924809
|
|
CHECK(getr(15) == static_cast<uint32_t>(-54924810));
|
|
|
|
// flags are not set
|
|
flags(false, false, false, false);
|
|
CHECK(psr(true).raw() == psr().raw());
|
|
}
|
|
}
|
|
|
|
#undef TAG
|