147 lines
4.3 KiB
C++
147 lines
4.3 KiB
C++
#pragma once
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#include "header.hh"
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#include "io/io.hh"
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#include <memory>
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#include <optional>
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#include <span>
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#include <vector>
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namespace matar {
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enum CpuAccess {
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Sequential,
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NonSequential
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};
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enum CpuAccessWidth {
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Word,
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Halfword,
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Byte
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};
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class Bus {
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private:
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struct Private {
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explicit Private() = default;
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};
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public:
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static constexpr uint32_t BIOS_SIZE = 1024 * 16;
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Bus(Private, std::array<uint8_t, BIOS_SIZE>&&, std::vector<uint8_t>&&);
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static std::shared_ptr<Bus> init(std::array<uint8_t, BIOS_SIZE>&&,
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std::vector<uint8_t>&&);
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uint8_t read_byte(uint32_t address, CpuAccess access) {
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add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
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return read_byte(address);
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};
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void write_byte(uint32_t address, uint8_t byte, CpuAccess access) {
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add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
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write_byte(address, byte);
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};
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uint16_t read_halfword(uint32_t address, CpuAccess access) {
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add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
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return read_halfword(address);
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}
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void write_halfword(uint32_t address, uint16_t halfword, CpuAccess access) {
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add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
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write_halfword(address, halfword);
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}
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uint32_t read_word(uint32_t address, CpuAccess access) {
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add_cpu_cycles<CpuAccessWidth::Word>(address, access);
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return read_word(address);
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}
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void write_word(uint32_t address, uint32_t word, CpuAccess access) {
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add_cpu_cycles<CpuAccessWidth::Word>(address, access);
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write_word(address, word);
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}
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uint8_t read_byte(uint32_t address);
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void write_byte(uint32_t address, uint8_t byte);
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uint16_t read_halfword(uint32_t address);
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void write_halfword(uint32_t address, uint16_t halfword);
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uint32_t read_word(uint32_t address);
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void write_word(uint32_t address, uint32_t word);
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// not sure what else to do?
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void internal_cycle() { cycles++; }
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uint32_t get_cycles() { return cycles; }
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private:
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template<CpuAccessWidth W>
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void add_cpu_cycles(uint32_t address, CpuAccess access) {
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auto cc = cycle_map[address >> 24 & 0xF];
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if constexpr (W == CpuAccessWidth::Word) {
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cycles += (access == CpuAccess::Sequential ? cc.s32 : cc.n32);
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} else {
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cycles += (access == CpuAccess::Sequential ? cc.s16 : cc.n16);
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}
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}
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template<unsigned int>
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std::optional<std::span<const uint8_t>> read(uint32_t) const;
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template<unsigned int>
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std::optional<std::span<uint8_t>> write(uint32_t);
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uint32_t cycles = 0;
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struct cycle_count {
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uint8_t n16; // non sequential 8/16 bit width access
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uint8_t n32; // non sequential 32 bit width access
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uint8_t s16; // seuquential 8/16 bit width access
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uint8_t s32; // sequential 32 bit width access
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};
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std::array<cycle_count, 0x10> cycle_map;
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static constexpr decltype(cycle_map) init_cycle_count();
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std::unique_ptr<IoDevices> io;
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#define MEMORY_REGION(name, start) \
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static constexpr uint32_t name##_START = start; \
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static constexpr uint8_t name##_REGION = start >> 24 & 0xF;
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#define DECL_MEMORY(name, ident, start, end) \
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MEMORY_REGION(name, start) \
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std::array<uint8_t, end - start + 1> ident = {};
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MEMORY_REGION(BIOS, 0x00000000)
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std::array<uint8_t, BIOS_SIZE> bios = {};
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// board working RAM
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DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
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// chip working RAM
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DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
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// palette RAM
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DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
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// video RAM
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DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
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// OAM OBJ attributes
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DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
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#undef DECL_MEMORY
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MEMORY_REGION(ROM_0, 0x08000000)
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MEMORY_REGION(ROM_1, 0x0A000000)
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MEMORY_REGION(ROM_2, 0x0C000000)
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MEMORY_REGION(IO, 0x04000000)
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static constexpr uint32_t IO_END = 0x040003FE;
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#undef MEMORY_REGION
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std::vector<uint8_t> rom;
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Header header;
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void parse_header();
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};
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}
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