Amneesh Singh
36d71a4ee2
also arm: fix some instructions Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
214 lines
7.1 KiB
C++
214 lines
7.1 KiB
C++
#include "instruction.hh"
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#include "util/bits.hh"
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#include "util/log.hh"
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namespace matar::thumb {
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Instruction::Instruction(uint16_t insn) {
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// Format 2: Add/Subtract
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if ((insn & 0xF800) == 0x1800) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rs = bit_range(insn, 3, 5);
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uint8_t offset = bit_range(insn, 6, 8);
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AddSubtract::OpCode opcode =
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static_cast<AddSubtract::OpCode>(get_bit(insn, 9));
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bool imm = get_bit(insn, 10);
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data = AddSubtract{
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.rd = rd, .rs = rs, .offset = offset, .opcode = opcode, .imm = imm
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};
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// Format 1: Move Shifted Register
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} else if ((insn & 0xE000) == 0x0000) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rs = bit_range(insn, 3, 5);
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uint8_t offset = bit_range(insn, 6, 10);
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ShiftType opcode = static_cast<ShiftType>(bit_range(insn, 11, 12));
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data = MoveShiftedRegister{
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.rd = rd, .rs = rs, .offset = offset, .opcode = opcode
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};
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// Format 3: Move/compare/add/subtract immediate
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} else if ((insn & 0xE000) == 0x2000) {
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uint8_t offset = bit_range(insn, 0, 7);
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uint8_t rd = bit_range(insn, 8, 10);
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MovCmpAddSubImmediate::OpCode opcode =
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static_cast<MovCmpAddSubImmediate::OpCode>(bit_range(insn, 11, 12));
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data =
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MovCmpAddSubImmediate{ .offset = offset, .rd = rd, .opcode = opcode };
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// Format 4: ALU operations
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} else if ((insn & 0xFC00) == 0x4000) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rs = bit_range(insn, 3, 5);
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AluOperations::OpCode opcode =
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static_cast<AluOperations::OpCode>(bit_range(insn, 6, 9));
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data = AluOperations{ .rd = rd, .rs = rs, .opcode = opcode };
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// Format 5: Hi register operations/branch exchange
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} else if ((insn & 0xFC00) == 0x4400) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rs = bit_range(insn, 3, 5);
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bool hi_2 = get_bit(insn, 6);
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bool hi_1 = get_bit(insn, 7);
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HiRegisterOperations::OpCode opcode =
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static_cast<HiRegisterOperations::OpCode>(bit_range(insn, 8, 9));
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if (opcode == HiRegisterOperations::OpCode::BX && hi_1)
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glogger.warn("H1 set with BX");
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rd += (hi_1 ? LO_GPR_COUNT : 0);
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rs += (hi_2 ? LO_GPR_COUNT : 0);
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data = HiRegisterOperations{ .rd = rd, .rs = rs, .opcode = opcode };
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// Format 6: PC-relative load
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} else if ((insn & 0xF800) == 0x4800) {
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uint16_t word = bit_range(insn, 0, 7);
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uint8_t rd = bit_range(insn, 8, 10);
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data =
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PcRelativeLoad{ .word = static_cast<uint16_t>(word << 2), .rd = rd };
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// Format 7: Load/store with register offset
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} else if ((insn & 0xF200) == 0x5000) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rb = bit_range(insn, 3, 5);
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uint8_t ro = bit_range(insn, 6, 8);
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bool byte = get_bit(insn, 10);
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bool load = get_bit(insn, 11);
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data = LoadStoreRegisterOffset{
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.rd = rd, .rb = rb, .ro = ro, .byte = byte, .load = load
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};
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// Format 8: Load/store sign-extended byte/halfword
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} else if ((insn & 0xF200) == 0x5200) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rb = bit_range(insn, 3, 5);
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uint8_t ro = bit_range(insn, 6, 8);
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bool s = get_bit(insn, 10);
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bool h = get_bit(insn, 11);
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data = LoadStoreSignExtendedHalfword{
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.rd = rd, .rb = rb, .ro = ro, .s = s, .h = h
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};
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// Format 9: Load/store with immediate offset
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} else if ((insn & 0xE000) == 0x6000) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rb = bit_range(insn, 3, 5);
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uint8_t offset = bit_range(insn, 6, 10);
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bool load = get_bit(insn, 11);
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bool byte = get_bit(insn, 12);
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if (!byte)
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offset <<= 2;
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data = LoadStoreImmediateOffset{
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.rd = rd, .rb = rb, .offset = offset, .load = load, .byte = byte
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};
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// Format 10: Load/store halfword
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} else if ((insn & 0xF000) == 0x8000) {
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uint8_t rd = bit_range(insn, 0, 2);
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uint8_t rb = bit_range(insn, 3, 5);
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uint8_t offset = bit_range(insn, 6, 10);
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bool load = get_bit(insn, 11);
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offset <<= 1;
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data = LoadStoreHalfword{
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.rd = rd, .rb = rb, .offset = offset, .load = load
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};
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// Format 11: SP-relative load/store
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} else if ((insn & 0xF000) == 0x9000) {
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uint16_t word = bit_range(insn, 0, 7);
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uint8_t rd = bit_range(insn, 8, 10);
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bool load = get_bit(insn, 11);
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word <<= 2;
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data = SpRelativeLoad{ .word = word, .rd = rd, .load = load };
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// Format 12: Load address
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} else if ((insn & 0xF000) == 0xA000) {
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uint16_t word = bit_range(insn, 0, 7);
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uint8_t rd = bit_range(insn, 8, 10);
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bool sp = get_bit(insn, 11);
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word <<= 2;
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data = LoadAddress{ .word = word, .rd = rd, .sp = sp };
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// Format 13: Add offset to stack pointer
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} else if ((insn & 0xFF00) == 0xB000) {
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int16_t word = static_cast<int16_t>(bit_range(insn, 0, 6));
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bool sign = get_bit(insn, 7);
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word <<= 2;
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word = static_cast<int16_t>(word * (sign ? -1 : 1));
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data = AddOffsetStackPointer{
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.word = word,
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};
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// Format 14: Push/pop registers
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} else if ((insn & 0xF600) == 0xB400) {
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uint8_t regs = bit_range(insn, 0, 7);
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bool pclr = get_bit(insn, 8);
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bool load = get_bit(insn, 11);
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data = PushPopRegister{ .regs = regs, .pclr = pclr, .load = load };
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// Format 15: Multiple load/store
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} else if ((insn & 0xF000) == 0xC000) {
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uint8_t regs = bit_range(insn, 0, 7);
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uint8_t rb = bit_range(insn, 8, 10);
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bool load = get_bit(insn, 11);
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data = MultipleLoad{ .regs = regs, .rb = rb, .load = load };
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// Format 17: Software interrupt
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} else if ((insn & 0xFF00) == 0xDF00) {
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uint8_t vector = bit_range(insn, 0, 7);
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data = SoftwareInterrupt{ .vector = vector };
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// Format 16: Conditional branch
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} else if ((insn & 0xF000) == 0xD000) {
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int32_t offset = bit_range(insn, 0, 7);
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Condition condition = static_cast<Condition>(bit_range(insn, 8, 11));
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offset <<= 1;
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// sign extend the 9 bit integer
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offset = (offset << 23) >> 23;
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data = ConditionalBranch{ .offset = offset, .condition = condition };
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// Format 18: Unconditional branch
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} else if ((insn & 0xF800) == 0xE000) {
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int32_t offset = bit_range(insn, 0, 10);
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offset <<= 1;
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// sign extend the 12 bit integer
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offset = (offset << 20) >> 20;
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data = UnconditionalBranch{ .offset = offset };
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// Format 19: Long branch with link
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} else if ((insn & 0xF000) == 0xF000) {
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uint16_t offset = bit_range(insn, 0, 10);
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bool high = get_bit(insn, 11);
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offset <<= 1;
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data = LongBranchWithLink{ .offset = offset, .high = high };
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}
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}
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}
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