231 lines
4.2 KiB
C++
231 lines
4.2 KiB
C++
#pragma once
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#include "cpu/alu.hh"
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#include "cpu/psr.hh"
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#include <cstdint>
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#include <string>
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#include <variant>
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namespace matar {
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class Cpu;
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namespace arm {
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// https://en.cppreference.com/w/cpp/utility/variant/visit
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template<class... Ts>
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struct overloaded : Ts... {
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using Ts::operator()...;
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};
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template<class... Ts>
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overloaded(Ts...) -> overloaded<Ts...>;
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static constexpr size_t INSTRUCTION_SIZE = 4;
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struct BranchAndExchange {
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uint8_t rn;
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};
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struct Branch {
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bool link;
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uint32_t offset;
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};
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struct Multiply {
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uint8_t rm;
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uint8_t rs;
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uint8_t rn;
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uint8_t rd;
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bool set;
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bool acc;
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};
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struct MultiplyLong {
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uint8_t rm;
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uint8_t rs;
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uint8_t rdlo;
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uint8_t rdhi;
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bool set;
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bool acc;
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bool uns;
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};
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struct SingleDataSwap {
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uint8_t rm;
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uint8_t rd;
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uint8_t rn;
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bool byte;
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};
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struct SingleDataTransfer {
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std::variant<uint16_t, Shift> offset;
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uint8_t rd;
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uint8_t rn;
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bool load;
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bool write;
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bool byte;
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bool up;
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bool pre;
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};
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struct HalfwordTransfer {
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uint8_t offset;
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bool half;
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bool sign;
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uint8_t rd;
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uint8_t rn;
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bool load;
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bool write;
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bool imm;
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bool up;
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bool pre;
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};
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struct BlockDataTransfer {
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uint16_t regs;
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uint8_t rn;
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bool load;
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bool write;
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bool s;
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bool up;
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bool pre;
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};
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struct DataProcessing {
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enum class OpCode {
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AND = 0b0000,
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EOR = 0b0001,
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SUB = 0b0010,
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RSB = 0b0011,
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ADD = 0b0100,
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ADC = 0b0101,
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SBC = 0b0110,
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RSC = 0b0111,
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TST = 0b1000,
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TEQ = 0b1001,
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CMP = 0b1010,
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CMN = 0b1011,
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ORR = 0b1100,
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MOV = 0b1101,
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BIC = 0b1110,
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MVN = 0b1111
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};
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std::variant<Shift, uint32_t> operand;
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uint8_t rd;
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uint8_t rn;
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bool set;
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OpCode opcode;
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};
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constexpr auto
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stringify(DataProcessing::OpCode opcode) {
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#define CASE(opcode) \
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case DataProcessing::OpCode::opcode: \
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return #opcode;
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switch (opcode) {
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CASE(AND)
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CASE(EOR)
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CASE(SUB)
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CASE(RSB)
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CASE(ADD)
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CASE(ADC)
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CASE(SBC)
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CASE(RSC)
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CASE(TST)
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CASE(TEQ)
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CASE(CMP)
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CASE(CMN)
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CASE(ORR)
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CASE(MOV)
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CASE(BIC)
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CASE(MVN)
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}
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#undef CASE
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return "";
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}
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struct PsrTransfer {
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enum class Type {
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Mrs,
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Msr,
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Msr_flg
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};
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uint32_t operand;
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bool spsr;
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Type type;
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// ignored outside MSR_flg
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bool imm;
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};
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struct CoprocessorDataTransfer {
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uint8_t offset;
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uint8_t cpn;
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uint8_t crd;
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uint8_t rn;
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bool load;
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bool write;
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bool len;
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bool up;
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bool pre;
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};
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struct CoprocessorDataOperation {
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uint8_t crm;
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uint8_t cp;
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uint8_t cpn;
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uint8_t crd;
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uint8_t crn;
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uint8_t cp_opc;
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};
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struct CoprocessorRegisterTransfer {
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uint8_t crm;
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uint8_t cp;
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uint8_t cpn;
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uint8_t rd;
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uint8_t crn;
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bool load;
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uint8_t cp_opc;
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};
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struct Undefined {};
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struct SoftwareInterrupt {};
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using InstructionData = std::variant<BranchAndExchange,
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Branch,
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Multiply,
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MultiplyLong,
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SingleDataSwap,
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SingleDataTransfer,
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HalfwordTransfer,
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BlockDataTransfer,
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DataProcessing,
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PsrTransfer,
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CoprocessorDataTransfer,
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CoprocessorDataOperation,
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CoprocessorRegisterTransfer,
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Undefined,
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SoftwareInterrupt>;
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struct Instruction {
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Instruction(uint32_t insn);
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Instruction(Condition condition, InstructionData data)
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: condition(condition)
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, data(data) {};
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void exec(Cpu& cpu);
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#ifdef DISASSEMBLER
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std::string disassemble();
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#endif
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Condition condition;
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InstructionData data;
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};
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}
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}
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