tests: add some exec tests

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

.clang-tidy

@@ -6,5 +6,4 @@ Checks: '
   , -cppcoreguidelines-macro-usage
   , -cppcoreguidelines-avoid-const-or-ref-data-members
   , -cppcoreguidelines-non-private-member-variables-in-classes
-  , -cppcoreguidelines-avoid-non-const-global-variables
 '

.github/workflows/clang.yml

@@ -1,36 +0,0 @@
-name: matar-clang
-on: [push, pull_request, workflow_dispatch]
-
-env:
-  BUILDDIR: build
-
-jobs:
-  build:
-    runs-on: ubuntu-latest
-    steps:
-      - uses: actions/checkout@v3
-      - uses: cachix/install-nix-action@v20
-        with:
-          extra_nix_config: |
-            auto-optimise-store = true
-            experimental-features = nix-command flakes
-      - uses: cachix/cachix-action@v12
-        with:
-          name: pain
-          authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
-
-
-      - name: setup
-        run: nix develop .#matar-clang -c meson setup $BUILDDIR
-
-      - name: fmt
-        run: nix develop .#matar-clang -c ninja clang-format-check -C $BUILDDIR
-
-      - name: lint
-        run: nix develop .#matar-clang -c ninja clang-tidy -C $BUILDDIR
-
-      - name: tests
-        run: nix develop .#matar-clang -c ninja test -C $BUILDDIR
-
-      - name: build
-        run: nix develop .#matar-clang -c ninja -C $BUILDDIR

.github/workflows/main.yml

@@ -1,4 +1,4 @@
-name: matar-gcc
+name: matar
 on: [push, pull_request, workflow_dispatch]
 
 env:
@@ -14,17 +14,18 @@ jobs:
           extra_nix_config: |
             auto-optimise-store = true
             experimental-features = nix-command flakes
-      - uses: cachix/cachix-action@v12
-        with:
-          name: pain
-          authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
-
 
       - name: setup
-        run: nix develop .#matar -c meson setup $BUILDDIR
+        run: nix develop -c meson setup $BUILDDIR
+
+      - name: fmt
+        run: nix develop -c ninja clang-format-check -C $BUILDDIR
+
+      - name: lint
+        run: nix develop -c ninja clang-tidy -C $BUILDDIR
 
       - name: tests
-        run: nix develop .#matar -c ninja test -C $BUILDDIR
+        run: nix develop -c ninja test -C $BUILDDIR
 
       - name: build
-        run: nix develop .#matar -c ninja -C $BUILDDIR
+        run: nix develop -c ninja -C $BUILDDIR

apps/target/main.cc

@@ -1,7 +1,6 @@
 #include "bus.hh"
 #include "cpu/cpu.hh"
 #include "memory.hh"
-#include "util/loglevel.hh"
 #include <array>
 #include <cstdlib>
 #include <fstream>
@@ -16,7 +15,7 @@
 int
 main(int argc, const char* argv[]) {
     std::vector<uint8_t> rom;
-    std::array<uint8_t, matar::Memory::BIOS_SIZE> bios = { 0 };
+    std::array<uint8_t, Memory::BIOS_SIZE> bios = { 0 };
 
     auto usage = [argv]() {
         std::cerr << "Usage: " << argv[0] << " <file> [-b <bios>]" << std::endl;
@@ -66,7 +65,7 @@ main(int argc, const char* argv[]) {
         ifile.seekg(0, std::ios::end);
         bios_size = ifile.tellg();
 
-        if (bios_size != matar::Memory::BIOS_SIZE) {
+        if (bios_size != Memory::BIOS_SIZE) {
             throw std::ios::failure("BIOS file has invalid size",
                                     std::error_code());
         }
@@ -85,15 +84,13 @@ main(int argc, const char* argv[]) {
     std::flush(std::cout);
     std::flush(std::cout);
 
-    matar::set_log_level(matar::LogLevel::Debug);
-
     try {
-        matar::Memory memory(std::move(bios), std::move(rom));
+        Memory memory(std::move(bios), std::move(rom));
-        matar::Bus bus(memory);
+        Bus bus(memory);
-        matar::Cpu cpu(bus);
+        Cpu cpu(bus);
         while (true) {
             cpu.step();
-            sleep(2);
+            sleep(1);
         }
     } catch (const std::exception& e) {
         std::cerr << "Exception: " << e.what() << std::endl;

apps/target/meson.build

@@ -7,7 +7,7 @@ target_sources = files(
 )
 
 executable(
-  'matar',
+  meson.project_name(),
   target_sources,
   link_with: target_deps,
   include_directories: inc,

flake.lock

@@ -1,60 +1,23 @@
 {
   "nodes": {
-    "flake-parts": {
-      "inputs": {
-        "nixpkgs-lib": "nixpkgs-lib"
-      },
-      "locked": {
-        "lastModified": 1693611461,
-        "narHash": "sha256-aPODl8vAgGQ0ZYFIRisxYG5MOGSkIczvu2Cd8Gb9+1Y=",
-        "owner": "hercules-ci",
-        "repo": "flake-parts",
-        "rev": "7f53fdb7bdc5bb237da7fefef12d099e4fd611ca",
-        "type": "github"
-      },
-      "original": {
-        "owner": "hercules-ci",
-        "repo": "flake-parts",
-        "type": "github"
-      }
-    },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1695318763,
+        "lastModified": 1694911158,
-        "narHash": "sha256-FHVPDRP2AfvsxAdc+AsgFJevMz5VBmnZglFUMlxBkcY=",
+        "narHash": "sha256-5WENkcO8O5SuA5pozpVppLGByWfHVv/1wOWgB2+TfV4=",
         "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "e12483116b3b51a185a33a272bf351e357ba9a99",
+        "rev": "46423a1a750594236673c1d741def4e93cf5a8f7",
         "type": "github"
       },
       "original": {
         "owner": "nixos",
-        "ref": "nixpkgs-unstable",
+        "ref": "master",
-        "repo": "nixpkgs",
-        "type": "github"
-      }
-    },
-    "nixpkgs-lib": {
-      "locked": {
-        "dir": "lib",
-        "lastModified": 1693471703,
-        "narHash": "sha256-0l03ZBL8P1P6z8MaSDS/MvuU8E75rVxe5eE1N6gxeTo=",
-        "owner": "NixOS",
-        "repo": "nixpkgs",
-        "rev": "3e52e76b70d5508f3cec70b882a29199f4d1ee85",
-        "type": "github"
-      },
-      "original": {
-        "dir": "lib",
-        "owner": "NixOS",
-        "ref": "nixos-unstable",
         "repo": "nixpkgs",
         "type": "github"
       }
     },
     "root": {
       "inputs": {
-        "flake-parts": "flake-parts",
         "nixpkgs": "nixpkgs"
       }
     }

flake.nix

@@ -2,39 +2,80 @@
   description = "matar";
 
   inputs = {
-    nixpkgs.url = github:nixos/nixpkgs/nixpkgs-unstable;
+    nixpkgs.url = github:nixos/nixpkgs/master;
-    flake-parts.url = github:hercules-ci/flake-parts;
   };
 
-  outputs = inputs@{ self, nixpkgs, flake-parts }:
+  outputs = { self, nixpkgs }:
-    flake-parts.lib.mkFlake { inherit inputs; } {
+    let
-
       systems = [
         "x86_64-linux"
         "aarch64-linux"
       ];
 
-      imports = [
+      eachSystem = with nixpkgs.lib; f: foldAttrs mergeAttrs { }
-        ./nix
+        (map (s: mapAttrs (_: v: { ${s} = v; }) (f s)) systems);
-      ];
+    in
+    eachSystem (system:
+      let
+        pkgs = import nixpkgs { inherit system; };
 
-      perSystem = { self', system, ... }:
+        # aliases
-        let
+        llvm = pkgs.llvmPackages_16;
-          pkgs = import nixpkgs { inherit system; };
+        stdenv = llvm.libcxxStdenv;
 
-          src = pkgs.lib.sourceFilesBySuffices ./. [
+
-            ".hh"
+        # TODO: this is ugly
-            ".cc"
+        #dependencies
-            ".build"
+        nativeBuildInputs = with pkgs;
-            "meson_options.txt"
+          [
+            meson
+            ninja
+
+            # libraries
+            pkg-config
+            cmake
+
+            ((pkgs.fmt.override {
+              inherit stdenv;
+              enableShared = false;
+            }).overrideAttrs (oa: {
+              cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
+            })).dev
+            (catch2_3.override { inherit stdenv; }).out
           ];
-        in
+      in
-        rec {
+      rec {
-          _module.args = {
+        packages = rec {
-            inherit src pkgs;
+          inherit (llvm) libcxxabi;
-          };
+          matar = stdenv.mkDerivation rec {
+            name = "matar";
+            version = "0.1";
+            src = pkgs.lib.sourceFilesBySuffices ./. [
+              ".hh"
+              ".cc"
+              ".build"
+              "meson_options.txt"
+            ];
+            outputs = [ "out" "dev" ];
 
-          formatter = pkgs.nixpkgs-fmt;
+            inherit nativeBuildInputs;
+
+            enableParallelBuilding = true;
+          };
+          default = matar;
         };
-    };
+
+        devShells = rec {
+          matar = pkgs.mkShell.override { inherit stdenv; } {
+            name = "matar";
+            packages = nativeBuildInputs ++ (with pkgs; [
+              # lsp
+              clang-tools_16
+            ]);
+          };
+          default = matar;
+        };
+
+        formatter = pkgs.nixpkgs-fmt;
+      });
 }

include/bus.hh

@@ -3,7 +3,6 @@
 #include "memory.hh"
 #include <memory>
 
-namespace matar {
 class Bus {
   public:
     Bus(const Memory& memory);
@@ -20,4 +19,3 @@ class Bus {
   private:
     std::shared_ptr<Memory> memory;
 };
-}

include/cpu/arm/instruction.hh

@@ -1,13 +1,7 @@
-#pragma once
+#include "cpu/utility.hh"
-#include "cpu/alu.hh"
-#include "cpu/psr.hh"
 #include <cstdint>
-#include <fmt/ostream.h>
 #include <variant>
 
-namespace matar {
-namespace arm {
-
 template<class... Ts>
 struct overloaded : Ts... {
     using Ts::operator()...;
@@ -15,8 +9,7 @@ struct overloaded : Ts... {
 template<class... Ts>
 overloaded(Ts...) -> overloaded<Ts...>;
 
-static constexpr size_t INSTRUCTION_SIZE = 4;
+namespace arm {
-
 struct BranchAndExchange {
     uint8_t rn;
 };
@@ -87,25 +80,6 @@ struct BlockDataTransfer {
 };
 
 struct DataProcessing {
-    enum class OpCode {
-        AND = 0b0000,
-        EOR = 0b0001,
-        SUB = 0b0010,
-        RSB = 0b0011,
-        ADD = 0b0100,
-        ADC = 0b0101,
-        SBC = 0b0110,
-        RSC = 0b0111,
-        TST = 0b1000,
-        TEQ = 0b1001,
-        CMP = 0b1010,
-        CMN = 0b1011,
-        ORR = 0b1100,
-        MOV = 0b1101,
-        BIC = 0b1110,
-        MVN = 0b1111
-    };
-
     std::variant<Shift, uint32_t> operand;
     uint8_t rd;
     uint8_t rn;
@@ -188,13 +162,4 @@ struct Instruction {
 
     std::string disassemble();
 };
-
-std::ostream&
-operator<<(std::ostream& os, const DataProcessing::OpCode cond);
-}
-}
-
-namespace fmt {
-template<>
-struct formatter<matar::arm::DataProcessing::OpCode> : ostream_formatter {};
 }

include/cpu/arm/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh',
+)

include/cpu/cpu.hh

@@ -1,21 +1,60 @@
-#include "bus.hh"
+#pragma once
 
-namespace matar {
+#include "arm/instruction.hh"
-class CpuImpl;
+#include "bus.hh"
+#include "psr.hh"
+
+#include <cstdint>
+
+using std::size_t;
 
 class Cpu {
   public:
-    Cpu(const Bus& bus) noexcept;
+    Cpu(const Bus& bus);
-    Cpu(const Cpu&)            = delete;
-    Cpu(Cpu&&)                 = delete;
-    Cpu& operator=(const Cpu&) = delete;
-    Cpu& operator=(Cpu&&)      = delete;
-
-    ~Cpu();
-
     void step();
 
   private:
-    std::unique_ptr<CpuImpl> impl;
+    static constexpr uint8_t GPR_COUNT = 16;
+
+    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
+    static constexpr uint8_t GPR_SVC_FIRST     = 13;
+    static constexpr uint8_t GPR_ABT_FIRST     = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
+    static constexpr uint8_t GPR_UND_FIRST     = 13;
+    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+
+    Psr cpsr; // current program status register
+    Psr spsr; // status program status register
+
+    static constexpr uint8_t PC_INDEX = 15;
+    static_assert(PC_INDEX < GPR_COUNT);
+
+    uint32_t& pc = gpr[PC_INDEX];
+
+    bool is_flushed;
+
+    void chg_mode(const Mode to);
+    void exec_arm(const arm::Instruction instruction);
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
+    } gpr_banked; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked; // banked saved program status registers
 };
-}

include/cpu/meson.build

@@ -1,3 +1,7 @@
 headers += files(
   'cpu.hh',
-)
+  'psr.hh',
+  'utility.hh'
+)
+
+subdir('arm')

include/cpu/psr.hh

@@ -1,42 +1,7 @@
 #pragma once
 
+#include "utility.hh"
 #include <cstdint>
-#include <fmt/ostream.h>
-
-namespace matar {
-enum class Mode {
-    /* M[4:0] in PSR */
-    User       = 0b10000,
-    Fiq        = 0b10001,
-    Irq        = 0b10010,
-    Supervisor = 0b10011,
-    Abort      = 0b10111,
-    Undefined  = 0b11011,
-    System     = 0b11111,
-};
-
-enum class State {
-    Arm   = 0,
-    Thumb = 1
-};
-
-enum class Condition {
-    EQ = 0b0000,
-    NE = 0b0001,
-    CS = 0b0010,
-    CC = 0b0011,
-    MI = 0b0100,
-    PL = 0b0101,
-    VS = 0b0110,
-    VC = 0b0111,
-    HI = 0b1000,
-    LS = 0b1001,
-    GE = 0b1010,
-    LT = 0b1011,
-    GT = 0b1100,
-    LE = 0b1101,
-    AL = 0b1110
-};
 
 class Psr {
   public:
@@ -88,13 +53,3 @@ class Psr {
 
     uint32_t psr;
 };
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const Condition cond);
-}
-
-namespace fmt {
-template<>
-struct formatter<matar::Condition> : ostream_formatter {};
-}

include/cpu/utility.hh

@@ -0,0 +1,99 @@
+#pragma once
+
+#include <fmt/ostream.h>
+#include <ostream>
+
+static constexpr size_t ARM_INSTRUCTION_SIZE   = 4;
+static constexpr size_t THUMB_INSTRUCTION_SIZE = 2;
+
+enum class Mode {
+    /* M[4:0] in PSR */
+    User       = 0b10000,
+    Fiq        = 0b10001,
+    Irq        = 0b10010,
+    Supervisor = 0b10011,
+    Abort      = 0b10111,
+    Undefined  = 0b11011,
+    System     = 0b11111,
+};
+
+enum class State {
+    Arm   = 0,
+    Thumb = 1
+};
+
+enum class Condition {
+    EQ = 0b0000,
+    NE = 0b0001,
+    CS = 0b0010,
+    CC = 0b0011,
+    MI = 0b0100,
+    PL = 0b0101,
+    VS = 0b0110,
+    VC = 0b0111,
+    HI = 0b1000,
+    LS = 0b1001,
+    GE = 0b1010,
+    LT = 0b1011,
+    GT = 0b1100,
+    LE = 0b1101,
+    AL = 0b1110
+};
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const Condition cond);
+template<>
+struct fmt::formatter<Condition> : ostream_formatter {};
+
+enum class OpCode {
+    AND = 0b0000,
+    EOR = 0b0001,
+    SUB = 0b0010,
+    RSB = 0b0011,
+    ADD = 0b0100,
+    ADC = 0b0101,
+    SBC = 0b0110,
+    RSC = 0b0111,
+    TST = 0b1000,
+    TEQ = 0b1001,
+    CMP = 0b1010,
+    CMN = 0b1011,
+    ORR = 0b1100,
+    MOV = 0b1101,
+    BIC = 0b1110,
+    MVN = 0b1111
+};
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const OpCode cond);
+template<>
+struct fmt::formatter<OpCode> : ostream_formatter {};
+
+enum class ShiftType {
+    LSL = 0b00,
+    LSR = 0b01,
+    ASR = 0b10,
+    ROR = 0b11
+};
+
+struct ShiftData {
+    ShiftType type;
+    bool immediate;
+    uint8_t operand;
+};
+
+struct Shift {
+    uint8_t rm;
+    ShiftData data;
+};
+
+uint32_t
+eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const ShiftType cond);
+template<>
+struct fmt::formatter<ShiftType> : ostream_formatter {};

include/header.hh

@@ -3,10 +3,7 @@
 #include <cstdint>
 #include <string>
 
-namespace matar {
 struct Header {
-    static constexpr uint8_t HEADER_SIZE = 192;
-
     enum class UniqueCode {
         Old,        // old games
         New,        // new games
@@ -45,4 +42,3 @@ struct Header {
     uint32_t multiboot_entrypoint;
     uint8_t slave_id;
 };
-}

include/memory.hh

@@ -4,10 +4,8 @@
 #include <array>
 #include <cstddef>
 #include <cstdint>
-#include <unordered_map>
 #include <vector>
 
-namespace matar {
 class Memory {
   public:
     static constexpr size_t BIOS_SIZE = 1024 * 16;
@@ -17,6 +15,12 @@ class Memory {
     uint8_t read(size_t address) const;
     void write(size_t address, uint8_t byte);
 
+    uint16_t read_halfword(size_t address) const;
+    void write_halfword(size_t address, uint16_t halfword);
+
+    uint32_t read_word(size_t address) const;
+    void write_word(size_t address, uint32_t word);
+
   private:
 #define MEMORY_REGION(name, start, end)                                        \
     static constexpr size_t name##_START = start;                              \
@@ -53,9 +57,7 @@ class Memory {
 
 #undef MEMORY_REGION
 
-    std::unordered_map<size_t, uint8_t> invalid_mem;
     std::vector<uint8_t> rom;
     Header header;
     void parse_header();
 };
-}

include/meson.build

@@ -4,9 +4,6 @@ headers = files(
   'header.hh',
 )
 
-inc = include_directories('.')
-
 subdir('cpu')
-subdir('util')
 
 install_headers(headers, subdir: meson.project_name(), preserve_path: true)

include/util/loglevel.hh

@@ -1,14 +0,0 @@
-#pragma once
-
-namespace matar {
-enum class LogLevel {
-    Off   = 1 << 0,
-    Error = 1 << 1,
-    Warn  = 1 << 2,
-    Info  = 1 << 3,
-    Debug = 1 << 4
-};
-
-void
-set_log_level(LogLevel level);
-}

include/util/meson.build

@@ -1,3 +0,0 @@
-headers += files(
-  'loglevel.hh'
-)

meson.build

@@ -4,8 +4,7 @@ project('matar', 'cpp',
   default_options : ['warning_level=3',
                      'werror=true',
                      'optimization=3',
-                     'cpp_std=c++20',
+                     'cpp_std=c++20'])
-                     'default_library=static'])
 
 compiler = meson.get_compiler('cpp')
 
@@ -31,6 +30,8 @@ else
 endif
 '''
 
+inc = include_directories('include')
+
 subdir('include')
 subdir('src')
 subdir('apps')

nix/build.nix

@@ -1,23 +0,0 @@
-{ stdenv
-, meson
-, ninja
-, pkg-config
-, src ? "../."
-, libraries ? [ ]
-}:
-
-stdenv.mkDerivation {
-  name = "matar";
-  version = "0.1";
-  inherit src;
-
-  outputs = [ "out" "dev" ];
-
-  nativeBuildInputs = [
-    meson
-    ninja
-    pkg-config
-  ] ++ libraries;
-
-  enableParallelBuilding = true;
-}

nix/default.nix

@@ -1,11 +0,0 @@
-{ ... }: {
-  imports = [
-    ./matar.nix
-    ./matar-clang.nix
-  ];
-
-  perSystem = { self', pkgs, ... }: {
-    packages.default = self'.packages.matar-clang;
-    devShells.default = self'.devShells.matar-clang;
-  };
-}

nix/matar-clang.nix

@@ -1,25 +0,0 @@
-{ ... }: {
-  perSystem = { pkgs, src, ... }:
-    let
-      llvm = pkgs.llvmPackages_16;
-      stdenv = llvm.libcxxStdenv;
-
-      libraries = with pkgs; [
-        ((pkgs.fmt.override {
-          inherit stdenv;
-          enableShared = false;
-        }).overrideAttrs (oa: {
-          cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
-        })).dev
-
-        (catch2_3.override { inherit stdenv; }).out
-      ];
-    in
-    {
-      packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
-      devShells.matar-clang = pkgs.callPackage ./shell.nix {
-        inherit libraries stdenv;
-        tools = with pkgs; [ clang-tools_16 ];
-      };
-    };
-}

nix/matar.nix

@@ -1,13 +0,0 @@
-{ ... }: {
-  perSystem = { pkgs, src, ... }:
-    let
-      libraries = with pkgs; [
-        (pkgs.fmt.override { enableShared = false; }).dev
-        catch2_3.out
-      ];
-    in
-    {
-      packages.matar = pkgs.callPackage ./build.nix { inherit src libraries; };
-      devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries; };
-    };
-}

nix/shell.nix

@@ -1,20 +0,0 @@
-{ stdenv
-, mkShell
-, meson
-, ninja
-, pkg-config
-, libraries ? [ ]
-, tools ? [ ]
-}:
-
-mkShell.override { inherit stdenv; } {
-  name = "matar";
-
-  packages = [
-    meson
-    ninja
-    pkg-config
-  ] ++ libraries ++ tools;
-
-  enableParallelBuilding = true;
-}

src/bus.cc

@@ -1,8 +1,6 @@
 #include "bus.hh"
-#include "util/log.hh"
 #include <memory>
 
-namespace matar {
 Bus::Bus(const Memory& memory)
   : memory(std::make_shared<Memory>(memory)) {}
 
@@ -18,38 +16,20 @@ Bus::write_byte(size_t address, uint8_t byte) {
 
 uint16_t
 Bus::read_halfword(size_t address) {
-    if (address & 0b01)
+    return memory->read_halfword(address);
-        glogger.warn("Reading a non aligned halfword address");
-
-    return memory->read(address) | memory->read(address + 1) << 8;
 }
 
 void
 Bus::write_halfword(size_t address, uint16_t halfword) {
-    if (address & 0b01)
+    memory->write_halfword(address, halfword);
-        glogger.warn("Writing to a non aligned halfword address");
-
-    memory->write(address, halfword & 0xFF);
-    memory->write(address + 1, halfword >> 8 & 0xFF);
 }
 
 uint32_t
 Bus::read_word(size_t address) {
-    if (address & 0b11)
+    return memory->read_word(address);
-        glogger.warn("Reading a non aligned word address");
-
-    return memory->read(address) | memory->read(address + 1) << 8 |
-           memory->read(address + 2) << 16 | memory->read(address + 3) << 24;
 }
 
 void
 Bus::write_word(size_t address, uint32_t word) {
-    if (address & 0b11)
+    memory->write_word(address, word);
-        glogger.warn("Writing to a non aligned word address");
-
-    memory->write(address, word & 0xFF);
-    memory->write(address + 1, word >> 8 & 0xFF);
-    memory->write(address + 2, word >> 16 & 0xFF);
-    memory->write(address + 3, word >> 24 & 0xFF);
-}
 }

src/cpu/alu.hh

@@ -1,35 +0,0 @@
-#pragma once
-#include <cstdint>
-#include <fmt/ostream.h>
-
-namespace matar {
-enum class ShiftType {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11
-};
-
-struct ShiftData {
-    ShiftType type;
-    bool immediate;
-    uint8_t operand;
-};
-
-struct Shift {
-    uint8_t rm;
-    ShiftData data;
-};
-
-uint32_t
-eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const ShiftType cond);
-}
-
-namespace fmt {
-template<>
-struct formatter<matar::ShiftType> : ostream_formatter {};
-}

src/cpu/arm/exec.cc

@@ -1,12 +1,13 @@
-#include "cpu/cpu-impl.hh"
+#include "cpu/cpu.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
-namespace matar {
+using namespace logger;
+
 void
-CpuImpl::exec_arm(const arm::Instruction instruction) {
+Cpu::exec_arm(const arm::Instruction instruction) {
-    Condition cond            = instruction.condition;
+    auto cond = instruction.condition;
-    arm::InstructionData data = instruction.data;
+    auto data = instruction.data;
 
     if (!cpsr.condition(cond)) {
         return;
@@ -14,12 +15,12 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
 
     auto pc_error = [](uint8_t r) {
         if (r == PC_INDEX)
-            glogger.error("Using PC (R15) as operand register");
+            log_error("Using PC (R15) as operand register");
     };
 
     auto pc_warn = [](uint8_t r) {
         if (r == PC_INDEX)
-            glogger.warn("Using PC (R15) as operand register");
+            log_warn("Using PC (R15) as operand register");
     };
 
     using namespace arm;
@@ -48,19 +49,20 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
         },
         [this](Branch& data) {
             if (data.link)
-                gpr[14] = pc - INSTRUCTION_SIZE;
+                gpr[14] = pc - ARM_INSTRUCTION_SIZE;
 
             // data.offset accounts for two instructions ahead when
             // disassembling, so need to adjust
-            pc = static_cast<int32_t>(pc) - 2 * INSTRUCTION_SIZE + data.offset;
+            pc =
+              static_cast<int32_t>(pc) - 2 * ARM_INSTRUCTION_SIZE + data.offset;
 
             // pc is affected so flush the pipeline
             is_flushed = true;
         },
         [this, pc_error](Multiply& data) {
             if (data.rd == data.rm)
-                glogger.error("rd and rm are not distinct in {}",
+                log_error("rd and rm are not distinct in {}",
-                              typeid(data).name());
+                          typeid(data).name());
 
             pc_error(data.rd);
             pc_error(data.rd);
@@ -78,8 +80,8 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
         [this, pc_error](MultiplyLong& data) {
             if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
                 data.rdlo == data.rm)
-                glogger.error("rdhi, rdlo and rm are not distinct in {}",
+                log_error("rdhi, rdlo and rm are not distinct in {}",
-                              typeid(data).name());
+                          typeid(data).name());
 
             pc_error(data.rdhi);
             pc_error(data.rdlo);
@@ -87,27 +89,23 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             pc_error(data.rs);
 
             if (data.uns) {
-                auto cast = [](uint32_t x) -> uint64_t {
+                uint64_t eval =
-                    return static_cast<uint64_t>(x);
+                  static_cast<uint64_t>(gpr[data.rm]) *
-                };
+                    static_cast<uint64_t>(gpr[data.rs]) +
-
+                  (data.acc ? (static_cast<uint64_t>(gpr[data.rdhi]) << 32) |
-                uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                                static_cast<uint64_t>(gpr[data.rdlo])
-                                (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                            : 0);
-                                              cast(gpr[data.rdlo])
-                                          : 0);
 
                 gpr[data.rdlo] = bit_range(eval, 0, 31);
                 gpr[data.rdhi] = bit_range(eval, 32, 63);
 
             } else {
-                auto cast = [](uint32_t x) -> int64_t {
+                int64_t eval =
-                    return static_cast<int64_t>(static_cast<int32_t>(x));
+                  static_cast<int64_t>(gpr[data.rm]) *
-                };
+                    static_cast<int64_t>(gpr[data.rs]) +
-
+                  (data.acc ? static_cast<int64_t>(gpr[data.rdhi]) << 32 |
-                int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                                static_cast<int64_t>(gpr[data.rdlo])
-                               (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                            : 0);
-                                             cast(gpr[data.rdlo])
-                                         : 0);
 
                 gpr[data.rdlo] = bit_range(eval, 0, 31);
                 gpr[data.rdhi] = bit_range(eval, 32, 63);
@@ -120,7 +118,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                 cpsr.set_v(0);
             }
         },
-        [](Undefined) { glogger.warn("Undefined instruction"); },
+        [](Undefined) { log_warn("Undefined instruction"); },
         [this, pc_error](SingleDataSwap& data) {
             pc_error(data.rm);
             pc_error(data.rn);
@@ -139,12 +137,12 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             uint32_t address = gpr[data.rn];
 
             if (!data.pre && data.write)
-                glogger.warn("Write-back enabled with post-indexing in {}",
+                log_warn("Write-back enabled with post-indexing in {}",
-                             typeid(data).name());
+                         typeid(data).name());
 
             if (data.rn == PC_INDEX && data.write)
-                glogger.warn("Write-back enabled with base register as PC {}",
+                log_warn("Write-back enabled with base register as PC {}",
-                             typeid(data).name());
+                         typeid(data).name());
 
             if (data.write)
                 pc_warn(data.rn);
@@ -172,11 +170,13 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
 
             // PC is always two instructions ahead
             if (data.rn == PC_INDEX)
-                address -= 2 * INSTRUCTION_SIZE;
+                address -= 2 * ARM_INSTRUCTION_SIZE;
 
             if (data.pre)
                 address += (data.up ? offset : -offset);
 
+            debug(address);
+
             // load
             if (data.load) {
                 // byte
@@ -189,7 +189,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             } else {
                 // take PC into consideration
                 if (data.rd == PC_INDEX)
-                    address += INSTRUCTION_SIZE;
+                    address += ARM_INSTRUCTION_SIZE;
 
                 // byte
                 if (data.byte)
@@ -210,32 +210,23 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
         },
         [this, pc_warn, pc_error](HalfwordTransfer& data) {
             uint32_t address = gpr[data.rn];
-            uint32_t offset  = 0;
 
             if (!data.pre && data.write)
-                glogger.error("Write-back enabled with post-indexing in {}",
+                log_error("Write-back enabled with post-indexing in {}",
-                              typeid(data).name());
+                          typeid(data).name());
 
             if (data.sign && !data.load)
-                glogger.error("Signed data found in {}", typeid(data).name());
+                log_error("Signed data found in {}", typeid(data).name());
 
             if (data.write)
                 pc_warn(data.rn);
 
             // offset is register number (4 bits) when not an immediate
-            if (!data.imm) {
+            if (!data.imm)
                 pc_error(data.offset);
-                offset = gpr[data.offset];
-            } else {
-                offset = data.offset;
-            }
-
-            // PC is always two instructions ahead
-            if (data.rn == PC_INDEX)
-                address -= 2 * INSTRUCTION_SIZE;
 
             if (data.pre)
-                address += (data.up ? offset : -offset);
+                address += (data.up ? data.offset : -data.offset);
 
             // load
             if (data.load) {
@@ -265,7 +256,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             } else {
                 // take PC into consideration
                 if (data.rd == PC_INDEX)
-                    address += INSTRUCTION_SIZE;
+                    address += ARM_INSTRUCTION_SIZE;
 
                 // halfword
                 if (data.half)
@@ -273,7 +264,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             }
 
             if (!data.pre)
-                address += (data.up ? offset : -offset);
+                address += (data.up ? data.offset : -data.offset);
 
             if (!data.pre || data.write)
                 gpr[data.rn] = address;
@@ -291,8 +282,8 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             pc_error(data.rn);
 
             if (cpsr.mode() == Mode::User && data.s) {
-                glogger.error("Bit S is set outside priviliged modes in {}",
+                log_error("Bit S is set outside priviliged modes in {}",
-                              typeid(data).name());
+                          typeid(data).name());
             }
 
             // we just change modes to load user registers
@@ -301,9 +292,8 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                 chg_mode(Mode::User);
 
                 if (data.write) {
-                    glogger.error(
+                    log_error("Write-back enable for user bank registers in {}",
-                      "Write-back enable for user bank registers in {}",
+                              typeid(data).name());
-                      typeid(data).name());
                 }
             }
 
@@ -342,8 +332,6 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             // reset back to original address + offset if incremented earlier
             if (data.up)
                 address -= n_regs * alignment;
-            else
-                address -= alignment;
 
             if (!data.pre || data.write)
                 gpr[data.rn] = address;
@@ -356,8 +344,8 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
         },
         [this, pc_error](PsrTransfer& data) {
             if (data.spsr && cpsr.mode() == Mode::User) {
-                glogger.error("Accessing SPSR in User mode in {}",
+                log_error("Accessing SPSR in User mode in {}",
-                              typeid(data).name());
+                          typeid(data).name());
             }
 
             Psr& psr = data.spsr ? spsr : cpsr;
@@ -375,23 +363,24 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                     }
                     break;
                 case PsrTransfer::Type::Msr_flg:
-                    uint32_t operand =
+                    psr.set_n(get_bit(data.operand, 31));
-                      (data.imm ? data.operand : gpr[data.operand]);
+                    psr.set_z(get_bit(data.operand, 30));
-                    psr.set_n(get_bit(operand, 31));
+                    psr.set_c(get_bit(data.operand, 29));
-                    psr.set_z(get_bit(operand, 30));
+                    psr.set_v(get_bit(data.operand, 28));
-                    psr.set_c(get_bit(operand, 29));
-                    psr.set_v(get_bit(operand, 28));
                     break;
             }
         },
         [this, pc_error](DataProcessing& data) {
-            using OpCode = DataProcessing::OpCode;
-
             uint32_t op_1 = gpr[data.rn];
             uint32_t op_2 = 0;
 
             uint32_t result = 0;
 
+            bool overflow = cpsr.v();
+            bool carry    = cpsr.c();
+            bool negative = cpsr.n();
+            bool zero     = cpsr.z();
+
             if (const uint32_t* immediate =
                   std::get_if<uint32_t>(&data.operand)) {
                 op_2 = *immediate;
@@ -413,107 +402,154 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
 
                 // PC is 12 bytes ahead when shifting
                 if (data.rn == PC_INDEX)
-                    op_1 += INSTRUCTION_SIZE;
+                    op_1 += ARM_INSTRUCTION_SIZE;
             }
 
-            bool overflow = cpsr.v();
-            bool carry    = cpsr.c();
-
-            auto sub = [&carry, &overflow](uint32_t a, uint32_t b) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                uint32_t result = a - b;
-
-                carry    = b <= a;
-                overflow = s1 != s2 && s2 == get_bit(result, 31);
-                return result;
-            };
-
-            auto add = [&carry, &overflow](
-                         uint32_t a, uint32_t b, bool c = 0) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                // 33 bits
-                uint64_t result_ = a + b + c;
-                uint32_t result  = result_ & 0xFFFFFFFF;
-
-                carry    = get_bit(result_, 32);
-                overflow = s1 == s2 && s2 != get_bit(result, 31);
-                return result;
-            };
-
-            auto sbc = [&carry,
-                        &overflow](uint32_t a, uint32_t b, bool c) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                uint64_t result_ = a - b + c - 1;
-                uint32_t result  = result_ & 0xFFFFFFFF;
-
-                carry    = get_bit(result_, 32);
-                overflow = s1 != s2 && s2 == get_bit(result, 31);
-                return result;
-            };
-
             switch (data.opcode) {
-                case OpCode::AND:
+                case OpCode::AND: {
-                case OpCode::TST:
                     result = op_1 & op_2;
-                    result = op_1 & op_2;
+
-                    break;
+                    negative = get_bit(result, 31);
-                case OpCode::EOR:
+                } break;
-                case OpCode::TEQ:
+                case OpCode::EOR: {
                     result = op_1 ^ op_2;
-                    break;
+
-                case OpCode::SUB:
+                    negative = get_bit(result, 31);
-                case OpCode::CMP:
+                } break;
-                    result = sub(op_1, op_2);
+                case OpCode::SUB: {
-                    break;
+                    bool s1  = get_bit(op_1, 31);
-                case OpCode::RSB:
+                    bool s2  = get_bit(op_2, 31);
-                    result = sub(op_2, op_1);
+                    result   = op_1 - op_2;
-                    break;
+                    negative = get_bit(result, 31);
-                case OpCode::ADD:
+                    carry    = op_1 < op_2;
-                case OpCode::CMN:
+                    overflow = s1 != s2 && s2 == negative;
-                    result = add(op_1, op_2);
+                } break;
-                    break;
+                case OpCode::RSB: {
-                case OpCode::ADC:
+                    bool s1 = get_bit(op_1, 31);
-                    result = add(op_1, op_2, carry);
+                    bool s2 = get_bit(op_2, 31);
-                    break;
+                    result  = op_2 - op_1;
-                case OpCode::SBC:
+
-                    result = sbc(op_1, op_2, carry);
+                    negative = get_bit(result, 31);
-                    break;
+                    carry    = op_2 < op_1;
-                case OpCode::RSC:
+                    overflow = s1 != s2 && s1 == negative;
-                    result = sbc(op_2, op_1, carry);
+                } break;
-                    break;
+                case OpCode::ADD: {
-                case OpCode::ORR:
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    // result_ is 33 bits
+                    uint64_t result_ = op_2 + op_1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 == s2 && s1 != negative;
+                } break;
+                case OpCode::ADC: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_2 + op_1 + carry;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 == s2 && s1 != negative;
+                } break;
+                case OpCode::SBC: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_1 - op_2 + carry - 1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 != s2 && s2 == negative;
+                } break;
+                case OpCode::RSC: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_1 - op_2 + carry - 1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 != s2 && s1 == negative;
+                } break;
+                case OpCode::TST: {
+                    result = op_1 & op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::TEQ: {
+                    result = op_1 ^ op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::CMP: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    result = op_1 - op_2;
+
+                    negative = get_bit(result, 31);
+                    carry    = op_1 < op_2;
+                    overflow = s1 != s2 && s2 == negative;
+                } break;
+                case OpCode::CMN: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_2 + op_1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 == s2 && s1 != negative;
+                } break;
+                case OpCode::ORR: {
                     result = op_1 | op_2;
-                    break;
+
-                case OpCode::MOV:
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::MOV: {
                     result = op_2;
-                    break;
+
-                case OpCode::BIC:
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::BIC: {
                     result = op_1 & ~op_2;
-                    break;
+
-                case OpCode::MVN:
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::MVN: {
                     result = ~op_2;
-                    break;
+
+                    negative = get_bit(result, 31);
+                } break;
             }
 
-            auto set_conditions = [this, carry, overflow, result]() {
+            zero = result == 0;
+
+            debug(carry);
+            debug(overflow);
+            debug(zero);
+            debug(negative);
+
+            auto set_conditions = [this, carry, overflow, negative, zero]() {
                 cpsr.set_c(carry);
                 cpsr.set_v(overflow);
-                cpsr.set_n(get_bit(result, 31));
+                cpsr.set_n(negative);
-                cpsr.set_z(result == 0);
+                cpsr.set_z(zero);
             };
 
             if (data.set) {
-                if (data.rd == PC_INDEX) {
+                if (data.rd == 15) {
                     if (cpsr.mode() == Mode::User)
-                        glogger.error("Running {} in User mode",
+                        log_error("Running {} in User mode",
-                                      typeid(data).name());
+                                  typeid(data).name());
-                    spsr = cpsr;
                 } else {
                     set_conditions();
                 }
@@ -524,7 +560,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                 set_conditions();
             } else {
                 gpr[data.rd] = result;
-                if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
+                if (data.rd == 15 || data.opcode == OpCode::MVN)
                     is_flushed = true;
             }
         },
@@ -534,8 +570,7 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             spsr = cpsr;
         },
         [](auto& data) {
-            glogger.error("Unimplemented {} instruction", typeid(data).name());
+            log_error("Unimplemented {} instruction", typeid(data).name());
         } },
       data);
 }
-}

src/cpu/arm/instruction.cc

@@ -1,9 +1,9 @@
-#include "instruction.hh"
+#include "cpu/arm/instruction.hh"
+#include "cpu/utility.hh"
 #include "util/bits.hh"
 #include <iterator>
 
-namespace matar {
+using namespace arm;
-namespace arm {
 
 Instruction::Instruction(uint32_t insn)
   : condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
@@ -21,7 +21,7 @@ Instruction::Instruction(uint32_t insn)
         // lsh 2 and sign extend the 26 bit offset to 32 bits
         offset = (static_cast<int32_t>(offset) << 8) >> 6;
 
-        offset += 2 * INSTRUCTION_SIZE;
+        offset += 2 * ARM_INSTRUCTION_SIZE;
 
         data = Branch{ .link = link, .offset = offset };
 
@@ -152,8 +152,6 @@ Instruction::Instruction(uint32_t insn)
 
         // Data Processing
     } else if ((insn & 0x0C000000) == 0x00000000) {
-        using OpCode = DataProcessing::OpCode;
-
         uint8_t rd    = bit_range(insn, 12, 15);
         uint8_t rn    = bit_range(insn, 16, 19);
         bool set      = get_bit(insn, 20);
@@ -421,8 +419,6 @@ Instruction::disassemble() {
             }
         },
         [this](DataProcessing& data) {
-            using OpCode = DataProcessing::OpCode;
-
             std::string op_2;
 
             if (const uint32_t* operand =
@@ -499,37 +495,3 @@ Instruction::disassemble() {
         [](auto) { return std::string("unknown instruction"); } },
       data);
 }
-
-std::ostream&
-operator<<(std::ostream& os, const DataProcessing::OpCode opcode) {
-
-#define CASE(opcode)                                                           \
-    case DataProcessing::OpCode::opcode:                                       \
-        os << #opcode;                                                         \
-        break;
-
-    switch (opcode) {
-        CASE(AND)
-        CASE(EOR)
-        CASE(SUB)
-        CASE(RSB)
-        CASE(ADD)
-        CASE(ADC)
-        CASE(SBC)
-        CASE(RSC)
-        CASE(TST)
-        CASE(TEQ)
-        CASE(CMP)
-        CASE(CMN)
-        CASE(ORR)
-        CASE(MOV)
-        CASE(BIC)
-        CASE(MVN)
-    }
-
-#undef CASE
-
-    return os;
-}
-}
-}

src/cpu/cpu-impl.cc

@@ -1,142 +0,0 @@
-#include "cpu-impl.hh"
-#include "util/bits.hh"
-#include "util/log.hh"
-#include <algorithm>
-#include <cstdio>
-
-namespace matar {
-CpuImpl::CpuImpl(const Bus& bus) noexcept
-  : bus(std::make_shared<Bus>(bus))
-  , gpr({ 0 })
-  , cpsr(0)
-  , spsr(0)
-  , is_flushed(false)
-  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
-  , spsr_banked({ 0, 0, 0, 0, 0 }) {
-    cpsr.set_mode(Mode::Supervisor);
-    cpsr.set_irq_disabled(true);
-    cpsr.set_fiq_disabled(true);
-    cpsr.set_state(State::Arm);
-    glogger.info("CPU successfully initialised");
-
-    // PC always points to two instructions ahead
-    // PC - 2 is the instruction being executed
-    pc += 2 * arm::INSTRUCTION_SIZE;
-}
-
-/* change modes */
-void
-CpuImpl::chg_mode(const Mode to) {
-    Mode from = cpsr.mode();
-
-    if (from == to)
-        return;
-
-/* TODO: replace visible registers with view once I understand how to
- * concatenate views */
-#define STORE_BANKED(mode, MODE)                                               \
-    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
-              gpr.begin() + gpr.size() - 1,                                    \
-              gpr_banked.mode.begin())
-
-    switch (from) {
-        case Mode::Fiq:
-            STORE_BANKED(fiq, FIQ);
-            spsr_banked.fiq = spsr;
-            break;
-
-        case Mode::Supervisor:
-            STORE_BANKED(svc, SVC);
-            spsr_banked.svc = spsr;
-            break;
-
-        case Mode::Abort:
-            STORE_BANKED(abt, ABT);
-            spsr_banked.abt = spsr;
-            break;
-
-        case Mode::Irq:
-            STORE_BANKED(irq, IRQ);
-            spsr_banked.irq = spsr;
-            break;
-
-        case Mode::Undefined:
-            STORE_BANKED(und, UND);
-            spsr_banked.und = spsr;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#define RESTORE_BANKED(mode, MODE)                                             \
-    std::copy(gpr_banked.mode.begin(),                                         \
-              gpr_banked.mode.end(),                                           \
-              gpr.begin() + GPR_##MODE##_FIRST)
-
-    switch (to) {
-        case Mode::Fiq:
-            RESTORE_BANKED(fiq, FIQ);
-            spsr = spsr_banked.fiq;
-            break;
-
-        case Mode::Supervisor:
-            RESTORE_BANKED(svc, SVC);
-            spsr = spsr_banked.svc;
-            break;
-
-        case Mode::Abort:
-            RESTORE_BANKED(abt, ABT);
-            spsr = spsr_banked.abt;
-            break;
-
-        case Mode::Irq:
-            RESTORE_BANKED(irq, IRQ);
-            spsr = spsr_banked.irq;
-            break;
-
-        case Mode::Undefined:
-            RESTORE_BANKED(und, UND);
-            spsr = spsr_banked.und;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#undef RESTORE_BANKED
-
-    cpsr.set_mode(to);
-}
-
-void
-CpuImpl::step() {
-    // Current instruction is two instructions behind PC
-    uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
-
-    if (cpsr.state() == State::Arm) {
-        uint32_t x = bus->read_word(cur_pc);
-        arm::Instruction instruction(x);
-        glogger.info("{:#034b}", x);
-
-        exec_arm(instruction);
-
-        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
-
-        if (is_flushed) {
-            // if flushed, do not increment the PC, instead set it to two
-            // instructions ahead to account for flushed "fetch" and "decode"
-            // instructions
-            pc += 2 * arm::INSTRUCTION_SIZE;
-            is_flushed = false;
-        } else {
-            // if not flushed continue like normal
-            pc += arm::INSTRUCTION_SIZE;
-        }
-    }
-}
-}

src/cpu/cpu-impl.hh

@@ -1,59 +0,0 @@
-#pragma once
-
-#include "bus.hh"
-#include "cpu/arm/instruction.hh"
-#include "cpu/psr.hh"
-
-#include <cstdint>
-
-namespace matar {
-class CpuImpl {
-  public:
-    CpuImpl(const Bus& bus) noexcept;
-
-    void step();
-    void chg_mode(const Mode to);
-    void exec_arm(const arm::Instruction instruction);
-
-    static constexpr uint8_t GPR_COUNT = 16;
-
-    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
-    static constexpr uint8_t GPR_SVC_FIRST     = 13;
-    static constexpr uint8_t GPR_ABT_FIRST     = 13;
-    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
-    static constexpr uint8_t GPR_UND_FIRST     = 13;
-    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
-
-    std::shared_ptr<Bus> bus;
-    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
-
-    Psr cpsr; // current program status register
-    Psr spsr; // status program status register
-
-    static constexpr uint8_t PC_INDEX = 15;
-    static_assert(PC_INDEX < GPR_COUNT);
-
-    uint32_t& pc = gpr[PC_INDEX];
-
-    bool is_flushed;
-
-    struct {
-        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
-        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
-        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
-        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
-        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
-
-        // visible registers before the mode switch
-        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
-    } gpr_banked; // banked general purpose registers
-
-    struct {
-        Psr fiq;
-        Psr svc;
-        Psr abt;
-        Psr irq;
-        Psr und;
-    } spsr_banked; // banked saved program status registers
-};
-}

src/cpu/cpu.cc

@@ -1,14 +1,144 @@
 #include "cpu/cpu.hh"
-#include "cpu-impl.hh"
+#include "cpu/utility.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+#include <algorithm>
+#include <cstdio>
 
-namespace matar {
+using namespace logger;
-Cpu::Cpu(const Bus& bus) noexcept
-  : impl(std::make_unique<CpuImpl>(bus)){};
 
-Cpu::~Cpu() = default;
+Cpu::Cpu(const Bus& bus)
+  : bus(std::make_shared<Bus>(bus))
+  , gpr({ 0 })
+  , cpsr(0)
+  , spsr(0)
+  , is_flushed(false)
+  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
+  , spsr_banked({ 0, 0, 0, 0, 0 }) {
+    cpsr.set_mode(Mode::Supervisor);
+    cpsr.set_irq_disabled(true);
+    cpsr.set_fiq_disabled(true);
+    cpsr.set_state(State::Arm);
+    log_info("CPU successfully initialised");
+
+    // PC always points to two instructions ahead
+    // PC - 2 is the instruction being executed
+    pc += 2 * ARM_INSTRUCTION_SIZE;
+}
+
+/* change modes */
+void
+Cpu::chg_mode(const Mode to) {
+    Mode from = cpsr.mode();
+
+    if (from == to)
+        return;
+
+/* TODO: replace visible registers with view once I understand how to
+ * concatenate views */
+#define STORE_BANKED(mode, MODE)                                               \
+    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
+              gpr.begin() + gpr.size() - 1,                                    \
+              gpr_banked.mode.begin())
+
+    switch (from) {
+        case Mode::Fiq:
+            STORE_BANKED(fiq, FIQ);
+            spsr_banked.fiq = spsr;
+            break;
+
+        case Mode::Supervisor:
+            STORE_BANKED(svc, SVC);
+            spsr_banked.svc = spsr;
+            break;
+
+        case Mode::Abort:
+            STORE_BANKED(abt, ABT);
+            spsr_banked.abt = spsr;
+            break;
+
+        case Mode::Irq:
+            STORE_BANKED(irq, IRQ);
+            spsr_banked.irq = spsr;
+            break;
+
+        case Mode::Undefined:
+            STORE_BANKED(und, UND);
+            spsr_banked.und = spsr;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            STORE_BANKED(old, SYS_USR);
+            break;
+    }
+
+#define RESTORE_BANKED(mode, MODE)                                             \
+    std::copy(gpr_banked.mode.begin(),                                         \
+              gpr_banked.mode.end(),                                           \
+              gpr.begin() + GPR_##MODE##_FIRST)
+
+    switch (to) {
+        case Mode::Fiq:
+            RESTORE_BANKED(fiq, FIQ);
+            spsr = spsr_banked.fiq;
+            break;
+
+        case Mode::Supervisor:
+            RESTORE_BANKED(svc, SVC);
+            spsr = spsr_banked.svc;
+            break;
+
+        case Mode::Abort:
+            RESTORE_BANKED(abt, ABT);
+            spsr = spsr_banked.abt;
+            break;
+
+        case Mode::Irq:
+            RESTORE_BANKED(irq, IRQ);
+            spsr = spsr_banked.irq;
+            break;
+
+        case Mode::Undefined:
+            RESTORE_BANKED(und, UND);
+            spsr = spsr_banked.und;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            STORE_BANKED(old, SYS_USR);
+            break;
+    }
+
+#undef RESTORE_BANKED
+
+    cpsr.set_mode(to);
+}
 
 void
 Cpu::step() {
-    impl->step();
+    // Current instruction is two instructions behind PC
-};
+    uint32_t cur_pc = pc - 2 * ARM_INSTRUCTION_SIZE;
+
+    if (cpsr.state() == State::Arm) {
+        debug(cur_pc);
+        uint32_t x = bus->read_word(cur_pc);
+        arm::Instruction instruction(x);
+        log_info("{:#034b}", x);
+
+        exec_arm(instruction);
+
+        log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
+
+        if (is_flushed) {
+            // if flushed, do not increment the PC, instead set it to two
+            // instructions ahead to account for flushed "fetch" and "decode"
+            // instructions
+            pc += 2 * ARM_INSTRUCTION_SIZE;
+            is_flushed = false;
+        } else {
+            // if not flushed continue like normal
+            pc += ARM_INSTRUCTION_SIZE;
+        }
+    }
 }

src/cpu/meson.build

@@ -1,8 +1,7 @@
 lib_sources += files(
-  'cpu-impl.cc',
   'cpu.cc',
   'psr.cc',
-  'alu.cc'
+  'utility.cc'
 )
 
 subdir('arm')

src/cpu/psr.cc

@@ -1,8 +1,7 @@
-#include "psr.hh"
+#include "cpu/psr.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
-namespace matar {
 Psr::Psr(uint32_t raw)
   : psr(raw & PSR_CLEAR_RESERVED) {}
 
@@ -91,42 +90,8 @@ Psr::condition(Condition cond) const {
         case Condition::LE:
             return z() || (n() != v());
         case Condition::AL:
-            return true && state() == State::Arm;
+            return true;
     }
 
     return false;
 }
-
-std::ostream&
-operator<<(std::ostream& os, const Condition cond) {
-
-#define CASE(cond)                                                             \
-    case Condition::cond:                                                      \
-        os << #cond;                                                           \
-        break;
-
-    switch (cond) {
-        CASE(EQ)
-        CASE(NE)
-        CASE(CS)
-        CASE(CC)
-        CASE(MI)
-        CASE(PL)
-        CASE(VS)
-        CASE(VC)
-        CASE(HI)
-        CASE(LS)
-        CASE(GE)
-        CASE(LT)
-        CASE(GT)
-        CASE(LE)
-        case Condition::AL: {
-            // empty
-        }
-    }
-
-#undef CASE
-
-    return os;
-}
-}

src/cpu/utility.cc

@@ -1,7 +1,72 @@
-#include "alu.hh"
+#include "cpu/utility.hh"
 #include "util/bits.hh"
+#include <bit>
+
+std::ostream&
+operator<<(std::ostream& os, const Condition cond) {
+
+#define CASE(cond)                                                             \
+    case Condition::cond:                                                      \
+        os << #cond;                                                           \
+        break;
+
+    switch (cond) {
+        CASE(EQ)
+        CASE(NE)
+        CASE(CS)
+        CASE(CC)
+        CASE(MI)
+        CASE(PL)
+        CASE(VS)
+        CASE(VC)
+        CASE(HI)
+        CASE(LS)
+        CASE(GE)
+        CASE(LT)
+        CASE(GT)
+        CASE(LE)
+        case Condition::AL: {
+            // empty
+        }
+    }
+
+#undef CASE
+
+    return os;
+}
+
+std::ostream&
+operator<<(std::ostream& os, const OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case OpCode::opcode:                                                       \
+        os << #opcode;                                                         \
+        break;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(SUB)
+        CASE(RSB)
+        CASE(ADD)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(RSC)
+        CASE(TST)
+        CASE(TEQ)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MOV)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+
+    return os;
+}
 
-namespace matar {
 uint32_t
 eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
     uint32_t eval = 0;
@@ -37,11 +102,13 @@ eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
             break;
         case ShiftType::ROR:
             if (amount == 0) {
-                eval  = (value >> 1) | (carry << 31);
+                bool old_carry = carry;
+
                 carry = get_bit(value, 0);
+                eval  = (value >> 1) | (old_carry << 31);
             } else {
-                eval  = std::rotr(value, amount);
                 carry = get_bit(value, (amount % 32 + 31) % 32);
+                eval  = std::rotr(value, amount);
             }
             break;
     }
@@ -68,4 +135,3 @@ operator<<(std::ostream& os, const ShiftType shift_type) {
 
     return os;
 }
-}

src/memory.cc

@@ -1,12 +1,13 @@
 #include "memory.hh"
 #include "header.hh"
 #include "util/bits.hh"
-#include "util/crypto.hh"
 #include "util/log.hh"
+#include "util/utils.hh"
 #include <bitset>
 #include <stdexcept>
 
-namespace matar {
+using namespace logger;
+
 Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
                std::vector<uint8_t>&& rom)
   : bios(std::move(bios))
@@ -21,17 +22,17 @@ Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
       "fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
 
     if (bios_hash != expected_hash) {
-        glogger.warn("BIOS hash failed to match, run at your own risk"
+        log_warn("BIOS hash failed to match, run at your own risk"
-                     "\nExpected : {} "
+                 "\nExpected : {} "
-                     "\nGot      : {}",
+                 "\nGot      : {}",
-                     expected_hash,
+                 expected_hash,
-                     bios_hash);
+                 bios_hash);
     }
 
     parse_header();
 
-    glogger.info("Memory successfully initialised");
+    log_info("Memory successfully initialised");
-    glogger.info("Cartridge Title: {}", header.title);
+    log_info("Cartridge Title: {}", header.title);
 };
 
 #define MATCHES(area) address >= area##_START&& address <= area##_END
@@ -57,7 +58,7 @@ Memory::read(size_t address) const {
     } else if (MATCHES(ROM_2)) {
         return rom[address - ROM_2_START];
     } else {
-        glogger.error("Invalid memory region accessed");
+        log_error("Invalid memory region accessed");
         return 0xFF;
     }
 }
@@ -83,16 +84,53 @@ Memory::write(size_t address, uint8_t byte) {
     } else if (MATCHES(ROM_2)) {
         rom[address - ROM_2_START] = byte;
     } else {
-        glogger.error("Invalid memory region accessed");
+        log_error("Invalid memory region accessed");
     }
 }
 
 #undef MATCHES
 
+uint16_t
+Memory::read_halfword(size_t address) const {
+    if (address & 0b01)
+        log_warn("Reading a non aligned halfword address");
+
+    return read(address) | read(address + 1) << 8;
+}
+
+void
+Memory::write_halfword(size_t address, uint16_t halfword) {
+    if (address & 0b01)
+        log_warn("Writing to a non aligned halfword address");
+
+    write(address, halfword & 0xFF);
+    write(address + 1, halfword >> 8 & 0xFF);
+}
+
+uint32_t
+Memory::read_word(size_t address) const {
+    if (address & 0b11)
+        log_warn("Reading a non aligned word address");
+
+    return read(address) | read(address + 1) << 8 | read(address + 2) << 16 |
+           read(address + 3) << 24;
+}
+
+void
+Memory::write_word(size_t address, uint32_t word) {
+    if (address & 0b11)
+        log_warn("Writing to a non aligned word address");
+
+    write(address, word & 0xFF);
+    write(address + 1, word >> 8 & 0xFF);
+    write(address + 2, word >> 16 & 0xFF);
+    write(address + 3, word >> 24 & 0xFF);
+}
+
 void
 Memory::parse_header() {
 
-    if (rom.size() < header.HEADER_SIZE) {
+    if (rom.size() < 192) {
         throw std::out_of_range(
           "ROM is not large enough to even have a header");
     }
@@ -103,7 +141,7 @@ Memory::parse_header() {
 
     // nintendo logo
     if (rom[0x9C] != 0x21)
-        glogger.info("HEADER: BIOS debugger bits not set to 0");
+        log_info("HEADER: BIOS debugger bits not set to 0");
 
     // game info
     header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
@@ -138,7 +176,7 @@ Memory::parse_header() {
             break;
 
         default:
-            glogger.error("HEADER: invalid unique code: {}", rom[0xAC]);
+            log_error("HEADER: invalid unique code: {}", rom[0xAC]);
     }
 
     header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
@@ -167,16 +205,15 @@ Memory::parse_header() {
             break;
 
         default:
-            glogger.error("HEADER: invalid destination/language: {}",
+            log_error("HEADER: invalid destination/language: {}", rom[0xAF]);
-                          rom[0xAF]);
     }
 
     if (rom[0xB2] != 0x96)
-        glogger.error("HEADER: invalid fixed byte at 0xB2");
+        log_error("HEADER: invalid fixed byte at 0xB2");
 
     for (size_t i = 0xB5; i < 0xBC; i++) {
         if (rom[i] != 0x00)
-            glogger.error("HEADER: invalid fixed bytes at 0xB5");
+            log_error("HEADER: invalid fixed bytes at 0xB5");
     }
 
     header.version = rom[0xBC];
@@ -190,9 +227,8 @@ Memory::parse_header() {
         chk &= 0xFF;
 
         if (chk != rom[0xBD])
-            glogger.error("HEADER: checksum does not match");
+            log_error("HEADER: checksum does not match");
     }
 
     // multiboot not required right now
 }
-}

src/meson.build

@@ -3,24 +3,15 @@ lib_sources = files(
   'bus.cc'
 )
 
-subdir('util')
 subdir('cpu')
 
-lib_cpp_args = [ ]
+fmt = dependency('fmt', version : '>=10.1.0')
-
-fmt = dependency('fmt', version : '>=10.1.0', static: true)
-if not fmt.found()
-  fmt = dependency('fmt', version : '>=10.1.0', static: false)
-  lib_cpp_args += 'DFMT_HEADER_ONLY'
-endif
-
 lib = library(
   meson.project_name(),
   lib_sources,
   dependencies: [fmt],
   include_directories: inc,
-  install: true,
+  install: true
-  cpp_args: lib_cpp_args
 )
 
 import('pkgconfig').generate(lib)

src/util/bits.hh

@@ -14,19 +14,19 @@ get_bit(Int num, size_t n) {
 template<std::integral Int>
 inline void
 set_bit(Int& num, size_t n) {
-    num |= (static_cast<Int>(1) << n);
+    num |= (1 << n);
 }
 
 template<std::integral Int>
 inline void
 rst_bit(Int& num, size_t n) {
-    num &= ~(static_cast<Int>(1) << n);
+    num &= ~(1 << n);
 }
 
 template<std::integral Int>
 inline void
 chg_bit(Int& num, size_t n, bool x) {
-    num = (num & ~(static_cast<Int>(1) << n)) | (static_cast<Int>(x) << n);
+    num = (num & ~(1 << n)) | (x << n);
 }
 
 /// read range of bits from start to end inclusive
@@ -36,5 +36,5 @@ bit_range(Int num, size_t start, size_t end) {
     // NOTE: we do not require -1 if it is a signed integral
     Int left =
       std::numeric_limits<Int>::digits - (std::is_unsigned<Int>::value) - end;
-    return static_cast<Int>(num << left) >> (left + start);
+    return num << left >> (left + start);
 }

src/util/log.cc

@@ -1,8 +0,0 @@
-#include "log.hh"
-
-logging::Logger glogger = logging::Logger();
-
-void
-matar::set_log_level(LogLevel level) {
-    glogger.set_level(level);
-}

src/util/log.hh

@@ -1,83 +1,58 @@
 #pragma once
 
-#include "util/loglevel.hh"
 #include <fmt/ostream.h>
 #include <iostream>
 
-namespace logging {
-namespace ansi {
-static constexpr auto RED     = "\033[31m";
-static constexpr auto YELLOW  = "\033[33m";
-static constexpr auto MAGENTA = "\033[35m";
-static constexpr auto WHITE   = "\033[37m";
-static constexpr auto BOLD    = "\033[1m";
-static constexpr auto RESET   = "\033[0m";
-}
-
 using fmt::print;
+using std::clog;
 
-class Logger {
+namespace logger {
-    using LogLevel = matar::LogLevel;
+namespace ansi {
-
+static constexpr std::string_view RED     = "\033[31m";
-  public:
+static constexpr std::string_view YELLOW  = "\033[33m";
-    Logger(LogLevel level = LogLevel::Debug, FILE* stream = stderr)
+static constexpr std::string_view MAGENTA = "\033[35m";
-      : level(0)
+static constexpr std::string_view WHITE   = "\033[37m";
-      , stream(stream) {
+static constexpr std::string_view BOLD    = "\033[1m";
-        set_level(level);
+static constexpr std::string_view RESET   = "\033[0m";
-    }
-
-    template<typename... Args>
-    void log(const fmt::format_string<Args...>& fmt, Args&&... args) {
-        fmt::println(stream, fmt, std::forward<Args>(args)...);
-    }
-
-    template<typename... Args>
-    void debug(const fmt::format_string<Args...>& fmt, Args&&... args) {
-        if (level & static_cast<uint8_t>(LogLevel::Debug)) {
-            print(stream, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
-            log(fmt, std::forward<Args>(args)...);
-            print(stream, ansi::RESET);
-        }
-    }
-
-    template<typename... Args>
-    void info(const fmt::format_string<Args...>& fmt, Args&&... args) {
-        if (level & static_cast<uint8_t>(LogLevel::Info)) {
-            print(stream, "{}[INFO] ", ansi::WHITE);
-            log(fmt, std::forward<Args>(args)...);
-            print(stream, ansi::RESET);
-        }
-    }
-
-    template<typename... Args>
-    void warn(const fmt::format_string<Args...>& fmt, Args&&... args) {
-        if (level & static_cast<uint8_t>(LogLevel::Warn)) {
-            print(stream, "{}[WARN] ", ansi::YELLOW);
-            log(fmt, std::forward<Args>(args)...);
-            print(stream, ansi::RESET);
-        }
-    }
-
-    template<typename... Args>
-    void error(const fmt::format_string<Args...>& fmt, Args&&... args) {
-        if (level & static_cast<uint8_t>(LogLevel::Error)) {
-            print(stream, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
-            log(fmt, std::forward<Args>(args)...);
-            print(stream, ansi::RESET);
-        }
-    }
-
-    void set_level(LogLevel level) {
-        this->level = (static_cast<uint8_t>(level) << 1) - 1;
-    }
-    void set_stream(FILE* stream) { this->stream = stream; }
-
-  private:
-    uint8_t level;
-    FILE* stream;
-};
 }
 
-extern logging::Logger glogger;
+template<typename... Args>
+inline void
+log_raw(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    fmt::println(clog, fmt, std::forward<Args>(args)...);
+}
 
-#define debug(x) glogger.debug("{} = {}", #x, x);
+template<typename... Args>
+inline void
+log_debug(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    print(clog, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
+    log_raw(fmt, std::forward<Args>(args)...);
+    print(clog, ansi::RESET);
+}
+
+template<typename... Args>
+inline void
+log_info(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    print(clog, "{}[INFO] ", ansi::WHITE);
+    log_raw(fmt, std::forward<Args>(args)...);
+    print(clog, ansi::RESET);
+}
+
+template<typename... Args>
+inline void
+log_warn(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    print(clog, "{}[WARN] ", ansi::YELLOW);
+    log_raw(fmt, std::forward<Args>(args)...);
+    print(clog, ansi::RESET);
+}
+
+template<typename... Args>
+inline void
+log_error(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    print(clog, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
+    log_raw(fmt, std::forward<Args>(args)...);
+    print(clog, ansi::RESET);
+}
+}
+
+#define debug(value) logger::log_debug("{} = {}", #value, value)

src/util/meson.build

@@ -1,3 +0,0 @@
-lib_sources += files(
-  'log.cc'
-)

tests/bus.cc

@@ -1,43 +0,0 @@
-#include "bus.hh"
-#include <catch2/catch_test_macros.hpp>
-
-static constexpr auto TAG = "[bus]";
-
-using namespace matar;
-
-class BusFixture {
-  public:
-    BusFixture()
-      : bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
-                   std::vector<uint8_t>(Header::HEADER_SIZE))) {}
-
-  protected:
-    Bus bus;
-};
-
-TEST_CASE_METHOD(BusFixture, "Byte", TAG) {
-    CHECK(bus.read_byte(3349) == 0);
-
-    bus.write_byte(3349, 0xEC);
-    CHECK(bus.read_byte(3349) == 0xEC);
-    CHECK(bus.read_word(3349) == 0xEC);
-    CHECK(bus.read_halfword(3349) == 0xEC);
-}
-
-TEST_CASE_METHOD(BusFixture, "Halfword", TAG) {
-    CHECK(bus.read_halfword(33750745) == 0);
-
-    bus.write_halfword(33750745, 0x1A4A);
-    CHECK(bus.read_halfword(33750745) == 0x1A4A);
-    CHECK(bus.read_word(33750745) == 0x1A4A);
-    CHECK(bus.read_byte(33750745) == 0x4A);
-}
-
-TEST_CASE_METHOD(BusFixture, "Word", TAG) {
-    CHECK(bus.read_word(100724276) == 0);
-
-    bus.write_word(100724276, 0x3ACC491D);
-    CHECK(bus.read_word(100724276) == 0x3ACC491D);
-    CHECK(bus.read_halfword(100724276) == 0x491D);
-    CHECK(bus.read_byte(100724276) == 0x1D);
-}

tests/cpu/arm/instruction.cc

@@ -1,9 +1,9 @@
 #include "cpu/arm/instruction.hh"
+#include "cpu/utility.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[arm][disassembly]";
+#define TAG "disassembler"
 
-using namespace matar;
 using namespace arm;
 
 TEST_CASE("Branch and Exchange", TAG) {
@@ -12,11 +12,11 @@ TEST_CASE("Branch and Exchange", TAG) {
     BranchAndExchange* bx = nullptr;
 
     REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
-    CHECK(instruction.condition == Condition::GT);
+    REQUIRE(instruction.condition == Condition::GT);
 
-    CHECK(bx->rn == 10);
+    REQUIRE(bx->rn == 10);
 
-    CHECK(instruction.disassemble() == "BXGT R10");
+    REQUIRE(instruction.disassemble() == "BXGT R10");
 }
 
 TEST_CASE("Branch", TAG) {
@@ -25,18 +25,18 @@ TEST_CASE("Branch", TAG) {
     Branch* b = nullptr;
 
     REQUIRE((b = std::get_if<Branch>(&instruction.data)));
-    CHECK(instruction.condition == Condition::AL);
+    REQUIRE(instruction.condition == Condition::AL);
 
     // last 24 bits = 8748995
     // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
     // Also +8 since PC is two instructions ahead
-    CHECK(b->offset == 0xFE15FF14);
+    REQUIRE(b->offset == 0xFE15FF14);
-    CHECK(b->link == true);
+    REQUIRE(b->link == true);
 
-    CHECK(instruction.disassemble() == "BL 0xFE15FF14");
+    REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
 
     b->link = false;
-    CHECK(instruction.disassemble() == "B 0xFE15FF14");
+    REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
 }
 
 TEST_CASE("Multiply", TAG) {
@@ -45,20 +45,20 @@ TEST_CASE("Multiply", TAG) {
     Multiply* mul = nullptr;
 
     REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
-    CHECK(instruction.condition == Condition::EQ);
+    REQUIRE(instruction.condition == Condition::EQ);
 
-    CHECK(mul->rm == 0);
+    REQUIRE(mul->rm == 0);
-    CHECK(mul->rs == 15);
+    REQUIRE(mul->rs == 15);
-    CHECK(mul->rn == 14);
+    REQUIRE(mul->rn == 14);
-    CHECK(mul->rd == 10);
+    REQUIRE(mul->rd == 10);
-    CHECK(mul->acc == true);
+    REQUIRE(mul->acc == true);
-    CHECK(mul->set == true);
+    REQUIRE(mul->set == true);
 
-    CHECK(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
+    REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
 
     mul->acc = false;
     mul->set = false;
-    CHECK(instruction.disassemble() == "MULEQ R10,R0,R15");
+    REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
 }
 
 TEST_CASE("Multiply Long", TAG) {
@@ -67,24 +67,24 @@ TEST_CASE("Multiply Long", TAG) {
     MultiplyLong* mull = nullptr;
 
     REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
-    CHECK(instruction.condition == Condition::NE);
+    REQUIRE(instruction.condition == Condition::NE);
 
-    CHECK(mull->rm == 2);
+    REQUIRE(mull->rm == 2);
-    CHECK(mull->rs == 6);
+    REQUIRE(mull->rs == 6);
-    CHECK(mull->rdlo == 7);
+    REQUIRE(mull->rdlo == 7);
-    CHECK(mull->rdhi == 14);
+    REQUIRE(mull->rdhi == 14);
-    CHECK(mull->acc == false);
+    REQUIRE(mull->acc == false);
-    CHECK(mull->set == true);
+    REQUIRE(mull->set == true);
-    CHECK(mull->uns == true);
+    REQUIRE(mull->uns == true);
 
-    CHECK(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
+    REQUIRE(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
 
     mull->acc = true;
-    CHECK(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
+    REQUIRE(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
 
     mull->uns = false;
     mull->set = false;
-    CHECK(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
+    REQUIRE(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
 }
 
 TEST_CASE("Undefined", TAG) {
@@ -93,8 +93,8 @@ TEST_CASE("Undefined", TAG) {
     uint32_t raw = 0b11100111101000101010111100010110;
     Instruction instruction(raw);
 
-    CHECK(instruction.condition == Condition::AL);
+    REQUIRE(instruction.condition == Condition::AL);
-    CHECK(instruction.disassemble() == "UND");
+    REQUIRE(instruction.disassemble() == "UND");
 }
 
 TEST_CASE("Single Data Swap", TAG) {
@@ -103,17 +103,17 @@ TEST_CASE("Single Data Swap", TAG) {
     SingleDataSwap* swp = nullptr;
 
     REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
-    CHECK(instruction.condition == Condition::GE);
+    REQUIRE(instruction.condition == Condition::GE);
 
-    CHECK(swp->rm == 6);
+    REQUIRE(swp->rm == 6);
-    CHECK(swp->rd == 5);
+    REQUIRE(swp->rd == 5);
-    CHECK(swp->rn == 9);
+    REQUIRE(swp->rn == 9);
-    CHECK(swp->byte == false);
+    REQUIRE(swp->byte == false);
 
-    CHECK(instruction.disassemble() == "SWPGE R5,R6,[R9]");
+    REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
 
     swp->byte = true;
-    CHECK(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
+    REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
 }
 
 TEST_CASE("Single Data Transfer", TAG) {
@@ -123,36 +123,36 @@ TEST_CASE("Single Data Transfer", TAG) {
     Shift* shift            = nullptr;
 
     REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
-    CHECK(instruction.condition == Condition::AL);
+    REQUIRE(instruction.condition == Condition::AL);
 
     REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
-    CHECK(shift->rm == 6);
+    REQUIRE(shift->rm == 6);
-    CHECK(shift->data.immediate == true);
+    REQUIRE(shift->data.immediate == true);
-    CHECK(shift->data.type == ShiftType::LSL);
+    REQUIRE(shift->data.type == ShiftType::LSL);
-    CHECK(shift->data.operand == 30);
+    REQUIRE(shift->data.operand == 30);
-    CHECK(ldr->rd == 10);
+    REQUIRE(ldr->rd == 10);
-    CHECK(ldr->rn == 2);
+    REQUIRE(ldr->rn == 2);
-    CHECK(ldr->load == false);
+    REQUIRE(ldr->load == false);
-    CHECK(ldr->write == true);
+    REQUIRE(ldr->write == true);
-    CHECK(ldr->byte == false);
+    REQUIRE(ldr->byte == false);
-    CHECK(ldr->up == true);
+    REQUIRE(ldr->up == true);
-    CHECK(ldr->pre == true);
+    REQUIRE(ldr->pre == true);
 
     ldr->load        = true;
     ldr->byte        = true;
     ldr->write       = false;
     shift->data.type = ShiftType::ROR;
-    CHECK(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
 
     ldr->up  = false;
     ldr->pre = false;
-    CHECK(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
 
     ldr->offset = static_cast<uint16_t>(9023);
-    CHECK(instruction.disassemble() == "LDRB R10,[R2],-#9023");
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
 
     ldr->pre = true;
-    CHECK(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
 }
 
 TEST_CASE("Halfword Transfer", TAG) {
@@ -161,38 +161,38 @@ TEST_CASE("Halfword Transfer", TAG) {
     HalfwordTransfer* ldr = nullptr;
 
     REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
-    CHECK(instruction.condition == Condition::CC);
+    REQUIRE(instruction.condition == Condition::CC);
 
     // offset is not immediate
-    CHECK(ldr->imm == 0);
+    REQUIRE(ldr->imm == 0);
     // hence this offset is a register number (rm)
-    CHECK(ldr->offset == 6);
+    REQUIRE(ldr->offset == 6);
-    CHECK(ldr->half == true);
+    REQUIRE(ldr->half == true);
-    CHECK(ldr->sign == false);
+    REQUIRE(ldr->sign == false);
-    CHECK(ldr->rd == 2);
+    REQUIRE(ldr->rd == 2);
-    CHECK(ldr->rn == 15);
+    REQUIRE(ldr->rn == 15);
-    CHECK(ldr->load == false);
+    REQUIRE(ldr->load == false);
-    CHECK(ldr->write == true);
+    REQUIRE(ldr->write == true);
-    CHECK(ldr->up == true);
+    REQUIRE(ldr->up == true);
-    CHECK(ldr->pre == true);
+    REQUIRE(ldr->pre == true);
 
-    CHECK(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
+    REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
 
     ldr->pre  = false;
     ldr->load = true;
     ldr->sign = true;
     ldr->up   = false;
 
-    CHECK(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
+    REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
 
     ldr->half = false;
-    CHECK(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
+    REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
 
     ldr->load = false;
     // not a register anymore
     ldr->imm    = 1;
     ldr->offset = 90;
-    CHECK(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
+    REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
 }
 
 TEST_CASE("Block Data Transfer", TAG) {
@@ -201,7 +201,7 @@ TEST_CASE("Block Data Transfer", TAG) {
     BlockDataTransfer* ldm = nullptr;
 
     REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
-    CHECK(instruction.condition == Condition::LS);
+    REQUIRE(instruction.condition == Condition::LS);
 
     {
         uint16_t regs = 0;
@@ -213,23 +213,23 @@ TEST_CASE("Block Data Transfer", TAG) {
         regs |= 1 << 8;
         regs |= 1 << 14;
 
-        CHECK(ldm->regs == regs);
+        REQUIRE(ldm->regs == regs);
     }
 
-    CHECK(ldm->rn == 7);
+    REQUIRE(ldm->rn == 7);
-    CHECK(ldm->load == true);
+    REQUIRE(ldm->load == true);
-    CHECK(ldm->write == false);
+    REQUIRE(ldm->write == false);
-    CHECK(ldm->s == true);
+    REQUIRE(ldm->s == true);
-    CHECK(ldm->up == false);
+    REQUIRE(ldm->up == false);
-    CHECK(ldm->pre == true);
+    REQUIRE(ldm->pre == true);
 
-    CHECK(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
+    REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
 
     ldm->write = true;
     ldm->s     = false;
     ldm->up    = true;
 
-    CHECK(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
+    REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
 
     ldm->regs &= ~(1 << 6);
     ldm->regs &= ~(1 << 3);
@@ -237,7 +237,7 @@ TEST_CASE("Block Data Transfer", TAG) {
     ldm->load = false;
     ldm->pre  = false;
 
-    CHECK(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
+    REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
 }
 
 TEST_CASE("PSR Transfer", TAG) {
@@ -249,14 +249,14 @@ TEST_CASE("PSR Transfer", TAG) {
         PsrTransfer* mrs = nullptr;
 
         REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
-        CHECK(instruction.condition == Condition::MI);
+        REQUIRE(instruction.condition == Condition::MI);
 
-        CHECK(mrs->type == PsrTransfer::Type::Mrs);
+        REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
         // Operand is a register in the case of MRS (PSR -> Register)
-        CHECK(mrs->operand == 10);
+        REQUIRE(mrs->operand == 10);
-        CHECK(mrs->spsr == true);
+        REQUIRE(mrs->spsr == true);
 
-        CHECK(instruction.disassemble() == "MRSMI R10,SPSR_all");
+        REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
     }
 
     SECTION("MSR") {
@@ -265,14 +265,14 @@ TEST_CASE("PSR Transfer", TAG) {
         PsrTransfer* msr = nullptr;
 
         REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
-        CHECK(instruction.condition == Condition::AL);
+        REQUIRE(instruction.condition == Condition::AL);
 
-        CHECK(msr->type == PsrTransfer::Type::Msr);
+        REQUIRE(msr->type == PsrTransfer::Type::Msr);
         // Operand is a register in the case of MSR (Register -> PSR)
-        CHECK(msr->operand == 8);
+        REQUIRE(msr->operand == 8);
-        CHECK(msr->spsr == false);
+        REQUIRE(msr->spsr == false);
 
-        CHECK(instruction.disassemble() == "MSR CPSR_all,R8");
+        REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
     }
 
     SECTION("MSR_flg with register operand") {
@@ -280,14 +280,14 @@ TEST_CASE("PSR Transfer", TAG) {
         Instruction instruction(raw);
 
         REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
-        CHECK(instruction.condition == Condition::VS);
+        REQUIRE(instruction.condition == Condition::VS);
 
-        CHECK(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
-        CHECK(msr->imm == 0);
+        REQUIRE(msr->imm == 0);
-        CHECK(msr->operand == 8);
+        REQUIRE(msr->operand == 8);
-        CHECK(msr->spsr == false);
+        REQUIRE(msr->spsr == false);
 
-        CHECK(instruction.disassemble() == "MSRVS CPSR_flg,R8");
+        REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
     }
 
     SECTION("MSR_flg with immediate operand") {
@@ -295,102 +295,100 @@ TEST_CASE("PSR Transfer", TAG) {
         Instruction instruction(raw);
 
         REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
-        CHECK(instruction.condition == Condition::AL);
+        REQUIRE(instruction.condition == Condition::AL);
 
-        CHECK(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
-        CHECK(msr->imm == 1);
+        REQUIRE(msr->imm == 1);
 
         // 104 (32 bits) rotated by 2 * 7
-        CHECK(msr->operand == 27262976);
+        REQUIRE(msr->operand == 27262976);
-        CHECK(msr->spsr == true);
+        REQUIRE(msr->spsr == true);
 
-        CHECK(instruction.disassemble() == "MSR SPSR_flg,#27262976");
+        REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
     }
 }
 
 TEST_CASE("Data Processing", TAG) {
-    using OpCode = DataProcessing::OpCode;
-
     uint32_t raw = 0b11100000000111100111101101100001;
     Instruction instruction(raw);
     DataProcessing* alu = nullptr;
     Shift* shift        = nullptr;
 
     REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
-    CHECK(instruction.condition == Condition::AL);
+    REQUIRE(instruction.condition == Condition::AL);
 
     // operand 2 is a shifted register
     REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
-    CHECK(shift->rm == 1);
+    REQUIRE(shift->rm == 1);
-    CHECK(shift->data.immediate == true);
+    REQUIRE(shift->data.immediate == true);
-    CHECK(shift->data.type == ShiftType::ROR);
+    REQUIRE(shift->data.type == ShiftType::ROR);
-    CHECK(shift->data.operand == 22);
+    REQUIRE(shift->data.operand == 22);
 
-    CHECK(alu->rd == 7);
+    REQUIRE(alu->rd == 7);
-    CHECK(alu->rn == 14);
+    REQUIRE(alu->rn == 14);
-    CHECK(alu->set == true);
+    REQUIRE(alu->set == true);
-    CHECK(alu->opcode == OpCode::AND);
+    REQUIRE(alu->opcode == OpCode::AND);
 
-    CHECK(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
+    REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
 
     shift->data.immediate = false;
     shift->data.operand   = 2;
     alu->set              = false;
 
-    CHECK(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
+    REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
 
     alu->operand = static_cast<uint32_t>(3300012);
-    CHECK(instruction.disassemble() == "AND R7,R14,#3300012");
+    REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
 
     SECTION("set-only operations") {
         alu->set = true;
 
         alu->opcode = OpCode::TST;
-        CHECK(instruction.disassemble() == "TST R14,#3300012");
+        REQUIRE(instruction.disassemble() == "TST R14,#3300012");
 
         alu->opcode = OpCode::TEQ;
-        CHECK(instruction.disassemble() == "TEQ R14,#3300012");
+        REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
 
         alu->opcode = OpCode::CMP;
-        CHECK(instruction.disassemble() == "CMP R14,#3300012");
+        REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
 
         alu->opcode = OpCode::CMN;
-        CHECK(instruction.disassemble() == "CMN R14,#3300012");
+        REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
     }
 
     SECTION("destination operations") {
         alu->opcode = OpCode::EOR;
-        CHECK(instruction.disassemble() == "EOR R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
 
         alu->opcode = OpCode::SUB;
-        CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
 
         alu->opcode = OpCode::RSB;
-        CHECK(instruction.disassemble() == "RSB R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
 
         alu->opcode = OpCode::SUB;
-        CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
 
         alu->opcode = OpCode::ADC;
-        CHECK(instruction.disassemble() == "ADC R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
 
         alu->opcode = OpCode::SBC;
-        CHECK(instruction.disassemble() == "SBC R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
 
         alu->opcode = OpCode::RSC;
-        CHECK(instruction.disassemble() == "RSC R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
 
         alu->opcode = OpCode::ORR;
-        CHECK(instruction.disassemble() == "ORR R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
 
         alu->opcode = OpCode::MOV;
-        CHECK(instruction.disassemble() == "MOV R7,#3300012");
+        REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
 
         alu->opcode = OpCode::BIC;
-        CHECK(instruction.disassemble() == "BIC R7,R14,#3300012");
+        REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
 
         alu->opcode = OpCode::MVN;
-        CHECK(instruction.disassemble() == "MVN R7,#3300012");
+        REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
     }
 }
 
@@ -400,26 +398,26 @@ TEST_CASE("Coprocessor Data Transfer", TAG) {
     CoprocessorDataTransfer* ldc = nullptr;
 
     REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
-    CHECK(instruction.condition == Condition::GE);
+    REQUIRE(instruction.condition == Condition::GE);
 
-    CHECK(ldc->offset == 70);
+    REQUIRE(ldc->offset == 70);
-    CHECK(ldc->cpn == 1);
+    REQUIRE(ldc->cpn == 1);
-    CHECK(ldc->crd == 15);
+    REQUIRE(ldc->crd == 15);
-    CHECK(ldc->rn == 5);
+    REQUIRE(ldc->rn == 5);
-    CHECK(ldc->load == false);
+    REQUIRE(ldc->load == false);
-    CHECK(ldc->write == true);
+    REQUIRE(ldc->write == true);
-    CHECK(ldc->len == false);
+    REQUIRE(ldc->len == false);
-    CHECK(ldc->up == true);
+    REQUIRE(ldc->up == true);
-    CHECK(ldc->pre == true);
+    REQUIRE(ldc->pre == true);
 
-    CHECK(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
+    REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
 
     ldc->load  = true;
     ldc->pre   = false;
     ldc->write = false;
     ldc->len   = true;
 
-    CHECK(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
+    REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
 }
 
 TEST_CASE("Coprocessor Operand Operation", TAG) {
@@ -428,16 +426,16 @@ TEST_CASE("Coprocessor Operand Operation", TAG) {
     CoprocessorDataOperation* cdp = nullptr;
 
     REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
-    CHECK(instruction.condition == Condition::AL);
+    REQUIRE(instruction.condition == Condition::AL);
 
-    CHECK(cdp->crm == 6);
+    REQUIRE(cdp->crm == 6);
-    CHECK(cdp->cp == 2);
+    REQUIRE(cdp->cp == 2);
-    CHECK(cdp->cpn == 1);
+    REQUIRE(cdp->cpn == 1);
-    CHECK(cdp->crd == 15);
+    REQUIRE(cdp->crd == 15);
-    CHECK(cdp->crn == 5);
+    REQUIRE(cdp->crn == 5);
-    CHECK(cdp->cp_opc == 10);
+    REQUIRE(cdp->cp_opc == 10);
 
-    CHECK(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
+    REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
 }
 
 TEST_CASE("Coprocessor Register Transfer", TAG) {
@@ -447,23 +445,25 @@ TEST_CASE("Coprocessor Register Transfer", TAG) {
 
     REQUIRE(
       (mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
-    CHECK(instruction.condition == Condition::AL);
+    REQUIRE(instruction.condition == Condition::AL);
 
-    CHECK(mrc->crm == 6);
+    REQUIRE(mrc->crm == 6);
-    CHECK(mrc->cp == 2);
+    REQUIRE(mrc->cp == 2);
-    CHECK(mrc->cpn == 1);
+    REQUIRE(mrc->cpn == 1);
-    CHECK(mrc->rd == 15);
+    REQUIRE(mrc->rd == 15);
-    CHECK(mrc->crn == 5);
+    REQUIRE(mrc->crn == 5);
-    CHECK(mrc->load == false);
+    REQUIRE(mrc->load == false);
-    CHECK(mrc->cp_opc == 5);
+    REQUIRE(mrc->cp_opc == 5);
 
-    CHECK(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
+    REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
 }
 
 TEST_CASE("Software Interrupt", TAG) {
     uint32_t raw = 0b00001111101010101010101010101010;
     Instruction instruction(raw);
 
-    CHECK(instruction.condition == Condition::EQ);
+    REQUIRE(instruction.condition == Condition::EQ);
-    CHECK(instruction.disassemble() == "SWIEQ");
+    REQUIRE(instruction.disassemble() == "SWIEQ");
 }
+
+#undef TAG

tests/cpu/instruction.cc

@@ -0,0 +1,467 @@
+#include "cpu/arm/instruction.hh"
+#include "cpu/utility.hh"
+#include <catch2/catch_test_macros.hpp>
+
+[[maybe_unused]] static constexpr auto TAG = "disassembler";
+
+using namespace arm;
+
+TEST_CASE("Branch and Exchange", TAG) {
+    uint32_t raw = 0b11000001001011111111111100011010;
+    Instruction instruction(raw);
+    BranchAndExchange* bx = nullptr;
+
+    REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GT);
+
+    REQUIRE(bx->rn == 10);
+
+    REQUIRE(instruction.disassemble() == "BXGT R10");
+}
+
+TEST_CASE("Branch", TAG) {
+    uint32_t raw = 0b11101011100001010111111111000011;
+    Instruction instruction(raw);
+    Branch* b = nullptr;
+
+    REQUIRE((b = std::get_if<Branch>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    // last 24 bits = 8748995
+    // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
+    // Also +8 since PC is two instructions ahead
+    REQUIRE(b->offset == 0xFE15FF14);
+    REQUIRE(b->link == true);
+
+    REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
+
+    b->link = false;
+    REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
+}
+
+TEST_CASE("Multiply", TAG) {
+    uint32_t raw = 0b00000000001110101110111110010000;
+    Instruction instruction(raw);
+    Multiply* mul = nullptr;
+
+    REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::EQ);
+
+    REQUIRE(mul->rm == 0);
+    REQUIRE(mul->rs == 15);
+    REQUIRE(mul->rn == 14);
+    REQUIRE(mul->rd == 10);
+    REQUIRE(mul->acc == true);
+    REQUIRE(mul->set == true);
+
+    REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
+
+    mul->acc = false;
+    mul->set = false;
+    REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
+}
+
+TEST_CASE("Multiply Long", TAG) {
+    uint32_t raw = 0b00010000100111100111011010010010;
+    Instruction instruction(raw);
+    MultiplyLong* mull = nullptr;
+
+    REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::NE);
+
+    REQUIRE(mull->rm == 2);
+    REQUIRE(mull->rs == 6);
+    REQUIRE(mull->rdlo == 7);
+    REQUIRE(mull->rdhi == 14);
+    REQUIRE(mull->acc == false);
+    REQUIRE(mull->set == true);
+    REQUIRE(mull->uns == false);
+
+    REQUIRE(instruction.disassemble() == "SMULLNES R7,R14,R2,R6");
+
+    mull->acc = true;
+    REQUIRE(instruction.disassemble() == "SMLALNES R7,R14,R2,R6");
+
+    mull->uns = true;
+    mull->set = false;
+    REQUIRE(instruction.disassemble() == "UMLALNE R7,R14,R2,R6");
+}
+
+TEST_CASE("Undefined", TAG) {
+    // notice how this is the same as single data transfer except the shift
+    // is now a register based shift
+    uint32_t raw = 0b11100111101000101010111100010110;
+    Instruction instruction(raw);
+
+    REQUIRE(instruction.condition == Condition::AL);
+    REQUIRE(instruction.disassemble() == "UND");
+}
+
+TEST_CASE("Single Data Swap", TAG) {
+    uint32_t raw = 0b10100001000010010101000010010110;
+    Instruction instruction(raw);
+    SingleDataSwap* swp = nullptr;
+
+    REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GE);
+
+    REQUIRE(swp->rm == 6);
+    REQUIRE(swp->rd == 5);
+    REQUIRE(swp->rn == 9);
+    REQUIRE(swp->byte == false);
+
+    REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
+
+    swp->byte = true;
+    REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
+}
+
+TEST_CASE("Single Data Transfer", TAG) {
+    uint32_t raw = 0b11100111101000101010111100000110;
+    Instruction instruction(raw);
+    SingleDataTransfer* ldr = nullptr;
+    Shift* shift            = nullptr;
+
+    REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
+    REQUIRE(shift->rm == 6);
+    REQUIRE(shift->data.immediate == true);
+    REQUIRE(shift->data.type == ShiftType::LSL);
+    REQUIRE(shift->data.operand == 30);
+    REQUIRE(ldr->rd == 10);
+    REQUIRE(ldr->rn == 2);
+    REQUIRE(ldr->load == false);
+    REQUIRE(ldr->write == true);
+    REQUIRE(ldr->byte == false);
+    REQUIRE(ldr->up == true);
+    REQUIRE(ldr->pre == true);
+
+    ldr->load        = true;
+    ldr->byte        = true;
+    ldr->write       = false;
+    shift->data.type = ShiftType::ROR;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
+
+    ldr->up  = false;
+    ldr->pre = false;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
+
+    ldr->offset = static_cast<uint16_t>(9023);
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
+
+    ldr->pre = true;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
+}
+
+TEST_CASE("Halfword Transfer", TAG) {
+    uint32_t raw = 0b00110001101011110010000010110110;
+    Instruction instruction(raw);
+    HalfwordTransfer* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::CC);
+
+    // offset is not immediate
+    REQUIRE(ldr->imm == 0);
+    // hence this offset is a register number (rm)
+    REQUIRE(ldr->offset == 6);
+    REQUIRE(ldr->half == true);
+    REQUIRE(ldr->sign == false);
+    REQUIRE(ldr->rd == 2);
+    REQUIRE(ldr->rn == 15);
+    REQUIRE(ldr->load == false);
+    REQUIRE(ldr->write == true);
+    REQUIRE(ldr->up == true);
+    REQUIRE(ldr->pre == true);
+
+    REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
+
+    ldr->pre  = false;
+    ldr->load = true;
+    ldr->sign = true;
+    ldr->up   = false;
+
+    REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
+
+    ldr->half = false;
+    REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
+
+    ldr->load = false;
+    // not a register anymore
+    ldr->imm    = 1;
+    ldr->offset = 90;
+    REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
+}
+
+TEST_CASE("Block Data Transfer", TAG) {
+    uint32_t raw = 0b10011001010101110100000101101101;
+    Instruction instruction(raw);
+    BlockDataTransfer* ldm = nullptr;
+
+    REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::LS);
+
+    {
+        uint16_t regs = 0;
+        regs |= 1 << 0;
+        regs |= 1 << 2;
+        regs |= 1 << 3;
+        regs |= 1 << 5;
+        regs |= 1 << 6;
+        regs |= 1 << 8;
+        regs |= 1 << 14;
+
+        REQUIRE(ldm->regs == regs);
+    }
+
+    REQUIRE(ldm->rn == 7);
+    REQUIRE(ldm->load == true);
+    REQUIRE(ldm->write == false);
+    REQUIRE(ldm->s == true);
+    REQUIRE(ldm->up == false);
+    REQUIRE(ldm->pre == true);
+
+    REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
+
+    ldm->write = true;
+    ldm->s     = false;
+    ldm->up    = true;
+
+    REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
+
+    ldm->regs &= ~(1 << 6);
+    ldm->regs &= ~(1 << 3);
+    ldm->regs &= ~(1 << 8);
+    ldm->load = false;
+    ldm->pre  = false;
+
+    REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
+}
+
+TEST_CASE("PSR Transfer", TAG) {
+    PsrTransfer* msr = nullptr;
+
+    SECTION("MRS") {
+        uint32_t raw = 0b01000001010011111010000000000000;
+        Instruction instruction(raw);
+        PsrTransfer* mrs = nullptr;
+
+        REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::MI);
+
+        REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
+        // Operand is a register in the case of MRS (PSR -> Register)
+        REQUIRE(mrs->operand == 10);
+        REQUIRE(mrs->spsr == true);
+
+        REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
+    }
+
+    SECTION("MSR") {
+        uint32_t raw = 0b11100001001010011111000000001000;
+        Instruction instruction(raw);
+        PsrTransfer* msr = nullptr;
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::AL);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr);
+        // Operand is a register in the case of MSR (Register -> PSR)
+        REQUIRE(msr->operand == 8);
+        REQUIRE(msr->spsr == false);
+
+        REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
+    }
+
+    SECTION("MSR_flg with register operand") {
+        uint32_t raw = 0b01100001001010001111000000001000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::VS);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->imm == 0);
+        REQUIRE(msr->operand == 8);
+        REQUIRE(msr->spsr == false);
+
+        REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
+    }
+
+    SECTION("MSR_flg with immediate operand") {
+        uint32_t raw = 0b11100011011010001111011101101000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::AL);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->imm == 1);
+
+        // 104 (32 bits) rotated by 2 * 7
+        REQUIRE(msr->operand == 27262976);
+        REQUIRE(msr->spsr == true);
+
+        REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
+    }
+}
+
+TEST_CASE("Data Processing", TAG) {
+    uint32_t raw = 0b11100010000111100111101101100001;
+    Instruction instruction(raw);
+    DataProcessing* alu = nullptr;
+    Shift* shift        = nullptr;
+
+    REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    // operand 2 is a shifted register
+    REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
+    REQUIRE(shift->rm == 1);
+    REQUIRE(shift->data.immediate == true);
+    REQUIRE(shift->data.type == ShiftType::ROR);
+    REQUIRE(shift->data.operand == 22);
+
+    REQUIRE(alu->rd == 7);
+    REQUIRE(alu->rn == 14);
+    REQUIRE(alu->set == true);
+    REQUIRE(alu->opcode == OpCode::AND);
+
+    REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
+
+    shift->data.immediate = false;
+    shift->data.operand   = 2;
+    alu->set              = false;
+
+    REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
+
+    alu->operand = static_cast<uint32_t>(3300012);
+    REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
+
+    SECTION("set-only operations") {
+        alu->set = true;
+
+        alu->opcode = OpCode::TST;
+        REQUIRE(instruction.disassemble() == "TST R14,#3300012");
+
+        alu->opcode = OpCode::TEQ;
+        REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
+
+        alu->opcode = OpCode::CMP;
+        REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
+
+        alu->opcode = OpCode::CMN;
+        REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
+    }
+
+    SECTION("destination operations") {
+        alu->opcode = OpCode::EOR;
+        REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSB;
+        REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::ADC;
+        REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
+
+        alu->opcode = OpCode::SBC;
+        REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSC;
+        REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
+
+        alu->opcode = OpCode::ORR;
+        REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
+
+        alu->opcode = OpCode::MOV;
+        REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
+
+        alu->opcode = OpCode::BIC;
+        REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
+
+        alu->opcode = OpCode::MVN;
+        REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
+    }
+}
+
+TEST_CASE("Coprocessor Data Transfer", TAG) {
+    uint32_t raw = 0b10101101101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataTransfer* ldc = nullptr;
+
+    REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GE);
+
+    REQUIRE(ldc->offset == 70);
+    REQUIRE(ldc->cpn == 1);
+    REQUIRE(ldc->crd == 15);
+    REQUIRE(ldc->rn == 5);
+    REQUIRE(ldc->load == false);
+    REQUIRE(ldc->write == true);
+    REQUIRE(ldc->len == false);
+    REQUIRE(ldc->up == true);
+    REQUIRE(ldc->pre == true);
+
+    REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
+
+    ldc->load  = true;
+    ldc->pre   = false;
+    ldc->write = false;
+    ldc->len   = true;
+
+    REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
+}
+
+TEST_CASE("Coprocessor Operand Operation", TAG) {
+    uint32_t raw = 0b11101110101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataOperation* cdp = nullptr;
+
+    REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE(cdp->crm == 6);
+    REQUIRE(cdp->cp == 2);
+    REQUIRE(cdp->cpn == 1);
+    REQUIRE(cdp->crd == 15);
+    REQUIRE(cdp->crn == 5);
+    REQUIRE(cdp->cp_opc == 10);
+
+    REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
+}
+
+TEST_CASE("Coprocessor Register Transfer", TAG) {
+    uint32_t raw = 0b11101110101001011111000101010110;
+    Instruction instruction(raw);
+    CoprocessorRegisterTransfer* mrc = nullptr;
+
+    REQUIRE(
+      (mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE(mrc->crm == 6);
+    REQUIRE(mrc->cp == 2);
+    REQUIRE(mrc->cpn == 1);
+    REQUIRE(mrc->rd == 15);
+    REQUIRE(mrc->crn == 5);
+    REQUIRE(mrc->load == false);
+    REQUIRE(mrc->cp_opc == 5);
+
+    REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
+}
+
+TEST_CASE("Software Interrupt", TAG) {
+    uint32_t raw = 0b00001111101010101010101010101010;
+    Instruction instruction(raw);
+
+    REQUIRE(instruction.condition == Condition::EQ);
+    REQUIRE(instruction.disassemble() == "SWIEQ");
+}

tests/main.cc

@@ -1,8 +0,0 @@
-#include "util/loglevel.hh"
-#include <catch2/catch_session.hpp>
-
-int
-main(int argc, char* argv[]) {
-    matar::set_log_level(matar::LogLevel::Off);
-    return Catch::Session().run(argc, argv);
-}

tests/memory.cc

@@ -1,121 +0,0 @@
-#include "memory.hh"
-#include <catch2/catch_test_macros.hpp>
-
-static constexpr auto TAG = "[memory]";
-
-using namespace matar;
-
-class MemFixture {
-  public:
-    MemFixture()
-      : memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
-               std::vector<uint8_t>(Header::HEADER_SIZE)) {}
-
-  protected:
-    Memory memory;
-};
-
-TEST_CASE_METHOD(MemFixture, "bios", TAG) {
-    memory.write(0, 0xAC);
-    CHECK(memory.read(0) == 0xAC);
-
-    memory.write(0x3FFF, 0x48);
-    CHECK(memory.read(0x3FFF) == 0x48);
-
-    memory.write(0x2A56, 0x10);
-    CHECK(memory.read(0x2A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "board wram", TAG) {
-    memory.write(0x2000000, 0xAC);
-    CHECK(memory.read(0x2000000) == 0xAC);
-
-    memory.write(0x203FFFF, 0x48);
-    CHECK(memory.read(0x203FFFF) == 0x48);
-
-    memory.write(0x2022A56, 0x10);
-    CHECK(memory.read(0x2022A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "chip wram", TAG) {
-    memory.write(0x3000000, 0xAC);
-    CHECK(memory.read(0x3000000) == 0xAC);
-
-    memory.write(0x3007FFF, 0x48);
-    CHECK(memory.read(0x3007FFF) == 0x48);
-
-    memory.write(0x3002A56, 0x10);
-    CHECK(memory.read(0x3002A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "palette ram", TAG) {
-    memory.write(0x5000000, 0xAC);
-    CHECK(memory.read(0x5000000) == 0xAC);
-
-    memory.write(0x50003FF, 0x48);
-    CHECK(memory.read(0x50003FF) == 0x48);
-
-    memory.write(0x5000156, 0x10);
-    CHECK(memory.read(0x5000156) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "video ram", TAG) {
-    memory.write(0x6000000, 0xAC);
-    CHECK(memory.read(0x6000000) == 0xAC);
-
-    memory.write(0x6017FFF, 0x48);
-    CHECK(memory.read(0x6017FFF) == 0x48);
-
-    memory.write(0x6012A56, 0x10);
-    CHECK(memory.read(0x6012A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "oam obj ram", TAG) {
-    memory.write(0x7000000, 0xAC);
-    CHECK(memory.read(0x7000000) == 0xAC);
-
-    memory.write(0x70003FF, 0x48);
-    CHECK(memory.read(0x70003FF) == 0x48);
-
-    memory.write(0x7000156, 0x10);
-    CHECK(memory.read(0x7000156) == 0x10);
-}
-
-TEST_CASE("rom", TAG) {
-    // 32 megabyte ROM
-    Memory memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
-                  std::vector<uint8_t>(32 * 1024 * 1024));
-
-    SECTION("ROM1") {
-        memory.write(0x8000000, 0xAC);
-        CHECK(memory.read(0x8000000) == 0xAC);
-
-        memory.write(0x9FFFFFF, 0x48);
-        CHECK(memory.read(0x9FFFFFF) == 0x48);
-
-        memory.write(0x8ef0256, 0x10);
-        CHECK(memory.read(0x8ef0256) == 0x10);
-    }
-
-    SECTION("ROM2") {
-        memory.write(0xA000000, 0xAC);
-        CHECK(memory.read(0xA000000) == 0xAC);
-
-        memory.write(0xBFFFFFF, 0x48);
-        CHECK(memory.read(0xBFFFFFF) == 0x48);
-
-        memory.write(0xAEF0256, 0x10);
-        CHECK(memory.read(0xAEF0256) == 0x10);
-    }
-
-    SECTION("ROM3") {
-        memory.write(0xC000000, 0xAC);
-        CHECK(memory.read(0xC000000) == 0xAC);
-
-        memory.write(0xDFFFFFF, 0x48);
-        CHECK(memory.read(0xDFFFFFF) == 0x48);
-
-        memory.write(0xCEF0256, 0x10);
-        CHECK(memory.read(0xCEF0256) == 0x10);
-    }
-}

tests/meson.build

@@ -2,25 +2,18 @@ tests_deps = [
   lib
 ]
 
-src = include_directories('../src')
+tests_sources = files()
-
-tests_sources = files(
-  'main.cc',
-  'bus.cc',
-  'memory.cc'
-)
 
 subdir('cpu')
-subdir('util')
 
-catch2 = dependency('catch2', version: '>=3.4.0', static: true)
+catch2 = dependency('catch2-with-main', version: '>=3.4.0', static: true)
 catch2_tests = executable(
-  'matar_tests',
+  meson.project_name() + '_tests',
   tests_sources,
   dependencies: catch2,
   link_with: tests_deps,
-  include_directories: [inc, src],
+  include_directories: inc,
-  build_by_default: false,
+  build_by_default: false
 )
 
 test('catch2 tests', catch2_tests)

tests/util/bits.cc

@@ -1,106 +0,0 @@
-#include "util/bits.hh"
-#include <catch2/catch_test_macros.hpp>
-
-static constexpr auto TAG = "[util][bits]";
-
-TEST_CASE("8 bits", TAG) {
-    uint8_t num = 45;
-
-    CHECK(get_bit(num, 0));
-    CHECK(!get_bit(num, 1));
-    CHECK(get_bit(num, 5));
-    CHECK(!get_bit(num, 6));
-    CHECK(!get_bit(num, 7));
-
-    set_bit(num, 6);
-    CHECK(get_bit(num, 6));
-
-    rst_bit(num, 6);
-    CHECK(!get_bit(num, 6));
-
-    chg_bit(num, 5, false);
-    CHECK(!get_bit(num, 5));
-
-    chg_bit(num, 5, true);
-    CHECK(get_bit(num, 5));
-
-    // 0b0110
-    CHECK(bit_range(num, 1, 4) == 6);
-}
-
-TEST_CASE("16 bits", TAG) {
-    uint16_t num = 34587;
-
-    CHECK(get_bit(num, 0));
-    CHECK(get_bit(num, 1));
-    CHECK(!get_bit(num, 5));
-    CHECK(!get_bit(num, 14));
-    CHECK(get_bit(num, 15));
-
-    set_bit(num, 14);
-    CHECK(get_bit(num, 14));
-
-    rst_bit(num, 14);
-    CHECK(!get_bit(num, 14));
-
-    chg_bit(num, 5, true);
-    CHECK(get_bit(num, 5));
-
-    // num = 45
-    chg_bit(num, 5, false);
-    CHECK(!get_bit(num, 5));
-
-    // 0b1000110
-    CHECK(bit_range(num, 2, 8) == 70);
-}
-
-TEST_CASE("32 bits", TAG) {
-    uint32_t num = 3194142523;
-
-    CHECK(get_bit(num, 0));
-    CHECK(get_bit(num, 1));
-    CHECK(get_bit(num, 12));
-    CHECK(get_bit(num, 29));
-    CHECK(!get_bit(num, 30));
-    CHECK(get_bit(num, 31));
-
-    set_bit(num, 30);
-    CHECK(get_bit(num, 30));
-
-    rst_bit(num, 30);
-    CHECK(!get_bit(num, 30));
-
-    chg_bit(num, 12, false);
-    CHECK(!get_bit(num, 12));
-
-    chg_bit(num, 12, true);
-    CHECK(get_bit(num, 12));
-
-    // 0b10011000101011111100111
-    CHECK(bit_range(num, 3, 25) == 5003239);
-}
-
-TEST_CASE("64 bits", TAG) {
-    uint64_t num = 58943208889991935;
-
-    CHECK(get_bit(num, 0));
-    CHECK(get_bit(num, 1));
-    CHECK(!get_bit(num, 10));
-    CHECK(get_bit(num, 55));
-    CHECK(!get_bit(num, 60));
-
-    set_bit(num, 63);
-    CHECK(get_bit(num, 63));
-
-    rst_bit(num, 63);
-    CHECK(!get_bit(num, 63));
-
-    chg_bit(num, 10, true);
-    CHECK(get_bit(num, 10));
-
-    chg_bit(num, 10, false);
-    CHECK(!get_bit(num, 10));
-
-    // 0b011010001
-    CHECK(bit_range(num, 39, 47) == 209);
-}

tests/util/crypto.cc

@@ -1,21 +0,0 @@
-#include "util/crypto.hh"
-#include <catch2/catch_test_macros.hpp>
-
-static constexpr auto TAG = "[util][crypto]";
-
-TEST_CASE("sha256 matar", TAG) {
-    std::array<uint8_t, 5> data = { 'm', 'a', 't', 'a', 'r' };
-
-    CHECK(crypto::sha256(data) ==
-          "3b02a908fd5743c0e868675bb6ae77d2a62b3b5f7637413238e2a1e0e94b6a53");
-}
-
-TEST_CASE("sha256 forgis", TAG) {
-    std::array<uint8_t, 32> data = { 'i', ' ', 'p', 'u', 't', ' ', 't', 'h',
-                                     'e', ' ', 'n', 'e', 'w', ' ', 'f', 'o',
-                                     'r', 'g', 'i', 's', ' ', 'o', 'n', ' ',
-                                     't', 'h', 'e', ' ', 'j', 'e', 'e', 'p' };
-
-    CHECK(crypto::sha256(data) ==
-          "cfddca2ce2673f355518cbe2df2a8522693c54723a469e8b36a4f68b90d2b759");
-}

tests/util/meson.build

@@ -1,4 +0,0 @@
-tests_sources += files(
-  'bits.cc',
-  'crypto.cc'
-)