tests: add tests for memory

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

.clang-tidy

@@ -0,0 +1,10 @@
+Checks: '
+  , clang-analyzer-*
+  , cppcoreguidelines-*
+  , -cppcoreguidelines-avoid-magic-numbers
+  , -cppcoreguidelines-pro-bounds-constant-array-index
+  , -cppcoreguidelines-macro-usage
+  , -cppcoreguidelines-avoid-const-or-ref-data-members
+  , -cppcoreguidelines-non-private-member-variables-in-classes
+  , -cppcoreguidelines-avoid-non-const-global-variables
+'

.github/workflows/clang.yml

@@ -0,0 +1,36 @@
+name: matar-clang
+on: [push, pull_request, workflow_dispatch]
+
+env:
+  BUILDDIR: build
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - uses: cachix/install-nix-action@v20
+        with:
+          extra_nix_config: |
+            auto-optimise-store = true
+            experimental-features = nix-command flakes
+      - uses: cachix/cachix-action@v12
+        with:
+          name: pain
+          authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
+
+
+      - name: setup
+        run: nix develop .#matar-clang -c meson setup $BUILDDIR
+
+      - name: fmt
+        run: nix develop .#matar-clang -c ninja clang-format-check -C $BUILDDIR
+
+      - name: lint
+        run: nix develop .#matar-clang -c ninja clang-tidy -C $BUILDDIR
+
+      - name: tests
+        run: nix develop .#matar-clang -c ninja test -C $BUILDDIR
+
+      - name: build
+        run: nix develop .#matar-clang -c ninja -C $BUILDDIR

.github/workflows/gcc.yml

@@ -0,0 +1,30 @@
+name: matar-gcc
+on: [push, pull_request, workflow_dispatch]
+
+env:
+  BUILDDIR: build
+
+jobs:
+  build:
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v3
+      - uses: cachix/install-nix-action@v20
+        with:
+          extra_nix_config: |
+            auto-optimise-store = true
+            experimental-features = nix-command flakes
+      - uses: cachix/cachix-action@v12
+        with:
+          name: pain
+          authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
+
+
+      - name: setup
+        run: nix develop .#matar -c meson setup $BUILDDIR
+
+      - name: tests
+        run: nix develop .#matar -c ninja test -C $BUILDDIR
+
+      - name: build
+        run: nix develop .#matar -c ninja -C $BUILDDIR

README

@@ -1 +0,0 @@
-nothing to be seen here yet. LEAVE

README.md

@@ -0,0 +1,22 @@
+nothing to be seen here yet. LEAVE
+
+But if you are curious (probably not), read ahead
+
+# Dependencies
+## Tested toolchains
+
+- LLVM 16.0.6
+- GCC 12.3.0
+
+In theory, any toolchain supporting at least the C++20 standard should work.
+I am using LLVM's clang and libcxx as the primary toolchain.
+
+## Static libraries
+
+| Name   | Version   | Required? |
+|:------:|:----------|:---------:|
+| fmt    | >= 10.1.1 | yes       |
+| catch2 | >= 3.4    | for tests |
+
+This goes without saying but using a different toolchain to compile these libraries before linking probably won't work.
+I will add meson wrap support once LLVM 17 is out, since I want to get rid of fmt.

apps/target/main.cc

@@ -1,12 +1,23 @@
+#include "bus.hh"
+#include "cpu/cpu.hh"
 #include "memory.hh"
+#include "util/loglevel.hh"
 #include <array>
 #include <cstdlib>
 #include <fstream>
 #include <iostream>
+#include <memory>
+#include <ostream>
+#include <unistd.h>
 #include <vector>
 
+// NOLINTBEGIN
+
 int
 main(int argc, const char* argv[]) {
+    std::vector<uint8_t> rom;
+    std::array<uint8_t, matar::Memory::BIOS_SIZE> bios = { 0 };
+
     auto usage = [argv]() {
         std::cerr << "Usage: " << argv[0] << " <file> [-b <bios>]" << std::endl;
         std::exit(EXIT_FAILURE);
@@ -35,8 +46,6 @@ main(int argc, const char* argv[]) {
 
     try {
         std::ifstream ifile(rom_file, std::ios::in | std::ios::binary);
-        std::vector<uint8_t> rom;
-        std::array<uint8_t, Memory::BIOS_SIZE> bios;
         std::streampos bios_size;
 
         if (!ifile.is_open()) {
@@ -57,7 +66,7 @@ main(int argc, const char* argv[]) {
         ifile.seekg(0, std::ios::end);
         bios_size = ifile.tellg();
 
-        if (bios_size != Memory::BIOS_SIZE) {
+        if (bios_size != matar::Memory::BIOS_SIZE) {
             throw std::ios::failure("BIOS file has invalid size",
                                     std::error_code());
         }
@@ -68,7 +77,24 @@ main(int argc, const char* argv[]) {
 
         ifile.close();
 
-        Memory memory(std::move(bios), std::move(rom));
+    } catch (const std::exception& e) {
+        std::cerr << "Exception: " << e.what() << std::endl;
+        return 1;
+    }
+
+    std::flush(std::cout);
+    std::flush(std::cout);
+
+    matar::set_log_level(matar::LogLevel::Debug);
+
+    try {
+        matar::Memory memory(std::move(bios), std::move(rom));
+        matar::Bus bus(memory);
+        matar::Cpu cpu(bus);
+        while (true) {
+            cpu.step();
+            sleep(2);
+        }
     } catch (const std::exception& e) {
         std::cerr << "Exception: " << e.what() << std::endl;
         return 1;
@@ -76,3 +102,5 @@ main(int argc, const char* argv[]) {
 
     return 0;
 }
+
+// NOLINTEND

apps/target/meson.build

@@ -7,7 +7,7 @@ target_sources = files(
 )
 
 executable(
-  meson.project_name(),
+  'matar',
   target_sources,
   link_with: target_deps,
   include_directories: inc,

flake.lock

@@ -1,12 +1,30 @@
 {
   "nodes": {
+    "flake-parts": {
+      "inputs": {
+        "nixpkgs-lib": "nixpkgs-lib"
+      },
+      "locked": {
+        "lastModified": 1693611461,
+        "narHash": "sha256-aPODl8vAgGQ0ZYFIRisxYG5MOGSkIczvu2Cd8Gb9+1Y=",
+        "owner": "hercules-ci",
+        "repo": "flake-parts",
+        "rev": "7f53fdb7bdc5bb237da7fefef12d099e4fd611ca",
+        "type": "github"
+      },
+      "original": {
+        "owner": "hercules-ci",
+        "repo": "flake-parts",
+        "type": "github"
+      }
+    },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1692007866,
+        "lastModified": 1695318763,
-        "narHash": "sha256-X8w0vPZjZxMm68VCwh/BHDoKRGp+BgzQ6w7Nkif6IVM=",
+        "narHash": "sha256-FHVPDRP2AfvsxAdc+AsgFJevMz5VBmnZglFUMlxBkcY=",
         "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "de2b8ddf94d6cc6161b7659649594c79bd66c13b",
+        "rev": "e12483116b3b51a185a33a272bf351e357ba9a99",
         "type": "github"
       },
       "original": {
@@ -16,8 +34,27 @@
         "type": "github"
       }
     },
+    "nixpkgs-lib": {
+      "locked": {
+        "dir": "lib",
+        "lastModified": 1693471703,
+        "narHash": "sha256-0l03ZBL8P1P6z8MaSDS/MvuU8E75rVxe5eE1N6gxeTo=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "3e52e76b70d5508f3cec70b882a29199f4d1ee85",
+        "type": "github"
+      },
+      "original": {
+        "dir": "lib",
+        "owner": "NixOS",
+        "ref": "nixos-unstable",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
     "root": {
       "inputs": {
+        "flake-parts": "flake-parts",
         "nixpkgs": "nixpkgs"
       }
     }

flake.nix

@@ -1,61 +1,40 @@
 {
   description = "matar";
+
   inputs = {
     nixpkgs.url = github:nixos/nixpkgs/nixpkgs-unstable;
+    flake-parts.url = github:hercules-ci/flake-parts;
   };
-  outputs = { self, nixpkgs }:
+
-    let
+  outputs = inputs@{ self, nixpkgs, flake-parts }:
+    flake-parts.lib.mkFlake { inherit inputs; } {
+
       systems = [
         "x86_64-linux"
         "aarch64-linux"
-        "i686-linux"
       ];
-      eachSystem = with nixpkgs.lib; f: foldAttrs mergeAttrs { }
-        (map (s: mapAttrs (_: v: { ${s} = v; }) (f s)) systems);
-    in
-    eachSystem (system:
-      let
-        pkgs = import nixpkgs { inherit system; };
-        llvm = pkgs.llvmPackages_16;
-        stdenv = llvm.libcxxStdenv;
 
-        nativeBuildInputs = with pkgs; [ meson ninja ];
+      imports = [
-      in
+        ./nix
-      rec {
+      ];
-        packages = rec {
-          matar = stdenv.mkDerivation rec {
-            name = "matar";
-            version = "0.1";
-            src = pkgs.lib.sourceFilesBySuffices ./. [
-              ".hh"
-              ".cc"
-              ".build"
-            ];
-            outputs = [ "dev" "out" ];
 
-            inherit nativeBuildInputs;
+      perSystem = { self', system, ... }:
+        let
+          pkgs = import nixpkgs { inherit system; };
 
-            enableParallelBuilding = true;
+          src = pkgs.lib.sourceFilesBySuffices ./. [
+            ".hh"
+            ".cc"
+            ".build"
+            "meson_options.txt"
+          ];
+        in
+        rec {
+          _module.args = {
+            inherit src pkgs;
           };
-          default = matar;
+
+          formatter = pkgs.nixpkgs-fmt;
         };
-
+    };
-        devShells = rec {
-          matar = pkgs.mkShell.override { inherit stdenv; } {
-            name = "matar";
-            packages = nativeBuildInputs ++ (with pkgs; [
-              # dev tools
-              clang-tools_16
-
-              # other tools
-              valgrind
-
-              llvm.lldb
-            ]);
-          };
-          default = matar;
-        };
-
-        formatter = pkgs.nixpkgs-fmt;
-      });
 }

include/bus.hh

@@ -0,0 +1,23 @@
+#pragma once
+
+#include "memory.hh"
+#include <memory>
+
+namespace matar {
+class Bus {
+  public:
+    Bus(const Memory& memory);
+
+    uint8_t read_byte(size_t address);
+    void write_byte(size_t address, uint8_t byte);
+
+    uint16_t read_halfword(size_t address);
+    void write_halfword(size_t address, uint16_t halfword);
+
+    uint32_t read_word(size_t address);
+    void write_word(size_t address, uint32_t word);
+
+  private:
+    std::shared_ptr<Memory> memory;
+};
+}

include/cpu/cpu.hh

@@ -0,0 +1,21 @@
+#include "bus.hh"
+
+namespace matar {
+class CpuImpl;
+
+class Cpu {
+  public:
+    Cpu(const Bus& bus) noexcept;
+    Cpu(const Cpu&)            = delete;
+    Cpu(Cpu&&)                 = delete;
+    Cpu& operator=(const Cpu&) = delete;
+    Cpu& operator=(Cpu&&)      = delete;
+
+    ~Cpu();
+
+    void step();
+
+  private:
+    std::unique_ptr<CpuImpl> impl;
+};
+}

include/cpu/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'cpu.hh',
+)

include/header.hh

@@ -1 +0,0 @@
-../src/header.hh

include/header.hh

@@ -0,0 +1,48 @@
+#pragma once
+
+#include <cstdint>
+#include <string>
+
+namespace matar {
+struct Header {
+    static constexpr uint8_t HEADER_SIZE = 192;
+
+    enum class UniqueCode {
+        Old,        // old games
+        New,        // new games
+        Newer,      // unused (newer games)
+        Famicom,    // NES
+        YoshiKoro,  // acceleration sensor
+        Ereader,    // dot code scanner
+        Warioware,  // rumble and z-axis gyro
+        Boktai,     // RTC and solar sensor
+        DrillDozer, // rumble
+    };
+
+    enum class I18n {
+        Japan,
+        Europe,
+        French,
+        Spanish,
+        Usa,
+        German,
+        Italian
+    };
+
+    enum class BootMode {
+        Joybus,
+        Normal,
+        Multiplay
+    };
+
+    uint32_t entrypoint;
+    std::string title;
+    std::string title_code;
+    UniqueCode unique_code;
+    I18n i18n;
+    uint8_t version;
+    BootMode multiboot;
+    uint32_t multiboot_entrypoint;
+    uint8_t slave_id;
+};
+}

include/memory.hh

@@ -1 +0,0 @@
-../src/memory.hh

include/memory.hh

@@ -0,0 +1,61 @@
+#pragma once
+
+#include "header.hh"
+#include <array>
+#include <cstddef>
+#include <cstdint>
+#include <unordered_map>
+#include <vector>
+
+namespace matar {
+class Memory {
+  public:
+    static constexpr size_t BIOS_SIZE = 1024 * 16;
+
+    Memory(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
+
+    uint8_t read(size_t address) const;
+    void write(size_t address, uint8_t byte);
+
+  private:
+#define MEMORY_REGION(name, start, end)                                        \
+    static constexpr size_t name##_START = start;                              \
+    static constexpr size_t name##_END   = end;
+
+#define DECL_MEMORY(name, ident, start, end)                                   \
+    MEMORY_REGION(name, start, end)                                            \
+    std::array<uint8_t, name##_END - name##_START + 1> ident;
+
+    MEMORY_REGION(BIOS, 0x00000000, 0x00003FFF)
+    std::array<uint8_t, BIOS_SIZE> bios;
+    static_assert(BIOS_END - BIOS_START + 1 == BIOS_SIZE);
+
+    // board working RAM
+    DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
+
+    // chip working RAM
+    DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
+
+    // palette RAM
+    DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
+
+    // video RAM
+    DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
+
+    // OAM OBJ attributes
+    DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
+
+#undef DECL_MEMORY
+
+    MEMORY_REGION(ROM_0, 0x08000000, 0x09FFFFFF)
+    MEMORY_REGION(ROM_1, 0x0A000000, 0x0BFFFFFF)
+    MEMORY_REGION(ROM_2, 0x0C000000, 0x0DFFFFFF)
+
+#undef MEMORY_REGION
+
+    std::unordered_map<size_t, uint8_t> invalid_mem;
+    std::vector<uint8_t> rom;
+    Header header;
+    void parse_header();
+};
+}

include/meson.build

@@ -1,6 +1,12 @@
 headers = files(
   'memory.hh',
-  'header.hh'
+  'bus.hh',
+  'header.hh',
 )
 
+inc = include_directories('.')
+
+subdir('cpu')
+subdir('util')
+
 install_headers(headers, subdir: meson.project_name(), preserve_path: true)

include/util/loglevel.hh

@@ -0,0 +1,14 @@
+#pragma once
+
+namespace matar {
+enum class LogLevel {
+    Off   = 1 << 0,
+    Error = 1 << 1,
+    Warn  = 1 << 2,
+    Info  = 1 << 3,
+    Debug = 1 << 4
+};
+
+void
+set_log_level(LogLevel level);
+}

include/util/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'loglevel.hh'
+)

meson.build

@@ -4,9 +4,37 @@ project('matar', 'cpp',
   default_options : ['warning_level=3',
                      'werror=true',
                      'optimization=3',
-                     'cpp_std=c++20'])
+                     'cpp_std=c++20',
+                     'default_library=static'])
+
+compiler = meson.get_compiler('cpp')
+
+'''
+TODO: use <print> and <format> instead of libfmt once LLVM 17 is out
+
+if compiler.has_argument('-std=c++2c')
+  add_global_arguments('-std=c++2c', language: 'cpp')
+elif compiler.has_argument('-std=c++23')
+  add_global_arguments('-std=c++23', language: 'cpp')
+elif compiler.has_argument('-std=c++2b')
+  add_global_arguments('-std=c++2b', language: 'cpp')
+elif compiler.has_argument('-std=c++20')
+  add_global_arguments('-std=c++20', language: 'cpp')
+else
+  error(compiler.get_id() + ' ' + compiler.version() + 'does not meet the compiler requirements')
+endif
+
+if compiler.has_argument('-fexperimental-library')
+  add_global_arguments('-fexperimental-library', language: 'cpp')
+else
+  error(compiler.get_id() + ' ' + compiler.version() + 'does not support -fexperimental-library')
+endif
+'''
 
-inc = include_directories('include')
 subdir('include')
 subdir('src')
 subdir('apps')
+
+if get_option('tests')
+  subdir('tests')
+endif

meson_options.txt

@@ -0,0 +1 @@
+option('tests', type : 'boolean', value : true, description: 'enable tests')

nix/build.nix

@@ -0,0 +1,23 @@
+{ stdenv
+, meson
+, ninja
+, pkg-config
+, src ? "../."
+, libraries ? [ ]
+}:
+
+stdenv.mkDerivation {
+  name = "matar";
+  version = "0.1";
+  inherit src;
+
+  outputs = [ "out" "dev" ];
+
+  nativeBuildInputs = [
+    meson
+    ninja
+    pkg-config
+  ] ++ libraries;
+
+  enableParallelBuilding = true;
+}

nix/default.nix

@@ -0,0 +1,11 @@
+{ ... }: {
+  imports = [
+    ./matar.nix
+    ./matar-clang.nix
+  ];
+
+  perSystem = { self', pkgs, ... }: {
+    packages.default = self'.packages.matar-clang;
+    devShells.default = self'.devShells.matar-clang;
+  };
+}

nix/matar-clang.nix

@@ -0,0 +1,25 @@
+{ ... }: {
+  perSystem = { pkgs, src, ... }:
+    let
+      llvm = pkgs.llvmPackages_16;
+      stdenv = llvm.libcxxStdenv;
+
+      libraries = with pkgs; [
+        ((pkgs.fmt.override {
+          inherit stdenv;
+          enableShared = false;
+        }).overrideAttrs (oa: {
+          cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
+        })).dev
+
+        (catch2_3.override { inherit stdenv; }).out
+      ];
+    in
+    {
+      packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
+      devShells.matar-clang = pkgs.callPackage ./shell.nix {
+        inherit libraries stdenv;
+        tools = with pkgs; [ clang-tools_16 ];
+      };
+    };
+}

nix/matar.nix

@@ -0,0 +1,13 @@
+{ ... }: {
+  perSystem = { pkgs, src, ... }:
+    let
+      libraries = with pkgs; [
+        (pkgs.fmt.override { enableShared = false; }).dev
+        catch2_3.out
+      ];
+    in
+    {
+      packages.matar = pkgs.callPackage ./build.nix { inherit src libraries; };
+      devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries; };
+    };
+}

nix/shell.nix

@@ -0,0 +1,20 @@
+{ stdenv
+, mkShell
+, meson
+, ninja
+, pkg-config
+, libraries ? [ ]
+, tools ? [ ]
+}:
+
+mkShell.override { inherit stdenv; } {
+  name = "matar";
+
+  packages = [
+    meson
+    ninja
+    pkg-config
+  ] ++ libraries ++ tools;
+
+  enableParallelBuilding = true;
+}

src/bus.cc

@@ -1,4 +1,55 @@
 #include "bus.hh"
+#include "util/log.hh"
+#include <memory>
 
-Bus::Bus(Memory&& memory)
+namespace matar {
-  : memory(std::move(memory)) {}
+Bus::Bus(const Memory& memory)
+  : memory(std::make_shared<Memory>(memory)) {}
+
+uint8_t
+Bus::read_byte(size_t address) {
+    return memory->read(address);
+}
+
+void
+Bus::write_byte(size_t address, uint8_t byte) {
+    memory->write(address, byte);
+}
+
+uint16_t
+Bus::read_halfword(size_t address) {
+    if (address & 0b01)
+        glogger.warn("Reading a non aligned halfword address");
+
+    return memory->read(address) | memory->read(address + 1) << 8;
+}
+
+void
+Bus::write_halfword(size_t address, uint16_t halfword) {
+    if (address & 0b01)
+        glogger.warn("Writing to a non aligned halfword address");
+
+    memory->write(address, halfword & 0xFF);
+    memory->write(address + 1, halfword >> 8 & 0xFF);
+}
+
+uint32_t
+Bus::read_word(size_t address) {
+    if (address & 0b11)
+        glogger.warn("Reading a non aligned word address");
+
+    return memory->read(address) | memory->read(address + 1) << 8 |
+           memory->read(address + 2) << 16 | memory->read(address + 3) << 24;
+}
+
+void
+Bus::write_word(size_t address, uint32_t word) {
+    if (address & 0b11)
+        glogger.warn("Writing to a non aligned word address");
+
+    memory->write(address, word & 0xFF);
+    memory->write(address + 1, word >> 8 & 0xFF);
+    memory->write(address + 2, word >> 16 & 0xFF);
+    memory->write(address + 3, word >> 24 & 0xFF);
+}
+}

src/bus.hh

@@ -1,11 +0,0 @@
-#pragma once
-
-#include "memory.hh"
-
-class Bus {
-  public:
-    Bus(Memory&& memory);
-
-  private:
-    Memory memory;
-};

src/cpu/alu.cc

@@ -0,0 +1,71 @@
+#include "alu.hh"
+#include "util/bits.hh"
+
+namespace matar {
+uint32_t
+eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
+    uint32_t eval = 0;
+
+    switch (shift_type) {
+        case ShiftType::LSL:
+
+            if (amount > 0 && amount <= 32)
+                carry = get_bit(value, 32 - amount);
+            else if (amount > 32)
+                carry = 0;
+
+            eval = value << amount;
+            break;
+        case ShiftType::LSR:
+
+            if (amount > 0 && amount <= 32)
+                carry = get_bit(value, amount - 1);
+            else if (amount > 32)
+                carry = 0;
+            else
+                carry = get_bit(value, 31);
+
+            eval = value >> amount;
+            break;
+        case ShiftType::ASR:
+            if (amount > 0 && amount <= 32)
+                carry = get_bit(value, amount - 1);
+            else
+                carry = get_bit(value, 31);
+
+            return static_cast<int32_t>(value) >> amount;
+            break;
+        case ShiftType::ROR:
+            if (amount == 0) {
+                eval  = (value >> 1) | (carry << 31);
+                carry = get_bit(value, 0);
+            } else {
+                eval  = std::rotr(value, amount);
+                carry = get_bit(value, (amount % 32 + 31) % 32);
+            }
+            break;
+    }
+
+    return eval;
+}
+
+std::ostream&
+operator<<(std::ostream& os, const ShiftType shift_type) {
+
+#define CASE(type)                                                             \
+    case ShiftType::type:                                                      \
+        os << #type;                                                           \
+        break;
+
+    switch (shift_type) {
+        CASE(LSL)
+        CASE(LSR)
+        CASE(ASR)
+        CASE(ROR)
+    }
+
+#undef CASE
+
+    return os;
+}
+}

src/cpu/alu.hh

@@ -0,0 +1,35 @@
+#pragma once
+#include <cstdint>
+#include <fmt/ostream.h>
+
+namespace matar {
+enum class ShiftType {
+    LSL = 0b00,
+    LSR = 0b01,
+    ASR = 0b10,
+    ROR = 0b11
+};
+
+struct ShiftData {
+    ShiftType type;
+    bool immediate;
+    uint8_t operand;
+};
+
+struct Shift {
+    uint8_t rm;
+    ShiftData data;
+};
+
+uint32_t
+eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const ShiftType cond);
+}
+
+namespace fmt {
+template<>
+struct formatter<matar::ShiftType> : ostream_formatter {};
+}

src/cpu/arm/exec.cc

@@ -0,0 +1,541 @@
+#include "cpu/cpu-impl.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+namespace matar {
+void
+CpuImpl::exec_arm(const arm::Instruction instruction) {
+    Condition cond            = instruction.condition;
+    arm::InstructionData data = instruction.data;
+
+    if (!cpsr.condition(cond)) {
+        return;
+    }
+
+    auto pc_error = [](uint8_t r) {
+        if (r == PC_INDEX)
+            glogger.error("Using PC (R15) as operand register");
+    };
+
+    auto pc_warn = [](uint8_t r) {
+        if (r == PC_INDEX)
+            glogger.warn("Using PC (R15) as operand register");
+    };
+
+    using namespace arm;
+
+    std::visit(
+      overloaded{
+        [this, pc_warn](BranchAndExchange& data) {
+            State state = static_cast<State>(data.rn & 1);
+
+            pc_warn(data.rn);
+
+            // set state
+            cpsr.set_state(state);
+
+            // copy to PC
+            pc = gpr[data.rn];
+
+            // ignore [1:0] bits for arm and 0 bit for thumb
+            rst_bit(pc, 0);
+
+            if (state == State::Arm)
+                rst_bit(pc, 1);
+
+            // pc is affected so flush the pipeline
+            is_flushed = true;
+        },
+        [this](Branch& data) {
+            if (data.link)
+                gpr[14] = pc - INSTRUCTION_SIZE;
+
+            // data.offset accounts for two instructions ahead when
+            // disassembling, so need to adjust
+            pc = static_cast<int32_t>(pc) - 2 * INSTRUCTION_SIZE + data.offset;
+
+            // pc is affected so flush the pipeline
+            is_flushed = true;
+        },
+        [this, pc_error](Multiply& data) {
+            if (data.rd == data.rm)
+                glogger.error("rd and rm are not distinct in {}",
+                              typeid(data).name());
+
+            pc_error(data.rd);
+            pc_error(data.rd);
+            pc_error(data.rd);
+
+            gpr[data.rd] =
+              gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
+
+            if (data.set) {
+                cpsr.set_z(gpr[data.rd] == 0);
+                cpsr.set_n(get_bit(gpr[data.rd], 31));
+                cpsr.set_c(0);
+            }
+        },
+        [this, pc_error](MultiplyLong& data) {
+            if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
+                data.rdlo == data.rm)
+                glogger.error("rdhi, rdlo and rm are not distinct in {}",
+                              typeid(data).name());
+
+            pc_error(data.rdhi);
+            pc_error(data.rdlo);
+            pc_error(data.rm);
+            pc_error(data.rs);
+
+            if (data.uns) {
+                auto cast = [](uint32_t x) -> uint64_t {
+                    return static_cast<uint64_t>(x);
+                };
+
+                uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                                (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                                              cast(gpr[data.rdlo])
+                                          : 0);
+
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
+
+            } else {
+                auto cast = [](uint32_t x) -> int64_t {
+                    return static_cast<int64_t>(static_cast<int32_t>(x));
+                };
+
+                int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                               (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                                             cast(gpr[data.rdlo])
+                                         : 0);
+
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
+            }
+
+            if (data.set) {
+                cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
+                cpsr.set_n(get_bit(gpr[data.rdhi], 31));
+                cpsr.set_c(0);
+                cpsr.set_v(0);
+            }
+        },
+        [](Undefined) { glogger.warn("Undefined instruction"); },
+        [this, pc_error](SingleDataSwap& data) {
+            pc_error(data.rm);
+            pc_error(data.rn);
+            pc_error(data.rd);
+
+            if (data.byte) {
+                gpr[data.rd] = bus->read_byte(gpr[data.rn]);
+                bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
+            } else {
+                gpr[data.rd] = bus->read_word(gpr[data.rn]);
+                bus->write_word(gpr[data.rn], gpr[data.rm]);
+            }
+        },
+        [this, pc_warn, pc_error](SingleDataTransfer& data) {
+            uint32_t offset  = 0;
+            uint32_t address = gpr[data.rn];
+
+            if (!data.pre && data.write)
+                glogger.warn("Write-back enabled with post-indexing in {}",
+                             typeid(data).name());
+
+            if (data.rn == PC_INDEX && data.write)
+                glogger.warn("Write-back enabled with base register as PC {}",
+                             typeid(data).name());
+
+            if (data.write)
+                pc_warn(data.rn);
+
+            // evaluate the offset
+            if (const uint16_t* immediate =
+                  std::get_if<uint16_t>(&data.offset)) {
+                offset = *immediate;
+            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
+                uint8_t amount =
+                  (shift->data.immediate ? shift->data.operand
+                                         : gpr[shift->data.operand] & 0xFF);
+
+                bool carry = cpsr.c();
+
+                if (!shift->data.immediate)
+                    pc_error(shift->data.operand);
+                pc_error(shift->rm);
+
+                offset =
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+
+                cpsr.set_c(carry);
+            }
+
+            // PC is always two instructions ahead
+            if (data.rn == PC_INDEX)
+                address -= 2 * INSTRUCTION_SIZE;
+
+            if (data.pre)
+                address += (data.up ? offset : -offset);
+
+            // load
+            if (data.load) {
+                // byte
+                if (data.byte)
+                    gpr[data.rd] = bus->read_byte(address);
+                // word
+                else
+                    gpr[data.rd] = bus->read_word(address);
+                // store
+            } else {
+                // take PC into consideration
+                if (data.rd == PC_INDEX)
+                    address += INSTRUCTION_SIZE;
+
+                // byte
+                if (data.byte)
+                    bus->write_byte(address, gpr[data.rd] & 0xFF);
+                // word
+                else
+                    bus->write_word(address, gpr[data.rd]);
+            }
+
+            if (!data.pre)
+                address += (data.up ? offset : -offset);
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.rd == PC_INDEX && data.load)
+                is_flushed = true;
+        },
+        [this, pc_warn, pc_error](HalfwordTransfer& data) {
+            uint32_t address = gpr[data.rn];
+            uint32_t offset  = 0;
+
+            if (!data.pre && data.write)
+                glogger.error("Write-back enabled with post-indexing in {}",
+                              typeid(data).name());
+
+            if (data.sign && !data.load)
+                glogger.error("Signed data found in {}", typeid(data).name());
+
+            if (data.write)
+                pc_warn(data.rn);
+
+            // offset is register number (4 bits) when not an immediate
+            if (!data.imm) {
+                pc_error(data.offset);
+                offset = gpr[data.offset];
+            } else {
+                offset = data.offset;
+            }
+
+            // PC is always two instructions ahead
+            if (data.rn == PC_INDEX)
+                address -= 2 * INSTRUCTION_SIZE;
+
+            if (data.pre)
+                address += (data.up ? offset : -offset);
+
+            // load
+            if (data.load) {
+                // signed
+                if (data.sign) {
+                    // halfword
+                    if (data.half) {
+                        gpr[data.rd] = bus->read_halfword(address);
+
+                        // sign extend the halfword
+                        gpr[data.rd] =
+                          (static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
+
+                        // byte
+                    } else {
+                        gpr[data.rd] = bus->read_byte(address);
+
+                        // sign extend the byte
+                        gpr[data.rd] =
+                          (static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
+                    }
+                    // unsigned halfword
+                } else if (data.half) {
+                    gpr[data.rd] = bus->read_halfword(address);
+                }
+                // store
+            } else {
+                // take PC into consideration
+                if (data.rd == PC_INDEX)
+                    address += INSTRUCTION_SIZE;
+
+                // halfword
+                if (data.half)
+                    bus->write_halfword(address, gpr[data.rd]);
+            }
+
+            if (!data.pre)
+                address += (data.up ? offset : -offset);
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.rd == PC_INDEX && data.load)
+                is_flushed = true;
+        },
+        [this, pc_error](BlockDataTransfer& data) {
+            uint32_t address  = gpr[data.rn];
+            Mode mode         = cpsr.mode();
+            uint8_t alignment = 4; // word
+            uint8_t i         = 0;
+            uint8_t n_regs    = std::popcount(data.regs);
+
+            pc_error(data.rn);
+
+            if (cpsr.mode() == Mode::User && data.s) {
+                glogger.error("Bit S is set outside priviliged modes in {}",
+                              typeid(data).name());
+            }
+
+            // we just change modes to load user registers
+            if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
+                (!data.load && data.s)) {
+                chg_mode(Mode::User);
+
+                if (data.write) {
+                    glogger.error(
+                      "Write-back enable for user bank registers in {}",
+                      typeid(data).name());
+                }
+            }
+
+            // account for decrement
+            if (!data.up)
+                address -= (n_regs - 1) * alignment;
+
+            if (data.pre)
+                address += (data.up ? alignment : -alignment);
+
+            if (data.load) {
+                if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
+                    // current mode's spsr is already loaded when it was
+                    // switched
+                    spsr = cpsr;
+                }
+
+                for (i = 0; i < GPR_COUNT; i++) {
+                    if (get_bit(data.regs, i)) {
+                        gpr[i] = bus->read_word(address);
+                        address += alignment;
+                    }
+                }
+            } else {
+                for (i = 0; i < GPR_COUNT; i++) {
+                    if (get_bit(data.regs, i)) {
+                        bus->write_word(address, gpr[i]);
+                        address += alignment;
+                    }
+                }
+            }
+
+            if (!data.pre)
+                address += (data.up ? alignment : -alignment);
+
+            // reset back to original address + offset if incremented earlier
+            if (data.up)
+                address -= n_regs * alignment;
+            else
+                address -= alignment;
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.load && get_bit(data.regs, PC_INDEX))
+                is_flushed = true;
+
+            // load back the original mode registers
+            chg_mode(mode);
+        },
+        [this, pc_error](PsrTransfer& data) {
+            if (data.spsr && cpsr.mode() == Mode::User) {
+                glogger.error("Accessing SPSR in User mode in {}",
+                              typeid(data).name());
+            }
+
+            Psr& psr = data.spsr ? spsr : cpsr;
+
+            switch (data.type) {
+                case PsrTransfer::Type::Mrs:
+                    pc_error(data.operand);
+                    gpr[data.operand] = psr.raw();
+                    break;
+                case PsrTransfer::Type::Msr:
+                    pc_error(data.operand);
+
+                    if (cpsr.mode() != Mode::User) {
+                        psr.set_all(gpr[data.operand]);
+                    }
+                    break;
+                case PsrTransfer::Type::Msr_flg:
+                    uint32_t operand =
+                      (data.imm ? data.operand : gpr[data.operand]);
+                    psr.set_n(get_bit(operand, 31));
+                    psr.set_z(get_bit(operand, 30));
+                    psr.set_c(get_bit(operand, 29));
+                    psr.set_v(get_bit(operand, 28));
+                    break;
+            }
+        },
+        [this, pc_error](DataProcessing& data) {
+            using OpCode = DataProcessing::OpCode;
+
+            uint32_t op_1 = gpr[data.rn];
+            uint32_t op_2 = 0;
+
+            uint32_t result = 0;
+
+            if (const uint32_t* immediate =
+                  std::get_if<uint32_t>(&data.operand)) {
+                op_2 = *immediate;
+            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
+                uint8_t amount =
+                  (shift->data.immediate ? shift->data.operand
+                                         : gpr[shift->data.operand] & 0xFF);
+
+                bool carry = cpsr.c();
+
+                if (!shift->data.immediate)
+                    pc_error(shift->data.operand);
+                pc_error(shift->rm);
+
+                op_2 =
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+
+                cpsr.set_c(carry);
+
+                // PC is 12 bytes ahead when shifting
+                if (data.rn == PC_INDEX)
+                    op_1 += INSTRUCTION_SIZE;
+            }
+
+            bool overflow = cpsr.v();
+            bool carry    = cpsr.c();
+
+            auto sub = [&carry, &overflow](uint32_t a, uint32_t b) -> uint32_t {
+                bool s1 = get_bit(a, 31);
+                bool s2 = get_bit(b, 31);
+
+                uint32_t result = a - b;
+
+                carry    = b <= a;
+                overflow = s1 != s2 && s2 == get_bit(result, 31);
+                return result;
+            };
+
+            auto add = [&carry, &overflow](
+                         uint32_t a, uint32_t b, bool c = 0) -> uint32_t {
+                bool s1 = get_bit(a, 31);
+                bool s2 = get_bit(b, 31);
+
+                // 33 bits
+                uint64_t result_ = a + b + c;
+                uint32_t result  = result_ & 0xFFFFFFFF;
+
+                carry    = get_bit(result_, 32);
+                overflow = s1 == s2 && s2 != get_bit(result, 31);
+                return result;
+            };
+
+            auto sbc = [&carry,
+                        &overflow](uint32_t a, uint32_t b, bool c) -> uint32_t {
+                bool s1 = get_bit(a, 31);
+                bool s2 = get_bit(b, 31);
+
+                uint64_t result_ = a - b + c - 1;
+                uint32_t result  = result_ & 0xFFFFFFFF;
+
+                carry    = get_bit(result_, 32);
+                overflow = s1 != s2 && s2 == get_bit(result, 31);
+                return result;
+            };
+
+            switch (data.opcode) {
+                case OpCode::AND:
+                case OpCode::TST:
+                    result = op_1 & op_2;
+                    result = op_1 & op_2;
+                    break;
+                case OpCode::EOR:
+                case OpCode::TEQ:
+                    result = op_1 ^ op_2;
+                    break;
+                case OpCode::SUB:
+                case OpCode::CMP:
+                    result = sub(op_1, op_2);
+                    break;
+                case OpCode::RSB:
+                    result = sub(op_2, op_1);
+                    break;
+                case OpCode::ADD:
+                case OpCode::CMN:
+                    result = add(op_1, op_2);
+                    break;
+                case OpCode::ADC:
+                    result = add(op_1, op_2, carry);
+                    break;
+                case OpCode::SBC:
+                    result = sbc(op_1, op_2, carry);
+                    break;
+                case OpCode::RSC:
+                    result = sbc(op_2, op_1, carry);
+                    break;
+                case OpCode::ORR:
+                    result = op_1 | op_2;
+                    break;
+                case OpCode::MOV:
+                    result = op_2;
+                    break;
+                case OpCode::BIC:
+                    result = op_1 & ~op_2;
+                    break;
+                case OpCode::MVN:
+                    result = ~op_2;
+                    break;
+            }
+
+            auto set_conditions = [this, carry, overflow, result]() {
+                cpsr.set_c(carry);
+                cpsr.set_v(overflow);
+                cpsr.set_n(get_bit(result, 31));
+                cpsr.set_z(result == 0);
+            };
+
+            if (data.set) {
+                if (data.rd == PC_INDEX) {
+                    if (cpsr.mode() == Mode::User)
+                        glogger.error("Running {} in User mode",
+                                      typeid(data).name());
+                    spsr = cpsr;
+                } else {
+                    set_conditions();
+                }
+            }
+
+            if (data.opcode == OpCode::TST || data.opcode == OpCode::TEQ ||
+                data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
+                set_conditions();
+            } else {
+                gpr[data.rd] = result;
+                if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
+                    is_flushed = true;
+            }
+        },
+        [this](SoftwareInterrupt) {
+            chg_mode(Mode::Supervisor);
+            pc   = 0x08;
+            spsr = cpsr;
+        },
+        [](auto& data) {
+            glogger.error("Unimplemented {} instruction", typeid(data).name());
+        } },
+      data);
+}
+}

src/cpu/arm/insruction.hh

@@ -1,43 +0,0 @@
-enum class Condition {
-    EQ = 0b0000,
-    NE = 0b0001,
-    CS = 0b0010,
-    CC = 0b0011,
-    MI = 0b0100,
-    PL = 0b0101,
-    VS = 0b0110,
-    VC = 0b0111,
-    HI = 0b1000,
-    LS = 0b1001,
-    GE = 0b1010,
-    LT = 0b1011,
-    GT = 0b1100,
-    LE = 0b1101,
-    AL = 0b1110
-};
-
-enum class OpCode {
-    AND = 0b0000,
-    EOR = 0b0001,
-    SUB = 0b0010,
-    RSB = 0b0011,
-    ADD = 0b0100,
-    ADC = 0b0101,
-    SBC = 0b0110,
-    RSC = 0b0111,
-    TST = 0b1000,
-    TEQ = 0b1001,
-    CMP = 0b1010,
-    CMN = 0b1011,
-    ORR = 0b1100,
-    MOV = 0b1101,
-    BIC = 0b1110,
-    MVN = 0b1111
-};
-
-enum class ShiftType {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11
-};

src/cpu/arm/instruction.cc

@@ -0,0 +1,535 @@
+#include "instruction.hh"
+#include "util/bits.hh"
+#include <iterator>
+
+namespace matar {
+namespace arm {
+
+Instruction::Instruction(uint32_t insn)
+  : condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
+    // Branch and exhcange
+    if ((insn & 0x0FFFFFF0) == 0x012FFF10) {
+        uint8_t rn = insn & 0b1111;
+
+        data = BranchAndExchange{ rn };
+
+        // Branch
+    } else if ((insn & 0x0E000000) == 0x0A000000) {
+        bool link       = get_bit(insn, 24);
+        uint32_t offset = bit_range(insn, 0, 23);
+
+        // lsh 2 and sign extend the 26 bit offset to 32 bits
+        offset = (static_cast<int32_t>(offset) << 8) >> 6;
+
+        offset += 2 * INSTRUCTION_SIZE;
+
+        data = Branch{ .link = link, .offset = offset };
+
+        // Multiply
+    } else if ((insn & 0x0FC000F0) == 0x00000090) {
+        uint8_t rm = bit_range(insn, 0, 3);
+        uint8_t rs = bit_range(insn, 8, 11);
+        uint8_t rn = bit_range(insn, 12, 15);
+        uint8_t rd = bit_range(insn, 16, 19);
+        bool set   = get_bit(insn, 20);
+        bool acc   = get_bit(insn, 21);
+
+        data = Multiply{
+            .rm = rm, .rs = rs, .rn = rn, .rd = rd, .set = set, .acc = acc
+        };
+
+        // Multiply long
+    } else if ((insn & 0x0F8000F0) == 0x00800090) {
+        uint8_t rm   = bit_range(insn, 0, 3);
+        uint8_t rs   = bit_range(insn, 8, 11);
+        uint8_t rdlo = bit_range(insn, 12, 15);
+        uint8_t rdhi = bit_range(insn, 16, 19);
+        bool set     = get_bit(insn, 20);
+        bool acc     = get_bit(insn, 21);
+        bool uns     = !get_bit(insn, 22);
+
+        data = MultiplyLong{ .rm   = rm,
+                             .rs   = rs,
+                             .rdlo = rdlo,
+                             .rdhi = rdhi,
+                             .set  = set,
+                             .acc  = acc,
+                             .uns  = uns };
+
+        // Undefined
+    } else if ((insn & 0x0E000010) == 0x06000010) {
+        data = Undefined{};
+
+        // Single data swap
+    } else if ((insn & 0x0FB00FF0) == 0x01000090) {
+        uint8_t rm = bit_range(insn, 0, 3);
+        uint8_t rd = bit_range(insn, 12, 15);
+        uint8_t rn = bit_range(insn, 16, 19);
+        bool byte  = get_bit(insn, 22);
+
+        data = SingleDataSwap{ .rm = rm, .rd = rd, .rn = rn, .byte = byte };
+
+        // Single data transfer
+    } else if ((insn & 0x0C000000) == 0x04000000) {
+        std::variant<uint16_t, Shift> offset;
+        uint8_t rd = bit_range(insn, 12, 15);
+        uint8_t rn = bit_range(insn, 16, 19);
+        bool load  = get_bit(insn, 20);
+        bool write = get_bit(insn, 21);
+        bool byte  = get_bit(insn, 22);
+        bool up    = get_bit(insn, 23);
+        bool pre   = get_bit(insn, 24);
+        bool imm   = get_bit(insn, 25);
+
+        if (imm) {
+            // register specified shift amounts not available in single data
+            // transfer (see Undefined)
+            uint8_t rm = bit_range(insn, 0, 3);
+            ShiftType shift_type =
+              static_cast<ShiftType>(bit_range(insn, 5, 6));
+            uint8_t operand = bit_range(insn, 7, 11);
+
+            offset = Shift{ .rm   = rm,
+                            .data = ShiftData{ .type      = shift_type,
+                                               .immediate = true,
+                                               .operand   = operand } };
+        } else {
+            offset = static_cast<uint16_t>(bit_range(insn, 0, 11));
+        }
+
+        data = SingleDataTransfer{ .offset = offset,
+                                   .rd     = rd,
+                                   .rn     = rn,
+                                   .load   = load,
+                                   .write  = write,
+                                   .byte   = byte,
+                                   .up     = up,
+                                   .pre    = pre };
+
+        // Halfword transfer
+    } else if ((insn & 0x0E000090) == 0x00000090) {
+        uint8_t offset = bit_range(insn, 0, 3);
+        bool half      = get_bit(insn, 5);
+        bool sign      = get_bit(insn, 6);
+        uint8_t rd     = bit_range(insn, 12, 15);
+        uint8_t rn     = bit_range(insn, 16, 19);
+        bool load      = get_bit(insn, 20);
+        bool write     = get_bit(insn, 21);
+        bool imm       = get_bit(insn, 22);
+        bool up        = get_bit(insn, 23);
+        bool pre       = get_bit(insn, 24);
+
+        offset |= (imm ? bit_range(insn, 8, 11) << 2 : 0);
+
+        data = HalfwordTransfer{ .offset = offset,
+                                 .half   = half,
+                                 .sign   = sign,
+                                 .rd     = rd,
+                                 .rn     = rn,
+                                 .load   = load,
+                                 .write  = write,
+                                 .imm    = imm,
+                                 .up     = up,
+                                 .pre    = pre };
+
+        // Block data transfer
+    } else if ((insn & 0x0E000000) == 0x08000000) {
+        uint16_t regs = bit_range(insn, 0, 15);
+        uint8_t rn    = bit_range(insn, 16, 19);
+        bool load     = get_bit(insn, 20);
+        bool write    = get_bit(insn, 21);
+        bool s        = get_bit(insn, 22);
+        bool up       = get_bit(insn, 23);
+        bool pre      = get_bit(insn, 24);
+
+        data = BlockDataTransfer{ .regs  = regs,
+                                  .rn    = rn,
+                                  .load  = load,
+                                  .write = write,
+                                  .s     = s,
+                                  .up    = up,
+                                  .pre   = pre };
+
+        // Data Processing
+    } else if ((insn & 0x0C000000) == 0x00000000) {
+        using OpCode = DataProcessing::OpCode;
+
+        uint8_t rd    = bit_range(insn, 12, 15);
+        uint8_t rn    = bit_range(insn, 16, 19);
+        bool set      = get_bit(insn, 20);
+        OpCode opcode = static_cast<OpCode>(bit_range(insn, 21, 24));
+        bool imm      = get_bit(insn, 25);
+
+        if ((opcode == OpCode::TST || opcode == OpCode::CMP) && !set) {
+            data = PsrTransfer{ .operand = rd,
+                                .spsr    = get_bit(insn, 22),
+                                .type    = PsrTransfer::Type::Mrs,
+                                .imm     = 0 };
+        } else if ((opcode == OpCode::TEQ || opcode == OpCode::CMN) && !set) {
+            uint32_t operand = 0;
+
+            if (imm) {
+                uint32_t immediate = bit_range(insn, 0, 7);
+                uint8_t rotate     = bit_range(insn, 8, 11);
+
+                operand = std::rotr(immediate, rotate * 2);
+            } else {
+                operand = bit_range(insn, 0, 3);
+            }
+
+            data = PsrTransfer{ .operand = operand,
+                                .spsr    = get_bit(insn, 22),
+                                .type    = (get_bit(insn, 16)
+                                              ? PsrTransfer::Type::Msr
+                                              : PsrTransfer::Type::Msr_flg),
+                                .imm     = imm };
+        } else {
+            std::variant<Shift, uint32_t> operand;
+
+            if (imm) {
+                uint32_t immediate = bit_range(insn, 0, 7);
+                uint8_t rotate     = bit_range(insn, 8, 11);
+
+                operand = std::rotr(immediate, rotate * 2);
+            } else {
+                uint8_t rm = bit_range(insn, 0, 3);
+                bool reg   = get_bit(insn, 4);
+                ShiftType shift_type =
+                  static_cast<ShiftType>(bit_range(insn, 5, 6));
+                uint8_t sh_operand = bit_range(insn, (reg ? 8 : 7), 11);
+
+                operand = Shift{ .rm   = rm,
+                                 .data = ShiftData{ .type      = shift_type,
+                                                    .immediate = !reg,
+                                                    .operand   = sh_operand } };
+            }
+
+            data = DataProcessing{ .operand = operand,
+                                   .rd      = rd,
+                                   .rn      = rn,
+                                   .set     = set,
+                                   .opcode  = opcode };
+        }
+
+        // Software interrupt
+    } else if ((insn & 0x0F000000) == 0x0F000000) {
+
+        data = SoftwareInterrupt{};
+
+        // Coprocessor data transfer
+    } else if ((insn & 0x0E000000) == 0x0C000000) {
+        uint8_t offset = bit_range(insn, 0, 7);
+        uint8_t cpn    = bit_range(insn, 8, 11);
+        uint8_t crd    = bit_range(insn, 12, 15);
+        uint8_t rn     = bit_range(insn, 16, 19);
+        bool load      = get_bit(insn, 20);
+        bool write     = get_bit(insn, 21);
+        bool len       = get_bit(insn, 22);
+        bool up        = get_bit(insn, 23);
+        bool pre       = get_bit(insn, 24);
+
+        data = CoprocessorDataTransfer{ .offset = offset,
+                                        .cpn    = cpn,
+                                        .crd    = crd,
+                                        .rn     = rn,
+                                        .load   = load,
+                                        .write  = write,
+                                        .len    = len,
+                                        .up     = up,
+                                        .pre    = pre };
+
+        // Coprocessor data operation
+    } else if ((insn & 0x0F000010) == 0x0E000000) {
+        uint8_t crm    = bit_range(insn, 0, 3);
+        uint8_t cp     = bit_range(insn, 5, 7);
+        uint8_t cpn    = bit_range(insn, 8, 11);
+        uint8_t crd    = bit_range(insn, 12, 15);
+        uint8_t crn    = bit_range(insn, 16, 19);
+        uint8_t cp_opc = bit_range(insn, 20, 23);
+
+        data = CoprocessorDataOperation{ .crm    = crm,
+                                         .cp     = cp,
+                                         .cpn    = cpn,
+                                         .crd    = crd,
+                                         .crn    = crn,
+                                         .cp_opc = cp_opc };
+
+        // Coprocessor register transfer
+    } else if ((insn & 0x0F000010) == 0x0E000010) {
+        uint8_t crm    = bit_range(insn, 0, 3);
+        uint8_t cp     = bit_range(insn, 5, 7);
+        uint8_t cpn    = bit_range(insn, 8, 11);
+        uint8_t rd     = bit_range(insn, 12, 15);
+        uint8_t crn    = bit_range(insn, 16, 19);
+        bool load      = get_bit(insn, 20);
+        uint8_t cp_opc = bit_range(insn, 21, 23);
+
+        data = CoprocessorRegisterTransfer{ .crm    = crm,
+                                            .cp     = cp,
+                                            .cpn    = cpn,
+                                            .rd     = rd,
+                                            .crn    = crn,
+                                            .load   = load,
+                                            .cp_opc = cp_opc };
+    } else {
+        data = Undefined{};
+    }
+}
+
+std::string
+Instruction::disassemble() {
+    // goddamn this is gore
+    // TODO: make this less ugly
+    return std::visit(
+      overloaded{
+        [this](BranchAndExchange& data) {
+            return fmt::format("BX{} R{:d}", condition, data.rn);
+        },
+        [this](Branch& data) {
+            return fmt::format(
+              "B{}{} 0x{:06X}", (data.link ? "L" : ""), condition, data.offset);
+        },
+        [this](Multiply& data) {
+            if (data.acc) {
+                return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
+                                   condition,
+                                   (data.set ? "S" : ""),
+                                   data.rd,
+                                   data.rm,
+                                   data.rs,
+                                   data.rn);
+            } else {
+                return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
+                                   condition,
+                                   (data.set ? "S" : ""),
+                                   data.rd,
+                                   data.rm,
+                                   data.rs);
+            }
+        },
+        [this](MultiplyLong& data) {
+            return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
+                               (data.uns ? 'U' : 'S'),
+                               (data.acc ? "MLAL" : "MULL"),
+                               condition,
+                               (data.set ? "S" : ""),
+                               data.rdlo,
+                               data.rdhi,
+                               data.rm,
+                               data.rs);
+        },
+        [](Undefined) { return std::string("UND"); },
+        [this](SingleDataSwap& data) {
+            return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
+                               condition,
+                               (data.byte ? "B" : ""),
+                               data.rd,
+                               data.rm,
+                               data.rn);
+        },
+        [this](SingleDataTransfer& data) {
+            std::string expression;
+            std::string address;
+
+            if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
+                if (*offset == 0) {
+                    expression = "";
+                } else {
+                    expression =
+                      fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
+                }
+            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
+                // Shifts are always immediate in single data transfer
+                expression = fmt::format(",{}R{:d},{} #{:d}",
+                                         (data.up ? '+' : '-'),
+                                         shift->rm,
+                                         shift->data.type,
+                                         shift->data.operand);
+            }
+
+            return fmt::format(
+              "{}{}{}{} R{:d},[R{:d}{}]{}",
+              (data.load ? "LDR" : "STR"),
+              condition,
+              (data.byte ? "B" : ""),
+              (!data.pre && data.write ? "T" : ""),
+              data.rd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [this](HalfwordTransfer& data) {
+            std::string expression;
+
+            if (data.imm) {
+                if (data.offset == 0) {
+                    expression = "";
+                } else {
+                    expression = fmt::format(
+                      ",{}#{:d}", (data.up ? '+' : '-'), data.offset);
+                }
+            } else {
+                expression =
+                  fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
+            }
+
+            return fmt::format(
+              "{}{}{}{} R{:d},[R{:d}{}]{}",
+              (data.load ? "LDR" : "STR"),
+              condition,
+              (data.sign ? "S" : ""),
+              (data.half ? 'H' : 'B'),
+              data.rd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [this](BlockDataTransfer& data) {
+            std::string regs;
+
+            for (uint8_t i = 0; i < 16; i++) {
+                if (get_bit(data.regs, i))
+                    fmt::format_to(std::back_inserter(regs), "R{:d},", i);
+            };
+
+            regs.pop_back();
+
+            return fmt::format("{}{}{}{} R{:d}{},{{{}}}{}",
+                               (data.load ? "LDM" : "STM"),
+                               condition,
+                               (data.up ? 'I' : 'D'),
+                               (data.pre ? 'B' : 'A'),
+                               data.rn,
+                               (data.write ? "!" : ""),
+                               regs,
+                               (data.s ? "^" : ""));
+        },
+        [this](PsrTransfer& data) {
+            if (data.type == PsrTransfer::Type::Mrs) {
+                return fmt::format("MRS{} R{:d},{}",
+                                   condition,
+                                   data.operand,
+                                   (data.spsr ? "SPSR_all" : "CPSR_all"));
+            } else {
+                return fmt::format(
+                  "MSR{} {}_{},{}{}",
+                  condition,
+                  (data.spsr ? "SPSR" : "CPSR"),
+                  (data.type == PsrTransfer::Type::Msr_flg ? "flg" : "all"),
+                  (data.imm ? '#' : 'R'),
+                  data.operand);
+            }
+        },
+        [this](DataProcessing& data) {
+            using OpCode = DataProcessing::OpCode;
+
+            std::string op_2;
+
+            if (const uint32_t* operand =
+                  std::get_if<uint32_t>(&data.operand)) {
+                op_2 = fmt::format("#{:d}", *operand);
+            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
+                op_2 = fmt::format("R{:d},{} {}{:d}",
+                                   shift->rm,
+                                   shift->data.type,
+                                   (shift->data.immediate ? '#' : 'R'),
+                                   shift->data.operand);
+            }
+
+            switch (data.opcode) {
+                case OpCode::MOV:
+                case OpCode::MVN:
+                    return fmt::format("{}{}{} R{:d},{}",
+                                       data.opcode,
+                                       condition,
+                                       (data.set ? "S" : ""),
+                                       data.rd,
+                                       op_2);
+                case OpCode::TST:
+                case OpCode::TEQ:
+                case OpCode::CMP:
+                case OpCode::CMN:
+                    return fmt::format(
+                      "{}{} R{:d},{}", data.opcode, condition, data.rn, op_2);
+                default:
+                    return fmt::format("{}{}{} R{:d},R{:d},{}",
+                                       data.opcode,
+                                       condition,
+                                       (data.set ? "S" : ""),
+                                       data.rd,
+                                       data.rn,
+                                       op_2);
+            }
+        },
+        [this](SoftwareInterrupt) { return fmt::format("SWI{}", condition); },
+        [this](CoprocessorDataTransfer& data) {
+            std::string expression = fmt::format(",#{:d}", data.offset);
+            return fmt::format(
+              "{}{}{} p{:d},c{:d},[R{:d}{}]{}",
+              (data.load ? "LDC" : "STC"),
+              condition,
+              (data.len ? "L" : ""),
+              data.cpn,
+              data.crd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [this](CoprocessorDataOperation& data) {
+            return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
+                               condition,
+                               data.cpn,
+                               data.cp_opc,
+                               data.crd,
+                               data.crn,
+                               data.crm,
+                               data.cp);
+        },
+        [this](CoprocessorRegisterTransfer& data) {
+            return fmt::format("{}{} p{},{},R{},c{},c{},{}",
+                               (data.load ? "MRC" : "MCR"),
+                               condition,
+                               data.cpn,
+                               data.cp_opc,
+                               data.rd,
+                               data.crn,
+                               data.crm,
+                               data.cp);
+        },
+        [](auto) { return std::string("unknown instruction"); } },
+      data);
+}
+
+std::ostream&
+operator<<(std::ostream& os, const DataProcessing::OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case DataProcessing::OpCode::opcode:                                       \
+        os << #opcode;                                                         \
+        break;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(SUB)
+        CASE(RSB)
+        CASE(ADD)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(RSC)
+        CASE(TST)
+        CASE(TEQ)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MOV)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+
+    return os;
+}
+}
+}

src/cpu/arm/instruction.hh

@@ -0,0 +1,200 @@
+#pragma once
+#include "cpu/alu.hh"
+#include "cpu/psr.hh"
+#include <cstdint>
+#include <fmt/ostream.h>
+#include <variant>
+
+namespace matar {
+namespace arm {
+
+template<class... Ts>
+struct overloaded : Ts... {
+    using Ts::operator()...;
+};
+template<class... Ts>
+overloaded(Ts...) -> overloaded<Ts...>;
+
+static constexpr size_t INSTRUCTION_SIZE = 4;
+
+struct BranchAndExchange {
+    uint8_t rn;
+};
+
+struct Branch {
+    bool link;
+    uint32_t offset;
+};
+
+struct Multiply {
+    uint8_t rm;
+    uint8_t rs;
+    uint8_t rn;
+    uint8_t rd;
+    bool set;
+    bool acc;
+};
+
+struct MultiplyLong {
+    uint8_t rm;
+    uint8_t rs;
+    uint8_t rdlo;
+    uint8_t rdhi;
+    bool set;
+    bool acc;
+    bool uns;
+};
+
+struct SingleDataSwap {
+    uint8_t rm;
+    uint8_t rd;
+    uint8_t rn;
+    bool byte;
+};
+
+struct SingleDataTransfer {
+    std::variant<uint16_t, Shift> offset;
+    uint8_t rd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool byte;
+    bool up;
+    bool pre;
+};
+
+struct HalfwordTransfer {
+    uint8_t offset;
+    bool half;
+    bool sign;
+    uint8_t rd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool imm;
+    bool up;
+    bool pre;
+};
+
+struct BlockDataTransfer {
+    uint16_t regs;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool s;
+    bool up;
+    bool pre;
+};
+
+struct DataProcessing {
+    enum class OpCode {
+        AND = 0b0000,
+        EOR = 0b0001,
+        SUB = 0b0010,
+        RSB = 0b0011,
+        ADD = 0b0100,
+        ADC = 0b0101,
+        SBC = 0b0110,
+        RSC = 0b0111,
+        TST = 0b1000,
+        TEQ = 0b1001,
+        CMP = 0b1010,
+        CMN = 0b1011,
+        ORR = 0b1100,
+        MOV = 0b1101,
+        BIC = 0b1110,
+        MVN = 0b1111
+    };
+
+    std::variant<Shift, uint32_t> operand;
+    uint8_t rd;
+    uint8_t rn;
+    bool set;
+    OpCode opcode;
+};
+
+struct PsrTransfer {
+    enum class Type {
+        Mrs,
+        Msr,
+        Msr_flg
+    };
+
+    uint32_t operand;
+    bool spsr;
+    Type type;
+    // ignored outside MSR_flg
+    bool imm;
+};
+
+struct CoprocessorDataTransfer {
+    uint8_t offset;
+    uint8_t cpn;
+    uint8_t crd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool len;
+    bool up;
+    bool pre;
+};
+
+struct CoprocessorDataOperation {
+    uint8_t crm;
+    uint8_t cp;
+    uint8_t cpn;
+    uint8_t crd;
+    uint8_t crn;
+    uint8_t cp_opc;
+};
+
+struct CoprocessorRegisterTransfer {
+    uint8_t crm;
+    uint8_t cp;
+    uint8_t cpn;
+    uint8_t rd;
+    uint8_t crn;
+    bool load;
+    uint8_t cp_opc;
+};
+
+struct Undefined {};
+struct SoftwareInterrupt {};
+
+using InstructionData = std::variant<BranchAndExchange,
+                                     Branch,
+                                     Multiply,
+                                     MultiplyLong,
+                                     SingleDataSwap,
+                                     SingleDataTransfer,
+                                     HalfwordTransfer,
+                                     BlockDataTransfer,
+                                     DataProcessing,
+                                     PsrTransfer,
+                                     CoprocessorDataTransfer,
+                                     CoprocessorDataOperation,
+                                     CoprocessorRegisterTransfer,
+                                     Undefined,
+                                     SoftwareInterrupt>;
+
+struct Instruction {
+    Condition condition;
+    InstructionData data;
+
+    Instruction(uint32_t insn);
+    Instruction(Condition condition, InstructionData data) noexcept
+      : condition(condition)
+      , data(data){};
+
+    std::string disassemble();
+};
+
+std::ostream&
+operator<<(std::ostream& os, const DataProcessing::OpCode cond);
+}
+}
+
+namespace fmt {
+template<>
+struct formatter<matar::arm::DataProcessing::OpCode> : ostream_formatter {};
+}

src/cpu/arm/meson.build

@@ -1,2 +1,4 @@
 lib_sources += files(
+  'instruction.cc',
+  'exec.cc'
 )

src/cpu/cpu-impl.cc

@@ -0,0 +1,142 @@
+#include "cpu-impl.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+#include <algorithm>
+#include <cstdio>
+
+namespace matar {
+CpuImpl::CpuImpl(const Bus& bus) noexcept
+  : bus(std::make_shared<Bus>(bus))
+  , gpr({ 0 })
+  , cpsr(0)
+  , spsr(0)
+  , is_flushed(false)
+  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
+  , spsr_banked({ 0, 0, 0, 0, 0 }) {
+    cpsr.set_mode(Mode::Supervisor);
+    cpsr.set_irq_disabled(true);
+    cpsr.set_fiq_disabled(true);
+    cpsr.set_state(State::Arm);
+    glogger.info("CPU successfully initialised");
+
+    // PC always points to two instructions ahead
+    // PC - 2 is the instruction being executed
+    pc += 2 * arm::INSTRUCTION_SIZE;
+}
+
+/* change modes */
+void
+CpuImpl::chg_mode(const Mode to) {
+    Mode from = cpsr.mode();
+
+    if (from == to)
+        return;
+
+/* TODO: replace visible registers with view once I understand how to
+ * concatenate views */
+#define STORE_BANKED(mode, MODE)                                               \
+    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
+              gpr.begin() + gpr.size() - 1,                                    \
+              gpr_banked.mode.begin())
+
+    switch (from) {
+        case Mode::Fiq:
+            STORE_BANKED(fiq, FIQ);
+            spsr_banked.fiq = spsr;
+            break;
+
+        case Mode::Supervisor:
+            STORE_BANKED(svc, SVC);
+            spsr_banked.svc = spsr;
+            break;
+
+        case Mode::Abort:
+            STORE_BANKED(abt, ABT);
+            spsr_banked.abt = spsr;
+            break;
+
+        case Mode::Irq:
+            STORE_BANKED(irq, IRQ);
+            spsr_banked.irq = spsr;
+            break;
+
+        case Mode::Undefined:
+            STORE_BANKED(und, UND);
+            spsr_banked.und = spsr;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            STORE_BANKED(old, SYS_USR);
+            break;
+    }
+
+#define RESTORE_BANKED(mode, MODE)                                             \
+    std::copy(gpr_banked.mode.begin(),                                         \
+              gpr_banked.mode.end(),                                           \
+              gpr.begin() + GPR_##MODE##_FIRST)
+
+    switch (to) {
+        case Mode::Fiq:
+            RESTORE_BANKED(fiq, FIQ);
+            spsr = spsr_banked.fiq;
+            break;
+
+        case Mode::Supervisor:
+            RESTORE_BANKED(svc, SVC);
+            spsr = spsr_banked.svc;
+            break;
+
+        case Mode::Abort:
+            RESTORE_BANKED(abt, ABT);
+            spsr = spsr_banked.abt;
+            break;
+
+        case Mode::Irq:
+            RESTORE_BANKED(irq, IRQ);
+            spsr = spsr_banked.irq;
+            break;
+
+        case Mode::Undefined:
+            RESTORE_BANKED(und, UND);
+            spsr = spsr_banked.und;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            STORE_BANKED(old, SYS_USR);
+            break;
+    }
+
+#undef RESTORE_BANKED
+
+    cpsr.set_mode(to);
+}
+
+void
+CpuImpl::step() {
+    // Current instruction is two instructions behind PC
+    uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
+
+    if (cpsr.state() == State::Arm) {
+        uint32_t x = bus->read_word(cur_pc);
+        arm::Instruction instruction(x);
+        glogger.info("{:#034b}", x);
+
+        exec_arm(instruction);
+
+        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
+
+        if (is_flushed) {
+            // if flushed, do not increment the PC, instead set it to two
+            // instructions ahead to account for flushed "fetch" and "decode"
+            // instructions
+            pc += 2 * arm::INSTRUCTION_SIZE;
+            is_flushed = false;
+        } else {
+            // if not flushed continue like normal
+            pc += arm::INSTRUCTION_SIZE;
+        }
+    }
+}
+}

src/cpu/cpu-impl.hh

@@ -0,0 +1,59 @@
+#pragma once
+
+#include "bus.hh"
+#include "cpu/arm/instruction.hh"
+#include "cpu/psr.hh"
+
+#include <cstdint>
+
+namespace matar {
+class CpuImpl {
+  public:
+    CpuImpl(const Bus& bus) noexcept;
+
+    void step();
+    void chg_mode(const Mode to);
+    void exec_arm(const arm::Instruction instruction);
+
+    static constexpr uint8_t GPR_COUNT = 16;
+
+    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
+    static constexpr uint8_t GPR_SVC_FIRST     = 13;
+    static constexpr uint8_t GPR_ABT_FIRST     = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
+    static constexpr uint8_t GPR_UND_FIRST     = 13;
+    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+
+    Psr cpsr; // current program status register
+    Psr spsr; // status program status register
+
+    static constexpr uint8_t PC_INDEX = 15;
+    static_assert(PC_INDEX < GPR_COUNT);
+
+    uint32_t& pc = gpr[PC_INDEX];
+
+    bool is_flushed;
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
+    } gpr_banked; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked; // banked saved program status registers
+};
+}

src/cpu/cpu.cc

@@ -1,117 +1,14 @@
-#include "cpu.hh"
+#include "cpu/cpu.hh"
-#include "cpu/utility.hh"
+#include "cpu-impl.hh"
-#include <algorithm>
-#include <cstdio>
 
-Cpu::Cpu(Bus bus)
+namespace matar {
-  : gpr(0)
+Cpu::Cpu(const Bus& bus) noexcept
-  , cpsr(0)
+  : impl(std::make_unique<CpuImpl>(bus)){};
-  , spsr(0)
+
-  , bus(bus)
+Cpu::~Cpu() = default;
-  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
-  , spsr_banked({ 0, 0, 0, 0, 0 }) {
-    cpsr.set_mode(Mode::System);
-    cpsr.set_irq_disabled(true);
-    cpsr.set_fiq_disabled(true);
-    cpsr.set_state(State::Arm);
-}
 
-/* change modes */
 void
-Cpu::chg_mode(Mode from, Mode to) {
+Cpu::step() {
-    if (from == to)
+    impl->step();
-        return;
+};
-
-/* TODO: replace visible registers with view once I understand how to
- * concatenate views */
-#define STORE_BANKED(mode, MODE)                                               \
-    std::copy(gpr + GPR_##MODE##_BANKED_FIRST,                                 \
-              gpr + GPR_##MODE##_BANKED_FIRST + GPR_##MODE##_BANKED_COUNT,     \
-              gpr_banked.mode)
-
-    switch (from) {
-        case Mode::Fiq:
-            STORE_BANKED(fiq, FIQ);
-            spsr_banked.fiq = spsr;
-            break;
-
-        case Mode::Supervisor:
-            STORE_BANKED(svc, SVC);
-            spsr_banked.svc = spsr;
-            break;
-
-        case Mode::Abort:
-            STORE_BANKED(abt, ABT);
-            spsr_banked.abt = spsr;
-            break;
-
-        case Mode::Irq:
-            STORE_BANKED(irq, IRQ);
-            spsr_banked.irq = spsr;
-            break;
-
-        case Mode::Undefined:
-            STORE_BANKED(und, UND);
-            spsr_banked.und = spsr;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#define RESTORE_BANKED(mode, MODE)                                             \
-    std::copy(gpr_banked.mode,                                                 \
-              gpr_banked.mode + GPR_##MODE##_BANKED_COUNT,                     \
-              gpr + GPR_##MODE##_BANKED_FIRST)
-
-    switch (to) {
-        case Mode::Fiq:
-            RESTORE_BANKED(fiq, FIQ);
-            spsr = spsr_banked.fiq;
-            break;
-
-        case Mode::Supervisor:
-            RESTORE_BANKED(svc, SVC);
-            spsr = spsr_banked.svc;
-            break;
-
-        case Mode::Abort:
-            RESTORE_BANKED(abt, ABT);
-            spsr = spsr_banked.abt;
-            break;
-
-        case Mode::Irq:
-            RESTORE_BANKED(irq, IRQ);
-            spsr = spsr_banked.irq;
-            break;
-
-        case Mode::Undefined:
-            RESTORE_BANKED(und, UND);
-            spsr = spsr_banked.und;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#undef RESTORE_BANKED
-
-    cpsr.set_mode(to);
-}
-
-//  set register
-inline uint32_t&
-Cpu::operator[](uint8_t idx) {
-    // avoid unneeded complexity like index checks
-    return gpr[idx];
-}
-
-// get register
-inline const uint32_t&
-Cpu::operator[](uint8_t idx) const {
-    return gpr[idx];
 }

src/cpu/cpu.hh

@@ -1,63 +0,0 @@
-#pragma once
-
-#include "bus.hh"
-#include "psr.hh"
-
-#include <cstdint>
-
-using std::size_t;
-
-class Cpu {
-  public:
-    Cpu(Bus bus);
-
-  private:
-    static constexpr size_t GPR_FIQ_BANKED_FIRST = 8;
-    static constexpr size_t GPR_FIQ_BANKED_COUNT = 7;
-
-    static constexpr size_t GPR_SVC_BANKED_FIRST = 13;
-    static constexpr size_t GPR_SVC_BANKED_COUNT = 2;
-
-    static constexpr size_t GPR_ABT_BANKED_FIRST = 13;
-    static constexpr size_t GPR_ABT_BANKED_COUNT = 2;
-
-    static constexpr size_t GPR_IRQ_BANKED_FIRST = 13;
-    static constexpr size_t GPR_IRQ_BANKED_COUNT = 2;
-
-    static constexpr size_t GPR_UND_BANKED_FIRST = 13;
-    static constexpr size_t GPR_UND_BANKED_COUNT = 2;
-
-    static constexpr size_t GPR_SYS_USR_BANKED_FIRST = 8;
-    static constexpr size_t GPR_SYS_USR_BANKED_COUNT = 7;
-
-    static constexpr size_t GPR_VISIBLE_COUNT = 16;
-
-    uint32_t gpr[GPR_VISIBLE_COUNT]; // general purpose registers
-    Psr cpsr;                        // current program status register
-    Psr spsr;                        // status program status register
-    Bus bus;
-
-    struct {
-        uint32_t fiq[GPR_FIQ_BANKED_COUNT];
-        uint32_t svc[GPR_SVC_BANKED_COUNT];
-        uint32_t abt[GPR_ABT_BANKED_COUNT];
-        uint32_t irq[GPR_IRQ_BANKED_COUNT];
-        uint32_t und[GPR_UND_BANKED_COUNT];
-
-        // visible registers before the mode switch
-        uint32_t old[GPR_SYS_USR_BANKED_COUNT];
-    } gpr_banked; // banked general purpose registers
-
-    struct {
-        Psr fiq;
-        Psr svc;
-        Psr abt;
-        Psr irq;
-        Psr und;
-    } spsr_banked; // banked saved program status registers
-
-    void chg_mode(Mode from, Mode to);
-
-    uint32_t& operator[](uint8_t idx);
-    const uint32_t& operator[](uint8_t idx) const;
-};

src/cpu/meson.build

@@ -1,6 +1,8 @@
 lib_sources += files(
+  'cpu-impl.cc',
   'cpu.cc',
-  'psr.cc'
+  'psr.cc',
+  'alu.cc'
 )
 
 subdir('arm')

src/cpu/psr.cc

@@ -1,8 +1,19 @@
 #include "psr.hh"
 #include "util/bits.hh"
+#include "util/log.hh"
 
-Psr::Psr(uint32_t raw) {
+namespace matar {
-    psr = raw & PSR_CLEAR_RESERVED;
+Psr::Psr(uint32_t raw)
+  : psr(raw & PSR_CLEAR_RESERVED) {}
+
+uint32_t
+Psr::raw() const {
+    return psr;
+}
+
+void
+Psr::set_all(uint32_t raw) {
+    psr = raw & ~PSR_CLEAR_RESERVED;
 }
 
 Mode
@@ -16,22 +27,22 @@ Psr::set_mode(Mode mode) {
     psr |= static_cast<uint32_t>(mode);
 }
 
-bool
+State
 Psr::state() const {
-    return get_nth_bit(psr, 5);
+    return static_cast<State>(get_bit(psr, 5));
 }
 
 void
 Psr::set_state(State state) {
-    chg_nth_bit(psr, 5, static_cast<bool>(state));
+    chg_bit(psr, 5, static_cast<bool>(state));
 }
 
 #define GET_SET_NTH_BIT_FUNCTIONS(name, n)                                     \
     bool Psr::name() const {                                                   \
-        return get_nth_bit(psr, n);                                            \
+        return get_bit(psr, n);                                                \
     }                                                                          \
     void Psr::set_##name(bool val) {                                           \
-        chg_nth_bit(psr, n, val);                                              \
+        chg_bit(psr, n, val);                                                  \
     }
 
 GET_SET_NTH_BIT_FUNCTIONS(fiq_disabled, 6)
@@ -47,3 +58,75 @@ GET_SET_NTH_BIT_FUNCTIONS(z, 30);
 GET_SET_NTH_BIT_FUNCTIONS(n, 31);
 
 #undef GET_SET_NTH_BIT_FUNCTIONS
+
+bool
+Psr::condition(Condition cond) const {
+    switch (cond) {
+        case Condition::EQ:
+            return z();
+        case Condition::NE:
+            return !z();
+        case Condition::CS:
+            return c();
+        case Condition::CC:
+            return !c();
+        case Condition::MI:
+            return n();
+        case Condition::PL:
+            return !n();
+        case Condition::VS:
+            return v();
+        case Condition::VC:
+            return !v();
+        case Condition::HI:
+            return c() && !z();
+        case Condition::LS:
+            return !c() || z();
+        case Condition::GE:
+            return n() == v();
+        case Condition::LT:
+            return n() != v();
+        case Condition::GT:
+            return !z() && (n() == v());
+        case Condition::LE:
+            return z() || (n() != v());
+        case Condition::AL:
+            return true && state() == State::Arm;
+    }
+
+    return false;
+}
+
+std::ostream&
+operator<<(std::ostream& os, const Condition cond) {
+
+#define CASE(cond)                                                             \
+    case Condition::cond:                                                      \
+        os << #cond;                                                           \
+        break;
+
+    switch (cond) {
+        CASE(EQ)
+        CASE(NE)
+        CASE(CS)
+        CASE(CC)
+        CASE(MI)
+        CASE(PL)
+        CASE(VS)
+        CASE(VC)
+        CASE(HI)
+        CASE(LS)
+        CASE(GE)
+        CASE(LT)
+        CASE(GT)
+        CASE(LE)
+        case Condition::AL: {
+            // empty
+        }
+    }
+
+#undef CASE
+
+    return os;
+}
+}

src/cpu/psr.hh

@@ -1,20 +1,57 @@
 #pragma once
 
-#include "util/bits.hh"
-#include "utility.hh"
 #include <cstdint>
+#include <fmt/ostream.h>
+
+namespace matar {
+enum class Mode {
+    /* M[4:0] in PSR */
+    User       = 0b10000,
+    Fiq        = 0b10001,
+    Irq        = 0b10010,
+    Supervisor = 0b10011,
+    Abort      = 0b10111,
+    Undefined  = 0b11011,
+    System     = 0b11111,
+};
+
+enum class State {
+    Arm   = 0,
+    Thumb = 1
+};
+
+enum class Condition {
+    EQ = 0b0000,
+    NE = 0b0001,
+    CS = 0b0010,
+    CC = 0b0011,
+    MI = 0b0100,
+    PL = 0b0101,
+    VS = 0b0110,
+    VC = 0b0111,
+    HI = 0b1000,
+    LS = 0b1001,
+    GE = 0b1010,
+    LT = 0b1011,
+    GT = 0b1100,
+    LE = 0b1101,
+    AL = 0b1110
+};
 
 class Psr {
   public:
     // clear the reserved bits i.e, [8:27]
     Psr(uint32_t raw);
 
+    uint32_t raw() const;
+    void set_all(uint32_t raw);
+
     // Mode : [4:0]
     Mode mode() const;
     void set_mode(Mode mode);
 
     // State : [5]
-    bool state() const;
+    State state() const;
     void set_state(State state);
 
 #define GET_SET_NTH_BIT_FUNCTIONS(name)                                        \
@@ -43,9 +80,21 @@ class Psr {
 
 #undef GET_SET_NTH_BIT_FUNCTIONS
 
+    bool condition(Condition cond) const;
+
   private:
-    static constexpr uint32_t PSR_CLEAR_RESERVED = 0xf00000ff;
+    static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
-    static constexpr uint32_t PSR_CLEAR_MODE     = 0x0b00000;
+    static constexpr uint32_t PSR_CLEAR_MODE     = 0xFFFFFFE0;
 
     uint32_t psr;
 };
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const Condition cond);
+}
+
+namespace fmt {
+template<>
+struct formatter<matar::Condition> : ostream_formatter {};
+}

src/cpu/utility.hh

@@ -1,17 +0,0 @@
-#pragma once
-
-enum class Mode {
-    /* M[4:0] in PSR */
-    User       = 0b10000,
-    Fiq        = 0b10001,
-    Irq        = 0b10010,
-    Supervisor = 0b10011,
-    Abort      = 0b10111,
-    Undefined  = 0b11011,
-    System     = 0b11111,
-};
-
-enum class State {
-    Arm   = 0,
-    Thumb = 1
-};

src/header.hh

@@ -1,44 +0,0 @@
-#pragma once
-
-#include <cstdint>
-#include <vector>
-
-typedef struct {
-    enum class UniqueCode {
-        Old,        // old games
-        New,        // new games
-        Newer,      // unused (newer games)
-        Famicom,    // NES
-        YoshiKoro,  // acceleration sensor
-        Ereader,    // dot code scanner
-        Warioware,  // rumble and z-axis gyro
-        Boktai,     // RTC and solar sensor
-        DrillDozer, // rumble
-    };
-
-    enum class I18n {
-        Japan,
-        Europe,
-        French,
-        Spanish,
-        Usa,
-        German,
-        Italian
-    };
-
-    enum class BootMode {
-        Joybus,
-        Normal,
-        Multiplay
-    };
-
-    uint32_t entrypoint;
-    char title[12];
-    UniqueCode unique_code;
-    char title_code[2];
-    I18n i18n;
-    uint8_t version;
-    BootMode multiboot;
-    uint32_t multiboot_entrypoint;
-    uint8_t slave_id;
-} Header;

src/memory.cc

@@ -1,32 +1,37 @@
 #include "memory.hh"
 #include "header.hh"
+#include "util/bits.hh"
+#include "util/crypto.hh"
 #include "util/log.hh"
-#include "util/utils.hh"
+#include <bitset>
+#include <stdexcept>
 
+namespace matar {
 Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-               std::vector<uint8_t>&& rom) noexcept
+               std::vector<uint8_t>&& rom)
   : bios(std::move(bios))
-  , board_wram(0)
+  , board_wram({ 0 })
-  , chip_wram(0)
+  , chip_wram({ 0 })
-  , palette_ram(0)
+  , palette_ram({ 0 })
-  , vram(0)
+  , vram({ 0 })
-  , oam_obj_attr(0)
+  , oam_obj_attr({ 0 })
   , rom(std::move(rom)) {
-    std::string bios_hash = crypto::sha256(bios.data(), bios.size());
+    std::string bios_hash = crypto::sha256(this->bios);
-    std::string expected_hash =
+    static constexpr std::string_view expected_hash =
       "fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
 
     if (bios_hash != expected_hash) {
-        log_warn("BIOS hash failed to match, run at your own risk",
+        glogger.warn("BIOS hash failed to match, run at your own risk"
-                 "\nExpected : ",
+                     "\nExpected : {} "
-                 expected_hash,
+                     "\nGot      : {}",
-                 "\nGot      : ",
+                     expected_hash,
-                 bios_hash);
+                     bios_hash);
     }
 
     parse_header();
 
-    log("Memory successfully initialised");
+    glogger.info("Memory successfully initialised");
+    glogger.info("Cartridge Title: {}", header.title);
 };
 
 #define MATCHES(area) address >= area##_START&& address <= area##_END
@@ -52,8 +57,8 @@ Memory::read(size_t address) const {
     } else if (MATCHES(ROM_2)) {
         return rom[address - ROM_2_START];
     } else {
-        log_error("Invalid memory region accessed");
+        glogger.error("Invalid memory region accessed");
-        return 0;
+        return 0xFF;
     }
 }
 
@@ -78,61 +83,30 @@ Memory::write(size_t address, uint8_t byte) {
     } else if (MATCHES(ROM_2)) {
         rom[address - ROM_2_START] = byte;
     } else {
-        log_error("Invalid memory region accessed");
+        glogger.error("Invalid memory region accessed");
     }
 }
 
 #undef MATCHES
 
-uint16_t
-Memory::read_halfword(size_t address) const {
-    if (address & 0b01)
-        log_warn("Reading a non aligned halfword address");
-
-    return read(address) | read(address + 1) << 8;
-}
-
-void
-Memory::write_halfword(size_t address, uint16_t halfword) {
-    if (address & 0b01)
-        log_warn("Writing to a non aligned halfword address");
-
-    write(address, halfword & 0xFF);
-    write(address + 1, halfword >> 8 & 0xFF);
-}
-
-uint32_t
-Memory::read_word(size_t address) const {
-    if (address & 0b11)
-        log_warn("Reading a non aligned word address");
-
-    return read(address) | read(address + 1) << 8 | read(address + 2) << 16 |
-           read(address + 3) << 24;
-}
-
-void
-Memory::write_word(size_t address, uint32_t halfword) {
-    if (address & 0b11)
-        log_warn("Writing to a non aligned word address");
-
-    write(address, halfword & 0xFF);
-    write(address + 1, halfword >> 8 & 0xFF);
-    write(address + 2, halfword >> 16 & 0xFF);
-    write(address + 3, halfword >> 24 & 0xFF);
-}
-
 void
 Memory::parse_header() {
+
+    if (rom.size() < header.HEADER_SIZE) {
+        throw std::out_of_range(
+          "ROM is not large enough to even have a header");
+    }
+
     // entrypoint
     header.entrypoint =
       rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
 
     // nintendo logo
     if (rom[0x9C] != 0x21)
-        log_info("HEADER: BIOS debugger bits not set to 0");
+        glogger.info("HEADER: BIOS debugger bits not set to 0");
 
     // game info
-    std::copy(&rom[0xA0], &rom[0xA0 + 12], header.title);
+    header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
 
     switch (rom[0xAC]) {
         case 'A':
@@ -164,11 +138,10 @@ Memory::parse_header() {
             break;
 
         default:
-            log_error("HEADER: invalid unique code: ", rom[0xAC]);
+            glogger.error("HEADER: invalid unique code: {}", rom[0xAC]);
     }
 
-    header.title_code[0] = rom[0xAD];
+    header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
-    header.title_code[1] = rom[0xAE];
 
     switch (rom[0xAF]) {
         case 'J':
@@ -194,15 +167,16 @@ Memory::parse_header() {
             break;
 
         default:
-            log_error("HEADER: invalid destination/language - ", rom[0xAF]);
+            glogger.error("HEADER: invalid destination/language: {}",
+                          rom[0xAF]);
     }
 
     if (rom[0xB2] != 0x96)
-        log_error("HEADER: invalid fixed byte at 0xB2");
+        glogger.error("HEADER: invalid fixed byte at 0xB2");
 
     for (size_t i = 0xB5; i < 0xBC; i++) {
         if (rom[i] != 0x00)
-            log_error("HEADER: invalid fixed bytes at 0xB5");
+            glogger.error("HEADER: invalid fixed bytes at 0xB5");
     }
 
     header.version = rom[0xBC];
@@ -216,8 +190,9 @@ Memory::parse_header() {
         chk &= 0xFF;
 
         if (chk != rom[0xBD])
-            log_error("HEADER: checksum does not match");
+            glogger.error("HEADER: checksum does not match");
     }
 
     // multiboot not required right now
 }
+}

src/memory.hh

@@ -1,64 +0,0 @@
-#pragma once
-
-#include "header.hh"
-#include <array>
-#include <cstddef>
-#include <cstdint>
-#include <vector>
-
-class Memory {
-  public:
-    static constexpr size_t BIOS_SIZE = 1024 * 16;
-
-    Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-           std::vector<uint8_t>&& rom) noexcept;
-
-    uint8_t read(size_t address) const;
-    void write(size_t address, uint8_t byte);
-
-    uint16_t read_halfword(size_t address) const;
-    void write_halfword(size_t address, uint16_t halfword);
-
-    uint32_t read_word(size_t address) const;
-    void write_word(size_t address, uint32_t word);
-
-  private:
-#define MEMORY_REGION(name, start, end)                                        \
-    static constexpr size_t name##_START = start;                              \
-    static constexpr size_t name##_END   = end;
-
-#define DECL_MEMORY(name, ident, start, end)                                   \
-    MEMORY_REGION(name, start, end)                                            \
-    uint8_t ident[name##_END - name##_START + 1];
-
-    MEMORY_REGION(BIOS, 0x00000000, 0x00003FFF)
-    std::array<uint8_t, BIOS_SIZE> bios;
-    static_assert(BIOS_END - BIOS_START + 1 == BIOS_SIZE);
-
-    // board working RAM
-    DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
-
-    // chip working RAM
-    DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
-
-    // palette RAM
-    DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
-
-    // video RAM
-    DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
-
-    // OAM OBJ attributes
-    DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
-
-#undef DECL_MEMORY
-
-    MEMORY_REGION(ROM_0, 0x08000000, 0x09FFFFFF)
-    MEMORY_REGION(ROM_1, 0x0A000000, 0x0BFFFFFF)
-    MEMORY_REGION(ROM_2, 0x0C000000, 0x0DFFFFFF)
-
-#undef MEMORY_REGION
-
-    std::vector<uint8_t> rom;
-    Header header;
-    void parse_header();
-};

src/meson.build

@@ -6,10 +6,21 @@ lib_sources = files(
 subdir('util')
 subdir('cpu')
 
+lib_cpp_args = [ ]
+
+fmt = dependency('fmt', version : '>=10.1.0', static: true)
+if not fmt.found()
+  fmt = dependency('fmt', version : '>=10.1.0', static: false)
+  lib_cpp_args += 'DFMT_HEADER_ONLY'
+endif
+
 lib = library(
   meson.project_name(),
   lib_sources,
-  install: true
+  dependencies: [fmt],
+  include_directories: inc,
+  install: true,
+  cpp_args: lib_cpp_args
 )
 
-import('pkgconfig').generate(lib)
+import('pkgconfig').generate(lib)

src/util/bits.hh

@@ -7,33 +7,34 @@ using std::size_t;
 
 template<std::integral Int>
 inline bool
-get_nth_bit(Int num, size_t n) {
+get_bit(Int num, size_t n) {
-    return (1 && (num >> n));
+    return (num >> n) & 1;
 }
 
 template<std::integral Int>
 inline void
-set_nth_bit(Int& num, size_t n) {
+set_bit(Int& num, size_t n) {
-    num |= (1 << n);
+    num |= (static_cast<Int>(1) << n);
 }
 
 template<std::integral Int>
 inline void
-rst_nth_bit(Int& num, size_t n) {
+rst_bit(Int& num, size_t n) {
-    num &= ~(1 << n);
+    num &= ~(static_cast<Int>(1) << n);
 }
 
 template<std::integral Int>
 inline void
-chg_nth_bit(Int& num, size_t n, bool x) {
+chg_bit(Int& num, size_t n, bool x) {
-    num ^= (num ^ -x) & 1 << n;
+    num = (num & ~(static_cast<Int>(1) << n)) | (static_cast<Int>(x) << n);
 }
 
 /// read range of bits from start to end inclusive
-template<std::unsigned_integral Int>
+template<std::integral Int>
 inline Int
-get_bit_range(Int& num, size_t start, size_t end) {
+bit_range(Int num, size_t start, size_t end) {
-    // NOTE: we do not require -1 if it is a signed integral (which it is not)
+    // NOTE: we do not require -1 if it is a signed integral
-    Int left = std::numeric_limits<Int>::digits - 1 - end;
+    Int left =
-    return num << left >> (left + start);
+      std::numeric_limits<Int>::digits - (std::is_unsigned<Int>::value) - end;
+    return static_cast<Int>(num << left) >> (left + start);
 }

src/util/crypto.hh

@@ -1,23 +1,27 @@
-#include "utils.hh"
+#pragma once
-#include <bit>
-#include <iomanip>
-#include <sstream>
-#include <vector>
 
+#include <array>
+#include <bit>
+#include <fmt/core.h>
+#include <string>
+
+// Why I wrote this myself? I do not know
+// I will off myself 😹😹😹😹
 namespace crypto {
 
 using std::rotr;
 
+template<typename std::size_t N>
 std::string
-sha256(const uint8_t* data, const size_t size) {
+sha256(std::array<uint8_t, N>& data) {
     // Assuming 1 byte = 8 bits
-    std::stringstream string;
+    std::string string;
-    size_t k = 512 - (size * 8 + 65) % 512;
+    size_t k = 512 - (N * 8 + 65) % 512;
-    size_t L = size + (65 + k) / 8;
+    size_t L = N + (65 + k) / 8;
-    size_t i, j;
+    size_t i = 0, j = 0;
     bool c = 0;
 
-    static constexpr uint32_t K[64] = {
+    static constexpr std::array<uint32_t, 64> K = {
         0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1,
         0x923f82a4, 0xab1c5ed5, 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3,
         0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, 0xe49b69c1, 0xefbe4786,
@@ -31,13 +35,15 @@ sha256(const uint8_t* data, const size_t size) {
         0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2
     };
 
-    uint32_t h[8] = { 0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a,
+    std::array<uint32_t, 8> h = { 0x6a09e667, 0xbb67ae85, 0x3c6ef372,
-                      0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19 };
+                                  0xa54ff53a, 0x510e527f, 0x9b05688c,
+                                  0x1f83d9ab, 0x5be0cd19 };
 
     for (i = 0; i < L; i += 64) {
-        size_t n = (size > i ? size - i : 0);
+        size_t n = (N > i ? N - i : 0);
-        uint32_t h0[8];
+
-        uint32_t w[64] = { 0 };
+        std::array<uint32_t, 8> h0 = { 0 };
+        std::array<uint32_t, 64> w = { 0 };
 
         if (n == 64)
             c = 1;
@@ -48,10 +54,10 @@ sha256(const uint8_t* data, const size_t size) {
                        data[i + j * 4 + 2] << 8 | data[i + j * 4 + 3];
             }
         } else {
-            uint8_t cur[64] = { 0 };
+            std::array<uint32_t, 64> cur = { 0 };
 
             if (n) {
-                std::copy(data + i, data + size, cur);
+                std::copy(data.begin() + i, data.begin() + N, cur.begin());
                 cur[n] = 0x80;
             } else if (c) {
                 cur[n] = 0x80;
@@ -59,7 +65,7 @@ sha256(const uint8_t* data, const size_t size) {
 
             if (n < 54) {
                 for (j = 56; j < 64; j++) {
-                    cur[j] = (size * 8 >> ((63 - j) * 8)) & 0xFF;
+                    cur[j] = (N * 8 >> ((63 - j) * 8)) & 0xFF;
                 }
             }
 
@@ -78,7 +84,7 @@ sha256(const uint8_t* data, const size_t size) {
             w[j] = w[j - 16] + w[j - 7] + s0 + s1;
         }
 
-        std::copy(h, h + 8, h0);
+        std::copy(h.begin(), h.end(), h0.begin());
 
         for (j = 0; j < 64; j++) {
             uint32_t s1  = rotr(h0[4], 6) ^ rotr(h0[4], 11) ^ rotr(h0[4], 25);
@@ -102,12 +108,12 @@ sha256(const uint8_t* data, const size_t size) {
             h[j] += h0[j];
     }
 
-    string << std::hex << std::setfill('0');
-
     for (j = 0; j < 8; j++)
         for (i = 0; i < 4; i++)
-            string << std::setw(2) << ((h[j] >> (24 - i * 8)) & 0xFF);
+            fmt::format_to(std::back_inserter(string),
+                           "{:02x}",
+                           ((h[j] >> (24 - i * 8)) & 0xFF));
 
-    return string.str();
+    return string;
 }
 }

src/util/log.cc

@@ -1,49 +1,8 @@
 #include "log.hh"
 
-namespace logging {
+logging::Logger glogger = logging::Logger();
-
-namespace ansi {
-static const char* RED     = "\033[31m";
-static const char* YELLOW  = "\033[33m";
-static const char* MAGENTA = "\033[35m";
-static const char* WHITE   = "\033[37m";
-static const char* BOLD    = "\033[1m";
-static const char* RESET   = "\033[0m";
-}
-
-Logger::Logger(std::ostream& os)
-  : os(os){};
 
 void
-Logger::set_level(Level level) {
+matar::set_log_level(LogLevel level) {
-    switch (level) {
+    glogger.set_level(level);
-        case Level::Debug:
-            os << ansi::MAGENTA << ansi::BOLD << "[DEBUG] ";
-            break;
-
-        case Level::Info:
-            os << ansi::WHITE << "[INFO] ";
-            break;
-
-        case Level::Warn:
-            os << ansi::YELLOW << "[WARN] ";
-            break;
-
-        case Level::Error:
-            os << ansi::RED << ansi::BOLD << "[ERROR] ";
-            break;
-
-            // unreachable
-        default: {
-        }
-    }
 }
-
-void
-Logger::reset_level() {
-    os << ansi::RESET;
-}
-}
-
-// Global logger
-logging::Logger logger;

src/util/log.hh

@@ -1,42 +1,83 @@
 #pragma once
 
-#include <iomanip>
+#include "util/loglevel.hh"
+#include <fmt/ostream.h>
 #include <iostream>
-#include <source_location>
-#include <streambuf>
 
 namespace logging {
-enum class Level {
+namespace ansi {
-    Debug,
+static constexpr auto RED     = "\033[31m";
-    Info,
+static constexpr auto YELLOW  = "\033[33m";
-    Warn,
+static constexpr auto MAGENTA = "\033[35m";
-    Error,
+static constexpr auto WHITE   = "\033[37m";
-};
+static constexpr auto BOLD    = "\033[1m";
+static constexpr auto RESET   = "\033[0m";
+}
+
+using fmt::print;
 
 class Logger {
-  public:
+    using LogLevel = matar::LogLevel;
-    Logger(std::ostream& os = std::clog);
 
-    template<typename... Args>
+  public:
-    void print(Level level, Args&&... args) {
+    Logger(LogLevel level = LogLevel::Debug, FILE* stream = stderr)
+      : level(0)
+      , stream(stream) {
         set_level(level);
-        (os << ... << args);
-        reset_level();
-        os << std::endl;
     }
 
+    template<typename... Args>
+    void log(const fmt::format_string<Args...>& fmt, Args&&... args) {
+        fmt::println(stream, fmt, std::forward<Args>(args)...);
+    }
+
+    template<typename... Args>
+    void debug(const fmt::format_string<Args...>& fmt, Args&&... args) {
+        if (level & static_cast<uint8_t>(LogLevel::Debug)) {
+            print(stream, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
+            log(fmt, std::forward<Args>(args)...);
+            print(stream, ansi::RESET);
+        }
+    }
+
+    template<typename... Args>
+    void info(const fmt::format_string<Args...>& fmt, Args&&... args) {
+        if (level & static_cast<uint8_t>(LogLevel::Info)) {
+            print(stream, "{}[INFO] ", ansi::WHITE);
+            log(fmt, std::forward<Args>(args)...);
+            print(stream, ansi::RESET);
+        }
+    }
+
+    template<typename... Args>
+    void warn(const fmt::format_string<Args...>& fmt, Args&&... args) {
+        if (level & static_cast<uint8_t>(LogLevel::Warn)) {
+            print(stream, "{}[WARN] ", ansi::YELLOW);
+            log(fmt, std::forward<Args>(args)...);
+            print(stream, ansi::RESET);
+        }
+    }
+
+    template<typename... Args>
+    void error(const fmt::format_string<Args...>& fmt, Args&&... args) {
+        if (level & static_cast<uint8_t>(LogLevel::Error)) {
+            print(stream, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
+            log(fmt, std::forward<Args>(args)...);
+            print(stream, ansi::RESET);
+        }
+    }
+
+    void set_level(LogLevel level) {
+        this->level = (static_cast<uint8_t>(level) << 1) - 1;
+    }
+    void set_stream(FILE* stream) { this->stream = stream; }
+
   private:
-    std::ostream& os;
+    uint8_t level;
-    void set_level(Level level);
+    FILE* stream;
-    void reset_level();
 };
 }
 
-extern logging::Logger logger;
+extern logging::Logger glogger;
 
-#define log_debug(...) logger.print(logging::Level::Debug, __VA_ARGS__)
+#define debug(x) glogger.debug("{} = {}", #x, x);
-#define log_info(...) logger.print(logging::Level::Info, __VA_ARGS__)
-#define log_warn(...) logger.print(logging::Level::Warn, __VA_ARGS__)
-#define log_error(...) logger.print(logging::Level::Error, __VA_ARGS__)
-#define log(...) log_info(__VA_ARGS__)
-#define debug(value) log_debug(#value, " = ", value)

src/util/meson.build

@@ -1,4 +1,3 @@
 lib_sources += files(
-  'log.cc',
+  'log.cc'
-  'utils.cc'
 )

src/util/utils.hh

@@ -1,10 +0,0 @@
-#pragma once
-
-#include <string>
-
-// Why I wrote this myself? I do not know
-// I will off myself 😹😹😹😹
-namespace crypto {
-std::string
-sha256(const uint8_t* data, const size_t size);
-}

tests/bus.cc

@@ -0,0 +1,43 @@
+#include "bus.hh"
+#include <catch2/catch_test_macros.hpp>
+
+static constexpr auto TAG = "[bus]";
+
+using namespace matar;
+
+class BusFixture {
+  public:
+    BusFixture()
+      : bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+                   std::vector<uint8_t>(Header::HEADER_SIZE))) {}
+
+  protected:
+    Bus bus;
+};
+
+TEST_CASE_METHOD(BusFixture, "Byte", TAG) {
+    CHECK(bus.read_byte(3349) == 0);
+
+    bus.write_byte(3349, 0xEC);
+    CHECK(bus.read_byte(3349) == 0xEC);
+    CHECK(bus.read_word(3349) == 0xEC);
+    CHECK(bus.read_halfword(3349) == 0xEC);
+}
+
+TEST_CASE_METHOD(BusFixture, "Halfword", TAG) {
+    CHECK(bus.read_halfword(33750745) == 0);
+
+    bus.write_halfword(33750745, 0x1A4A);
+    CHECK(bus.read_halfword(33750745) == 0x1A4A);
+    CHECK(bus.read_word(33750745) == 0x1A4A);
+    CHECK(bus.read_byte(33750745) == 0x4A);
+}
+
+TEST_CASE_METHOD(BusFixture, "Word", TAG) {
+    CHECK(bus.read_word(100724276) == 0);
+
+    bus.write_word(100724276, 0x3ACC491D);
+    CHECK(bus.read_word(100724276) == 0x3ACC491D);
+    CHECK(bus.read_halfword(100724276) == 0x491D);
+    CHECK(bus.read_byte(100724276) == 0x1D);
+}

tests/cpu/arm/instruction.cc

@@ -0,0 +1,469 @@
+#include "cpu/arm/instruction.hh"
+#include <catch2/catch_test_macros.hpp>
+
+static constexpr auto TAG = "[arm][disassembly]";
+
+using namespace matar;
+using namespace arm;
+
+TEST_CASE("Branch and Exchange", TAG) {
+    uint32_t raw = 0b11000001001011111111111100011010;
+    Instruction instruction(raw);
+    BranchAndExchange* bx = nullptr;
+
+    REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
+    CHECK(instruction.condition == Condition::GT);
+
+    CHECK(bx->rn == 10);
+
+    CHECK(instruction.disassemble() == "BXGT R10");
+}
+
+TEST_CASE("Branch", TAG) {
+    uint32_t raw = 0b11101011100001010111111111000011;
+    Instruction instruction(raw);
+    Branch* b = nullptr;
+
+    REQUIRE((b = std::get_if<Branch>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    // last 24 bits = 8748995
+    // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
+    // Also +8 since PC is two instructions ahead
+    CHECK(b->offset == 0xFE15FF14);
+    CHECK(b->link == true);
+
+    CHECK(instruction.disassemble() == "BL 0xFE15FF14");
+
+    b->link = false;
+    CHECK(instruction.disassemble() == "B 0xFE15FF14");
+}
+
+TEST_CASE("Multiply", TAG) {
+    uint32_t raw = 0b00000000001110101110111110010000;
+    Instruction instruction(raw);
+    Multiply* mul = nullptr;
+
+    REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
+    CHECK(instruction.condition == Condition::EQ);
+
+    CHECK(mul->rm == 0);
+    CHECK(mul->rs == 15);
+    CHECK(mul->rn == 14);
+    CHECK(mul->rd == 10);
+    CHECK(mul->acc == true);
+    CHECK(mul->set == true);
+
+    CHECK(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
+
+    mul->acc = false;
+    mul->set = false;
+    CHECK(instruction.disassemble() == "MULEQ R10,R0,R15");
+}
+
+TEST_CASE("Multiply Long", TAG) {
+    uint32_t raw = 0b00010000100111100111011010010010;
+    Instruction instruction(raw);
+    MultiplyLong* mull = nullptr;
+
+    REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
+    CHECK(instruction.condition == Condition::NE);
+
+    CHECK(mull->rm == 2);
+    CHECK(mull->rs == 6);
+    CHECK(mull->rdlo == 7);
+    CHECK(mull->rdhi == 14);
+    CHECK(mull->acc == false);
+    CHECK(mull->set == true);
+    CHECK(mull->uns == true);
+
+    CHECK(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
+
+    mull->acc = true;
+    CHECK(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
+
+    mull->uns = false;
+    mull->set = false;
+    CHECK(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
+}
+
+TEST_CASE("Undefined", TAG) {
+    // notice how this is the same as single data transfer except the shift
+    // is now a register based shift
+    uint32_t raw = 0b11100111101000101010111100010110;
+    Instruction instruction(raw);
+
+    CHECK(instruction.condition == Condition::AL);
+    CHECK(instruction.disassemble() == "UND");
+}
+
+TEST_CASE("Single Data Swap", TAG) {
+    uint32_t raw = 0b10100001000010010101000010010110;
+    Instruction instruction(raw);
+    SingleDataSwap* swp = nullptr;
+
+    REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
+    CHECK(instruction.condition == Condition::GE);
+
+    CHECK(swp->rm == 6);
+    CHECK(swp->rd == 5);
+    CHECK(swp->rn == 9);
+    CHECK(swp->byte == false);
+
+    CHECK(instruction.disassemble() == "SWPGE R5,R6,[R9]");
+
+    swp->byte = true;
+    CHECK(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
+}
+
+TEST_CASE("Single Data Transfer", TAG) {
+    uint32_t raw = 0b11100111101000101010111100000110;
+    Instruction instruction(raw);
+    SingleDataTransfer* ldr = nullptr;
+    Shift* shift            = nullptr;
+
+    REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
+    CHECK(shift->rm == 6);
+    CHECK(shift->data.immediate == true);
+    CHECK(shift->data.type == ShiftType::LSL);
+    CHECK(shift->data.operand == 30);
+    CHECK(ldr->rd == 10);
+    CHECK(ldr->rn == 2);
+    CHECK(ldr->load == false);
+    CHECK(ldr->write == true);
+    CHECK(ldr->byte == false);
+    CHECK(ldr->up == true);
+    CHECK(ldr->pre == true);
+
+    ldr->load        = true;
+    ldr->byte        = true;
+    ldr->write       = false;
+    shift->data.type = ShiftType::ROR;
+    CHECK(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
+
+    ldr->up  = false;
+    ldr->pre = false;
+    CHECK(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
+
+    ldr->offset = static_cast<uint16_t>(9023);
+    CHECK(instruction.disassemble() == "LDRB R10,[R2],-#9023");
+
+    ldr->pre = true;
+    CHECK(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
+}
+
+TEST_CASE("Halfword Transfer", TAG) {
+    uint32_t raw = 0b00110001101011110010000010110110;
+    Instruction instruction(raw);
+    HalfwordTransfer* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::CC);
+
+    // offset is not immediate
+    CHECK(ldr->imm == 0);
+    // hence this offset is a register number (rm)
+    CHECK(ldr->offset == 6);
+    CHECK(ldr->half == true);
+    CHECK(ldr->sign == false);
+    CHECK(ldr->rd == 2);
+    CHECK(ldr->rn == 15);
+    CHECK(ldr->load == false);
+    CHECK(ldr->write == true);
+    CHECK(ldr->up == true);
+    CHECK(ldr->pre == true);
+
+    CHECK(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
+
+    ldr->pre  = false;
+    ldr->load = true;
+    ldr->sign = true;
+    ldr->up   = false;
+
+    CHECK(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
+
+    ldr->half = false;
+    CHECK(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
+
+    ldr->load = false;
+    // not a register anymore
+    ldr->imm    = 1;
+    ldr->offset = 90;
+    CHECK(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
+}
+
+TEST_CASE("Block Data Transfer", TAG) {
+    uint32_t raw = 0b10011001010101110100000101101101;
+    Instruction instruction(raw);
+    BlockDataTransfer* ldm = nullptr;
+
+    REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::LS);
+
+    {
+        uint16_t regs = 0;
+        regs |= 1 << 0;
+        regs |= 1 << 2;
+        regs |= 1 << 3;
+        regs |= 1 << 5;
+        regs |= 1 << 6;
+        regs |= 1 << 8;
+        regs |= 1 << 14;
+
+        CHECK(ldm->regs == regs);
+    }
+
+    CHECK(ldm->rn == 7);
+    CHECK(ldm->load == true);
+    CHECK(ldm->write == false);
+    CHECK(ldm->s == true);
+    CHECK(ldm->up == false);
+    CHECK(ldm->pre == true);
+
+    CHECK(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
+
+    ldm->write = true;
+    ldm->s     = false;
+    ldm->up    = true;
+
+    CHECK(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
+
+    ldm->regs &= ~(1 << 6);
+    ldm->regs &= ~(1 << 3);
+    ldm->regs &= ~(1 << 8);
+    ldm->load = false;
+    ldm->pre  = false;
+
+    CHECK(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
+}
+
+TEST_CASE("PSR Transfer", TAG) {
+    PsrTransfer* msr = nullptr;
+
+    SECTION("MRS") {
+        uint32_t raw = 0b01000001010011111010000000000000;
+        Instruction instruction(raw);
+        PsrTransfer* mrs = nullptr;
+
+        REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::MI);
+
+        CHECK(mrs->type == PsrTransfer::Type::Mrs);
+        // Operand is a register in the case of MRS (PSR -> Register)
+        CHECK(mrs->operand == 10);
+        CHECK(mrs->spsr == true);
+
+        CHECK(instruction.disassemble() == "MRSMI R10,SPSR_all");
+    }
+
+    SECTION("MSR") {
+        uint32_t raw = 0b11100001001010011111000000001000;
+        Instruction instruction(raw);
+        PsrTransfer* msr = nullptr;
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::AL);
+
+        CHECK(msr->type == PsrTransfer::Type::Msr);
+        // Operand is a register in the case of MSR (Register -> PSR)
+        CHECK(msr->operand == 8);
+        CHECK(msr->spsr == false);
+
+        CHECK(instruction.disassemble() == "MSR CPSR_all,R8");
+    }
+
+    SECTION("MSR_flg with register operand") {
+        uint32_t raw = 0b01100001001010001111000000001000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::VS);
+
+        CHECK(msr->type == PsrTransfer::Type::Msr_flg);
+        CHECK(msr->imm == 0);
+        CHECK(msr->operand == 8);
+        CHECK(msr->spsr == false);
+
+        CHECK(instruction.disassemble() == "MSRVS CPSR_flg,R8");
+    }
+
+    SECTION("MSR_flg with immediate operand") {
+        uint32_t raw = 0b11100011011010001111011101101000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        CHECK(instruction.condition == Condition::AL);
+
+        CHECK(msr->type == PsrTransfer::Type::Msr_flg);
+        CHECK(msr->imm == 1);
+
+        // 104 (32 bits) rotated by 2 * 7
+        CHECK(msr->operand == 27262976);
+        CHECK(msr->spsr == true);
+
+        CHECK(instruction.disassemble() == "MSR SPSR_flg,#27262976");
+    }
+}
+
+TEST_CASE("Data Processing", TAG) {
+    using OpCode = DataProcessing::OpCode;
+
+    uint32_t raw = 0b11100000000111100111101101100001;
+    Instruction instruction(raw);
+    DataProcessing* alu = nullptr;
+    Shift* shift        = nullptr;
+
+    REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    // operand 2 is a shifted register
+    REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
+    CHECK(shift->rm == 1);
+    CHECK(shift->data.immediate == true);
+    CHECK(shift->data.type == ShiftType::ROR);
+    CHECK(shift->data.operand == 22);
+
+    CHECK(alu->rd == 7);
+    CHECK(alu->rn == 14);
+    CHECK(alu->set == true);
+    CHECK(alu->opcode == OpCode::AND);
+
+    CHECK(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
+
+    shift->data.immediate = false;
+    shift->data.operand   = 2;
+    alu->set              = false;
+
+    CHECK(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
+
+    alu->operand = static_cast<uint32_t>(3300012);
+    CHECK(instruction.disassemble() == "AND R7,R14,#3300012");
+
+    SECTION("set-only operations") {
+        alu->set = true;
+
+        alu->opcode = OpCode::TST;
+        CHECK(instruction.disassemble() == "TST R14,#3300012");
+
+        alu->opcode = OpCode::TEQ;
+        CHECK(instruction.disassemble() == "TEQ R14,#3300012");
+
+        alu->opcode = OpCode::CMP;
+        CHECK(instruction.disassemble() == "CMP R14,#3300012");
+
+        alu->opcode = OpCode::CMN;
+        CHECK(instruction.disassemble() == "CMN R14,#3300012");
+    }
+
+    SECTION("destination operations") {
+        alu->opcode = OpCode::EOR;
+        CHECK(instruction.disassemble() == "EOR R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSB;
+        CHECK(instruction.disassemble() == "RSB R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::ADC;
+        CHECK(instruction.disassemble() == "ADC R7,R14,#3300012");
+
+        alu->opcode = OpCode::SBC;
+        CHECK(instruction.disassemble() == "SBC R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSC;
+        CHECK(instruction.disassemble() == "RSC R7,R14,#3300012");
+
+        alu->opcode = OpCode::ORR;
+        CHECK(instruction.disassemble() == "ORR R7,R14,#3300012");
+
+        alu->opcode = OpCode::MOV;
+        CHECK(instruction.disassemble() == "MOV R7,#3300012");
+
+        alu->opcode = OpCode::BIC;
+        CHECK(instruction.disassemble() == "BIC R7,R14,#3300012");
+
+        alu->opcode = OpCode::MVN;
+        CHECK(instruction.disassemble() == "MVN R7,#3300012");
+    }
+}
+
+TEST_CASE("Coprocessor Data Transfer", TAG) {
+    uint32_t raw = 0b10101101101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataTransfer* ldc = nullptr;
+
+    REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::GE);
+
+    CHECK(ldc->offset == 70);
+    CHECK(ldc->cpn == 1);
+    CHECK(ldc->crd == 15);
+    CHECK(ldc->rn == 5);
+    CHECK(ldc->load == false);
+    CHECK(ldc->write == true);
+    CHECK(ldc->len == false);
+    CHECK(ldc->up == true);
+    CHECK(ldc->pre == true);
+
+    CHECK(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
+
+    ldc->load  = true;
+    ldc->pre   = false;
+    ldc->write = false;
+    ldc->len   = true;
+
+    CHECK(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
+}
+
+TEST_CASE("Coprocessor Operand Operation", TAG) {
+    uint32_t raw = 0b11101110101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataOperation* cdp = nullptr;
+
+    REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    CHECK(cdp->crm == 6);
+    CHECK(cdp->cp == 2);
+    CHECK(cdp->cpn == 1);
+    CHECK(cdp->crd == 15);
+    CHECK(cdp->crn == 5);
+    CHECK(cdp->cp_opc == 10);
+
+    CHECK(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
+}
+
+TEST_CASE("Coprocessor Register Transfer", TAG) {
+    uint32_t raw = 0b11101110101001011111000101010110;
+    Instruction instruction(raw);
+    CoprocessorRegisterTransfer* mrc = nullptr;
+
+    REQUIRE(
+      (mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
+    CHECK(instruction.condition == Condition::AL);
+
+    CHECK(mrc->crm == 6);
+    CHECK(mrc->cp == 2);
+    CHECK(mrc->cpn == 1);
+    CHECK(mrc->rd == 15);
+    CHECK(mrc->crn == 5);
+    CHECK(mrc->load == false);
+    CHECK(mrc->cp_opc == 5);
+
+    CHECK(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
+}
+
+TEST_CASE("Software Interrupt", TAG) {
+    uint32_t raw = 0b00001111101010101010101010101010;
+    Instruction instruction(raw);
+
+    CHECK(instruction.condition == Condition::EQ);
+    CHECK(instruction.disassemble() == "SWIEQ");
+}

tests/cpu/arm/meson.build

@@ -0,0 +1,4 @@
+tests_sources += files(
+  'instruction.cc',
+  'exec.cc'
+)

tests/cpu/meson.build

@@ -0,0 +1 @@
+subdir('arm')

tests/main.cc

@@ -0,0 +1,8 @@
+#include "util/loglevel.hh"
+#include <catch2/catch_session.hpp>
+
+int
+main(int argc, char* argv[]) {
+    matar::set_log_level(matar::LogLevel::Off);
+    return Catch::Session().run(argc, argv);
+}

tests/memory.cc

@@ -0,0 +1,121 @@
+#include "memory.hh"
+#include <catch2/catch_test_macros.hpp>
+
+static constexpr auto TAG = "[memory]";
+
+using namespace matar;
+
+class MemFixture {
+  public:
+    MemFixture()
+      : memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+               std::vector<uint8_t>(Header::HEADER_SIZE)) {}
+
+  protected:
+    Memory memory;
+};
+
+TEST_CASE_METHOD(MemFixture, "bios", TAG) {
+    memory.write(0, 0xAC);
+    CHECK(memory.read(0) == 0xAC);
+
+    memory.write(0x3FFF, 0x48);
+    CHECK(memory.read(0x3FFF) == 0x48);
+
+    memory.write(0x2A56, 0x10);
+    CHECK(memory.read(0x2A56) == 0x10);
+}
+
+TEST_CASE_METHOD(MemFixture, "board wram", TAG) {
+    memory.write(0x2000000, 0xAC);
+    CHECK(memory.read(0x2000000) == 0xAC);
+
+    memory.write(0x203FFFF, 0x48);
+    CHECK(memory.read(0x203FFFF) == 0x48);
+
+    memory.write(0x2022A56, 0x10);
+    CHECK(memory.read(0x2022A56) == 0x10);
+}
+
+TEST_CASE_METHOD(MemFixture, "chip wram", TAG) {
+    memory.write(0x3000000, 0xAC);
+    CHECK(memory.read(0x3000000) == 0xAC);
+
+    memory.write(0x3007FFF, 0x48);
+    CHECK(memory.read(0x3007FFF) == 0x48);
+
+    memory.write(0x3002A56, 0x10);
+    CHECK(memory.read(0x3002A56) == 0x10);
+}
+
+TEST_CASE_METHOD(MemFixture, "palette ram", TAG) {
+    memory.write(0x5000000, 0xAC);
+    CHECK(memory.read(0x5000000) == 0xAC);
+
+    memory.write(0x50003FF, 0x48);
+    CHECK(memory.read(0x50003FF) == 0x48);
+
+    memory.write(0x5000156, 0x10);
+    CHECK(memory.read(0x5000156) == 0x10);
+}
+
+TEST_CASE_METHOD(MemFixture, "video ram", TAG) {
+    memory.write(0x6000000, 0xAC);
+    CHECK(memory.read(0x6000000) == 0xAC);
+
+    memory.write(0x6017FFF, 0x48);
+    CHECK(memory.read(0x6017FFF) == 0x48);
+
+    memory.write(0x6012A56, 0x10);
+    CHECK(memory.read(0x6012A56) == 0x10);
+}
+
+TEST_CASE_METHOD(MemFixture, "oam obj ram", TAG) {
+    memory.write(0x7000000, 0xAC);
+    CHECK(memory.read(0x7000000) == 0xAC);
+
+    memory.write(0x70003FF, 0x48);
+    CHECK(memory.read(0x70003FF) == 0x48);
+
+    memory.write(0x7000156, 0x10);
+    CHECK(memory.read(0x7000156) == 0x10);
+}
+
+TEST_CASE("rom", TAG) {
+    // 32 megabyte ROM
+    Memory memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+                  std::vector<uint8_t>(32 * 1024 * 1024));
+
+    SECTION("ROM1") {
+        memory.write(0x8000000, 0xAC);
+        CHECK(memory.read(0x8000000) == 0xAC);
+
+        memory.write(0x9FFFFFF, 0x48);
+        CHECK(memory.read(0x9FFFFFF) == 0x48);
+
+        memory.write(0x8ef0256, 0x10);
+        CHECK(memory.read(0x8ef0256) == 0x10);
+    }
+
+    SECTION("ROM2") {
+        memory.write(0xA000000, 0xAC);
+        CHECK(memory.read(0xA000000) == 0xAC);
+
+        memory.write(0xBFFFFFF, 0x48);
+        CHECK(memory.read(0xBFFFFFF) == 0x48);
+
+        memory.write(0xAEF0256, 0x10);
+        CHECK(memory.read(0xAEF0256) == 0x10);
+    }
+
+    SECTION("ROM3") {
+        memory.write(0xC000000, 0xAC);
+        CHECK(memory.read(0xC000000) == 0xAC);
+
+        memory.write(0xDFFFFFF, 0x48);
+        CHECK(memory.read(0xDFFFFFF) == 0x48);
+
+        memory.write(0xCEF0256, 0x10);
+        CHECK(memory.read(0xCEF0256) == 0x10);
+    }
+}

tests/meson.build

@@ -0,0 +1,26 @@
+tests_deps = [
+  lib
+]
+
+src = include_directories('../src')
+
+tests_sources = files(
+  'main.cc',
+  'bus.cc',
+  'memory.cc'
+)
+
+subdir('cpu')
+subdir('util')
+
+catch2 = dependency('catch2', version: '>=3.4.0', static: true)
+catch2_tests = executable(
+  'matar_tests',
+  tests_sources,
+  dependencies: catch2,
+  link_with: tests_deps,
+  include_directories: [inc, src],
+  build_by_default: false,
+)
+
+test('catch2 tests', catch2_tests)

tests/util/bits.cc

@@ -0,0 +1,106 @@
+#include "util/bits.hh"
+#include <catch2/catch_test_macros.hpp>
+
+static constexpr auto TAG = "[util][bits]";
+
+TEST_CASE("8 bits", TAG) {
+    uint8_t num = 45;
+
+    CHECK(get_bit(num, 0));
+    CHECK(!get_bit(num, 1));
+    CHECK(get_bit(num, 5));
+    CHECK(!get_bit(num, 6));
+    CHECK(!get_bit(num, 7));
+
+    set_bit(num, 6);
+    CHECK(get_bit(num, 6));
+
+    rst_bit(num, 6);
+    CHECK(!get_bit(num, 6));
+
+    chg_bit(num, 5, false);
+    CHECK(!get_bit(num, 5));
+
+    chg_bit(num, 5, true);
+    CHECK(get_bit(num, 5));
+
+    // 0b0110
+    CHECK(bit_range(num, 1, 4) == 6);
+}
+
+TEST_CASE("16 bits", TAG) {
+    uint16_t num = 34587;
+
+    CHECK(get_bit(num, 0));
+    CHECK(get_bit(num, 1));
+    CHECK(!get_bit(num, 5));
+    CHECK(!get_bit(num, 14));
+    CHECK(get_bit(num, 15));
+
+    set_bit(num, 14);
+    CHECK(get_bit(num, 14));
+
+    rst_bit(num, 14);
+    CHECK(!get_bit(num, 14));
+
+    chg_bit(num, 5, true);
+    CHECK(get_bit(num, 5));
+
+    // num = 45
+    chg_bit(num, 5, false);
+    CHECK(!get_bit(num, 5));
+
+    // 0b1000110
+    CHECK(bit_range(num, 2, 8) == 70);
+}
+
+TEST_CASE("32 bits", TAG) {
+    uint32_t num = 3194142523;
+
+    CHECK(get_bit(num, 0));
+    CHECK(get_bit(num, 1));
+    CHECK(get_bit(num, 12));
+    CHECK(get_bit(num, 29));
+    CHECK(!get_bit(num, 30));
+    CHECK(get_bit(num, 31));
+
+    set_bit(num, 30);
+    CHECK(get_bit(num, 30));
+
+    rst_bit(num, 30);
+    CHECK(!get_bit(num, 30));
+
+    chg_bit(num, 12, false);
+    CHECK(!get_bit(num, 12));
+
+    chg_bit(num, 12, true);
+    CHECK(get_bit(num, 12));
+
+    // 0b10011000101011111100111
+    CHECK(bit_range(num, 3, 25) == 5003239);
+}
+
+TEST_CASE("64 bits", TAG) {
+    uint64_t num = 58943208889991935;
+
+    CHECK(get_bit(num, 0));
+    CHECK(get_bit(num, 1));
+    CHECK(!get_bit(num, 10));
+    CHECK(get_bit(num, 55));
+    CHECK(!get_bit(num, 60));
+
+    set_bit(num, 63);
+    CHECK(get_bit(num, 63));
+
+    rst_bit(num, 63);
+    CHECK(!get_bit(num, 63));
+
+    chg_bit(num, 10, true);
+    CHECK(get_bit(num, 10));
+
+    chg_bit(num, 10, false);
+    CHECK(!get_bit(num, 10));
+
+    // 0b011010001
+    CHECK(bit_range(num, 39, 47) == 209);
+}

tests/util/crypto.cc

@@ -0,0 +1,21 @@
+#include "util/crypto.hh"
+#include <catch2/catch_test_macros.hpp>
+
+static constexpr auto TAG = "[util][crypto]";
+
+TEST_CASE("sha256 matar", TAG) {
+    std::array<uint8_t, 5> data = { 'm', 'a', 't', 'a', 'r' };
+
+    CHECK(crypto::sha256(data) ==
+          "3b02a908fd5743c0e868675bb6ae77d2a62b3b5f7637413238e2a1e0e94b6a53");
+}
+
+TEST_CASE("sha256 forgis", TAG) {
+    std::array<uint8_t, 32> data = { 'i', ' ', 'p', 'u', 't', ' ', 't', 'h',
+                                     'e', ' ', 'n', 'e', 'w', ' ', 'f', 'o',
+                                     'r', 'g', 'i', 's', ' ', 'o', 'n', ' ',
+                                     't', 'h', 'e', ' ', 'j', 'e', 'e', 'p' };
+
+    CHECK(crypto::sha256(data) ==
+          "cfddca2ce2673f355518cbe2df2a8522693c54723a469e8b36a4f68b90d2b759");
+}

tests/util/meson.build

@@ -0,0 +1,4 @@
+tests_sources += files(
+  'bits.cc',
+  'crypto.cc'
+)