tests: add some exec tests

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

.clang-tidy

@@ -5,4 +5,5 @@ Checks: '
   , -cppcoreguidelines-pro-bounds-constant-array-index
   , -cppcoreguidelines-macro-usage
   , -cppcoreguidelines-avoid-const-or-ref-data-members
+  , -cppcoreguidelines-non-private-member-variables-in-classes
 '

.github/workflows/main.yml

@@ -15,14 +15,17 @@ jobs:
             auto-optimise-store = true
             experimental-features = nix-command flakes
 
-      - name: meson build
+      - name: setup
         run: nix develop -c meson setup $BUILDDIR
 
-      - name: clang-format check
+      - name: fmt
         run: nix develop -c ninja clang-format-check -C $BUILDDIR
 
-      - name: clang-tidy check
+      - name: lint
         run: nix develop -c ninja clang-tidy -C $BUILDDIR
 
-      - name: ninja compile
+      - name: tests
+        run: nix develop -c ninja test -C $BUILDDIR
+
+      - name: build
         run: nix develop -c ninja -C $BUILDDIR

README

@@ -1 +0,0 @@
-nothing to be seen here yet. LEAVE

README.md

@@ -0,0 +1,22 @@
+nothing to be seen here yet. LEAVE
+
+But if you are curious (probably not), read ahead
+
+# Dependencies
+## Tested toolchains
+
+- LLVM 16.0.6
+- GCC 12.3.0
+
+In theory, any toolchain supporting at least the C++20 standard should work.
+I am using LLVM's clang and libcxx as the primary toolchain.
+
+## Static libraries
+
+| Name   | Version   | Required? |
+|:------:|:----------|:---------:|
+| fmt    | >= 10.1.1 | yes       |
+| catch2 | >= 3.4    | for tests |
+
+This goes without saying but using a different toolchain to compile these libraries before linking probably won't work.
+I will add meson wrap support once LLVM 17 is out, since I want to get rid of fmt.

apps/target/main.cc

@@ -6,6 +6,7 @@
 #include <fstream>
 #include <iostream>
 #include <memory>
+#include <ostream>
 #include <unistd.h>
 #include <vector>
 
@@ -80,7 +81,10 @@ main(int argc, const char* argv[]) {
         return 1;
     }
 
-    {
+    std::flush(std::cout);
+    std::flush(std::cout);
+
+    try {
         Memory memory(std::move(bios), std::move(rom));
         Bus bus(memory);
         Cpu cpu(bus);
@@ -88,7 +92,11 @@ main(int argc, const char* argv[]) {
             cpu.step();
             sleep(1);
         }
+    } catch (const std::exception& e) {
+        std::cerr << "Exception: " << e.what() << std::endl;
+        return 1;
     }
+
     return 0;
 }
 

flake.lock

@@ -2,16 +2,16 @@
   "nodes": {
     "nixpkgs": {
       "locked": {
-        "lastModified": 1692007866,
+        "lastModified": 1694911158,
-        "narHash": "sha256-X8w0vPZjZxMm68VCwh/BHDoKRGp+BgzQ6w7Nkif6IVM=",
+        "narHash": "sha256-5WENkcO8O5SuA5pozpVppLGByWfHVv/1wOWgB2+TfV4=",
         "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "de2b8ddf94d6cc6161b7659649594c79bd66c13b",
+        "rev": "46423a1a750594236673c1d741def4e93cf5a8f7",
         "type": "github"
       },
       "original": {
         "owner": "nixos",
-        "ref": "nixpkgs-unstable",
+        "ref": "master",
         "repo": "nixpkgs",
         "type": "github"
       }

flake.nix

@@ -1,35 +1,52 @@
 {
   description = "matar";
+
   inputs = {
-    nixpkgs.url = github:nixos/nixpkgs/nixpkgs-unstable;
+    nixpkgs.url = github:nixos/nixpkgs/master;
   };
+
   outputs = { self, nixpkgs }:
     let
       systems = [
         "x86_64-linux"
         "aarch64-linux"
- #       "i686-linux"
       ];
+
       eachSystem = with nixpkgs.lib; f: foldAttrs mergeAttrs { }
         (map (s: mapAttrs (_: v: { ${s} = v; }) (f s)) systems);
     in
     eachSystem (system:
       let
         pkgs = import nixpkgs { inherit system; };
+
+        # aliases
         llvm = pkgs.llvmPackages_16;
         stdenv = llvm.libcxxStdenv;
 
-        nativeBuildInputs = with pkgs; [
+
+        # TODO: this is ugly
+        #dependencies
+        nativeBuildInputs = with pkgs;
+          [
             meson
             ninja
 
             # libraries
             pkg-config
-          fmt.dev
+            cmake
+
+            ((pkgs.fmt.override {
+              inherit stdenv;
+              enableShared = false;
+            }).overrideAttrs (oa: {
+              cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
+            })).dev
+            (catch2_3.override { inherit stdenv; }).out
           ];
       in
       rec {
         packages = rec {
+          inherit (llvm) libcxxabi;
           matar = stdenv.mkDerivation rec {
             name = "matar";
             version = "0.1";
@@ -37,6 +54,7 @@
               ".hh"
               ".cc"
               ".build"
+              "meson_options.txt"
             ];
             outputs = [ "out" "dev" ];
 
@@ -51,7 +69,7 @@
           matar = pkgs.mkShell.override { inherit stdenv; } {
             name = "matar";
             packages = nativeBuildInputs ++ (with pkgs; [
-              # dev tools
+              # lsp
               clang-tools_16
             ]);
           };

include/bus.hh

@@ -1 +0,0 @@
-../src/bus.hh

include/bus.hh

@@ -0,0 +1,21 @@
+#pragma once
+
+#include "memory.hh"
+#include <memory>
+
+class Bus {
+  public:
+    Bus(const Memory& memory);
+
+    uint8_t read_byte(size_t address);
+    void write_byte(size_t address, uint8_t byte);
+
+    uint16_t read_halfword(size_t address);
+    void write_halfword(size_t address, uint16_t halfword);
+
+    uint32_t read_word(size_t address);
+    void write_word(size_t address, uint32_t word);
+
+  private:
+    std::shared_ptr<Memory> memory;
+};

include/cpu/arm/instruction.hh

@@ -0,0 +1,165 @@
+#include "cpu/utility.hh"
+#include <cstdint>
+#include <variant>
+
+template<class... Ts>
+struct overloaded : Ts... {
+    using Ts::operator()...;
+};
+template<class... Ts>
+overloaded(Ts...) -> overloaded<Ts...>;
+
+namespace arm {
+struct BranchAndExchange {
+    uint8_t rn;
+};
+
+struct Branch {
+    bool link;
+    uint32_t offset;
+};
+
+struct Multiply {
+    uint8_t rm;
+    uint8_t rs;
+    uint8_t rn;
+    uint8_t rd;
+    bool set;
+    bool acc;
+};
+
+struct MultiplyLong {
+    uint8_t rm;
+    uint8_t rs;
+    uint8_t rdlo;
+    uint8_t rdhi;
+    bool set;
+    bool acc;
+    bool uns;
+};
+
+struct SingleDataSwap {
+    uint8_t rm;
+    uint8_t rd;
+    uint8_t rn;
+    bool byte;
+};
+
+struct SingleDataTransfer {
+    std::variant<uint16_t, Shift> offset;
+    uint8_t rd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool byte;
+    bool up;
+    bool pre;
+};
+
+struct HalfwordTransfer {
+    uint8_t offset;
+    bool half;
+    bool sign;
+    uint8_t rd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool imm;
+    bool up;
+    bool pre;
+};
+
+struct BlockDataTransfer {
+    uint16_t regs;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool s;
+    bool up;
+    bool pre;
+};
+
+struct DataProcessing {
+    std::variant<Shift, uint32_t> operand;
+    uint8_t rd;
+    uint8_t rn;
+    bool set;
+    OpCode opcode;
+};
+
+struct PsrTransfer {
+    enum class Type {
+        Mrs,
+        Msr,
+        Msr_flg
+    };
+
+    uint32_t operand;
+    bool spsr;
+    Type type;
+    // ignored outside MSR_flg
+    bool imm;
+};
+
+struct CoprocessorDataTransfer {
+    uint8_t offset;
+    uint8_t cpn;
+    uint8_t crd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool len;
+    bool up;
+    bool pre;
+};
+
+struct CoprocessorDataOperation {
+    uint8_t crm;
+    uint8_t cp;
+    uint8_t cpn;
+    uint8_t crd;
+    uint8_t crn;
+    uint8_t cp_opc;
+};
+
+struct CoprocessorRegisterTransfer {
+    uint8_t crm;
+    uint8_t cp;
+    uint8_t cpn;
+    uint8_t rd;
+    uint8_t crn;
+    bool load;
+    uint8_t cp_opc;
+};
+
+struct Undefined {};
+struct SoftwareInterrupt {};
+
+using InstructionData = std::variant<BranchAndExchange,
+                                     Branch,
+                                     Multiply,
+                                     MultiplyLong,
+                                     SingleDataSwap,
+                                     SingleDataTransfer,
+                                     HalfwordTransfer,
+                                     BlockDataTransfer,
+                                     DataProcessing,
+                                     PsrTransfer,
+                                     CoprocessorDataTransfer,
+                                     CoprocessorDataOperation,
+                                     CoprocessorRegisterTransfer,
+                                     Undefined,
+                                     SoftwareInterrupt>;
+
+struct Instruction {
+    Condition condition;
+    InstructionData data;
+
+    Instruction(uint32_t insn);
+    Instruction(Condition condition, InstructionData data) noexcept
+      : condition(condition)
+      , data(data){};
+
+    std::string disassemble();
+};
+}

include/cpu/arm/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh',
+)

include/cpu/cpu.hh

@@ -1 +0,0 @@
-../../src/cpu/cpu.hh

include/cpu/cpu.hh

@@ -0,0 +1,60 @@
+#pragma once
+
+#include "arm/instruction.hh"
+#include "bus.hh"
+#include "psr.hh"
+
+#include <cstdint>
+
+using std::size_t;
+
+class Cpu {
+  public:
+    Cpu(const Bus& bus);
+    void step();
+
+  private:
+    static constexpr uint8_t GPR_COUNT = 16;
+
+    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
+    static constexpr uint8_t GPR_SVC_FIRST     = 13;
+    static constexpr uint8_t GPR_ABT_FIRST     = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
+    static constexpr uint8_t GPR_UND_FIRST     = 13;
+    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+
+    Psr cpsr; // current program status register
+    Psr spsr; // status program status register
+
+    static constexpr uint8_t PC_INDEX = 15;
+    static_assert(PC_INDEX < GPR_COUNT);
+
+    uint32_t& pc = gpr[PC_INDEX];
+
+    bool is_flushed;
+
+    void chg_mode(const Mode to);
+    void exec_arm(const arm::Instruction instruction);
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
+    } gpr_banked; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked; // banked saved program status registers
+};

include/cpu/instruction.hh

@@ -1 +0,0 @@
-../../src/cpu/instruction.hh

include/cpu/meson.build

@@ -1,6 +1,7 @@
 headers += files(
   'cpu.hh',
-  'instruction.hh',
   'psr.hh',
   'utility.hh'
 )
+
+subdir('arm')

include/cpu/psr.hh

@@ -1 +0,0 @@
-../../src/cpu/psr.hh

include/cpu/psr.hh

@@ -0,0 +1,55 @@
+#pragma once
+
+#include "utility.hh"
+#include <cstdint>
+
+class Psr {
+  public:
+    // clear the reserved bits i.e, [8:27]
+    Psr(uint32_t raw);
+
+    uint32_t raw() const;
+    void set_all(uint32_t raw);
+
+    // Mode : [4:0]
+    Mode mode() const;
+    void set_mode(Mode mode);
+
+    // State : [5]
+    State state() const;
+    void set_state(State state);
+
+#define GET_SET_NTH_BIT_FUNCTIONS(name)                                        \
+    bool name() const;                                                         \
+    void set_##name(bool val);
+
+    // FIQ disable : [6]
+    GET_SET_NTH_BIT_FUNCTIONS(fiq_disabled)
+
+    // IRQ disable : [7]
+    GET_SET_NTH_BIT_FUNCTIONS(irq_disabled)
+
+    // Reserved bits : [27:8]
+
+    // Overflow flag : [28]
+    GET_SET_NTH_BIT_FUNCTIONS(v)
+
+    // Carry flag : [29]
+    GET_SET_NTH_BIT_FUNCTIONS(c)
+
+    // Zero flag : [30]
+    GET_SET_NTH_BIT_FUNCTIONS(z)
+
+    // Negative flag : [30]
+    GET_SET_NTH_BIT_FUNCTIONS(n)
+
+#undef GET_SET_NTH_BIT_FUNCTIONS
+
+    bool condition(Condition cond) const;
+
+  private:
+    static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
+    static constexpr uint32_t PSR_CLEAR_MODE     = 0xFFFFFFE0;
+
+    uint32_t psr;
+};

include/cpu/utility.hh

@@ -1 +0,0 @@
-../../src/cpu/utility.hh

include/cpu/utility.hh

@@ -0,0 +1,99 @@
+#pragma once
+
+#include <fmt/ostream.h>
+#include <ostream>
+
+static constexpr size_t ARM_INSTRUCTION_SIZE   = 4;
+static constexpr size_t THUMB_INSTRUCTION_SIZE = 2;
+
+enum class Mode {
+    /* M[4:0] in PSR */
+    User       = 0b10000,
+    Fiq        = 0b10001,
+    Irq        = 0b10010,
+    Supervisor = 0b10011,
+    Abort      = 0b10111,
+    Undefined  = 0b11011,
+    System     = 0b11111,
+};
+
+enum class State {
+    Arm   = 0,
+    Thumb = 1
+};
+
+enum class Condition {
+    EQ = 0b0000,
+    NE = 0b0001,
+    CS = 0b0010,
+    CC = 0b0011,
+    MI = 0b0100,
+    PL = 0b0101,
+    VS = 0b0110,
+    VC = 0b0111,
+    HI = 0b1000,
+    LS = 0b1001,
+    GE = 0b1010,
+    LT = 0b1011,
+    GT = 0b1100,
+    LE = 0b1101,
+    AL = 0b1110
+};
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const Condition cond);
+template<>
+struct fmt::formatter<Condition> : ostream_formatter {};
+
+enum class OpCode {
+    AND = 0b0000,
+    EOR = 0b0001,
+    SUB = 0b0010,
+    RSB = 0b0011,
+    ADD = 0b0100,
+    ADC = 0b0101,
+    SBC = 0b0110,
+    RSC = 0b0111,
+    TST = 0b1000,
+    TEQ = 0b1001,
+    CMP = 0b1010,
+    CMN = 0b1011,
+    ORR = 0b1100,
+    MOV = 0b1101,
+    BIC = 0b1110,
+    MVN = 0b1111
+};
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const OpCode cond);
+template<>
+struct fmt::formatter<OpCode> : ostream_formatter {};
+
+enum class ShiftType {
+    LSL = 0b00,
+    LSR = 0b01,
+    ASR = 0b10,
+    ROR = 0b11
+};
+
+struct ShiftData {
+    ShiftType type;
+    bool immediate;
+    uint8_t operand;
+};
+
+struct Shift {
+    uint8_t rm;
+    ShiftData data;
+};
+
+uint32_t
+eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
+
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const ShiftType cond);
+template<>
+struct fmt::formatter<ShiftType> : ostream_formatter {};

include/header.hh

@@ -1 +0,0 @@
-../src/header.hh

include/header.hh

@@ -0,0 +1,44 @@
+#pragma once
+
+#include <cstdint>
+#include <string>
+
+struct Header {
+    enum class UniqueCode {
+        Old,        // old games
+        New,        // new games
+        Newer,      // unused (newer games)
+        Famicom,    // NES
+        YoshiKoro,  // acceleration sensor
+        Ereader,    // dot code scanner
+        Warioware,  // rumble and z-axis gyro
+        Boktai,     // RTC and solar sensor
+        DrillDozer, // rumble
+    };
+
+    enum class I18n {
+        Japan,
+        Europe,
+        French,
+        Spanish,
+        Usa,
+        German,
+        Italian
+    };
+
+    enum class BootMode {
+        Joybus,
+        Normal,
+        Multiplay
+    };
+
+    uint32_t entrypoint;
+    std::string title;
+    std::string title_code;
+    UniqueCode unique_code;
+    I18n i18n;
+    uint8_t version;
+    BootMode multiboot;
+    uint32_t multiboot_entrypoint;
+    uint8_t slave_id;
+};

include/memory.hh

@@ -1 +0,0 @@
-../src/memory.hh

include/memory.hh

@@ -0,0 +1,63 @@
+#pragma once
+
+#include "header.hh"
+#include <array>
+#include <cstddef>
+#include <cstdint>
+#include <vector>
+
+class Memory {
+  public:
+    static constexpr size_t BIOS_SIZE = 1024 * 16;
+
+    Memory(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
+
+    uint8_t read(size_t address) const;
+    void write(size_t address, uint8_t byte);
+
+    uint16_t read_halfword(size_t address) const;
+    void write_halfword(size_t address, uint16_t halfword);
+
+    uint32_t read_word(size_t address) const;
+    void write_word(size_t address, uint32_t word);
+
+  private:
+#define MEMORY_REGION(name, start, end)                                        \
+    static constexpr size_t name##_START = start;                              \
+    static constexpr size_t name##_END   = end;
+
+#define DECL_MEMORY(name, ident, start, end)                                   \
+    MEMORY_REGION(name, start, end)                                            \
+    std::array<uint8_t, name##_END - name##_START + 1> ident;
+
+    MEMORY_REGION(BIOS, 0x00000000, 0x00003FFF)
+    std::array<uint8_t, BIOS_SIZE> bios;
+    static_assert(BIOS_END - BIOS_START + 1 == BIOS_SIZE);
+
+    // board working RAM
+    DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
+
+    // chip working RAM
+    DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
+
+    // palette RAM
+    DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
+
+    // video RAM
+    DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
+
+    // OAM OBJ attributes
+    DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
+
+#undef DECL_MEMORY
+
+    MEMORY_REGION(ROM_0, 0x08000000, 0x09FFFFFF)
+    MEMORY_REGION(ROM_1, 0x0A000000, 0x0BFFFFFF)
+    MEMORY_REGION(ROM_2, 0x0C000000, 0x0DFFFFFF)
+
+#undef MEMORY_REGION
+
+    std::vector<uint8_t> rom;
+    Header header;
+    void parse_header();
+};

meson.build

@@ -6,7 +6,36 @@ project('matar', 'cpp',
                      'optimization=3',
                      'cpp_std=c++20'])
 
+compiler = meson.get_compiler('cpp')
+
+'''
+TODO: use <print> and <format> instead of libfmt once LLVM 17 is out
+
+if compiler.has_argument('-std=c++2c')
+  add_global_arguments('-std=c++2c', language: 'cpp')
+elif compiler.has_argument('-std=c++23')
+  add_global_arguments('-std=c++23', language: 'cpp')
+elif compiler.has_argument('-std=c++2b')
+  add_global_arguments('-std=c++2b', language: 'cpp')
+elif compiler.has_argument('-std=c++20')
+  add_global_arguments('-std=c++20', language: 'cpp')
+else
+  error(compiler.get_id() + ' ' + compiler.version() + 'does not meet the compiler requirements')
+endif
+
+if compiler.has_argument('-fexperimental-library')
+  add_global_arguments('-fexperimental-library', language: 'cpp')
+else
+  error(compiler.get_id() + ' ' + compiler.version() + 'does not support -fexperimental-library')
+endif
+'''
+
 inc = include_directories('include')
+
 subdir('include')
 subdir('src')
 subdir('apps')
+
+if get_option('tests')
+  subdir('tests')
+endif

meson_options.txt

@@ -0,0 +1 @@
+option('tests', type : 'boolean', value : true, description: 'enable tests')

src/bus.cc

@@ -1,7 +1,7 @@
 #include "bus.hh"
 #include <memory>
 
-Bus::Bus(Memory& memory)
+Bus::Bus(const Memory& memory)
   : memory(std::make_shared<Memory>(memory)) {}
 
 uint8_t
@@ -31,5 +31,5 @@ Bus::read_word(size_t address) {
 
 void
 Bus::write_word(size_t address, uint32_t word) {
-    memory->write_halfword(address, word);
+    memory->write_word(address, word);
 }

src/bus.hh

@@ -1,21 +0,0 @@
-#pragma once
-
-#include "memory.hh"
-#include <memory>
-
-class Bus {
-  public:
-    Bus(Memory& memory);
-
-    uint8_t read_byte(size_t address);
-    void write_byte(size_t address, uint8_t byte);
-
-    uint16_t read_halfword(size_t address);
-    void write_halfword(size_t address, uint16_t halfword);
-
-    uint32_t read_word(size_t address);
-    void write_word(size_t address, uint32_t word);
-
-  private:
-    std::shared_ptr<Memory> memory;
-};

src/cpu/arm/exec.cc

@@ -0,0 +1,576 @@
+#include "cpu/cpu.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+using namespace logger;
+
+void
+Cpu::exec_arm(const arm::Instruction instruction) {
+    auto cond = instruction.condition;
+    auto data = instruction.data;
+
+    if (!cpsr.condition(cond)) {
+        return;
+    }
+
+    auto pc_error = [](uint8_t r) {
+        if (r == PC_INDEX)
+            log_error("Using PC (R15) as operand register");
+    };
+
+    auto pc_warn = [](uint8_t r) {
+        if (r == PC_INDEX)
+            log_warn("Using PC (R15) as operand register");
+    };
+
+    using namespace arm;
+
+    std::visit(
+      overloaded{
+        [this, pc_warn](BranchAndExchange& data) {
+            State state = static_cast<State>(data.rn & 1);
+
+            pc_warn(data.rn);
+
+            // set state
+            cpsr.set_state(state);
+
+            // copy to PC
+            pc = gpr[data.rn];
+
+            // ignore [1:0] bits for arm and 0 bit for thumb
+            rst_bit(pc, 0);
+
+            if (state == State::Arm)
+                rst_bit(pc, 1);
+
+            // pc is affected so flush the pipeline
+            is_flushed = true;
+        },
+        [this](Branch& data) {
+            if (data.link)
+                gpr[14] = pc - ARM_INSTRUCTION_SIZE;
+
+            // data.offset accounts for two instructions ahead when
+            // disassembling, so need to adjust
+            pc =
+              static_cast<int32_t>(pc) - 2 * ARM_INSTRUCTION_SIZE + data.offset;
+
+            // pc is affected so flush the pipeline
+            is_flushed = true;
+        },
+        [this, pc_error](Multiply& data) {
+            if (data.rd == data.rm)
+                log_error("rd and rm are not distinct in {}",
+                          typeid(data).name());
+
+            pc_error(data.rd);
+            pc_error(data.rd);
+            pc_error(data.rd);
+
+            gpr[data.rd] =
+              gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
+
+            if (data.set) {
+                cpsr.set_z(gpr[data.rd] == 0);
+                cpsr.set_n(get_bit(gpr[data.rd], 31));
+                cpsr.set_c(0);
+            }
+        },
+        [this, pc_error](MultiplyLong& data) {
+            if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
+                data.rdlo == data.rm)
+                log_error("rdhi, rdlo and rm are not distinct in {}",
+                          typeid(data).name());
+
+            pc_error(data.rdhi);
+            pc_error(data.rdlo);
+            pc_error(data.rm);
+            pc_error(data.rs);
+
+            if (data.uns) {
+                uint64_t eval =
+                  static_cast<uint64_t>(gpr[data.rm]) *
+                    static_cast<uint64_t>(gpr[data.rs]) +
+                  (data.acc ? (static_cast<uint64_t>(gpr[data.rdhi]) << 32) |
+                                static_cast<uint64_t>(gpr[data.rdlo])
+                            : 0);
+
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
+
+            } else {
+                int64_t eval =
+                  static_cast<int64_t>(gpr[data.rm]) *
+                    static_cast<int64_t>(gpr[data.rs]) +
+                  (data.acc ? static_cast<int64_t>(gpr[data.rdhi]) << 32 |
+                                static_cast<int64_t>(gpr[data.rdlo])
+                            : 0);
+
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
+            }
+
+            if (data.set) {
+                cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
+                cpsr.set_n(get_bit(gpr[data.rdhi], 31));
+                cpsr.set_c(0);
+                cpsr.set_v(0);
+            }
+        },
+        [](Undefined) { log_warn("Undefined instruction"); },
+        [this, pc_error](SingleDataSwap& data) {
+            pc_error(data.rm);
+            pc_error(data.rn);
+            pc_error(data.rd);
+
+            if (data.byte) {
+                gpr[data.rd] = bus->read_byte(gpr[data.rn]);
+                bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
+            } else {
+                gpr[data.rd] = bus->read_word(gpr[data.rn]);
+                bus->write_word(gpr[data.rn], gpr[data.rm]);
+            }
+        },
+        [this, pc_warn, pc_error](SingleDataTransfer& data) {
+            uint32_t offset  = 0;
+            uint32_t address = gpr[data.rn];
+
+            if (!data.pre && data.write)
+                log_warn("Write-back enabled with post-indexing in {}",
+                         typeid(data).name());
+
+            if (data.rn == PC_INDEX && data.write)
+                log_warn("Write-back enabled with base register as PC {}",
+                         typeid(data).name());
+
+            if (data.write)
+                pc_warn(data.rn);
+
+            // evaluate the offset
+            if (const uint16_t* immediate =
+                  std::get_if<uint16_t>(&data.offset)) {
+                offset = *immediate;
+            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
+                uint8_t amount =
+                  (shift->data.immediate ? shift->data.operand
+                                         : gpr[shift->data.operand] & 0xFF);
+
+                bool carry = cpsr.c();
+
+                if (!shift->data.immediate)
+                    pc_error(shift->data.operand);
+                pc_error(shift->rm);
+
+                offset =
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+
+                cpsr.set_c(carry);
+            }
+
+            // PC is always two instructions ahead
+            if (data.rn == PC_INDEX)
+                address -= 2 * ARM_INSTRUCTION_SIZE;
+
+            if (data.pre)
+                address += (data.up ? offset : -offset);
+
+            debug(address);
+
+            // load
+            if (data.load) {
+                // byte
+                if (data.byte)
+                    gpr[data.rd] = bus->read_byte(address);
+                // word
+                else
+                    gpr[data.rd] = bus->read_word(address);
+                // store
+            } else {
+                // take PC into consideration
+                if (data.rd == PC_INDEX)
+                    address += ARM_INSTRUCTION_SIZE;
+
+                // byte
+                if (data.byte)
+                    bus->write_byte(address, gpr[data.rd] & 0xFF);
+                // word
+                else
+                    bus->write_word(address, gpr[data.rd]);
+            }
+
+            if (!data.pre)
+                address += (data.up ? offset : -offset);
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.rd == PC_INDEX && data.load)
+                is_flushed = true;
+        },
+        [this, pc_warn, pc_error](HalfwordTransfer& data) {
+            uint32_t address = gpr[data.rn];
+
+            if (!data.pre && data.write)
+                log_error("Write-back enabled with post-indexing in {}",
+                          typeid(data).name());
+
+            if (data.sign && !data.load)
+                log_error("Signed data found in {}", typeid(data).name());
+
+            if (data.write)
+                pc_warn(data.rn);
+
+            // offset is register number (4 bits) when not an immediate
+            if (!data.imm)
+                pc_error(data.offset);
+
+            if (data.pre)
+                address += (data.up ? data.offset : -data.offset);
+
+            // load
+            if (data.load) {
+                // signed
+                if (data.sign) {
+                    // halfword
+                    if (data.half) {
+                        gpr[data.rd] = bus->read_halfword(address);
+
+                        // sign extend the halfword
+                        gpr[data.rd] =
+                          (static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
+
+                        // byte
+                    } else {
+                        gpr[data.rd] = bus->read_byte(address);
+
+                        // sign extend the byte
+                        gpr[data.rd] =
+                          (static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
+                    }
+                    // unsigned halfword
+                } else if (data.half) {
+                    gpr[data.rd] = bus->read_halfword(address);
+                }
+                // store
+            } else {
+                // take PC into consideration
+                if (data.rd == PC_INDEX)
+                    address += ARM_INSTRUCTION_SIZE;
+
+                // halfword
+                if (data.half)
+                    bus->write_halfword(address, gpr[data.rd]);
+            }
+
+            if (!data.pre)
+                address += (data.up ? data.offset : -data.offset);
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.rd == PC_INDEX && data.load)
+                is_flushed = true;
+        },
+        [this, pc_error](BlockDataTransfer& data) {
+            uint32_t address  = gpr[data.rn];
+            Mode mode         = cpsr.mode();
+            uint8_t alignment = 4; // word
+            uint8_t i         = 0;
+            uint8_t n_regs    = std::popcount(data.regs);
+
+            pc_error(data.rn);
+
+            if (cpsr.mode() == Mode::User && data.s) {
+                log_error("Bit S is set outside priviliged modes in {}",
+                          typeid(data).name());
+            }
+
+            // we just change modes to load user registers
+            if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
+                (!data.load && data.s)) {
+                chg_mode(Mode::User);
+
+                if (data.write) {
+                    log_error("Write-back enable for user bank registers in {}",
+                              typeid(data).name());
+                }
+            }
+
+            // account for decrement
+            if (!data.up)
+                address -= (n_regs - 1) * alignment;
+
+            if (data.pre)
+                address += (data.up ? alignment : -alignment);
+
+            if (data.load) {
+                if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
+                    // current mode's spsr is already loaded when it was
+                    // switched
+                    spsr = cpsr;
+                }
+
+                for (i = 0; i < GPR_COUNT; i++) {
+                    if (get_bit(data.regs, i)) {
+                        gpr[i] = bus->read_word(address);
+                        address += alignment;
+                    }
+                }
+            } else {
+                for (i = 0; i < GPR_COUNT; i++) {
+                    if (get_bit(data.regs, i)) {
+                        bus->write_word(address, gpr[i]);
+                        address += alignment;
+                    }
+                }
+            }
+
+            if (!data.pre)
+                address += (data.up ? alignment : -alignment);
+
+            // reset back to original address + offset if incremented earlier
+            if (data.up)
+                address -= n_regs * alignment;
+
+            if (!data.pre || data.write)
+                gpr[data.rn] = address;
+
+            if (data.load && get_bit(data.regs, PC_INDEX))
+                is_flushed = true;
+
+            // load back the original mode registers
+            chg_mode(mode);
+        },
+        [this, pc_error](PsrTransfer& data) {
+            if (data.spsr && cpsr.mode() == Mode::User) {
+                log_error("Accessing SPSR in User mode in {}",
+                          typeid(data).name());
+            }
+
+            Psr& psr = data.spsr ? spsr : cpsr;
+
+            switch (data.type) {
+                case PsrTransfer::Type::Mrs:
+                    pc_error(data.operand);
+                    gpr[data.operand] = psr.raw();
+                    break;
+                case PsrTransfer::Type::Msr:
+                    pc_error(data.operand);
+
+                    if (cpsr.mode() != Mode::User) {
+                        psr.set_all(gpr[data.operand]);
+                    }
+                    break;
+                case PsrTransfer::Type::Msr_flg:
+                    psr.set_n(get_bit(data.operand, 31));
+                    psr.set_z(get_bit(data.operand, 30));
+                    psr.set_c(get_bit(data.operand, 29));
+                    psr.set_v(get_bit(data.operand, 28));
+                    break;
+            }
+        },
+        [this, pc_error](DataProcessing& data) {
+            uint32_t op_1 = gpr[data.rn];
+            uint32_t op_2 = 0;
+
+            uint32_t result = 0;
+
+            bool overflow = cpsr.v();
+            bool carry    = cpsr.c();
+            bool negative = cpsr.n();
+            bool zero     = cpsr.z();
+
+            if (const uint32_t* immediate =
+                  std::get_if<uint32_t>(&data.operand)) {
+                op_2 = *immediate;
+            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
+                uint8_t amount =
+                  (shift->data.immediate ? shift->data.operand
+                                         : gpr[shift->data.operand] & 0xFF);
+
+                bool carry = cpsr.c();
+
+                if (!shift->data.immediate)
+                    pc_error(shift->data.operand);
+                pc_error(shift->rm);
+
+                op_2 =
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+
+                cpsr.set_c(carry);
+
+                // PC is 12 bytes ahead when shifting
+                if (data.rn == PC_INDEX)
+                    op_1 += ARM_INSTRUCTION_SIZE;
+            }
+
+            switch (data.opcode) {
+                case OpCode::AND: {
+                    result = op_1 & op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::EOR: {
+                    result = op_1 ^ op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::SUB: {
+                    bool s1  = get_bit(op_1, 31);
+                    bool s2  = get_bit(op_2, 31);
+                    result   = op_1 - op_2;
+                    negative = get_bit(result, 31);
+                    carry    = op_1 < op_2;
+                    overflow = s1 != s2 && s2 == negative;
+                } break;
+                case OpCode::RSB: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+                    result  = op_2 - op_1;
+
+                    negative = get_bit(result, 31);
+                    carry    = op_2 < op_1;
+                    overflow = s1 != s2 && s1 == negative;
+                } break;
+                case OpCode::ADD: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    // result_ is 33 bits
+                    uint64_t result_ = op_2 + op_1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 == s2 && s1 != negative;
+                } break;
+                case OpCode::ADC: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_2 + op_1 + carry;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 == s2 && s1 != negative;
+                } break;
+                case OpCode::SBC: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_1 - op_2 + carry - 1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 != s2 && s2 == negative;
+                } break;
+                case OpCode::RSC: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_1 - op_2 + carry - 1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 != s2 && s1 == negative;
+                } break;
+                case OpCode::TST: {
+                    result = op_1 & op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::TEQ: {
+                    result = op_1 ^ op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::CMP: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    result = op_1 - op_2;
+
+                    negative = get_bit(result, 31);
+                    carry    = op_1 < op_2;
+                    overflow = s1 != s2 && s2 == negative;
+                } break;
+                case OpCode::CMN: {
+                    bool s1 = get_bit(op_1, 31);
+                    bool s2 = get_bit(op_2, 31);
+
+                    uint64_t result_ = op_2 + op_1;
+                    result           = result_ & 0xFFFFFFFF;
+
+                    negative = get_bit(result, 31);
+                    carry    = get_bit(result_, 32);
+                    overflow = s1 == s2 && s1 != negative;
+                } break;
+                case OpCode::ORR: {
+                    result = op_1 | op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::MOV: {
+                    result = op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::BIC: {
+                    result = op_1 & ~op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+                case OpCode::MVN: {
+                    result = ~op_2;
+
+                    negative = get_bit(result, 31);
+                } break;
+            }
+
+            zero = result == 0;
+
+            debug(carry);
+            debug(overflow);
+            debug(zero);
+            debug(negative);
+
+            auto set_conditions = [this, carry, overflow, negative, zero]() {
+                cpsr.set_c(carry);
+                cpsr.set_v(overflow);
+                cpsr.set_n(negative);
+                cpsr.set_z(zero);
+            };
+
+            if (data.set) {
+                if (data.rd == 15) {
+                    if (cpsr.mode() == Mode::User)
+                        log_error("Running {} in User mode",
+                                  typeid(data).name());
+                } else {
+                    set_conditions();
+                }
+            }
+
+            if (data.opcode == OpCode::TST || data.opcode == OpCode::TEQ ||
+                data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
+                set_conditions();
+            } else {
+                gpr[data.rd] = result;
+                if (data.rd == 15 || data.opcode == OpCode::MVN)
+                    is_flushed = true;
+            }
+        },
+        [this](SoftwareInterrupt) {
+            chg_mode(Mode::Supervisor);
+            pc   = 0x08;
+            spsr = cpsr;
+        },
+        [](auto& data) {
+            log_error("Unimplemented {} instruction", typeid(data).name());
+        } },
+      data);
+}

src/cpu/arm/instruction.cc

@@ -0,0 +1,497 @@
+#include "cpu/arm/instruction.hh"
+#include "cpu/utility.hh"
+#include "util/bits.hh"
+#include <iterator>
+
+using namespace arm;
+
+Instruction::Instruction(uint32_t insn)
+  : condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
+    // Branch and exhcange
+    if ((insn & 0x0FFFFFF0) == 0x012FFF10) {
+        uint8_t rn = insn & 0b1111;
+
+        data = BranchAndExchange{ rn };
+
+        // Branch
+    } else if ((insn & 0x0E000000) == 0x0A000000) {
+        bool link       = get_bit(insn, 24);
+        uint32_t offset = bit_range(insn, 0, 23);
+
+        // lsh 2 and sign extend the 26 bit offset to 32 bits
+        offset = (static_cast<int32_t>(offset) << 8) >> 6;
+
+        offset += 2 * ARM_INSTRUCTION_SIZE;
+
+        data = Branch{ .link = link, .offset = offset };
+
+        // Multiply
+    } else if ((insn & 0x0FC000F0) == 0x00000090) {
+        uint8_t rm = bit_range(insn, 0, 3);
+        uint8_t rs = bit_range(insn, 8, 11);
+        uint8_t rn = bit_range(insn, 12, 15);
+        uint8_t rd = bit_range(insn, 16, 19);
+        bool set   = get_bit(insn, 20);
+        bool acc   = get_bit(insn, 21);
+
+        data = Multiply{
+            .rm = rm, .rs = rs, .rn = rn, .rd = rd, .set = set, .acc = acc
+        };
+
+        // Multiply long
+    } else if ((insn & 0x0F8000F0) == 0x00800090) {
+        uint8_t rm   = bit_range(insn, 0, 3);
+        uint8_t rs   = bit_range(insn, 8, 11);
+        uint8_t rdlo = bit_range(insn, 12, 15);
+        uint8_t rdhi = bit_range(insn, 16, 19);
+        bool set     = get_bit(insn, 20);
+        bool acc     = get_bit(insn, 21);
+        bool uns     = !get_bit(insn, 22);
+
+        data = MultiplyLong{ .rm   = rm,
+                             .rs   = rs,
+                             .rdlo = rdlo,
+                             .rdhi = rdhi,
+                             .set  = set,
+                             .acc  = acc,
+                             .uns  = uns };
+
+        // Undefined
+    } else if ((insn & 0x0E000010) == 0x06000010) {
+        data = Undefined{};
+
+        // Single data swap
+    } else if ((insn & 0x0FB00FF0) == 0x01000090) {
+        uint8_t rm = bit_range(insn, 0, 3);
+        uint8_t rd = bit_range(insn, 12, 15);
+        uint8_t rn = bit_range(insn, 16, 19);
+        bool byte  = get_bit(insn, 22);
+
+        data = SingleDataSwap{ .rm = rm, .rd = rd, .rn = rn, .byte = byte };
+
+        // Single data transfer
+    } else if ((insn & 0x0C000000) == 0x04000000) {
+        std::variant<uint16_t, Shift> offset;
+        uint8_t rd = bit_range(insn, 12, 15);
+        uint8_t rn = bit_range(insn, 16, 19);
+        bool load  = get_bit(insn, 20);
+        bool write = get_bit(insn, 21);
+        bool byte  = get_bit(insn, 22);
+        bool up    = get_bit(insn, 23);
+        bool pre   = get_bit(insn, 24);
+        bool imm   = get_bit(insn, 25);
+
+        if (imm) {
+            // register specified shift amounts not available in single data
+            // transfer (see Undefined)
+            uint8_t rm = bit_range(insn, 0, 3);
+            ShiftType shift_type =
+              static_cast<ShiftType>(bit_range(insn, 5, 6));
+            uint8_t operand = bit_range(insn, 7, 11);
+
+            offset = Shift{ .rm   = rm,
+                            .data = ShiftData{ .type      = shift_type,
+                                               .immediate = true,
+                                               .operand   = operand } };
+        } else {
+            offset = static_cast<uint16_t>(bit_range(insn, 0, 11));
+        }
+
+        data = SingleDataTransfer{ .offset = offset,
+                                   .rd     = rd,
+                                   .rn     = rn,
+                                   .load   = load,
+                                   .write  = write,
+                                   .byte   = byte,
+                                   .up     = up,
+                                   .pre    = pre };
+
+        // Halfword transfer
+    } else if ((insn & 0x0E000090) == 0x00000090) {
+        uint8_t offset = bit_range(insn, 0, 3);
+        bool half      = get_bit(insn, 5);
+        bool sign      = get_bit(insn, 6);
+        uint8_t rd     = bit_range(insn, 12, 15);
+        uint8_t rn     = bit_range(insn, 16, 19);
+        bool load      = get_bit(insn, 20);
+        bool write     = get_bit(insn, 21);
+        bool imm       = get_bit(insn, 22);
+        bool up        = get_bit(insn, 23);
+        bool pre       = get_bit(insn, 24);
+
+        offset |= (imm ? bit_range(insn, 8, 11) << 2 : 0);
+
+        data = HalfwordTransfer{ .offset = offset,
+                                 .half   = half,
+                                 .sign   = sign,
+                                 .rd     = rd,
+                                 .rn     = rn,
+                                 .load   = load,
+                                 .write  = write,
+                                 .imm    = imm,
+                                 .up     = up,
+                                 .pre    = pre };
+
+        // Block data transfer
+    } else if ((insn & 0x0E000000) == 0x08000000) {
+        uint16_t regs = bit_range(insn, 0, 15);
+        uint8_t rn    = bit_range(insn, 16, 19);
+        bool load     = get_bit(insn, 20);
+        bool write    = get_bit(insn, 21);
+        bool s        = get_bit(insn, 22);
+        bool up       = get_bit(insn, 23);
+        bool pre      = get_bit(insn, 24);
+
+        data = BlockDataTransfer{ .regs  = regs,
+                                  .rn    = rn,
+                                  .load  = load,
+                                  .write = write,
+                                  .s     = s,
+                                  .up    = up,
+                                  .pre   = pre };
+
+        // Data Processing
+    } else if ((insn & 0x0C000000) == 0x00000000) {
+        uint8_t rd    = bit_range(insn, 12, 15);
+        uint8_t rn    = bit_range(insn, 16, 19);
+        bool set      = get_bit(insn, 20);
+        OpCode opcode = static_cast<OpCode>(bit_range(insn, 21, 24));
+        bool imm      = get_bit(insn, 25);
+
+        if ((opcode == OpCode::TST || opcode == OpCode::CMP) && !set) {
+            data = PsrTransfer{ .operand = rd,
+                                .spsr    = get_bit(insn, 22),
+                                .type    = PsrTransfer::Type::Mrs,
+                                .imm     = 0 };
+        } else if ((opcode == OpCode::TEQ || opcode == OpCode::CMN) && !set) {
+            uint32_t operand = 0;
+
+            if (imm) {
+                uint32_t immediate = bit_range(insn, 0, 7);
+                uint8_t rotate     = bit_range(insn, 8, 11);
+
+                operand = std::rotr(immediate, rotate * 2);
+            } else {
+                operand = bit_range(insn, 0, 3);
+            }
+
+            data = PsrTransfer{ .operand = operand,
+                                .spsr    = get_bit(insn, 22),
+                                .type    = (get_bit(insn, 16)
+                                              ? PsrTransfer::Type::Msr
+                                              : PsrTransfer::Type::Msr_flg),
+                                .imm     = imm };
+        } else {
+            std::variant<Shift, uint32_t> operand;
+
+            if (imm) {
+                uint32_t immediate = bit_range(insn, 0, 7);
+                uint8_t rotate     = bit_range(insn, 8, 11);
+
+                operand = std::rotr(immediate, rotate * 2);
+            } else {
+                uint8_t rm = bit_range(insn, 0, 3);
+                bool reg   = get_bit(insn, 4);
+                ShiftType shift_type =
+                  static_cast<ShiftType>(bit_range(insn, 5, 6));
+                uint8_t sh_operand = bit_range(insn, (reg ? 8 : 7), 11);
+
+                operand = Shift{ .rm   = rm,
+                                 .data = ShiftData{ .type      = shift_type,
+                                                    .immediate = !reg,
+                                                    .operand   = sh_operand } };
+            }
+
+            data = DataProcessing{ .operand = operand,
+                                   .rd      = rd,
+                                   .rn      = rn,
+                                   .set     = set,
+                                   .opcode  = opcode };
+        }
+
+        // Software interrupt
+    } else if ((insn & 0x0F000000) == 0x0F000000) {
+
+        data = SoftwareInterrupt{};
+
+        // Coprocessor data transfer
+    } else if ((insn & 0x0E000000) == 0x0C000000) {
+        uint8_t offset = bit_range(insn, 0, 7);
+        uint8_t cpn    = bit_range(insn, 8, 11);
+        uint8_t crd    = bit_range(insn, 12, 15);
+        uint8_t rn     = bit_range(insn, 16, 19);
+        bool load      = get_bit(insn, 20);
+        bool write     = get_bit(insn, 21);
+        bool len       = get_bit(insn, 22);
+        bool up        = get_bit(insn, 23);
+        bool pre       = get_bit(insn, 24);
+
+        data = CoprocessorDataTransfer{ .offset = offset,
+                                        .cpn    = cpn,
+                                        .crd    = crd,
+                                        .rn     = rn,
+                                        .load   = load,
+                                        .write  = write,
+                                        .len    = len,
+                                        .up     = up,
+                                        .pre    = pre };
+
+        // Coprocessor data operation
+    } else if ((insn & 0x0F000010) == 0x0E000000) {
+        uint8_t crm    = bit_range(insn, 0, 3);
+        uint8_t cp     = bit_range(insn, 5, 7);
+        uint8_t cpn    = bit_range(insn, 8, 11);
+        uint8_t crd    = bit_range(insn, 12, 15);
+        uint8_t crn    = bit_range(insn, 16, 19);
+        uint8_t cp_opc = bit_range(insn, 20, 23);
+
+        data = CoprocessorDataOperation{ .crm    = crm,
+                                         .cp     = cp,
+                                         .cpn    = cpn,
+                                         .crd    = crd,
+                                         .crn    = crn,
+                                         .cp_opc = cp_opc };
+
+        // Coprocessor register transfer
+    } else if ((insn & 0x0F000010) == 0x0E000010) {
+        uint8_t crm    = bit_range(insn, 0, 3);
+        uint8_t cp     = bit_range(insn, 5, 7);
+        uint8_t cpn    = bit_range(insn, 8, 11);
+        uint8_t rd     = bit_range(insn, 12, 15);
+        uint8_t crn    = bit_range(insn, 16, 19);
+        bool load      = get_bit(insn, 20);
+        uint8_t cp_opc = bit_range(insn, 21, 23);
+
+        data = CoprocessorRegisterTransfer{ .crm    = crm,
+                                            .cp     = cp,
+                                            .cpn    = cpn,
+                                            .rd     = rd,
+                                            .crn    = crn,
+                                            .load   = load,
+                                            .cp_opc = cp_opc };
+    } else {
+        data = Undefined{};
+    }
+}
+
+std::string
+Instruction::disassemble() {
+    // goddamn this is gore
+    // TODO: make this less ugly
+    return std::visit(
+      overloaded{
+        [this](BranchAndExchange& data) {
+            return fmt::format("BX{} R{:d}", condition, data.rn);
+        },
+        [this](Branch& data) {
+            return fmt::format(
+              "B{}{} 0x{:06X}", (data.link ? "L" : ""), condition, data.offset);
+        },
+        [this](Multiply& data) {
+            if (data.acc) {
+                return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
+                                   condition,
+                                   (data.set ? "S" : ""),
+                                   data.rd,
+                                   data.rm,
+                                   data.rs,
+                                   data.rn);
+            } else {
+                return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
+                                   condition,
+                                   (data.set ? "S" : ""),
+                                   data.rd,
+                                   data.rm,
+                                   data.rs);
+            }
+        },
+        [this](MultiplyLong& data) {
+            return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
+                               (data.uns ? 'U' : 'S'),
+                               (data.acc ? "MLAL" : "MULL"),
+                               condition,
+                               (data.set ? "S" : ""),
+                               data.rdlo,
+                               data.rdhi,
+                               data.rm,
+                               data.rs);
+        },
+        [](Undefined) { return std::string("UND"); },
+        [this](SingleDataSwap& data) {
+            return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
+                               condition,
+                               (data.byte ? "B" : ""),
+                               data.rd,
+                               data.rm,
+                               data.rn);
+        },
+        [this](SingleDataTransfer& data) {
+            std::string expression;
+            std::string address;
+
+            if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
+                if (*offset == 0) {
+                    expression = "";
+                } else {
+                    expression =
+                      fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
+                }
+            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
+                // Shifts are always immediate in single data transfer
+                expression = fmt::format(",{}R{:d},{} #{:d}",
+                                         (data.up ? '+' : '-'),
+                                         shift->rm,
+                                         shift->data.type,
+                                         shift->data.operand);
+            }
+
+            return fmt::format(
+              "{}{}{}{} R{:d},[R{:d}{}]{}",
+              (data.load ? "LDR" : "STR"),
+              condition,
+              (data.byte ? "B" : ""),
+              (!data.pre && data.write ? "T" : ""),
+              data.rd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [this](HalfwordTransfer& data) {
+            std::string expression;
+
+            if (data.imm) {
+                if (data.offset == 0) {
+                    expression = "";
+                } else {
+                    expression = fmt::format(
+                      ",{}#{:d}", (data.up ? '+' : '-'), data.offset);
+                }
+            } else {
+                expression =
+                  fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
+            }
+
+            return fmt::format(
+              "{}{}{}{} R{:d},[R{:d}{}]{}",
+              (data.load ? "LDR" : "STR"),
+              condition,
+              (data.sign ? "S" : ""),
+              (data.half ? 'H' : 'B'),
+              data.rd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [this](BlockDataTransfer& data) {
+            std::string regs;
+
+            for (uint8_t i = 0; i < 16; i++) {
+                if (get_bit(data.regs, i))
+                    fmt::format_to(std::back_inserter(regs), "R{:d},", i);
+            };
+
+            regs.pop_back();
+
+            return fmt::format("{}{}{}{} R{:d}{},{{{}}}{}",
+                               (data.load ? "LDM" : "STM"),
+                               condition,
+                               (data.up ? 'I' : 'D'),
+                               (data.pre ? 'B' : 'A'),
+                               data.rn,
+                               (data.write ? "!" : ""),
+                               regs,
+                               (data.s ? "^" : ""));
+        },
+        [this](PsrTransfer& data) {
+            if (data.type == PsrTransfer::Type::Mrs) {
+                return fmt::format("MRS{} R{:d},{}",
+                                   condition,
+                                   data.operand,
+                                   (data.spsr ? "SPSR_all" : "CPSR_all"));
+            } else {
+                return fmt::format(
+                  "MSR{} {}_{},{}{}",
+                  condition,
+                  (data.spsr ? "SPSR" : "CPSR"),
+                  (data.type == PsrTransfer::Type::Msr_flg ? "flg" : "all"),
+                  (data.imm ? '#' : 'R'),
+                  data.operand);
+            }
+        },
+        [this](DataProcessing& data) {
+            std::string op_2;
+
+            if (const uint32_t* operand =
+                  std::get_if<uint32_t>(&data.operand)) {
+                op_2 = fmt::format("#{:d}", *operand);
+            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
+                op_2 = fmt::format("R{:d},{} {}{:d}",
+                                   shift->rm,
+                                   shift->data.type,
+                                   (shift->data.immediate ? '#' : 'R'),
+                                   shift->data.operand);
+            }
+
+            switch (data.opcode) {
+                case OpCode::MOV:
+                case OpCode::MVN:
+                    return fmt::format("{}{}{} R{:d},{}",
+                                       data.opcode,
+                                       condition,
+                                       (data.set ? "S" : ""),
+                                       data.rd,
+                                       op_2);
+                case OpCode::TST:
+                case OpCode::TEQ:
+                case OpCode::CMP:
+                case OpCode::CMN:
+                    return fmt::format(
+                      "{}{} R{:d},{}", data.opcode, condition, data.rn, op_2);
+                default:
+                    return fmt::format("{}{}{} R{:d},R{:d},{}",
+                                       data.opcode,
+                                       condition,
+                                       (data.set ? "S" : ""),
+                                       data.rd,
+                                       data.rn,
+                                       op_2);
+            }
+        },
+        [this](SoftwareInterrupt) { return fmt::format("SWI{}", condition); },
+        [this](CoprocessorDataTransfer& data) {
+            std::string expression = fmt::format(",#{:d}", data.offset);
+            return fmt::format(
+              "{}{}{} p{:d},c{:d},[R{:d}{}]{}",
+              (data.load ? "LDC" : "STC"),
+              condition,
+              (data.len ? "L" : ""),
+              data.cpn,
+              data.crd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [this](CoprocessorDataOperation& data) {
+            return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
+                               condition,
+                               data.cpn,
+                               data.cp_opc,
+                               data.crd,
+                               data.crn,
+                               data.crm,
+                               data.cp);
+        },
+        [this](CoprocessorRegisterTransfer& data) {
+            return fmt::format("{}{} p{},{},R{},c{},c{},{}",
+                               (data.load ? "MRC" : "MCR"),
+                               condition,
+                               data.cpn,
+                               data.cp_opc,
+                               data.rd,
+                               data.crn,
+                               data.crm,
+                               data.cp);
+        },
+        [](auto) { return std::string("unknown instruction"); } },
+      data);
+}

src/cpu/arm/meson.build

@@ -0,0 +1,4 @@
+lib_sources += files(
+  'instruction.cc',
+  'exec.cc'
+)

src/cpu/cpu.cc

@@ -1,26 +1,28 @@
-#include "cpu.hh"
+#include "cpu/cpu.hh"
+#include "cpu/utility.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
-#include "utility.hh"
 #include <algorithm>
 #include <cstdio>
 
 using namespace logger;
 
-Cpu::Cpu(Bus& bus)
+Cpu::Cpu(const Bus& bus)
   : bus(std::make_shared<Bus>(bus))
   , gpr({ 0 })
   , cpsr(0)
   , spsr(0)
+  , is_flushed(false)
   , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
   , spsr_banked({ 0, 0, 0, 0, 0 }) {
-    cpsr.set_mode(Mode::System);
+    cpsr.set_mode(Mode::Supervisor);
     cpsr.set_irq_disabled(true);
     cpsr.set_fiq_disabled(true);
     cpsr.set_state(State::Arm);
     log_info("CPU successfully initialised");
 
-    // PC is always two instructions ahead in the pipeline
+    // PC always points to two instructions ahead
+    // PC - 2 is the instruction being executed
     pc += 2 * ARM_INSTRUCTION_SIZE;
 }
 
@@ -36,7 +38,7 @@ Cpu::chg_mode(const Mode to) {
  * concatenate views */
 #define STORE_BANKED(mode, MODE)                                               \
     std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
-              gpr.begin() + GPR_COUNT - 1,                                     \
+              gpr.begin() + gpr.size() - 1,                                    \
               gpr_banked.mode.begin())
 
     switch (from) {
@@ -113,277 +115,30 @@ Cpu::chg_mode(const Mode to) {
     cpsr.set_mode(to);
 }
 
-void
-Cpu::exec_arm(const ArmInstruction instruction) {
-    auto cond = instruction.get_condition();
-    auto data = instruction.get_data();
-
-    if (!cpsr.condition(cond)) {
-        return;
-    }
-
-    auto pc_error = [](uint8_t r) {
-        if (r == 15)
-            log_error("Using PC (R15) as operand register");
-    };
-
-    auto pc_warn = [](uint8_t r) {
-        if (r == 15)
-            log_warn("Using PC (R15) as operand register");
-    };
-
-    std::visit(
-      overloaded{
-        [this, pc_warn](ArmInstruction::BranchAndExchange& data) {
-            State state = static_cast<State>(data.rn & 1);
-
-            pc_warn(data.rn);
-
-            // set state
-            cpsr.set_state(state);
-
-            // copy to PC
-            pc = gpr[data.rn];
-
-            // ignore [1:0] bits for arm and 0 bit for thumb
-            rst_nth_bit(pc, 0);
-
-            if (state == State::Arm)
-                rst_nth_bit(pc, 1);
-        },
-        [this](ArmInstruction::Branch& data) {
-            auto offset = data.offset;
-            // lsh 2 and sign extend the 26 bit offset to 32 bits
-            offset <<= 2;
-
-            if (get_nth_bit(offset, 25))
-                offset |= 0xFC000000;
-
-            if (data.link)
-                gpr[14] = pc - ARM_INSTRUCTION_SIZE;
-
-            pc += offset - ARM_INSTRUCTION_SIZE;
-        },
-        [this, pc_error](ArmInstruction::Multiply& data) {
-            if (data.rd == data.rm)
-                log_error("rd and rm are not distinct in {}",
-                          typeid(data).name());
-
-            pc_error(data.rd);
-            pc_error(data.rd);
-            pc_error(data.rd);
-
-            gpr[data.rd] =
-              gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
-
-            if (data.set) {
-                cpsr.set_z(!static_cast<bool>(gpr[data.rd]));
-                cpsr.set_n(get_nth_bit(gpr[data.rd], 31));
-                cpsr.set_c(0);
-            }
-        },
-        [this, pc_error](ArmInstruction::MultiplyLong& data) {
-            if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
-                data.rdlo == data.rm)
-                log_error("rdhi, rdlo and rm are not distinct in {}",
-                          typeid(data).name());
-
-            pc_error(data.rdhi);
-            pc_error(data.rdlo);
-            pc_error(data.rm);
-            pc_error(data.rs);
-            if (data.uns) {
-                uint64_t eval =
-                  static_cast<uint64_t>(gpr[data.rm]) *
-                    static_cast<uint64_t>(gpr[data.rs]) +
-                  (data.acc ? static_cast<uint64_t>(gpr[data.rdhi]) << 32 |
-                                static_cast<uint64_t>(gpr[data.rdlo])
-                            : 0);
-
-                gpr[data.rdlo] = get_bit_range(eval, 0, 31);
-                gpr[data.rdhi] = get_bit_range(eval, 32, 63);
-
-            } else {
-                int64_t eval =
-                  static_cast<int64_t>(gpr[data.rm]) *
-                    static_cast<int64_t>(gpr[data.rs]) +
-                  (data.acc ? static_cast<int64_t>(gpr[data.rdhi]) << 32 |
-                                static_cast<int64_t>(gpr[data.rdlo])
-                            : 0);
-
-                gpr[data.rdlo] = get_bit_range(eval, 0, 31);
-                gpr[data.rdhi] = get_bit_range(eval, 32, 63);
-            }
-
-            if (data.set) {
-                cpsr.set_z(!(static_cast<bool>(gpr[data.rdhi]) ||
-                             static_cast<bool>(gpr[data.rdlo])));
-                cpsr.set_n(get_nth_bit(gpr[data.rdhi], 31));
-                cpsr.set_c(0);
-                cpsr.set_v(0);
-            }
-        },
-        [](ArmInstruction::Undefined) { log_warn("Undefined instruction"); },
-        [this, pc_warn](ArmInstruction::SingleDataSwap& data) {
-            pc_warn(data.rm);
-            pc_warn(data.rn);
-            pc_warn(data.rd);
-
-            if (data.byte) {
-                gpr[data.rd] = bus->read_byte(gpr[data.rn]);
-                bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
-            } else {
-                gpr[data.rd] = bus->read_word(gpr[data.rn]);
-                bus->write_word(gpr[data.rn], gpr[data.rm]);
-            }
-        },
-        [this, pc_warn, pc_error](ArmInstruction::SingleDataTransfer& data) {
-            uint32_t offset  = 0;
-            uint32_t address = gpr[data.rn];
-
-            if (!data.pre && data.write)
-                log_warn("Write-back enabled with post-indexing in {}",
-                         typeid(data).name());
-
-            if (data.write)
-                pc_warn(data.rn);
-
-            // evaluate the offset
-            if (const uint16_t* immediate =
-                  std::get_if<uint16_t>(&data.offset)) {
-                offset = *immediate;
-            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
-                uint8_t amount =
-                  (shift->data.immediate ? shift->data.operand
-                                         : gpr[shift->data.operand] & 0xFF);
-
-                bool carry = cpsr.c();
-
-                if (!shift->data.immediate)
-                    pc_error(shift->data.operand);
-                pc_error(shift->rm);
-
-                eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
-
-                cpsr.set_c(carry);
-            }
-
-            // PC is always two instructions ahead
-            if (data.rn == 15)
-                address -= 2 * ARM_INSTRUCTION_SIZE;
-
-            if (data.pre)
-                address += (data.up ? offset : -offset);
-
-            // load
-            if (data.load) {
-                // byte
-                if (data.byte)
-                    gpr[data.rd] = bus->read_byte(address);
-                // word
-                else
-                    gpr[data.rd] = bus->read_word(address);
-                // store
-            } else {
-                // take PC into consideration
-                if (data.rd == 15)
-                    address += ARM_INSTRUCTION_SIZE;
-
-                // byte
-                if (data.byte)
-                    bus->write_byte(address, gpr[data.rd] & 0xFF);
-                // word
-                else
-                    bus->write_word(address, gpr[data.rd]);
-            }
-
-            if (!data.pre)
-                address += (data.up ? offset : -offset);
-
-            if (!data.pre || data.write)
-                gpr[data.rn] = address;
-        },
-        [this, pc_warn, pc_error](ArmInstruction::HalfwordTransfer& data) {
-            uint32_t address = gpr[data.rn];
-
-            if (!data.pre && data.write)
-                log_error("Write-back enabled with post-indexing in {}",
-                          typeid(data).name());
-
-            if (data.sign && !data.load)
-                log_error("Signed data found in {}", typeid(data).name());
-
-            if (data.write)
-                pc_warn(data.rn);
-
-            // offset is register number (4 bits) when not an immediate
-            if (!data.imm)
-                pc_error(data.offset);
-
-            if (data.pre)
-                address += (data.up ? data.offset : -data.offset);
-
-            // load
-            if (data.load) {
-                // signed
-                if (data.sign) {
-                    // halfword
-                    if (data.half) {
-                        gpr[data.rd] = bus->read_halfword(address);
-
-                        // sign extend the halfword
-                        if (get_nth_bit(gpr[data.rd], 15))
-                            gpr[data.rd] |= 0xFFFF0000;
-                        // byte
-                    } else {
-                        gpr[data.rd] = bus->read_byte(address);
-
-                        // sign extend the byte
-                        if (get_nth_bit(gpr[data.rd], 7))
-                            gpr[data.rd] |= 0xFFFFFF00;
-                    }
-                    // unsigned halfword
-                } else if (data.half) {
-                    gpr[data.rd] = bus->read_halfword(address);
-                }
-                // store
-            } else {
-                // take PC into consideration
-                if (data.rd == 15)
-                    address += ARM_INSTRUCTION_SIZE;
-
-                // halfword
-                if (data.half)
-                    bus->write_halfword(address, gpr[data.rd]);
-            }
-
-            if (!data.pre)
-                address += (data.up ? data.offset : -data.offset);
-
-            if (!data.pre || data.write)
-                gpr[data.rn] = address;
-        },
-        [this](ArmInstruction::SoftwareInterrupt) {
-            chg_mode(Mode::Supervisor);
-            pc   = 0x08;
-            spsr = cpsr;
-        },
-        [](auto& data) { log_error("{} instruction", typeid(data).name()); } },
-      data);
-}
-
 void
 Cpu::step() {
+    // Current instruction is two instructions behind PC
     uint32_t cur_pc = pc - 2 * ARM_INSTRUCTION_SIZE;
 
     if (cpsr.state() == State::Arm) {
-        ArmInstruction instruction(bus->read_word(cur_pc));
+        debug(cur_pc);
-        log_info("{:#034b}", bus->read_word(cur_pc));
+        uint32_t x = bus->read_word(cur_pc);
+        arm::Instruction instruction(x);
+        log_info("{:#034b}", x);
 
         exec_arm(instruction);
 
-        log_info("{:#010X} : {}", cur_pc, instruction.disassemble());
+        log_info("0x{:08X} : {}", cur_pc, instruction.disassemble());
 
+        if (is_flushed) {
+            // if flushed, do not increment the PC, instead set it to two
+            // instructions ahead to account for flushed "fetch" and "decode"
+            // instructions
+            pc += 2 * ARM_INSTRUCTION_SIZE;
+            is_flushed = false;
+        } else {
+            // if not flushed continue like normal
             pc += ARM_INSTRUCTION_SIZE;
         }
+    }
 }

src/cpu/cpu.hh

@@ -1,55 +0,0 @@
-#pragma once
-
-#include "bus.hh"
-#include "instruction.hh"
-#include "psr.hh"
-
-#include <cstdint>
-
-using std::size_t;
-
-class Cpu {
-  public:
-    Cpu(Bus& bus);
-    void step();
-
-  private:
-    static constexpr size_t GPR_COUNT = 16;
-
-    static constexpr size_t GPR_FIQ_FIRST     = 8;
-    static constexpr size_t GPR_SVC_FIRST     = 13;
-    static constexpr size_t GPR_ABT_FIRST     = 13;
-    static constexpr size_t GPR_IRQ_FIRST     = 13;
-    static constexpr size_t GPR_UND_FIRST     = 13;
-    static constexpr size_t GPR_SYS_USR_FIRST = 8;
-
-    std::shared_ptr<Bus> bus;
-    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
-
-    Psr cpsr; // current program status register
-    Psr spsr; // status program status register
-
-    uint32_t& pc = gpr[15];
-
-    struct {
-        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
-        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
-        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
-        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
-        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
-
-        // visible registers before the mode switch
-        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
-    } gpr_banked; // banked general purpose registers
-
-    struct {
-        Psr fiq;
-        Psr svc;
-        Psr abt;
-        Psr irq;
-        Psr und;
-    } spsr_banked; // banked saved program status registers
-
-    void chg_mode(const Mode to);
-    void exec_arm(const ArmInstruction instruction);
-};

src/cpu/instruction.cc

@@ -1,359 +0,0 @@
-#include "instruction.hh"
-#include "util/bits.hh"
-
-ArmInstruction::ArmInstruction(uint32_t insn)
-  : condition(static_cast<Condition>(get_bit_range(insn, 28, 31))) {
-    // Branch and exhcange
-    if ((insn & 0x0FFFFFF0) == 0x012FFF10) {
-        uint8_t rn = insn & 0b1111;
-
-        data = BranchAndExchange{ rn };
-
-        // Branch
-    } else if ((insn & 0x0E000000) == 0x0A000000) {
-        bool link       = get_nth_bit(insn, 24);
-        uint32_t offset = get_bit_range(insn, 0, 23);
-
-        data = Branch{ .link = link, .offset = offset };
-
-        // Multiply
-    } else if ((insn & 0x0FC000F0) == 0x00000090) {
-        uint8_t rm = get_bit_range(insn, 0, 3);
-        uint8_t rs = get_bit_range(insn, 8, 11);
-        uint8_t rn = get_bit_range(insn, 12, 15);
-        uint8_t rd = get_bit_range(insn, 16, 19);
-        bool set   = get_nth_bit(insn, 20);
-        bool acc   = get_nth_bit(insn, 21);
-
-        data = Multiply{
-            .rm = rm, .rs = rs, .rn = rn, .rd = rd, .set = set, .acc = acc
-        };
-
-        // Multiply long
-    } else if ((insn & 0x0F8000F0) == 0x00800090) {
-        uint8_t rm   = get_bit_range(insn, 0, 3);
-        uint8_t rs   = get_bit_range(insn, 8, 11);
-        uint8_t rdlo = get_bit_range(insn, 12, 15);
-        uint8_t rdhi = get_bit_range(insn, 16, 19);
-        bool set     = get_nth_bit(insn, 20);
-        bool acc     = get_nth_bit(insn, 21);
-        bool uns     = get_nth_bit(insn, 22);
-
-        data = MultiplyLong{ .rm   = rm,
-                             .rs   = rs,
-                             .rdlo = rdlo,
-                             .rdhi = rdhi,
-                             .set  = set,
-                             .acc  = acc,
-                             .uns  = uns };
-
-        // Undefined
-    } else if ((insn & 0x0E000010) == 0x06000010) {
-        data = Undefined{};
-
-        // Single data swap
-    } else if ((insn & 0x0FB00FF0) == 0x01000090) {
-        uint8_t rm = get_bit_range(insn, 0, 3);
-        uint8_t rd = get_bit_range(insn, 12, 15);
-        uint8_t rn = get_bit_range(insn, 16, 19);
-        bool byte  = get_nth_bit(insn, 22);
-
-        data = SingleDataSwap{ .rm = rm, .rd = rd, .rn = rn, .byte = byte };
-
-        // Single data transfer
-    } else if ((insn & 0x0C000000) == 0x04000000) {
-
-        std::variant<uint16_t, Shift> offset;
-        uint8_t rd = get_bit_range(insn, 12, 15);
-        uint8_t rn = get_bit_range(insn, 16, 19);
-        bool load  = get_nth_bit(insn, 20);
-        bool write = get_nth_bit(insn, 21);
-        bool byte  = get_nth_bit(insn, 22);
-        bool up    = get_nth_bit(insn, 23);
-        bool pre   = get_nth_bit(insn, 24);
-        bool imm   = get_nth_bit(insn, 25);
-
-        if (imm) {
-            uint8_t rm = get_bit_range(insn, 0, 3);
-            bool reg   = get_nth_bit(insn, 4);
-            ShiftType shift_type =
-              static_cast<ShiftType>(get_bit_range(insn, 5, 6));
-            uint8_t operand = get_bit_range(insn, (reg ? 8 : 7), 11);
-
-            offset = Shift{ .rm   = rm,
-                            .data = ShiftData{ .type      = shift_type,
-                                               .immediate = !reg,
-                                               .operand   = operand } };
-        } else {
-            offset = static_cast<uint16_t>(get_bit_range(insn, 0, 11));
-        }
-
-        data = SingleDataTransfer{ .offset = offset,
-                                   .rd     = rd,
-                                   .rn     = rn,
-                                   .load   = load,
-                                   .write  = write,
-                                   .byte   = byte,
-                                   .up     = up,
-                                   .pre    = pre };
-
-        // Halfword transfer
-    } else if ((insn & 0x0E000090) == 0x00000090) {
-        uint8_t offset = get_bit_range(insn, 0, 3);
-        bool half      = get_nth_bit(insn, 5);
-        bool sign      = get_nth_bit(insn, 6);
-        uint8_t rd     = get_bit_range(insn, 12, 15);
-        uint8_t rn     = get_bit_range(insn, 16, 19);
-        bool load      = get_nth_bit(insn, 20);
-        bool write     = get_nth_bit(insn, 21);
-        bool imm       = get_nth_bit(insn, 22);
-        bool up        = get_nth_bit(insn, 23);
-        bool pre       = get_nth_bit(insn, 24);
-
-        offset |= (imm ? get_bit_range(insn, 8, 11) << 2 : 0);
-
-        data = HalfwordTransfer{ .offset = offset,
-                                 .half   = half,
-                                 .sign   = sign,
-                                 .rd     = rd,
-                                 .rn     = rn,
-                                 .load   = load,
-                                 .write  = write,
-                                 .imm    = imm,
-                                 .up     = up,
-                                 .pre    = pre };
-
-        // Block data transfer
-    } else if ((insn & 0x0E000000) == 0x08000000) {
-        /*static constexpr array<stringv, 2> syn = { "STM", "LDM" };
-
-        uint16_t regs = get_bit_range(insn, 0, 15);
-        uint8_t rn    = get_bit_range(insn, 16, 19);
-        bool load     = get_nth_bit(insn, 20);
-        bool write    = get_nth_bit(insn, 21);
-        bool s        = get_nth_bit(insn, 22);
-        bool up       = get_nth_bit(insn, 23);
-        bool pre      = get_nth_bit(insn, 24);
-
-        // disassembly
-        {
-            uint8_t lpu = load << 2 | pre << 1 | up;
-            std::string addr_mode;
-
-            switch(lpu) {
-            }
-            }*/
-
-        data = Undefined{};
-
-        // Software Interrupt
-        // What to do here?
-    } else if ((insn & 0x0F000000) == 0x0F000000) {
-
-        data = SoftwareInterrupt{};
-
-        // Coprocessor data transfer
-    } else if ((insn & 0x0E000000) == 0x0C000000) {
-        uint8_t offset = get_bit_range(insn, 0, 7);
-        uint8_t cpn    = get_bit_range(insn, 8, 11);
-        uint8_t crd    = get_bit_range(insn, 12, 15);
-        uint8_t rn     = get_bit_range(insn, 16, 19);
-        bool load      = get_nth_bit(insn, 20);
-        bool write     = get_nth_bit(insn, 21);
-        bool len       = get_nth_bit(insn, 22);
-        bool up        = get_nth_bit(insn, 23);
-        bool pre       = get_nth_bit(insn, 24);
-
-        data = CoprocessorDataTransfer{ .offset = offset,
-                                        .cpn    = cpn,
-                                        .crd    = crd,
-                                        .rn     = rn,
-                                        .load   = load,
-                                        .write  = write,
-                                        .len    = len,
-                                        .up     = up,
-                                        .pre    = pre };
-
-        // Coprocessor data operation
-    } else if ((insn & 0x0F000010) == 0x0E000000) {
-        uint8_t crm    = get_bit_range(insn, 0, 4);
-        uint8_t cp     = get_bit_range(insn, 5, 7);
-        uint8_t cpn    = get_bit_range(insn, 8, 11);
-        uint8_t crd    = get_bit_range(insn, 12, 15);
-        uint8_t crn    = get_bit_range(insn, 16, 19);
-        uint8_t cp_opc = get_bit_range(insn, 20, 23);
-
-        data = CoprocessorDataOperation{ .crm    = crm,
-                                         .cp     = cp,
-                                         .cpn    = cpn,
-                                         .crd    = crd,
-                                         .crn    = crn,
-                                         .cp_opc = cp_opc };
-
-        // Coprocessor register transfer
-    } else if ((insn & 0x0F000010) == 0x0E000010) {
-        uint8_t crm    = get_bit_range(insn, 0, 4);
-        uint8_t cp     = get_bit_range(insn, 5, 7);
-        uint8_t cpn    = get_bit_range(insn, 8, 11);
-        uint8_t rd     = get_bit_range(insn, 12, 15);
-        uint8_t crn    = get_bit_range(insn, 16, 19);
-        bool load      = get_nth_bit(insn, 20);
-        uint8_t cp_opc = get_bit_range(insn, 21, 23);
-
-        data = CoprocessorRegisterTransfer{ .crm    = crm,
-                                            .cp     = cp,
-                                            .cpn    = cpn,
-                                            .rd     = rd,
-                                            .crn    = crn,
-                                            .load   = load,
-                                            .cp_opc = cp_opc };
-    } else {
-        data = Undefined{};
-    }
-}
-
-std::string
-ArmInstruction::disassemble() {
-    static const std::string undefined = "UNDEFINED";
-    // goddamn this is gore
-    // TODO: make this less ugly
-    return std::visit(
-      overloaded{
-        [this](BranchAndExchange& data) {
-            return fmt::format("BX{} R{:d}", condition, data.rn);
-        },
-        [this](Branch& data) {
-            return fmt::format(
-              "B{}{} {:#08X}", (data.link ? "L" : ""), condition, data.offset);
-        },
-        [this](Multiply& data) {
-            if (data.acc) {
-                return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
-                                   condition,
-                                   (data.set ? "S" : ""),
-                                   data.rd,
-                                   data.rm,
-                                   data.rs,
-                                   data.rn);
-            } else {
-                return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
-                                   condition,
-                                   (data.set ? "S" : ""),
-                                   data.rd,
-                                   data.rm,
-                                   data.rs);
-            }
-        },
-        [this](MultiplyLong& data) {
-            return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
-                               (data.uns ? 'U' : 'S'),
-                               (data.acc ? "MLAL" : "MULL"),
-                               condition,
-                               (data.set ? "S" : ""),
-                               data.rdlo,
-                               data.rdhi,
-                               data.rm,
-                               data.rs);
-        },
-        [](Undefined) { return undefined; },
-        [this](SingleDataSwap& data) {
-            return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
-                               condition,
-                               (data.byte ? "B" : ""),
-                               data.rd,
-                               data.rm,
-                               data.rn);
-        },
-        [this](SingleDataTransfer& data) {
-            std::string expression;
-            std::string address;
-
-            if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
-                if (*offset == 0) {
-                    expression = "";
-                } else {
-                    expression = fmt::format(",#{:d}", *offset);
-                }
-            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
-                expression = fmt::format(",{}R{:d},{} {}{:d}",
-                                         (data.up ? '+' : '-'),
-                                         shift->rm,
-                                         shift->data.type,
-                                         (shift->data.immediate ? '#' : 'R'),
-                                         shift->data.operand);
-            }
-
-            return fmt::format(
-              "{}{}{}{} R{:d},[R{:d}{}]{}",
-              (data.load ? "LDR" : "STR"),
-              condition,
-              (data.byte ? "B" : ""),
-              (!data.pre && data.write ? "T" : ""),
-              data.rd,
-              data.rn,
-              (data.pre ? expression : ""),
-              (data.pre ? (data.write ? "!" : "") : expression));
-        },
-        [this](HalfwordTransfer& data) {
-            std::string expression;
-
-            if (data.imm) {
-                if (data.offset == 0) {
-                    expression = "";
-                } else {
-                    expression = fmt::format(",#{:d}", data.offset);
-                }
-            } else {
-                expression =
-                  fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
-            }
-
-            return fmt::format(
-              "{}{}{}{} R{:d},[R{:d}{}]{}",
-              (data.load ? "LDR" : "STR"),
-              condition,
-              (data.sign ? "S" : ""),
-              (data.half ? 'H' : 'B'),
-              data.rd,
-              data.rn,
-              (data.pre ? expression : ""),
-              (data.pre ? (data.write ? "!" : "") : expression));
-        },
-        [this](SoftwareInterrupt) { return fmt::format("SWI{}", condition); },
-        [this](CoprocessorDataTransfer& data) {
-            std::string expression = fmt::format(",#{:d}", data.offset);
-            return fmt::format(
-              "{}{}{} p{:d},c{:d},[R{:d}{}]{}",
-              (data.load ? "LDC" : "STC"),
-              condition,
-              (data.len ? "L" : ""),
-              data.cpn,
-              data.crd,
-              data.rn,
-              (data.pre ? expression : ""),
-              (data.pre ? (data.write ? "!" : "") : expression));
-        },
-        [this](CoprocessorDataOperation& data) {
-            return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
-                               condition,
-                               data.cpn,
-                               data.cp_opc,
-                               data.crd,
-                               data.crn,
-                               data.crm,
-                               data.cp);
-        },
-        [this](CoprocessorRegisterTransfer& data) {
-            return fmt::format("{}{} p{},{},c{},c{},c{},{}",
-                               (data.load ? "MRC" : "MCR"),
-                               condition,
-                               data.cpn,
-                               data.cp_opc,
-                               data.rd,
-                               data.crn,
-                               data.crm,
-                               data.cp);
-        },
-        [](auto) { return undefined; } },
-      data);
-}

src/cpu/instruction.hh

@@ -1,132 +0,0 @@
-#include "cpu/utility.hh"
-#include <cstdint>
-#include <variant>
-
-template<class... Ts>
-struct overloaded : Ts... {
-    using Ts::operator()...;
-};
-template<class... Ts>
-overloaded(Ts...) -> overloaded<Ts...>;
-
-class ArmInstruction {
-  public:
-    ArmInstruction() = delete;
-    ArmInstruction(uint32_t insn);
-
-    auto get_condition() const { return condition; }
-    auto get_data() const { return data; }
-
-    std::string disassemble();
-
-    struct BranchAndExchange {
-        uint8_t rn;
-    };
-
-    struct Branch {
-        bool link;
-        uint32_t offset;
-    };
-
-    struct Multiply {
-        uint8_t rm;
-        uint8_t rs;
-        uint8_t rn;
-        uint8_t rd;
-        bool set;
-        bool acc;
-    };
-
-    struct MultiplyLong {
-        uint8_t rm;
-        uint8_t rs;
-        uint8_t rdlo;
-        uint8_t rdhi;
-        bool set;
-        bool acc;
-        bool uns;
-    };
-
-    struct SingleDataSwap {
-        uint8_t rm;
-        uint8_t rd;
-        uint8_t rn;
-        bool byte;
-    };
-
-    struct SingleDataTransfer {
-        std::variant<uint16_t, Shift> offset;
-        uint8_t rd;
-        uint8_t rn;
-        bool load;
-        bool write;
-        bool byte;
-        bool up;
-        bool pre;
-    };
-
-    struct HalfwordTransfer {
-        uint8_t offset;
-        bool half;
-        bool sign;
-        uint8_t rd;
-        uint8_t rn;
-        bool load;
-        bool write;
-        bool byte;
-        bool imm;
-        bool up;
-        bool pre;
-    };
-
-    struct CoprocessorDataTransfer {
-        uint8_t offset;
-        uint8_t cpn;
-        uint8_t crd;
-        uint8_t rn;
-        bool load;
-        bool write;
-        bool len;
-        bool up;
-        bool pre;
-    };
-
-    struct CoprocessorDataOperation {
-        uint8_t crm;
-        uint8_t cp;
-        uint8_t cpn;
-        uint8_t crd;
-        uint8_t crn;
-        uint8_t cp_opc;
-    };
-
-    struct CoprocessorRegisterTransfer {
-        uint8_t crm;
-        uint8_t cp;
-        uint8_t cpn;
-        uint8_t rd;
-        uint8_t crn;
-        bool load;
-        uint8_t cp_opc;
-    };
-
-    struct Undefined {};
-    struct SoftwareInterrupt {};
-
-    using InstructionData = std::variant<BranchAndExchange,
-                                         Branch,
-                                         Multiply,
-                                         MultiplyLong,
-                                         SingleDataSwap,
-                                         SingleDataTransfer,
-                                         HalfwordTransfer,
-                                         CoprocessorDataTransfer,
-                                         CoprocessorDataOperation,
-                                         CoprocessorRegisterTransfer,
-                                         Undefined,
-                                         SoftwareInterrupt>;
-
-  private:
-    Condition condition;
-    InstructionData data;
-};

src/cpu/meson.build

@@ -1,6 +1,7 @@
 lib_sources += files(
   'cpu.cc',
-  'instruction.cc',
   'psr.cc',
   'utility.cc'
 )
+
+subdir('arm')

src/cpu/psr.cc

@@ -1,10 +1,20 @@
-#include "psr.hh"
+#include "cpu/psr.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
 Psr::Psr(uint32_t raw)
   : psr(raw & PSR_CLEAR_RESERVED) {}
 
+uint32_t
+Psr::raw() const {
+    return psr;
+}
+
+void
+Psr::set_all(uint32_t raw) {
+    psr = raw & ~PSR_CLEAR_RESERVED;
+}
+
 Mode
 Psr::mode() const {
     return static_cast<Mode>(psr & ~PSR_CLEAR_MODE);
@@ -18,20 +28,20 @@ Psr::set_mode(Mode mode) {
 
 State
 Psr::state() const {
-    return static_cast<State>(get_nth_bit(psr, 5));
+    return static_cast<State>(get_bit(psr, 5));
 }
 
 void
 Psr::set_state(State state) {
-    chg_nth_bit(psr, 5, static_cast<bool>(state));
+    chg_bit(psr, 5, static_cast<bool>(state));
 }
 
 #define GET_SET_NTH_BIT_FUNCTIONS(name, n)                                     \
     bool Psr::name() const {                                                   \
-        return get_nth_bit(psr, n);                                            \
+        return get_bit(psr, n);                                                \
     }                                                                          \
     void Psr::set_##name(bool val) {                                           \
-        chg_nth_bit(psr, n, val);                                              \
+        chg_bit(psr, n, val);                                                  \
     }
 
 GET_SET_NTH_BIT_FUNCTIONS(fiq_disabled, 6)
@@ -82,4 +92,6 @@ Psr::condition(Condition cond) const {
         case Condition::AL:
             return true;
     }
+
+    return false;
 }

src/cpu/psr.hh

@@ -1,52 +0,0 @@
-#pragma once
-
-#include "utility.hh"
-#include <cstdint>
-
-class Psr {
-  public:
-    // clear the reserved bits i.e, [8:27]
-    Psr(uint32_t raw);
-
-    // Mode : [4:0]
-    Mode mode() const;
-    void set_mode(Mode mode);
-
-    // State : [5]
-    State state() const;
-    void set_state(State state);
-
-#define GET_SET_NTH_BIT_FUNCTIONS(name)                                        \
-    bool name() const;                                                         \
-    void set_##name(bool val);
-
-    // FIQ disable : [6]
-    GET_SET_NTH_BIT_FUNCTIONS(fiq_disabled)
-
-    // IRQ disable : [7]
-    GET_SET_NTH_BIT_FUNCTIONS(irq_disabled)
-
-    // Reserved bits : [27:8]
-
-    // Overflow flag : [28]
-    GET_SET_NTH_BIT_FUNCTIONS(v)
-
-    // Carry flag : [29]
-    GET_SET_NTH_BIT_FUNCTIONS(c)
-
-    // Zero flag : [30]
-    GET_SET_NTH_BIT_FUNCTIONS(z)
-
-    // Negative flag : [30]
-    GET_SET_NTH_BIT_FUNCTIONS(n)
-
-#undef GET_SET_NTH_BIT_FUNCTIONS
-
-    bool condition(Condition cond) const;
-
-  private:
-    static constexpr uint32_t PSR_CLEAR_RESERVED = 0xf00000ff;
-    static constexpr uint32_t PSR_CLEAR_MODE     = 0x0b00000;
-
-    uint32_t psr;
-};

src/cpu/utility.cc

@@ -1,4 +1,4 @@
-#include "utility.hh"
+#include "cpu/utility.hh"
 #include "util/bits.hh"
 #include <bit>
 
@@ -35,45 +35,85 @@ operator<<(std::ostream& os, const Condition cond) {
     return os;
 }
 
+std::ostream&
+operator<<(std::ostream& os, const OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case OpCode::opcode:                                                       \
+        os << #opcode;                                                         \
+        break;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(SUB)
+        CASE(RSB)
+        CASE(ADD)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(RSC)
+        CASE(TST)
+        CASE(TEQ)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MOV)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+
+    return os;
+}
+
 uint32_t
 eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
+    uint32_t eval = 0;
+
     switch (shift_type) {
         case ShiftType::LSL:
 
             if (amount > 0 && amount <= 32)
-                carry = get_nth_bit(value, 32 - amount);
+                carry = get_bit(value, 32 - amount);
             else if (amount > 32)
                 carry = 0;
 
-            return value << amount;
+            eval = value << amount;
+            break;
         case ShiftType::LSR:
 
             if (amount > 0 && amount <= 32)
-                carry = get_nth_bit(value, amount - 1);
+                carry = get_bit(value, amount - 1);
             else if (amount > 32)
                 carry = 0;
             else
-                carry = get_nth_bit(value, 31);
+                carry = get_bit(value, 31);
 
-            return value >> amount;
+            eval = value >> amount;
+            break;
         case ShiftType::ASR:
             if (amount > 0 && amount <= 32)
-                carry = get_nth_bit(value, amount - 1);
+                carry = get_bit(value, amount - 1);
             else
-                carry = get_nth_bit(value, 31);
+                carry = get_bit(value, 31);
 
             return static_cast<int32_t>(value) >> amount;
+            break;
         case ShiftType::ROR:
             if (amount == 0) {
                 bool old_carry = carry;
 
-                carry = get_nth_bit(value, 0);
+                carry = get_bit(value, 0);
-                return (value >> 1) | (old_carry << 31);
+                eval  = (value >> 1) | (old_carry << 31);
             } else {
-                carry = get_nth_bit(value, (amount % 32 + 31) % 32);
+                carry = get_bit(value, (amount % 32 + 31) % 32);
-                return std::rotr(value, amount);
+                eval  = std::rotr(value, amount);
             }
+            break;
     }
+
+    return eval;
 }
 
 std::ostream&

src/cpu/utility.hh

@@ -1,93 +0,0 @@
-#pragma once
-
-#include <fmt/ostream.h>
-#include <ostream>
-
-static constexpr size_t ARM_INSTRUCTION_SIZE   = 4;
-static constexpr size_t THUMB_INSTRUCTION_SIZE = 2;
-
-enum class Mode {
-    /* M[4:0] in PSR */
-    User       = 0b10000,
-    Fiq        = 0b10001,
-    Irq        = 0b10010,
-    Supervisor = 0b10011,
-    Abort      = 0b10111,
-    Undefined  = 0b11011,
-    System     = 0b11111,
-};
-
-enum class State {
-    Arm   = 0,
-    Thumb = 1
-};
-
-enum class Condition {
-    EQ = 0b0000,
-    NE = 0b0001,
-    CS = 0b0010,
-    CC = 0b0011,
-    MI = 0b0100,
-    PL = 0b0101,
-    VS = 0b0110,
-    VC = 0b0111,
-    HI = 0b1000,
-    LS = 0b1001,
-    GE = 0b1010,
-    LT = 0b1011,
-    GT = 0b1100,
-    LE = 0b1101,
-    AL = 0b1110
-};
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const Condition cond);
-template<>
-struct fmt::formatter<Condition> : ostream_formatter {};
-
-enum class OpCode {
-    AND = 0b0000,
-    EOR = 0b0001,
-    SUB = 0b0010,
-    RSB = 0b0011,
-    ADD = 0b0100,
-    ADC = 0b0101,
-    SBC = 0b0110,
-    RSC = 0b0111,
-    TST = 0b1000,
-    TEQ = 0b1001,
-    CMP = 0b1010,
-    CMN = 0b1011,
-    ORR = 0b1100,
-    MOV = 0b1101,
-    BIC = 0b1110,
-    MVN = 0b1111
-};
-
-enum class ShiftType {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11
-};
-
-struct ShiftData {
-    ShiftType type;
-    bool immediate;
-    uint8_t operand;
-};
-
-struct Shift {
-    uint8_t rm;
-    ShiftData data;
-};
-
-uint32_t
-eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const ShiftType cond);
-template<>
-struct fmt::formatter<ShiftType> : ostream_formatter {};

src/header.hh

@@ -1,45 +0,0 @@
-#pragma once
-
-#include <cstdint>
-#include <string>
-#include <vector>
-
-struct Header {
-    enum class UniqueCode {
-        Old,        // old games
-        New,        // new games
-        Newer,      // unused (newer games)
-        Famicom,    // NES
-        YoshiKoro,  // acceleration sensor
-        Ereader,    // dot code scanner
-        Warioware,  // rumble and z-axis gyro
-        Boktai,     // RTC and solar sensor
-        DrillDozer, // rumble
-    };
-
-    enum class I18n {
-        Japan,
-        Europe,
-        French,
-        Spanish,
-        Usa,
-        German,
-        Italian
-    };
-
-    enum class BootMode {
-        Joybus,
-        Normal,
-        Multiplay
-    };
-
-    uint32_t entrypoint;
-    std::string title;
-    std::string title_code;
-    UniqueCode unique_code;
-    I18n i18n;
-    uint8_t version;
-    BootMode multiboot;
-    uint32_t multiboot_entrypoint;
-    uint8_t slave_id;
-};

src/memory.cc

@@ -4,11 +4,12 @@
 #include "util/log.hh"
 #include "util/utils.hh"
 #include <bitset>
+#include <stdexcept>
 
 using namespace logger;
 
 Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-               std::vector<uint8_t>&& rom) noexcept
+               std::vector<uint8_t>&& rom)
   : bios(std::move(bios))
   , board_wram({ 0 })
   , chip_wram({ 0 })
@@ -58,7 +59,7 @@ Memory::read(size_t address) const {
         return rom[address - ROM_2_START];
     } else {
         log_error("Invalid memory region accessed");
-        return 0;
+        return 0xFF;
     }
 }
 
@@ -116,18 +117,24 @@ Memory::read_word(size_t address) const {
 }
 
 void
-Memory::write_word(size_t address, uint32_t halfword) {
+Memory::write_word(size_t address, uint32_t word) {
     if (address & 0b11)
         log_warn("Writing to a non aligned word address");
 
-    write(address, halfword & 0xFF);
+    write(address, word & 0xFF);
-    write(address + 1, halfword >> 8 & 0xFF);
+    write(address + 1, word >> 8 & 0xFF);
-    write(address + 2, halfword >> 16 & 0xFF);
+    write(address + 2, word >> 16 & 0xFF);
-    write(address + 3, halfword >> 24 & 0xFF);
+    write(address + 3, word >> 24 & 0xFF);
 }
 
 void
 Memory::parse_header() {
+
+    if (rom.size() < 192) {
+        throw std::out_of_range(
+          "ROM is not large enough to even have a header");
+    }
+
     // entrypoint
     header.entrypoint =
       rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;

src/memory.hh

@@ -1,64 +0,0 @@
-#pragma once
-
-#include "header.hh"
-#include <array>
-#include <cstddef>
-#include <cstdint>
-#include <vector>
-
-class Memory {
-  public:
-    static constexpr size_t BIOS_SIZE = 1024 * 16;
-
-    Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-           std::vector<uint8_t>&& rom) noexcept;
-
-    uint8_t read(size_t address) const;
-    void write(size_t address, uint8_t byte);
-
-    uint16_t read_halfword(size_t address) const;
-    void write_halfword(size_t address, uint16_t halfword);
-
-    uint32_t read_word(size_t address) const;
-    void write_word(size_t address, uint32_t word);
-
-  private:
-#define MEMORY_REGION(name, start, end)                                        \
-    static constexpr size_t name##_START = start;                              \
-    static constexpr size_t name##_END   = end;
-
-#define DECL_MEMORY(name, ident, start, end)                                   \
-    MEMORY_REGION(name, start, end)                                            \
-    std::array<uint8_t, name##_END - name##_START + 1> ident;
-
-    MEMORY_REGION(BIOS, 0x00000000, 0x00003FFF)
-    std::array<uint8_t, BIOS_SIZE> bios;
-    static_assert(BIOS_END - BIOS_START + 1 == BIOS_SIZE);
-
-    // board working RAM
-    DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
-
-    // chip working RAM
-    DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
-
-    // palette RAM
-    DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
-
-    // video RAM
-    DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
-
-    // OAM OBJ attributes
-    DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
-
-#undef DECL_MEMORY
-
-    MEMORY_REGION(ROM_0, 0x08000000, 0x09FFFFFF)
-    MEMORY_REGION(ROM_1, 0x0A000000, 0x0BFFFFFF)
-    MEMORY_REGION(ROM_2, 0x0C000000, 0x0DFFFFFF)
-
-#undef MEMORY_REGION
-
-    std::vector<uint8_t> rom;
-    Header header;
-    void parse_header();
-};

src/meson.build

@@ -10,8 +10,8 @@ lib = library(
   meson.project_name(),
   lib_sources,
   dependencies: [fmt],
-  install: true,
+  include_directories: inc,
-  cpp_args: '-DFMT_HEADER_ONLY'
+  install: true
 )
 
 import('pkgconfig').generate(lib)

src/util/bits.hh

@@ -7,32 +7,32 @@ using std::size_t;
 
 template<std::integral Int>
 inline bool
-get_nth_bit(Int num, size_t n) {
+get_bit(Int num, size_t n) {
     return (num >> n) & 1;
 }
 
 template<std::integral Int>
 inline void
-set_nth_bit(Int& num, size_t n) {
+set_bit(Int& num, size_t n) {
     num |= (1 << n);
 }
 
 template<std::integral Int>
 inline void
-rst_nth_bit(Int& num, size_t n) {
+rst_bit(Int& num, size_t n) {
     num &= ~(1 << n);
 }
 
 template<std::integral Int>
 inline void
-chg_nth_bit(Int& num, size_t n, bool x) {
+chg_bit(Int& num, size_t n, bool x) {
     num = (num & ~(1 << n)) | (x << n);
 }
 
 /// read range of bits from start to end inclusive
 template<std::integral Int>
 inline Int
-get_bit_range(Int num, size_t start, size_t end) {
+bit_range(Int num, size_t start, size_t end) {
     // NOTE: we do not require -1 if it is a signed integral
     Int left =
       std::numeric_limits<Int>::digits - (std::is_unsigned<Int>::value) - end;

src/util/utils.hh

@@ -3,8 +3,6 @@
 #include <array>
 #include <bit>
 #include <fmt/core.h>
-#include <iomanip>
-#include <sstream>
 #include <string>
 
 // Why I wrote this myself? I do not know

tests/cpu/arm/exec.cc

@@ -0,0 +1,227 @@
+#include "cpu/cpu.hh"
+#include "cpu/utility.hh"
+#include <bit>
+#include <catch2/catch_test_macros.hpp>
+#include <iostream>
+#include <limits>
+#include <random>
+
+// I could have written some public API but that wouldn't be the best practice,
+// so instead I will try to do my best to test these functions using memory
+// manipulation. We also use a fake PC to match the current instruction's
+// address.
+//
+// We are going to use some addresses for specific tasks
+// - (4 * 400) + 4 => Storing, then reading registers
+//
+// We are also going to keep some registers reserved for testing
+// - R0 is always zero
+// - R1 for reading PSR
+
+class CpuFixture {
+  public:
+    uint32_t fake_pc = 2 * ARM_INSTRUCTION_SIZE;
+
+    CpuFixture()
+      // BIOS is all zeroes so let's do what we can
+      : memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+               std::vector<uint8_t>(192))
+      , bus(memory)
+      , cpu(bus) {}
+
+    void write_register(uint8_t rd, uint8_t value, uint8_t rotate = 0) {
+        // MOV
+        uint32_t raw = 0b11100011101000000000000000000000;
+        raw |= rd << 12;
+        raw |= rotate << 8;
+        raw |= value;
+        execute(raw);
+    }
+
+    uint32_t read_register(uint8_t rd) {
+        // use R0
+        static constexpr uint16_t offset = MAX_FAKE_PC + ARM_INSTRUCTION_SIZE;
+
+        uint32_t raw = 0b11100101100000000000000000000000;
+        raw |= rd << 12;
+        raw |= offset;
+        execute(raw);
+
+        return bus.read_word(offset + (rd == 15 ? ARM_INSTRUCTION_SIZE : 0));
+    }
+
+    Psr read_cpsr() {
+        // use R1
+        uint32_t raw = 0b11100001000011110001000000000000;
+        execute(raw);
+
+        return Psr(read_register(1));
+    }
+
+    void execute(uint32_t raw) {
+        bus.write_word(fake_pc - 2 * ARM_INSTRUCTION_SIZE, raw);
+        step();
+    }
+
+  private:
+    static constexpr uint32_t MAX_FAKE_PC = 400 * ARM_INSTRUCTION_SIZE;
+    Memory memory;
+
+    void step() {
+        cpu.step();
+        fake_pc += ARM_INSTRUCTION_SIZE;
+        if (fake_pc == MAX_FAKE_PC)
+            fake_pc = 0;
+    }
+
+  protected:
+    Bus bus;
+    Cpu cpu;
+};
+
+#define TAG "arm execution"
+
+using namespace arm;
+
+TEST_CASE_METHOD(CpuFixture, "Test fixture", TAG) {
+    std::random_device rd;
+    std::mt19937 gen(rd());
+    std::uniform_int_distribution<uint8_t> value_d;
+    std::uniform_int_distribution<uint8_t> shift_d(0, (1 << 4) - 1);
+
+    // R0 is reserved to be 0 so that it can be used as as offset
+    write_register(0, 0);
+    REQUIRE(read_register(0) == 0);
+
+    for (uint8_t i = 1; i < 15; i++) {
+        uint8_t value   = value_d(gen);
+        uint8_t shift   = shift_d(gen);
+        uint32_t amount = std::rotr(static_cast<uint32_t>(value), 2 * shift);
+
+        write_register(i, value, shift);
+        REQUIRE(read_register(i) == amount);
+    }
+
+    REQUIRE(read_cpsr().mode() == Mode::Supervisor);
+
+    INFO("Fixture is OK");
+}
+
+TEST_CASE_METHOD(CpuFixture, "Branch and Exchange", TAG) {
+    uint32_t raw = 0b11100001001011111111111100011010;
+
+    write_register(10, 240);
+
+    execute(raw);
+    fake_pc = 240 + 2 * ARM_INSTRUCTION_SIZE;
+
+    REQUIRE(read_register(15) == 240 + 2 * ARM_INSTRUCTION_SIZE);
+}
+
+// TODO write BX for when switching to thumb
+
+TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
+    uint32_t raw = 0b11101011000000000000000000111100;
+
+    uint32_t old_pc = fake_pc;
+    execute(raw);
+    fake_pc = old_pc + 240;
+
+    // pipeline is flushed
+    fake_pc += 2 * ARM_INSTRUCTION_SIZE;
+
+    REQUIRE(read_register(15) == old_pc + 240 + 2 * ARM_INSTRUCTION_SIZE);
+    REQUIRE(read_register(14) == old_pc - ARM_INSTRUCTION_SIZE);
+}
+
+TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
+    uint32_t raw    = 0b11100000001111011100101110011010;
+    uint32_t result = 0;
+
+    write_register(10, 230);
+    write_register(11, 192);
+    write_register(12, 37);
+
+    execute(raw);
+    result = 230 * 192 + 37;
+
+    REQUIRE(read_register(13) == result);
+    REQUIRE(read_cpsr().n() == (result >> 31 & 1));
+
+    // when product is zero
+    write_register(10, 230);
+    write_register(11, 0);
+    write_register(12, 0);
+
+    execute(raw);
+
+    REQUIRE(read_register(13) == 0);
+    REQUIRE(read_cpsr().z() == true);
+}
+
+TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
+    uint32_t raw    = 0b11100000101111011100101110011010;
+    uint64_t result = 0;
+
+    write_register(10, 230, 3);  // 2550136835
+    write_register(11, 192, 12); // 49152
+    write_register(12, 255, 9);  // 4177920
+    write_register(13, 11, 4);   // 184549376
+
+    result = 2550136835ull * 49152ull + (184549376ull << 32 | 4177920ull);
+
+    execute(raw);
+
+    REQUIRE(read_register(12) == (result & 0xFFFFFFFF));
+    REQUIRE(read_register(13) == (result >> 32 & 0xFFFFFFFF));
+    REQUIRE(read_cpsr().z() == false);
+    REQUIRE(read_cpsr().n() == (result >> 63 & 1));
+
+    // signed
+    raw = 0b11100000111111011100101110011010;
+
+    write_register(12, 255, 9); // 4177920
+    write_register(13, 11, 4);  // 184549376
+
+    execute(raw);
+
+    REQUIRE(read_register(12) == (result & 0xFFFFFFFF));
+    REQUIRE(read_register(13) == (result >> 32 & 0xFFFFFFFF));
+    REQUIRE(read_cpsr().z() == false);
+    REQUIRE(read_cpsr().n() == (result >> 63 & 1));
+
+    // 0 and no accumulation
+    raw = 0b11100000110111011100101110011010;
+
+    write_register(10, 0);
+    execute(raw);
+
+    REQUIRE(read_register(12) == 0);
+    REQUIRE(read_register(13) == 0);
+    REQUIRE(read_cpsr().z() == true);
+}
+
+TEST_CASE_METHOD(CpuFixture, "Single Data Swap", TAG) {
+    write_register(6, 230, 3); // 2550136835
+    write_register(9, 160, 0); // 160
+    bus.write_word(read_register(9), 49152);
+
+    SECTION("word") {
+        uint32_t raw = 0b11100001000010010101000010010110;
+        execute(raw);
+
+        REQUIRE(read_register(5) == 49152);
+        REQUIRE(bus.read_word(read_register(9)) == 2550136835);
+    }
+
+    SECTION("byte") {
+        uint32_t raw = 0b11100001010010010101000010010110;
+
+        execute(raw);
+
+        REQUIRE(read_register(5) == (49152 & 0xFF));
+        REQUIRE(bus.read_byte(read_register(9)) == (2550136835 & 0xFF));
+    }
+}
+
+#undef TAG

tests/cpu/arm/instruction.cc

@@ -0,0 +1,469 @@
+#include "cpu/arm/instruction.hh"
+#include "cpu/utility.hh"
+#include <catch2/catch_test_macros.hpp>
+
+#define TAG "disassembler"
+
+using namespace arm;
+
+TEST_CASE("Branch and Exchange", TAG) {
+    uint32_t raw = 0b11000001001011111111111100011010;
+    Instruction instruction(raw);
+    BranchAndExchange* bx = nullptr;
+
+    REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GT);
+
+    REQUIRE(bx->rn == 10);
+
+    REQUIRE(instruction.disassemble() == "BXGT R10");
+}
+
+TEST_CASE("Branch", TAG) {
+    uint32_t raw = 0b11101011100001010111111111000011;
+    Instruction instruction(raw);
+    Branch* b = nullptr;
+
+    REQUIRE((b = std::get_if<Branch>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    // last 24 bits = 8748995
+    // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
+    // Also +8 since PC is two instructions ahead
+    REQUIRE(b->offset == 0xFE15FF14);
+    REQUIRE(b->link == true);
+
+    REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
+
+    b->link = false;
+    REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
+}
+
+TEST_CASE("Multiply", TAG) {
+    uint32_t raw = 0b00000000001110101110111110010000;
+    Instruction instruction(raw);
+    Multiply* mul = nullptr;
+
+    REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::EQ);
+
+    REQUIRE(mul->rm == 0);
+    REQUIRE(mul->rs == 15);
+    REQUIRE(mul->rn == 14);
+    REQUIRE(mul->rd == 10);
+    REQUIRE(mul->acc == true);
+    REQUIRE(mul->set == true);
+
+    REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
+
+    mul->acc = false;
+    mul->set = false;
+    REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
+}
+
+TEST_CASE("Multiply Long", TAG) {
+    uint32_t raw = 0b00010000100111100111011010010010;
+    Instruction instruction(raw);
+    MultiplyLong* mull = nullptr;
+
+    REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::NE);
+
+    REQUIRE(mull->rm == 2);
+    REQUIRE(mull->rs == 6);
+    REQUIRE(mull->rdlo == 7);
+    REQUIRE(mull->rdhi == 14);
+    REQUIRE(mull->acc == false);
+    REQUIRE(mull->set == true);
+    REQUIRE(mull->uns == true);
+
+    REQUIRE(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
+
+    mull->acc = true;
+    REQUIRE(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
+
+    mull->uns = false;
+    mull->set = false;
+    REQUIRE(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
+}
+
+TEST_CASE("Undefined", TAG) {
+    // notice how this is the same as single data transfer except the shift
+    // is now a register based shift
+    uint32_t raw = 0b11100111101000101010111100010110;
+    Instruction instruction(raw);
+
+    REQUIRE(instruction.condition == Condition::AL);
+    REQUIRE(instruction.disassemble() == "UND");
+}
+
+TEST_CASE("Single Data Swap", TAG) {
+    uint32_t raw = 0b10100001000010010101000010010110;
+    Instruction instruction(raw);
+    SingleDataSwap* swp = nullptr;
+
+    REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GE);
+
+    REQUIRE(swp->rm == 6);
+    REQUIRE(swp->rd == 5);
+    REQUIRE(swp->rn == 9);
+    REQUIRE(swp->byte == false);
+
+    REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
+
+    swp->byte = true;
+    REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
+}
+
+TEST_CASE("Single Data Transfer", TAG) {
+    uint32_t raw = 0b11100111101000101010111100000110;
+    Instruction instruction(raw);
+    SingleDataTransfer* ldr = nullptr;
+    Shift* shift            = nullptr;
+
+    REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
+    REQUIRE(shift->rm == 6);
+    REQUIRE(shift->data.immediate == true);
+    REQUIRE(shift->data.type == ShiftType::LSL);
+    REQUIRE(shift->data.operand == 30);
+    REQUIRE(ldr->rd == 10);
+    REQUIRE(ldr->rn == 2);
+    REQUIRE(ldr->load == false);
+    REQUIRE(ldr->write == true);
+    REQUIRE(ldr->byte == false);
+    REQUIRE(ldr->up == true);
+    REQUIRE(ldr->pre == true);
+
+    ldr->load        = true;
+    ldr->byte        = true;
+    ldr->write       = false;
+    shift->data.type = ShiftType::ROR;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
+
+    ldr->up  = false;
+    ldr->pre = false;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
+
+    ldr->offset = static_cast<uint16_t>(9023);
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
+
+    ldr->pre = true;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
+}
+
+TEST_CASE("Halfword Transfer", TAG) {
+    uint32_t raw = 0b00110001101011110010000010110110;
+    Instruction instruction(raw);
+    HalfwordTransfer* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::CC);
+
+    // offset is not immediate
+    REQUIRE(ldr->imm == 0);
+    // hence this offset is a register number (rm)
+    REQUIRE(ldr->offset == 6);
+    REQUIRE(ldr->half == true);
+    REQUIRE(ldr->sign == false);
+    REQUIRE(ldr->rd == 2);
+    REQUIRE(ldr->rn == 15);
+    REQUIRE(ldr->load == false);
+    REQUIRE(ldr->write == true);
+    REQUIRE(ldr->up == true);
+    REQUIRE(ldr->pre == true);
+
+    REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
+
+    ldr->pre  = false;
+    ldr->load = true;
+    ldr->sign = true;
+    ldr->up   = false;
+
+    REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
+
+    ldr->half = false;
+    REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
+
+    ldr->load = false;
+    // not a register anymore
+    ldr->imm    = 1;
+    ldr->offset = 90;
+    REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
+}
+
+TEST_CASE("Block Data Transfer", TAG) {
+    uint32_t raw = 0b10011001010101110100000101101101;
+    Instruction instruction(raw);
+    BlockDataTransfer* ldm = nullptr;
+
+    REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::LS);
+
+    {
+        uint16_t regs = 0;
+        regs |= 1 << 0;
+        regs |= 1 << 2;
+        regs |= 1 << 3;
+        regs |= 1 << 5;
+        regs |= 1 << 6;
+        regs |= 1 << 8;
+        regs |= 1 << 14;
+
+        REQUIRE(ldm->regs == regs);
+    }
+
+    REQUIRE(ldm->rn == 7);
+    REQUIRE(ldm->load == true);
+    REQUIRE(ldm->write == false);
+    REQUIRE(ldm->s == true);
+    REQUIRE(ldm->up == false);
+    REQUIRE(ldm->pre == true);
+
+    REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
+
+    ldm->write = true;
+    ldm->s     = false;
+    ldm->up    = true;
+
+    REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
+
+    ldm->regs &= ~(1 << 6);
+    ldm->regs &= ~(1 << 3);
+    ldm->regs &= ~(1 << 8);
+    ldm->load = false;
+    ldm->pre  = false;
+
+    REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
+}
+
+TEST_CASE("PSR Transfer", TAG) {
+    PsrTransfer* msr = nullptr;
+
+    SECTION("MRS") {
+        uint32_t raw = 0b01000001010011111010000000000000;
+        Instruction instruction(raw);
+        PsrTransfer* mrs = nullptr;
+
+        REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::MI);
+
+        REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
+        // Operand is a register in the case of MRS (PSR -> Register)
+        REQUIRE(mrs->operand == 10);
+        REQUIRE(mrs->spsr == true);
+
+        REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
+    }
+
+    SECTION("MSR") {
+        uint32_t raw = 0b11100001001010011111000000001000;
+        Instruction instruction(raw);
+        PsrTransfer* msr = nullptr;
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::AL);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr);
+        // Operand is a register in the case of MSR (Register -> PSR)
+        REQUIRE(msr->operand == 8);
+        REQUIRE(msr->spsr == false);
+
+        REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
+    }
+
+    SECTION("MSR_flg with register operand") {
+        uint32_t raw = 0b01100001001010001111000000001000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::VS);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->imm == 0);
+        REQUIRE(msr->operand == 8);
+        REQUIRE(msr->spsr == false);
+
+        REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
+    }
+
+    SECTION("MSR_flg with immediate operand") {
+        uint32_t raw = 0b11100011011010001111011101101000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::AL);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->imm == 1);
+
+        // 104 (32 bits) rotated by 2 * 7
+        REQUIRE(msr->operand == 27262976);
+        REQUIRE(msr->spsr == true);
+
+        REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
+    }
+}
+
+TEST_CASE("Data Processing", TAG) {
+    uint32_t raw = 0b11100000000111100111101101100001;
+    Instruction instruction(raw);
+    DataProcessing* alu = nullptr;
+    Shift* shift        = nullptr;
+
+    REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    // operand 2 is a shifted register
+    REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
+    REQUIRE(shift->rm == 1);
+    REQUIRE(shift->data.immediate == true);
+    REQUIRE(shift->data.type == ShiftType::ROR);
+    REQUIRE(shift->data.operand == 22);
+
+    REQUIRE(alu->rd == 7);
+    REQUIRE(alu->rn == 14);
+    REQUIRE(alu->set == true);
+    REQUIRE(alu->opcode == OpCode::AND);
+
+    REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
+
+    shift->data.immediate = false;
+    shift->data.operand   = 2;
+    alu->set              = false;
+
+    REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
+
+    alu->operand = static_cast<uint32_t>(3300012);
+    REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
+
+    SECTION("set-only operations") {
+        alu->set = true;
+
+        alu->opcode = OpCode::TST;
+        REQUIRE(instruction.disassemble() == "TST R14,#3300012");
+
+        alu->opcode = OpCode::TEQ;
+        REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
+
+        alu->opcode = OpCode::CMP;
+        REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
+
+        alu->opcode = OpCode::CMN;
+        REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
+    }
+
+    SECTION("destination operations") {
+        alu->opcode = OpCode::EOR;
+        REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSB;
+        REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::ADC;
+        REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
+
+        alu->opcode = OpCode::SBC;
+        REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSC;
+        REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
+
+        alu->opcode = OpCode::ORR;
+        REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
+
+        alu->opcode = OpCode::MOV;
+        REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
+
+        alu->opcode = OpCode::BIC;
+        REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
+
+        alu->opcode = OpCode::MVN;
+        REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
+    }
+}
+
+TEST_CASE("Coprocessor Data Transfer", TAG) {
+    uint32_t raw = 0b10101101101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataTransfer* ldc = nullptr;
+
+    REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GE);
+
+    REQUIRE(ldc->offset == 70);
+    REQUIRE(ldc->cpn == 1);
+    REQUIRE(ldc->crd == 15);
+    REQUIRE(ldc->rn == 5);
+    REQUIRE(ldc->load == false);
+    REQUIRE(ldc->write == true);
+    REQUIRE(ldc->len == false);
+    REQUIRE(ldc->up == true);
+    REQUIRE(ldc->pre == true);
+
+    REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
+
+    ldc->load  = true;
+    ldc->pre   = false;
+    ldc->write = false;
+    ldc->len   = true;
+
+    REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
+}
+
+TEST_CASE("Coprocessor Operand Operation", TAG) {
+    uint32_t raw = 0b11101110101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataOperation* cdp = nullptr;
+
+    REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE(cdp->crm == 6);
+    REQUIRE(cdp->cp == 2);
+    REQUIRE(cdp->cpn == 1);
+    REQUIRE(cdp->crd == 15);
+    REQUIRE(cdp->crn == 5);
+    REQUIRE(cdp->cp_opc == 10);
+
+    REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
+}
+
+TEST_CASE("Coprocessor Register Transfer", TAG) {
+    uint32_t raw = 0b11101110101001011111000101010110;
+    Instruction instruction(raw);
+    CoprocessorRegisterTransfer* mrc = nullptr;
+
+    REQUIRE(
+      (mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE(mrc->crm == 6);
+    REQUIRE(mrc->cp == 2);
+    REQUIRE(mrc->cpn == 1);
+    REQUIRE(mrc->rd == 15);
+    REQUIRE(mrc->crn == 5);
+    REQUIRE(mrc->load == false);
+    REQUIRE(mrc->cp_opc == 5);
+
+    REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
+}
+
+TEST_CASE("Software Interrupt", TAG) {
+    uint32_t raw = 0b00001111101010101010101010101010;
+    Instruction instruction(raw);
+
+    REQUIRE(instruction.condition == Condition::EQ);
+    REQUIRE(instruction.disassemble() == "SWIEQ");
+}
+
+#undef TAG

tests/cpu/arm/meson.build

@@ -0,0 +1,4 @@
+tests_sources += files(
+  'instruction.cc',
+  'exec.cc'
+)

tests/cpu/instruction.cc

@@ -0,0 +1,467 @@
+#include "cpu/arm/instruction.hh"
+#include "cpu/utility.hh"
+#include <catch2/catch_test_macros.hpp>
+
+[[maybe_unused]] static constexpr auto TAG = "disassembler";
+
+using namespace arm;
+
+TEST_CASE("Branch and Exchange", TAG) {
+    uint32_t raw = 0b11000001001011111111111100011010;
+    Instruction instruction(raw);
+    BranchAndExchange* bx = nullptr;
+
+    REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GT);
+
+    REQUIRE(bx->rn == 10);
+
+    REQUIRE(instruction.disassemble() == "BXGT R10");
+}
+
+TEST_CASE("Branch", TAG) {
+    uint32_t raw = 0b11101011100001010111111111000011;
+    Instruction instruction(raw);
+    Branch* b = nullptr;
+
+    REQUIRE((b = std::get_if<Branch>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    // last 24 bits = 8748995
+    // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
+    // Also +8 since PC is two instructions ahead
+    REQUIRE(b->offset == 0xFE15FF14);
+    REQUIRE(b->link == true);
+
+    REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
+
+    b->link = false;
+    REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
+}
+
+TEST_CASE("Multiply", TAG) {
+    uint32_t raw = 0b00000000001110101110111110010000;
+    Instruction instruction(raw);
+    Multiply* mul = nullptr;
+
+    REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::EQ);
+
+    REQUIRE(mul->rm == 0);
+    REQUIRE(mul->rs == 15);
+    REQUIRE(mul->rn == 14);
+    REQUIRE(mul->rd == 10);
+    REQUIRE(mul->acc == true);
+    REQUIRE(mul->set == true);
+
+    REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
+
+    mul->acc = false;
+    mul->set = false;
+    REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
+}
+
+TEST_CASE("Multiply Long", TAG) {
+    uint32_t raw = 0b00010000100111100111011010010010;
+    Instruction instruction(raw);
+    MultiplyLong* mull = nullptr;
+
+    REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::NE);
+
+    REQUIRE(mull->rm == 2);
+    REQUIRE(mull->rs == 6);
+    REQUIRE(mull->rdlo == 7);
+    REQUIRE(mull->rdhi == 14);
+    REQUIRE(mull->acc == false);
+    REQUIRE(mull->set == true);
+    REQUIRE(mull->uns == false);
+
+    REQUIRE(instruction.disassemble() == "SMULLNES R7,R14,R2,R6");
+
+    mull->acc = true;
+    REQUIRE(instruction.disassemble() == "SMLALNES R7,R14,R2,R6");
+
+    mull->uns = true;
+    mull->set = false;
+    REQUIRE(instruction.disassemble() == "UMLALNE R7,R14,R2,R6");
+}
+
+TEST_CASE("Undefined", TAG) {
+    // notice how this is the same as single data transfer except the shift
+    // is now a register based shift
+    uint32_t raw = 0b11100111101000101010111100010110;
+    Instruction instruction(raw);
+
+    REQUIRE(instruction.condition == Condition::AL);
+    REQUIRE(instruction.disassemble() == "UND");
+}
+
+TEST_CASE("Single Data Swap", TAG) {
+    uint32_t raw = 0b10100001000010010101000010010110;
+    Instruction instruction(raw);
+    SingleDataSwap* swp = nullptr;
+
+    REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GE);
+
+    REQUIRE(swp->rm == 6);
+    REQUIRE(swp->rd == 5);
+    REQUIRE(swp->rn == 9);
+    REQUIRE(swp->byte == false);
+
+    REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
+
+    swp->byte = true;
+    REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
+}
+
+TEST_CASE("Single Data Transfer", TAG) {
+    uint32_t raw = 0b11100111101000101010111100000110;
+    Instruction instruction(raw);
+    SingleDataTransfer* ldr = nullptr;
+    Shift* shift            = nullptr;
+
+    REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
+    REQUIRE(shift->rm == 6);
+    REQUIRE(shift->data.immediate == true);
+    REQUIRE(shift->data.type == ShiftType::LSL);
+    REQUIRE(shift->data.operand == 30);
+    REQUIRE(ldr->rd == 10);
+    REQUIRE(ldr->rn == 2);
+    REQUIRE(ldr->load == false);
+    REQUIRE(ldr->write == true);
+    REQUIRE(ldr->byte == false);
+    REQUIRE(ldr->up == true);
+    REQUIRE(ldr->pre == true);
+
+    ldr->load        = true;
+    ldr->byte        = true;
+    ldr->write       = false;
+    shift->data.type = ShiftType::ROR;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
+
+    ldr->up  = false;
+    ldr->pre = false;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
+
+    ldr->offset = static_cast<uint16_t>(9023);
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
+
+    ldr->pre = true;
+    REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
+}
+
+TEST_CASE("Halfword Transfer", TAG) {
+    uint32_t raw = 0b00110001101011110010000010110110;
+    Instruction instruction(raw);
+    HalfwordTransfer* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::CC);
+
+    // offset is not immediate
+    REQUIRE(ldr->imm == 0);
+    // hence this offset is a register number (rm)
+    REQUIRE(ldr->offset == 6);
+    REQUIRE(ldr->half == true);
+    REQUIRE(ldr->sign == false);
+    REQUIRE(ldr->rd == 2);
+    REQUIRE(ldr->rn == 15);
+    REQUIRE(ldr->load == false);
+    REQUIRE(ldr->write == true);
+    REQUIRE(ldr->up == true);
+    REQUIRE(ldr->pre == true);
+
+    REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
+
+    ldr->pre  = false;
+    ldr->load = true;
+    ldr->sign = true;
+    ldr->up   = false;
+
+    REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
+
+    ldr->half = false;
+    REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
+
+    ldr->load = false;
+    // not a register anymore
+    ldr->imm    = 1;
+    ldr->offset = 90;
+    REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
+}
+
+TEST_CASE("Block Data Transfer", TAG) {
+    uint32_t raw = 0b10011001010101110100000101101101;
+    Instruction instruction(raw);
+    BlockDataTransfer* ldm = nullptr;
+
+    REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::LS);
+
+    {
+        uint16_t regs = 0;
+        regs |= 1 << 0;
+        regs |= 1 << 2;
+        regs |= 1 << 3;
+        regs |= 1 << 5;
+        regs |= 1 << 6;
+        regs |= 1 << 8;
+        regs |= 1 << 14;
+
+        REQUIRE(ldm->regs == regs);
+    }
+
+    REQUIRE(ldm->rn == 7);
+    REQUIRE(ldm->load == true);
+    REQUIRE(ldm->write == false);
+    REQUIRE(ldm->s == true);
+    REQUIRE(ldm->up == false);
+    REQUIRE(ldm->pre == true);
+
+    REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
+
+    ldm->write = true;
+    ldm->s     = false;
+    ldm->up    = true;
+
+    REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
+
+    ldm->regs &= ~(1 << 6);
+    ldm->regs &= ~(1 << 3);
+    ldm->regs &= ~(1 << 8);
+    ldm->load = false;
+    ldm->pre  = false;
+
+    REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
+}
+
+TEST_CASE("PSR Transfer", TAG) {
+    PsrTransfer* msr = nullptr;
+
+    SECTION("MRS") {
+        uint32_t raw = 0b01000001010011111010000000000000;
+        Instruction instruction(raw);
+        PsrTransfer* mrs = nullptr;
+
+        REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::MI);
+
+        REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
+        // Operand is a register in the case of MRS (PSR -> Register)
+        REQUIRE(mrs->operand == 10);
+        REQUIRE(mrs->spsr == true);
+
+        REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
+    }
+
+    SECTION("MSR") {
+        uint32_t raw = 0b11100001001010011111000000001000;
+        Instruction instruction(raw);
+        PsrTransfer* msr = nullptr;
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::AL);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr);
+        // Operand is a register in the case of MSR (Register -> PSR)
+        REQUIRE(msr->operand == 8);
+        REQUIRE(msr->spsr == false);
+
+        REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
+    }
+
+    SECTION("MSR_flg with register operand") {
+        uint32_t raw = 0b01100001001010001111000000001000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::VS);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->imm == 0);
+        REQUIRE(msr->operand == 8);
+        REQUIRE(msr->spsr == false);
+
+        REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
+    }
+
+    SECTION("MSR_flg with immediate operand") {
+        uint32_t raw = 0b11100011011010001111011101101000;
+        Instruction instruction(raw);
+
+        REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
+        REQUIRE(instruction.condition == Condition::AL);
+
+        REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
+        REQUIRE(msr->imm == 1);
+
+        // 104 (32 bits) rotated by 2 * 7
+        REQUIRE(msr->operand == 27262976);
+        REQUIRE(msr->spsr == true);
+
+        REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
+    }
+}
+
+TEST_CASE("Data Processing", TAG) {
+    uint32_t raw = 0b11100010000111100111101101100001;
+    Instruction instruction(raw);
+    DataProcessing* alu = nullptr;
+    Shift* shift        = nullptr;
+
+    REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    // operand 2 is a shifted register
+    REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
+    REQUIRE(shift->rm == 1);
+    REQUIRE(shift->data.immediate == true);
+    REQUIRE(shift->data.type == ShiftType::ROR);
+    REQUIRE(shift->data.operand == 22);
+
+    REQUIRE(alu->rd == 7);
+    REQUIRE(alu->rn == 14);
+    REQUIRE(alu->set == true);
+    REQUIRE(alu->opcode == OpCode::AND);
+
+    REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
+
+    shift->data.immediate = false;
+    shift->data.operand   = 2;
+    alu->set              = false;
+
+    REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
+
+    alu->operand = static_cast<uint32_t>(3300012);
+    REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
+
+    SECTION("set-only operations") {
+        alu->set = true;
+
+        alu->opcode = OpCode::TST;
+        REQUIRE(instruction.disassemble() == "TST R14,#3300012");
+
+        alu->opcode = OpCode::TEQ;
+        REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
+
+        alu->opcode = OpCode::CMP;
+        REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
+
+        alu->opcode = OpCode::CMN;
+        REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
+    }
+
+    SECTION("destination operations") {
+        alu->opcode = OpCode::EOR;
+        REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSB;
+        REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
+
+        alu->opcode = OpCode::SUB;
+        REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
+
+        alu->opcode = OpCode::ADC;
+        REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
+
+        alu->opcode = OpCode::SBC;
+        REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
+
+        alu->opcode = OpCode::RSC;
+        REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
+
+        alu->opcode = OpCode::ORR;
+        REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
+
+        alu->opcode = OpCode::MOV;
+        REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
+
+        alu->opcode = OpCode::BIC;
+        REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
+
+        alu->opcode = OpCode::MVN;
+        REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
+    }
+}
+
+TEST_CASE("Coprocessor Data Transfer", TAG) {
+    uint32_t raw = 0b10101101101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataTransfer* ldc = nullptr;
+
+    REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::GE);
+
+    REQUIRE(ldc->offset == 70);
+    REQUIRE(ldc->cpn == 1);
+    REQUIRE(ldc->crd == 15);
+    REQUIRE(ldc->rn == 5);
+    REQUIRE(ldc->load == false);
+    REQUIRE(ldc->write == true);
+    REQUIRE(ldc->len == false);
+    REQUIRE(ldc->up == true);
+    REQUIRE(ldc->pre == true);
+
+    REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
+
+    ldc->load  = true;
+    ldc->pre   = false;
+    ldc->write = false;
+    ldc->len   = true;
+
+    REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
+}
+
+TEST_CASE("Coprocessor Operand Operation", TAG) {
+    uint32_t raw = 0b11101110101001011111000101000110;
+    Instruction instruction(raw);
+    CoprocessorDataOperation* cdp = nullptr;
+
+    REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE(cdp->crm == 6);
+    REQUIRE(cdp->cp == 2);
+    REQUIRE(cdp->cpn == 1);
+    REQUIRE(cdp->crd == 15);
+    REQUIRE(cdp->crn == 5);
+    REQUIRE(cdp->cp_opc == 10);
+
+    REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
+}
+
+TEST_CASE("Coprocessor Register Transfer", TAG) {
+    uint32_t raw = 0b11101110101001011111000101010110;
+    Instruction instruction(raw);
+    CoprocessorRegisterTransfer* mrc = nullptr;
+
+    REQUIRE(
+      (mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
+    REQUIRE(instruction.condition == Condition::AL);
+
+    REQUIRE(mrc->crm == 6);
+    REQUIRE(mrc->cp == 2);
+    REQUIRE(mrc->cpn == 1);
+    REQUIRE(mrc->rd == 15);
+    REQUIRE(mrc->crn == 5);
+    REQUIRE(mrc->load == false);
+    REQUIRE(mrc->cp_opc == 5);
+
+    REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
+}
+
+TEST_CASE("Software Interrupt", TAG) {
+    uint32_t raw = 0b00001111101010101010101010101010;
+    Instruction instruction(raw);
+
+    REQUIRE(instruction.condition == Condition::EQ);
+    REQUIRE(instruction.disassemble() == "SWIEQ");
+}

tests/cpu/meson.build

@@ -0,0 +1 @@
+subdir('arm')

tests/meson.build

@@ -0,0 +1,19 @@
+tests_deps = [
+  lib
+]
+
+tests_sources = files()
+
+subdir('cpu')
+
+catch2 = dependency('catch2-with-main', version: '>=3.4.0', static: true)
+catch2_tests = executable(
+  meson.project_name() + '_tests',
+  tests_sources,
+  dependencies: catch2,
+  link_with: tests_deps,
+  include_directories: inc,
+  build_by_default: false
+)
+
+test('catch2 tests', catch2_tests)