1e8966553f
chore: enclose everything in namespace matar
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-21 10:52:40 +05:30
fa96a4d09f
tests: add execution tests
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all but data processing
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-18 18:23:52 +05:30
dd9dd5f116
tests: complete disassembler tests
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-17 09:50:32 +05:30
be7deb349a
tests: [WIP] add unit tests for some of the instructions
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-15 14:07:23 +05:30
7fc6876264
[UNTESTED] complete initial disassembler structure for ARM
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-15 05:23:07 +05:30
169723275e
replace symlinks
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 11:25:44 +05:30
81afd67e0b
delete symlinks
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 11:14:36 +05:30
0b674c7c64
[UNTESTED] refactor how instructions are parsed
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 10:16:03 +05:30
3cf5cbd024
refactor: make linter happy
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also add a few unused coprocessor instructions
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 01:19:41 +05:30
8a04eade92
add a basic structure for disassembler + executor
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Instructions added
Branch and Exchange (BX)
Branch and Link (B)
Multiply and Accumulate (MUL, MLA)
Multiply Long and Accumulate (SMULL, SMLAL, UMULL, UMLAL)
Single data swap (SWP)
[WIP] Halfword Transfer (STRH, LDRH)
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-13 03:44:36 +05:30
