08060a767f
cpu (feat): store three opcodes instead of one
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-14 20:27:13 +05:30
bafd534671
bus: send a weak ptr to io
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-14 20:25:36 +05:30
d1df555a6a
fix gcc build
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-14 05:48:13 +05:30
9397140473
get rid of memory.cc/.hh
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also fix bus' shared pointer in cpu
TODO: put cpu in bus not the other way around
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-14 05:42:09 +05:30
ffcdf5f3a7
ci: fix by bumping actions
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-13 04:01:24 +05:30
08cc582f23
io: i really ought to be working on the ppu and apu by now
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-13 03:53:25 +05:30
933b622493
io(placeholder): add naive io structure
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 23:30:22 +05:30
8b80f818c6
cpu/psr(chore): minor change
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 23:29:05 +05:30
f34efb183f
cpu: fix changing modes
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 23:26:02 +05:30
15c4802838
cpu/{arm|thumb}(chore): change how branch disassembly happens
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 23:21:39 +05:30
0062ad424b
chore: stage bunch of size_t to uint32_t
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 22:58:09 +05:30
028c80f6cb
comeback(?)
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 22:46:48 +05:30
e0f7f32699
refactor: reorganize everything
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-10-04 01:41:38 +05:30
9cdfa90acc
memory: remove unused functions
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-23 21:58:41 +05:30
91a82eec7c
log: encapsulate logger
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-23 21:09:44 +05:30
1e8966553f
chore: enclose everything in namespace matar
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-21 10:52:40 +05:30
fa96a4d09f
tests: add execution tests
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all but data processing
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-18 18:23:52 +05:30
dd9dd5f116
tests: complete disassembler tests
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-17 09:50:32 +05:30
be7deb349a
tests: [WIP] add unit tests for some of the instructions
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-15 14:07:23 +05:30
7fc6876264
[UNTESTED] complete initial disassembler structure for ARM
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-15 05:23:07 +05:30
169723275e
replace symlinks
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 11:25:44 +05:30
81afd67e0b
delete symlinks
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 11:14:36 +05:30
0b674c7c64
[UNTESTED] refactor how instructions are parsed
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 10:16:03 +05:30
3cf5cbd024
refactor: make linter happy
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also add a few unused coprocessor instructions
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 01:19:41 +05:30
8a04eade92
add a basic structure for disassembler + executor
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Instructions added
Branch and Exchange (BX)
Branch and Link (B)
Multiply and Accumulate (MUL, MLA)
Multiply Long and Accumulate (SMULL, SMLAL, UMULL, UMLAL)
Single data swap (SWP)
[WIP] Halfword Transfer (STRH, LDRH)
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-13 03:44:36 +05:30
332f0b87d6
initialise a memory structure or smth
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-11 10:53:32 +05:30
84c68a4e00
initial cpu structure :thonk:
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-08-27 21:43:09 +05:30
fe255f97f4
initial commit: set up a template
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-08-15 14:59:53 +05:30
