08060a767f
cpu (feat): store three opcodes instead of one
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-14 20:27:13 +05:30
8b80f818c6
cpu/psr(chore): minor change
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 23:29:05 +05:30
028c80f6cb
comeback(?)
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2024-06-11 22:46:48 +05:30
e0f7f32699
refactor: reorganize everything
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-10-04 01:41:38 +05:30
fa96a4d09f
tests: add execution tests
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all but data processing
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-18 18:23:52 +05:30
7fc6876264
[UNTESTED] complete initial disassembler structure for ARM
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-15 05:23:07 +05:30
169723275e
replace symlinks
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 11:25:44 +05:30
81afd67e0b
delete symlinks
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Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-14 11:14:36 +05:30
8a04eade92
add a basic structure for disassembler + executor
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Instructions added
Branch and Exchange (BX)
Branch and Link (B)
Multiply and Accumulate (MUL, MLA)
Multiply Long and Accumulate (SMULL, SMLAL, UMULL, UMLAL)
Single data swap (SWP)
[WIP] Halfword Transfer (STRH, LDRH)
Signed-off-by: Amneesh Singh <natto@weirdnatto.in >
2023-09-13 03:44:36 +05:30
