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tests: add execution tests

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all but data processing

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2023-09-18 18:23:52 +05:30
parent dd9dd5f116
commit fa96a4d09f
31 changed files with 2076 additions and 1265 deletions
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736
tests/cpu/arm/exec.cc Normal file
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#include "cpu/cpu-impl.hh"
#include "cpu/utility.hh"
#include "util/bits.hh"
#include <catch2/catch_test_macros.hpp>
#include <variant>
class CpuFixture {
public:
CpuFixture()
: cpu(Bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
std::vector<uint8_t>(Header::HEADER_SIZE)))) {}
protected:
void exec(arm::InstructionData data, Condition condition = Condition::AL) {
arm::Instruction instruction(condition, data);
cpu.exec_arm(instruction);
}
void reset(uint32_t value = 0) {
cpu.pc = value + arm::INSTRUCTION_SIZE * 2;
}
CpuImpl cpu;
};
#define TAG "arm execution"
using namespace arm;
TEST_CASE_METHOD(CpuFixture, "Branch and Exchange", TAG) {
InstructionData data = BranchAndExchange{ .rn = 3 };
cpu.gpr[3] = 342890;
exec(data);
CHECK(cpu.pc == 342890);
}
TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
InstructionData data = Branch{ .link = false, .offset = 3489748 };
Branch* branch = std::get_if<Branch>(&data);
exec(data);
CHECK(cpu.pc == 3489748);
CHECK(cpu.gpr[14] == 0);
// with link
reset();
branch->link = true;
exec(data);
CHECK(cpu.pc == 3489748);
CHECK(cpu.gpr[14] == 0 + INSTRUCTION_SIZE);
}
TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
InstructionData data = Multiply{
.rm = 10, .rs = 11, .rn = 3, .rd = 5, .set = false, .acc = false
};
Multiply* multiply = std::get_if<Multiply>(&data);
cpu.gpr[10] = 234912349;
cpu.gpr[11] = 124897;
cpu.gpr[3] = 99999;
{
uint32_t result = 234912349ull * 124897ull & 0xFFFFFFFF;
exec(data);
CHECK(cpu.gpr[5] == result);
}
// with accumulate
{
uint32_t result = 234912349ull * 124897ull + 99999ull & 0xFFFFFFFF;
multiply->acc = true;
exec(data);
CHECK(cpu.gpr[5] == result);
}
// with set
{
uint32_t result = 234912349ull * 124897ull + 99999ull & 0xFFFFFFFF;
multiply->set = true;
exec(data);
CHECK(cpu.gpr[5] == result);
CHECK(cpu.cpsr.n() == get_bit(result, 31));
}
// with set and zero
{
cpu.gpr[10] = 0;
cpu.gpr[3] = 0;
exec(data);
CHECK(cpu.gpr[5] == 0);
CHECK(cpu.cpsr.n() == false);
CHECK(cpu.cpsr.z() == true);
}
}
TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
InstructionData data = MultiplyLong{ .rm = 10,
.rs = 11,
.rdlo = 3,
.rdhi = 5,
.set = false,
.acc = false,
.uns = true };
MultiplyLong* multiply_long = std::get_if<MultiplyLong>(&data);
cpu.gpr[10] = 234912349;
cpu.gpr[11] = 124897;
// unsigned
{
uint64_t result = 234912349ull * 124897ull;
exec(data);
CHECK(cpu.gpr[3] == bit_range(result, 0, 31));
CHECK(cpu.gpr[5] == bit_range(result, 32, 63));
}
// signed
{
int64_t result = 234912349ll * -124897ll;
cpu.gpr[11] *= -1;
multiply_long->uns = false;
exec(data);
CHECK(cpu.gpr[3] == static_cast<uint32_t>(bit_range(result, 0, 31)));
CHECK(cpu.gpr[5] == static_cast<uint32_t>(bit_range(result, 32, 63)));
}
// accumulate
{
cpu.gpr[3] = 99999;
cpu.gpr[5] = -444333391;
int64_t result =
234912349ll * -124897ll + (99999ll | -444333391ll << 32);
multiply_long->acc = true;
exec(data);
CHECK(cpu.gpr[3] == static_cast<uint32_t>(bit_range(result, 0, 31)));
CHECK(cpu.gpr[5] == static_cast<uint32_t>(bit_range(result, 32, 63)));
}
// set
{
cpu.gpr[3] = 99999;
cpu.gpr[5] = -444333391;
int64_t result =
234912349ll * -124897ll + (99999ll | -444333391ll << 32);
multiply_long->set = true;
exec(data);
CHECK(cpu.gpr[3] == static_cast<uint32_t>(bit_range(result, 0, 31)));
CHECK(cpu.gpr[5] == static_cast<uint32_t>(bit_range(result, 32, 63)));
CHECK(cpu.cpsr.n() == true);
CHECK(cpu.cpsr.z() == false);
}
// zero
{
cpu.gpr[10] = 0;
cpu.gpr[5] = 0;
cpu.gpr[3] = 0;
exec(data);
CHECK(cpu.gpr[3] == 0);
CHECK(cpu.gpr[5] == 0);
CHECK(cpu.cpsr.n() == false);
CHECK(cpu.cpsr.z() == true);
}
}
TEST_CASE_METHOD(CpuFixture, "Single Data Swap", TAG) {
InstructionData data =
SingleDataSwap{ .rm = 3, .rd = 4, .rn = 9, .byte = false };
SingleDataSwap* swap = std::get_if<SingleDataSwap>(&data);
cpu.gpr[9] = 0x3FED;
cpu.gpr[3] = 94235087;
cpu.gpr[3] = -259039045;
cpu.bus->write_word(cpu.gpr[9], 3241011111);
SECTION("word") {
exec(data);
CHECK(cpu.gpr[4] == 3241011111);
CHECK(cpu.bus->read_word(cpu.gpr[9]) ==
static_cast<uint32_t>(-259039045));
}
SECTION("byte") {
swap->byte = true;
exec(data);
CHECK(cpu.gpr[4] == (3241011111 & 0xFF));
CHECK(cpu.bus->read_byte(cpu.gpr[9]) ==
static_cast<uint8_t>(-259039045 & 0xFF));
}
}
TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
InstructionData data =
SingleDataTransfer{ .offset = Shift{ .rm = 3,
.data =
ShiftData{
.type = ShiftType::ROR,
.immediate = true,
.operand = 29,
} },
.rd = 5,
.rn = 7,
.load = true,
.write = false,
.byte = false,
.up = true,
.pre = true };
SingleDataTransfer* data_transfer = std::get_if<SingleDataTransfer>(&data);
cpu.gpr[3] = 1596;
cpu.gpr[12] = 3;
cpu.gpr[7] = 6;
cpu.gpr[5] = -911111;
// shifted register (immediate)
{
cpu.bus->write_word(12774, 95995);
exec(data);
CHECK(cpu.gpr[5] == 95995);
}
// shifted register (register)
{
data_transfer->offset = Shift{ .rm = 3,
.data = ShiftData{
.type = ShiftType::LSL,
.immediate = false,
.operand = 12,
} };
cpu.bus->write_word(12774, 3948123487);
exec(data);
CHECK(cpu.gpr[5] == 3948123487);
}
// immediate
{
data_transfer->offset = static_cast<uint16_t>(3489);
// 6 + 3489
cpu.bus->write_word(3495, 68795467);
exec(data);
CHECK(cpu.gpr[5] == 68795467);
}
// down
{
cpu.gpr[7] = 18044;
data_transfer->up = false;
// 18044 - 3489
cpu.bus->write_word(14555, 5949595);
exec(data);
CHECK(cpu.gpr[5] == 5949595);
// no write back
CHECK(cpu.gpr[7] == 18044);
}
// write
{
data_transfer->write = true;
cpu.bus->write_word(14555, 967844);
exec(data);
CHECK(cpu.gpr[5] == 967844);
// 18044 - 3489
CHECK(cpu.gpr[7] == 14555);
}
// post
{
data_transfer->write = false;
data_transfer->pre = false;
cpu.bus->write_word(14555, 61119);
exec(data);
CHECK(cpu.gpr[5] == 61119);
// 14555 - 3489
CHECK(cpu.gpr[7] == 11066);
}
// store
{
data_transfer->load = false;
exec(data);
CHECK(cpu.bus->read_word(11066) == 61119);
// 11066 - 3489
CHECK(cpu.gpr[7] == 7577);
}
// r15 as rn
{
data_transfer->rn = 15;
cpu.gpr[15] = 7577;
exec(data);
CHECK(cpu.bus->read_word(7577 - 2 * INSTRUCTION_SIZE) == 61119);
// 7577 - 3489
CHECK(cpu.gpr[15] == 4088 - 2 * INSTRUCTION_SIZE);
// cleanup
data_transfer->rn = 7;
}
// r15 as rd
{
// 4088
data_transfer->rd = 15;
cpu.gpr[15] = 444444;
exec(data);
CHECK(cpu.bus->read_word(7577 + INSTRUCTION_SIZE) == 444444);
// 7577 - 3489
CHECK(cpu.gpr[7] == 4088 + INSTRUCTION_SIZE);
// cleanup
data_transfer->rd = 5;
cpu.gpr[7] -= INSTRUCTION_SIZE;
}
// byte
{
data_transfer->byte = true;
cpu.gpr[5] = 458267584;
exec(data);
CHECK(cpu.bus->read_word(4088) == (458267584 & 0xFF));
// 4088 - 3489
CHECK(cpu.gpr[7] == 599);
}
}
TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
InstructionData data = HalfwordTransfer{ .offset = 12,
.half = true,
.sign = false,
.rd = 11,
.rn = 10,
.load = true,
.write = false,
.imm = false,
.up = true,
.pre = true };
HalfwordTransfer* hw_transfer = std::get_if<HalfwordTransfer>(&data);
cpu.gpr[12] = 8404;
cpu.gpr[11] = 459058287;
cpu.gpr[10] = 900;
// register offset
{
// 900 + 8404
cpu.bus->write_word(9304, 3948123487);
exec(data);
CHECK(cpu.gpr[11] == (3948123487 & 0xFFFF));
}
// immediate offset
{
hw_transfer->imm = true;
hw_transfer->offset = 167;
// 900 + 167
cpu.bus->write_word(1067, 594633302);
exec(data);
CHECK(cpu.gpr[11] == (594633302 & 0xFFFF));
}
// down
{
hw_transfer->up = false;
// 900 - 167
cpu.bus->write_word(733, 222221);
exec(data);
CHECK(cpu.gpr[11] == (222221 & 0xFFFF));
// no write back
CHECK(cpu.gpr[10] == 900);
}
// write
{
hw_transfer->write = true;
// 900 - 167
cpu.bus->write_word(733, 100000005);
exec(data);
CHECK(cpu.gpr[11] == (100000005 & 0xFFFF));
// 900 - 167
CHECK(cpu.gpr[10] == 733);
}
// post
{
hw_transfer->pre = false;
hw_transfer->write = false;
cpu.bus->write_word(733, 6111909);
exec(data);
CHECK(cpu.gpr[11] == (6111909 & 0xFFFF));
// 733 - 167
CHECK(cpu.gpr[10] == 566);
}
// store
{
hw_transfer->load = false;
exec(data);
CHECK(cpu.bus->read_halfword(566) == (6111909 & 0xFFFF));
// 566 - 167
CHECK(cpu.gpr[10] == 399);
}
// r15 as rn
{
hw_transfer->rn = 15;
cpu.gpr[15] = 399;
exec(data);
CHECK(cpu.bus->read_halfword(399 - 2 * INSTRUCTION_SIZE) ==
(6111909 & 0xFFFF));
// 399 - 167
CHECK(cpu.gpr[15] == 232 - 2 * INSTRUCTION_SIZE);
// cleanup
hw_transfer->rn = 10;
}
// r15 as rd
{
hw_transfer->rd = 15;
cpu.gpr[15] = 224;
exec(data);
CHECK(cpu.bus->read_halfword(399 + INSTRUCTION_SIZE) == 224);
// 399 - 167
CHECK(cpu.gpr[10] == 232 + INSTRUCTION_SIZE);
// cleanup
hw_transfer->rd = 11;
cpu.gpr[10] = 399;
}
// signed halfword
{
hw_transfer->load = true;
hw_transfer->sign = true;
cpu.bus->write_halfword(399, -12345);
exec(data);
CHECK(cpu.gpr[11] == static_cast<uint32_t>(-12345));
// 399 - 167
CHECK(cpu.gpr[10] == 232);
}
// signed byte
{
hw_transfer->half = false;
cpu.bus->write_byte(232, -56);
exec(data);
CHECK(cpu.gpr[11] == static_cast<uint32_t>(-56));
// 232 - 167
CHECK(cpu.gpr[10] == 65);
}
}
TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
InstructionData data = BlockDataTransfer{ .regs = 0b1010100111000001,
.rn = 10,
.load = true,
.write = false,
.s = false,
.up = true,
.pre = true };
BlockDataTransfer* block_transfer = std::get_if<BlockDataTransfer>(&data);
// load
SECTION("load") {
// populate memory
cpu.bus->write_word(3448, 38947234);
cpu.bus->write_word(3452, 237164);
cpu.bus->write_word(3456, 679785111);
cpu.bus->write_word(3460, 905895898);
cpu.bus->write_word(3464, 131313333);
cpu.bus->write_word(3468, 131);
cpu.bus->write_word(3472, 989231);
cpu.bus->write_word(3476, 6);
auto checker = [](decltype(cpu.gpr)& gpr, uint32_t rnval = 0) {
CHECK(gpr[0] == 237164);
CHECK(gpr[1] == 0);
CHECK(gpr[2] == 0);
CHECK(gpr[3] == 0);
CHECK(gpr[4] == 0);
CHECK(gpr[5] == 0);
CHECK(gpr[6] == 679785111);
CHECK(gpr[7] == 905895898);
CHECK(gpr[8] == 131313333);
CHECK(gpr[9] == 0);
CHECK(gpr[10] == rnval);
CHECK(gpr[11] == 131);
CHECK(gpr[12] == 0);
CHECK(gpr[13] == 989231);
CHECK(gpr[14] == 0);
CHECK(gpr[15] == 6);
for (uint8_t i = 0; i < 16; i++) {
gpr[i] = 0;
}
};
cpu.gpr[10] = 3448;
exec(data);
checker(cpu.gpr, 3448);
// with write
cpu.gpr[10] = 3448;
block_transfer->write = true;
exec(data);
checker(cpu.gpr, 3448 + INSTRUCTION_SIZE);
// decrement
block_transfer->write = false;
block_transfer->up = false;
// adjust rn
cpu.gpr[10] = 3480;
exec(data);
checker(cpu.gpr, 3480);
// with write
cpu.gpr[10] = 3480;
block_transfer->write = true;
exec(data);
checker(cpu.gpr, 3480 - INSTRUCTION_SIZE);
// post increment
block_transfer->write = false;
block_transfer->up = true;
block_transfer->pre = false;
// adjust rn
cpu.gpr[10] = 3452;
exec(data);
checker(cpu.gpr, 3452 + INSTRUCTION_SIZE);
// post decrement
block_transfer->up = false;
// adjust rn
cpu.gpr[10] = 3476;
exec(data);
checker(cpu.gpr, 3476 - INSTRUCTION_SIZE);
// with s bit
cpu.chg_mode(Mode::Fiq);
block_transfer->s = true;
CHECK(cpu.cpsr.raw() != cpu.spsr.raw());
exec(data);
CHECK(cpu.cpsr.raw() == cpu.spsr.raw());
}
// store
SECTION("store") {
block_transfer->load = false;
// populate registers
cpu.gpr[0] = 237164;
cpu.gpr[6] = 679785111;
cpu.gpr[7] = 905895898;
cpu.gpr[8] = 131313333;
cpu.gpr[11] = 131;
cpu.gpr[13] = 989231;
cpu.gpr[15] = 6;
auto checker = [this]() {
CHECK(cpu.bus->read_word(5548) == 237164);
CHECK(cpu.bus->read_word(5552) == 679785111);
CHECK(cpu.bus->read_word(5556) == 905895898);
CHECK(cpu.bus->read_word(5560) == 131313333);
CHECK(cpu.bus->read_word(5564) == 131);
CHECK(cpu.bus->read_word(5568) == 989231);
CHECK(cpu.bus->read_word(5572) == 6);
for (uint8_t i = 0; i < 8; i++)
cpu.bus->write_word(5548 + i * 4, 0);
};
cpu.gpr[10] = 5544; // base
exec(data);
checker();
// decrement
block_transfer->write = false;
block_transfer->up = false;
// adjust rn
cpu.gpr[10] = 5576;
exec(data);
checker();
// post increment
block_transfer->up = true;
block_transfer->pre = false;
// adjust rn
cpu.gpr[10] = 5548;
exec(data);
checker();
// post decrement
block_transfer->up = false;
// adjust rn
cpu.gpr[10] = 5572;
exec(data);
checker();
// with s bit
cpu.chg_mode(Mode::Fiq);
block_transfer->s = true;
cpu.chg_mode(Mode::Supervisor);
// User's R13 is different (unset at this point)
CHECK(cpu.bus->read_word(5568) == 0);
exec(data);
}
}
TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
InstructionData data = PsrTransfer{
.operand = 12,
.spsr = false,
.type = PsrTransfer::Type::Mrs,
.imm = false,
};
PsrTransfer* psr_transfer = std::get_if<PsrTransfer>(&data);
SECTION("MRS") {
cpu.gpr[12] = 12389398;
CHECK(cpu.cpsr.raw() != cpu.gpr[12]);
exec(data);
CHECK(cpu.cpsr.raw() == cpu.gpr[12]);
psr_transfer->spsr = true;
// with SPSR
CHECK(cpu.spsr.raw() != cpu.gpr[12]);
exec(data);
CHECK(cpu.spsr.raw() == cpu.gpr[12]);
}
// MSR
SECTION("MSR") {
psr_transfer->type = PsrTransfer::Type::Msr;
cpu.gpr[12] = 0;
// go to the reserved bits
cpu.gpr[12] |= 16556 << 8;
CHECK(cpu.cpsr.raw() != cpu.gpr[12]);
exec(data);
CHECK(cpu.cpsr.raw() == cpu.gpr[12]);
psr_transfer->spsr = true;
// with SPSR
CHECK(cpu.spsr.raw() != cpu.gpr[12]);
exec(data);
CHECK(cpu.spsr.raw() == cpu.gpr[12]);
}
// MSR_flg
SECTION("MSR_flg") {
psr_transfer->type = PsrTransfer::Type::Msr_flg;
cpu.gpr[12] = 1490352945;
// go to the reserved bits
exec(data);
CHECK(cpu.cpsr.n() == get_bit(1490352945, 31));
CHECK(cpu.cpsr.z() == get_bit(1490352945, 30));
CHECK(cpu.cpsr.c() == get_bit(1490352945, 29));
CHECK(cpu.cpsr.v() == get_bit(1490352945, 28));
// with SPSR and immediate operand
psr_transfer->operand = 99333394;
psr_transfer->imm = true;
psr_transfer->spsr = true;
exec(data);
CHECK(cpu.spsr.n() == get_bit(9933394, 31));
CHECK(cpu.spsr.z() == get_bit(9933394, 30));
CHECK(cpu.spsr.c() == get_bit(9933394, 29));
CHECK(cpu.spsr.v() == get_bit(9933394, 28));
}
}
#undef TAG

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tests/cpu/arm/instruction.cc Normal file
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#include "cpu/arm/instruction.hh"
#include "cpu/utility.hh"
#include <catch2/catch_test_macros.hpp>
#define TAG "disassembler"
using namespace arm;
TEST_CASE("Branch and Exchange", TAG) {
uint32_t raw = 0b11000001001011111111111100011010;
Instruction instruction(raw);
BranchAndExchange* bx = nullptr;
REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
CHECK(instruction.condition == Condition::GT);
CHECK(bx->rn == 10);
CHECK(instruction.disassemble() == "BXGT R10");
}
TEST_CASE("Branch", TAG) {
uint32_t raw = 0b11101011100001010111111111000011;
Instruction instruction(raw);
Branch* b = nullptr;
REQUIRE((b = std::get_if<Branch>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
// last 24 bits = 8748995
// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
// Also +8 since PC is two instructions ahead
CHECK(b->offset == 0xFE15FF14);
CHECK(b->link == true);
CHECK(instruction.disassemble() == "BL 0xFE15FF14");
b->link = false;
CHECK(instruction.disassemble() == "B 0xFE15FF14");
}
TEST_CASE("Multiply", TAG) {
uint32_t raw = 0b00000000001110101110111110010000;
Instruction instruction(raw);
Multiply* mul = nullptr;
REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
CHECK(instruction.condition == Condition::EQ);
CHECK(mul->rm == 0);
CHECK(mul->rs == 15);
CHECK(mul->rn == 14);
CHECK(mul->rd == 10);
CHECK(mul->acc == true);
CHECK(mul->set == true);
CHECK(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
mul->acc = false;
mul->set = false;
CHECK(instruction.disassemble() == "MULEQ R10,R0,R15");
}
TEST_CASE("Multiply Long", TAG) {
uint32_t raw = 0b00010000100111100111011010010010;
Instruction instruction(raw);
MultiplyLong* mull = nullptr;
REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
CHECK(instruction.condition == Condition::NE);
CHECK(mull->rm == 2);
CHECK(mull->rs == 6);
CHECK(mull->rdlo == 7);
CHECK(mull->rdhi == 14);
CHECK(mull->acc == false);
CHECK(mull->set == true);
CHECK(mull->uns == true);
CHECK(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
mull->acc = true;
CHECK(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
mull->uns = false;
mull->set = false;
CHECK(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
}
TEST_CASE("Undefined", TAG) {
// notice how this is the same as single data transfer except the shift
// is now a register based shift
uint32_t raw = 0b11100111101000101010111100010110;
Instruction instruction(raw);
CHECK(instruction.condition == Condition::AL);
CHECK(instruction.disassemble() == "UND");
}
TEST_CASE("Single Data Swap", TAG) {
uint32_t raw = 0b10100001000010010101000010010110;
Instruction instruction(raw);
SingleDataSwap* swp = nullptr;
REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
CHECK(instruction.condition == Condition::GE);
CHECK(swp->rm == 6);
CHECK(swp->rd == 5);
CHECK(swp->rn == 9);
CHECK(swp->byte == false);
CHECK(instruction.disassemble() == "SWPGE R5,R6,[R9]");
swp->byte = true;
CHECK(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
}
TEST_CASE("Single Data Transfer", TAG) {
uint32_t raw = 0b11100111101000101010111100000110;
Instruction instruction(raw);
SingleDataTransfer* ldr = nullptr;
Shift* shift = nullptr;
REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
CHECK(shift->rm == 6);
CHECK(shift->data.immediate == true);
CHECK(shift->data.type == ShiftType::LSL);
CHECK(shift->data.operand == 30);
CHECK(ldr->rd == 10);
CHECK(ldr->rn == 2);
CHECK(ldr->load == false);
CHECK(ldr->write == true);
CHECK(ldr->byte == false);
CHECK(ldr->up == true);
CHECK(ldr->pre == true);
ldr->load = true;
ldr->byte = true;
ldr->write = false;
shift->data.type = ShiftType::ROR;
CHECK(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
ldr->up = false;
ldr->pre = false;
CHECK(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
ldr->offset = static_cast<uint16_t>(9023);
CHECK(instruction.disassemble() == "LDRB R10,[R2],-#9023");
ldr->pre = true;
CHECK(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
}
TEST_CASE("Halfword Transfer", TAG) {
uint32_t raw = 0b00110001101011110010000010110110;
Instruction instruction(raw);
HalfwordTransfer* ldr = nullptr;
REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::CC);
// offset is not immediate
CHECK(ldr->imm == 0);
// hence this offset is a register number (rm)
CHECK(ldr->offset == 6);
CHECK(ldr->half == true);
CHECK(ldr->sign == false);
CHECK(ldr->rd == 2);
CHECK(ldr->rn == 15);
CHECK(ldr->load == false);
CHECK(ldr->write == true);
CHECK(ldr->up == true);
CHECK(ldr->pre == true);
CHECK(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
ldr->pre = false;
ldr->load = true;
ldr->sign = true;
ldr->up = false;
CHECK(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
ldr->half = false;
CHECK(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
ldr->load = false;
// not a register anymore
ldr->imm = 1;
ldr->offset = 90;
CHECK(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
}
TEST_CASE("Block Data Transfer", TAG) {
uint32_t raw = 0b10011001010101110100000101101101;
Instruction instruction(raw);
BlockDataTransfer* ldm = nullptr;
REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::LS);
{
uint16_t regs = 0;
regs |= 1 << 0;
regs |= 1 << 2;
regs |= 1 << 3;
regs |= 1 << 5;
regs |= 1 << 6;
regs |= 1 << 8;
regs |= 1 << 14;
CHECK(ldm->regs == regs);
}
CHECK(ldm->rn == 7);
CHECK(ldm->load == true);
CHECK(ldm->write == false);
CHECK(ldm->s == true);
CHECK(ldm->up == false);
CHECK(ldm->pre == true);
CHECK(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
ldm->write = true;
ldm->s = false;
ldm->up = true;
CHECK(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
ldm->regs &= ~(1 << 6);
ldm->regs &= ~(1 << 3);
ldm->regs &= ~(1 << 8);
ldm->load = false;
ldm->pre = false;
CHECK(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
}
TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* msr = nullptr;
SECTION("MRS") {
uint32_t raw = 0b01000001010011111010000000000000;
Instruction instruction(raw);
PsrTransfer* mrs = nullptr;
REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::MI);
CHECK(mrs->type == PsrTransfer::Type::Mrs);
// Operand is a register in the case of MRS (PSR -> Register)
CHECK(mrs->operand == 10);
CHECK(mrs->spsr == true);
CHECK(instruction.disassemble() == "MRSMI R10,SPSR_all");
}
SECTION("MSR") {
uint32_t raw = 0b11100001001010011111000000001000;
Instruction instruction(raw);
PsrTransfer* msr = nullptr;
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
CHECK(msr->type == PsrTransfer::Type::Msr);
// Operand is a register in the case of MSR (Register -> PSR)
CHECK(msr->operand == 8);
CHECK(msr->spsr == false);
CHECK(instruction.disassemble() == "MSR CPSR_all,R8");
}
SECTION("MSR_flg with register operand") {
uint32_t raw = 0b01100001001010001111000000001000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::VS);
CHECK(msr->type == PsrTransfer::Type::Msr_flg);
CHECK(msr->imm == 0);
CHECK(msr->operand == 8);
CHECK(msr->spsr == false);
CHECK(instruction.disassemble() == "MSRVS CPSR_flg,R8");
}
SECTION("MSR_flg with immediate operand") {
uint32_t raw = 0b11100011011010001111011101101000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
CHECK(msr->type == PsrTransfer::Type::Msr_flg);
CHECK(msr->imm == 1);
// 104 (32 bits) rotated by 2 * 7
CHECK(msr->operand == 27262976);
CHECK(msr->spsr == true);
CHECK(instruction.disassemble() == "MSR SPSR_flg,#27262976");
}
}
TEST_CASE("Data Processing", TAG) {
uint32_t raw = 0b11100000000111100111101101100001;
Instruction instruction(raw);
DataProcessing* alu = nullptr;
Shift* shift = nullptr;
REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
// operand 2 is a shifted register
REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
CHECK(shift->rm == 1);
CHECK(shift->data.immediate == true);
CHECK(shift->data.type == ShiftType::ROR);
CHECK(shift->data.operand == 22);
CHECK(alu->rd == 7);
CHECK(alu->rn == 14);
CHECK(alu->set == true);
CHECK(alu->opcode == OpCode::AND);
CHECK(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
shift->data.immediate = false;
shift->data.operand = 2;
alu->set = false;
CHECK(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
alu->operand = static_cast<uint32_t>(3300012);
CHECK(instruction.disassemble() == "AND R7,R14,#3300012");
SECTION("set-only operations") {
alu->set = true;
alu->opcode = OpCode::TST;
CHECK(instruction.disassemble() == "TST R14,#3300012");
alu->opcode = OpCode::TEQ;
CHECK(instruction.disassemble() == "TEQ R14,#3300012");
alu->opcode = OpCode::CMP;
CHECK(instruction.disassemble() == "CMP R14,#3300012");
alu->opcode = OpCode::CMN;
CHECK(instruction.disassemble() == "CMN R14,#3300012");
}
SECTION("destination operations") {
alu->opcode = OpCode::EOR;
CHECK(instruction.disassemble() == "EOR R7,R14,#3300012");
alu->opcode = OpCode::SUB;
CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::RSB;
CHECK(instruction.disassemble() == "RSB R7,R14,#3300012");
alu->opcode = OpCode::SUB;
CHECK(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::ADC;
CHECK(instruction.disassemble() == "ADC R7,R14,#3300012");
alu->opcode = OpCode::SBC;
CHECK(instruction.disassemble() == "SBC R7,R14,#3300012");
alu->opcode = OpCode::RSC;
CHECK(instruction.disassemble() == "RSC R7,R14,#3300012");
alu->opcode = OpCode::ORR;
CHECK(instruction.disassemble() == "ORR R7,R14,#3300012");
alu->opcode = OpCode::MOV;
CHECK(instruction.disassemble() == "MOV R7,#3300012");
alu->opcode = OpCode::BIC;
CHECK(instruction.disassemble() == "BIC R7,R14,#3300012");
alu->opcode = OpCode::MVN;
CHECK(instruction.disassemble() == "MVN R7,#3300012");
}
}
TEST_CASE("Coprocessor Data Transfer", TAG) {
uint32_t raw = 0b10101101101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataTransfer* ldc = nullptr;
REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::GE);
CHECK(ldc->offset == 70);
CHECK(ldc->cpn == 1);
CHECK(ldc->crd == 15);
CHECK(ldc->rn == 5);
CHECK(ldc->load == false);
CHECK(ldc->write == true);
CHECK(ldc->len == false);
CHECK(ldc->up == true);
CHECK(ldc->pre == true);
CHECK(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
ldc->load = true;
ldc->pre = false;
ldc->write = false;
ldc->len = true;
CHECK(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
}
TEST_CASE("Coprocessor Operand Operation", TAG) {
uint32_t raw = 0b11101110101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataOperation* cdp = nullptr;
REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
CHECK(cdp->crm == 6);
CHECK(cdp->cp == 2);
CHECK(cdp->cpn == 1);
CHECK(cdp->crd == 15);
CHECK(cdp->crn == 5);
CHECK(cdp->cp_opc == 10);
CHECK(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
}
TEST_CASE("Coprocessor Register Transfer", TAG) {
uint32_t raw = 0b11101110101001011111000101010110;
Instruction instruction(raw);
CoprocessorRegisterTransfer* mrc = nullptr;
REQUIRE(
(mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
CHECK(instruction.condition == Condition::AL);
CHECK(mrc->crm == 6);
CHECK(mrc->cp == 2);
CHECK(mrc->cpn == 1);
CHECK(mrc->rd == 15);
CHECK(mrc->crn == 5);
CHECK(mrc->load == false);
CHECK(mrc->cp_opc == 5);
CHECK(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
}
TEST_CASE("Software Interrupt", TAG) {
uint32_t raw = 0b00001111101010101010101010101010;
Instruction instruction(raw);
CHECK(instruction.condition == Condition::EQ);
CHECK(instruction.disassemble() == "SWIEQ");
}
#undef TAG

4
tests/cpu/arm/meson.build Normal file
View File

@@ -0,0 +1,4 @@
tests_sources += files(
'instruction.cc',
'exec.cc'
)

468
tests/cpu/instruction.cc
View File

@@ -1,468 +0,0 @@
#include "cpu/instruction.hh"
#include "cpu/utility.hh"
#include <catch2/catch_test_macros.hpp>
#include <cstdint>
[[maybe_unused]] static constexpr auto TAG = "disassembler";
using namespace arm;
TEST_CASE("Branch and Exchange", TAG) {
uint32_t raw = 0b11000001001011111111111100011010;
Instruction instruction(raw);
BranchAndExchange* bx = nullptr;
REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GT);
REQUIRE(bx->rn == 10);
REQUIRE(instruction.disassemble() == "BXGT R10");
}
TEST_CASE("Branch", TAG) {
uint32_t raw = 0b11101011100001010111111111000011;
Instruction instruction(raw);
Branch* b = nullptr;
REQUIRE((b = std::get_if<Branch>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
// last 24 bits = 8748995
// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
// Also +8 since PC is two instructions ahead
REQUIRE(b->offset == 0xFE15FF14);
REQUIRE(b->link == true);
REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
b->link = false;
REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
}
TEST_CASE("Multiply", TAG) {
uint32_t raw = 0b00000000001110101110111110010000;
Instruction instruction(raw);
Multiply* mul = nullptr;
REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(mul->rm == 0);
REQUIRE(mul->rs == 15);
REQUIRE(mul->rn == 14);
REQUIRE(mul->rd == 10);
REQUIRE(mul->acc == true);
REQUIRE(mul->set == true);
REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
mul->acc = false;
mul->set = false;
REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
}
TEST_CASE("Multiply Long", TAG) {
uint32_t raw = 0b00010000100111100111011010010010;
Instruction instruction(raw);
MultiplyLong* mull = nullptr;
REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
REQUIRE(instruction.condition == Condition::NE);
REQUIRE(mull->rm == 2);
REQUIRE(mull->rs == 6);
REQUIRE(mull->rdlo == 7);
REQUIRE(mull->rdhi == 14);
REQUIRE(mull->acc == false);
REQUIRE(mull->set == true);
REQUIRE(mull->uns == false);
REQUIRE(instruction.disassemble() == "SMULLNES R7,R14,R2,R6");
mull->acc = true;
REQUIRE(instruction.disassemble() == "SMLALNES R7,R14,R2,R6");
mull->uns = true;
mull->set = false;
REQUIRE(instruction.disassemble() == "UMLALNE R7,R14,R2,R6");
}
TEST_CASE("Undefined", TAG) {
// notice how this is the same as single data transfer except the shift
// is now a register based shift
uint32_t raw = 0b11100111101000101010111100010110;
Instruction instruction(raw);
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(instruction.disassemble() == "UND");
}
TEST_CASE("Single Data Swap", TAG) {
uint32_t raw = 0b10100001000010010101000010010110;
Instruction instruction(raw);
SingleDataSwap* swp = nullptr;
REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GE);
REQUIRE(swp->rm == 6);
REQUIRE(swp->rd == 5);
REQUIRE(swp->rn == 9);
REQUIRE(swp->byte == false);
REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
swp->byte = true;
REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
}
TEST_CASE("Single Data Transfer", TAG) {
uint32_t raw = 0b11100111101000101010111100000110;
Instruction instruction(raw);
SingleDataTransfer* ldr = nullptr;
Shift* shift = nullptr;
REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
REQUIRE(shift->rm == 6);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::LSL);
REQUIRE(shift->data.operand == 30);
REQUIRE(ldr->rd == 10);
REQUIRE(ldr->rn == 2);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->byte == false);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
ldr->load = true;
ldr->byte = true;
ldr->write = false;
shift->data.type = ShiftType::ROR;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
ldr->up = false;
ldr->pre = false;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
ldr->offset = static_cast<uint16_t>(9023);
REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
ldr->pre = true;
REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
}
TEST_CASE("Halfword Transfer", TAG) {
uint32_t raw = 0b00110001101011110010000010110110;
Instruction instruction(raw);
HalfwordTransfer* ldr = nullptr;
REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::CC);
// offset is not immediate
REQUIRE(ldr->imm == 0);
// hence this offset is a register number (rm)
REQUIRE(ldr->offset == 6);
REQUIRE(ldr->half == true);
REQUIRE(ldr->sign == false);
REQUIRE(ldr->rd == 2);
REQUIRE(ldr->rn == 15);
REQUIRE(ldr->load == false);
REQUIRE(ldr->write == true);
REQUIRE(ldr->up == true);
REQUIRE(ldr->pre == true);
REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
ldr->pre = false;
ldr->load = true;
ldr->sign = true;
ldr->up = false;
REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
ldr->half = false;
REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
ldr->load = false;
// not a register anymore
ldr->imm = 1;
ldr->offset = 90;
REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
}
TEST_CASE("Block Data Transfer", TAG) {
uint32_t raw = 0b10011001010101110100000101101101;
Instruction instruction(raw);
BlockDataTransfer* ldm = nullptr;
REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::LS);
{
uint16_t regs = 0;
regs |= 1 << 0;
regs |= 1 << 2;
regs |= 1 << 3;
regs |= 1 << 5;
regs |= 1 << 6;
regs |= 1 << 8;
regs |= 1 << 14;
REQUIRE(ldm->regs == regs);
}
REQUIRE(ldm->rn == 7);
REQUIRE(ldm->load == true);
REQUIRE(ldm->write == false);
REQUIRE(ldm->s == true);
REQUIRE(ldm->up == false);
REQUIRE(ldm->pre == true);
REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
ldm->write = true;
ldm->s = false;
ldm->up = true;
REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
ldm->regs &= ~(1 << 6);
ldm->regs &= ~(1 << 3);
ldm->regs &= ~(1 << 8);
ldm->load = false;
ldm->pre = false;
REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
}
TEST_CASE("PSR Transfer", TAG) {
PsrTransfer* msr = nullptr;
SECTION("MRS") {
uint32_t raw = 0b01000001010011111010000000000000;
Instruction instruction(raw);
PsrTransfer* mrs = nullptr;
REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::MI);
REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
// Operand is a register in the case of MRS (PSR -> Register)
REQUIRE(mrs->operand == 10);
REQUIRE(mrs->spsr == true);
REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
}
SECTION("MSR") {
uint32_t raw = 0b11100001001010011111000000001000;
Instruction instruction(raw);
PsrTransfer* msr = nullptr;
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(msr->type == PsrTransfer::Type::Msr);
// Operand is a register in the case of MSR (Register -> PSR)
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
}
SECTION("MSR_flg with register operand") {
uint32_t raw = 0b01100001001010001111000000001000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::VS);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 0);
REQUIRE(msr->operand == 8);
REQUIRE(msr->spsr == false);
REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
}
SECTION("MSR_flg with immediate operand") {
uint32_t raw = 0b11100011011010001111011101101000;
Instruction instruction(raw);
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
REQUIRE(msr->imm == 1);
// 104 (32 bits) rotated by 2 * 7
REQUIRE(msr->operand == 27262976);
REQUIRE(msr->spsr == true);
REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
}
}
TEST_CASE("Data Processing", TAG) {
uint32_t raw = 0b11100010000111100111101101100001;
Instruction instruction(raw);
DataProcessing* alu = nullptr;
Shift* shift = nullptr;
REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
// operand 2 is a shifted register
REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
REQUIRE(shift->rm == 1);
REQUIRE(shift->data.immediate == true);
REQUIRE(shift->data.type == ShiftType::ROR);
REQUIRE(shift->data.operand == 22);
REQUIRE(alu->rd == 7);
REQUIRE(alu->rn == 14);
REQUIRE(alu->set == true);
REQUIRE(alu->opcode == OpCode::AND);
REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
shift->data.immediate = false;
shift->data.operand = 2;
alu->set = false;
REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
alu->operand = static_cast<uint32_t>(3300012);
REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
SECTION("set-only operations") {
alu->set = true;
alu->opcode = OpCode::TST;
REQUIRE(instruction.disassemble() == "TST R14,#3300012");
alu->opcode = OpCode::TEQ;
REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
alu->opcode = OpCode::CMP;
REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
alu->opcode = OpCode::CMN;
REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
}
SECTION("destination operations") {
alu->opcode = OpCode::EOR;
REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
alu->opcode = OpCode::SUB;
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::RSB;
REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
alu->opcode = OpCode::SUB;
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
alu->opcode = OpCode::ADC;
REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
alu->opcode = OpCode::SBC;
REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
alu->opcode = OpCode::RSC;
REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
alu->opcode = OpCode::ORR;
REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
alu->opcode = OpCode::MOV;
REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
alu->opcode = OpCode::BIC;
REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
alu->opcode = OpCode::MVN;
REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
}
}
TEST_CASE("Coprocessor Data Transfer", TAG) {
uint32_t raw = 0b10101101101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataTransfer* ldc = nullptr;
REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::GE);
REQUIRE(ldc->offset == 70);
REQUIRE(ldc->cpn == 1);
REQUIRE(ldc->crd == 15);
REQUIRE(ldc->rn == 5);
REQUIRE(ldc->load == false);
REQUIRE(ldc->write == true);
REQUIRE(ldc->len == false);
REQUIRE(ldc->up == true);
REQUIRE(ldc->pre == true);
REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
ldc->load = true;
ldc->pre = false;
ldc->write = false;
ldc->len = true;
REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
}
TEST_CASE("Coprocessor Operand Operation", TAG) {
uint32_t raw = 0b11101110101001011111000101000110;
Instruction instruction(raw);
CoprocessorDataOperation* cdp = nullptr;
REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(cdp->crm == 6);
REQUIRE(cdp->cp == 2);
REQUIRE(cdp->cpn == 1);
REQUIRE(cdp->crd == 15);
REQUIRE(cdp->crn == 5);
REQUIRE(cdp->cp_opc == 10);
REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
}
TEST_CASE("Coprocessor Register Transfer", TAG) {
uint32_t raw = 0b11101110101001011111000101010110;
Instruction instruction(raw);
CoprocessorRegisterTransfer* mrc = nullptr;
REQUIRE(
(mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
REQUIRE(instruction.condition == Condition::AL);
REQUIRE(mrc->crm == 6);
REQUIRE(mrc->cp == 2);
REQUIRE(mrc->cpn == 1);
REQUIRE(mrc->rd == 15);
REQUIRE(mrc->crn == 5);
REQUIRE(mrc->load == false);
REQUIRE(mrc->cp_opc == 5);
REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
}
TEST_CASE("Software Interrupt", TAG) {
uint32_t raw = 0b00001111101010101010101010101010;
Instruction instruction(raw);
REQUIRE(instruction.condition == Condition::EQ);
REQUIRE(instruction.disassemble() == "SWIEQ");
}

4
tests/cpu/meson.build
View File

@@ -1,3 +1 @@
tests_sources += files(
'instruction.cc'
)
subdir('arm')