tests: add execution tests
all but data processing Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
497
src/cpu/arm/instruction.cc
Normal file
497
src/cpu/arm/instruction.cc
Normal file
@@ -0,0 +1,497 @@
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#include "instruction.hh"
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#include "cpu/utility.hh"
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#include "util/bits.hh"
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#include <iterator>
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using namespace arm;
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Instruction::Instruction(uint32_t insn)
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: condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
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// Branch and exhcange
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if ((insn & 0x0FFFFFF0) == 0x012FFF10) {
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uint8_t rn = insn & 0b1111;
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data = BranchAndExchange{ rn };
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// Branch
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} else if ((insn & 0x0E000000) == 0x0A000000) {
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bool link = get_bit(insn, 24);
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uint32_t offset = bit_range(insn, 0, 23);
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// lsh 2 and sign extend the 26 bit offset to 32 bits
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offset = (static_cast<int32_t>(offset) << 8) >> 6;
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offset += 2 * INSTRUCTION_SIZE;
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data = Branch{ .link = link, .offset = offset };
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// Multiply
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} else if ((insn & 0x0FC000F0) == 0x00000090) {
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uint8_t rm = bit_range(insn, 0, 3);
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uint8_t rs = bit_range(insn, 8, 11);
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uint8_t rn = bit_range(insn, 12, 15);
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uint8_t rd = bit_range(insn, 16, 19);
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bool set = get_bit(insn, 20);
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bool acc = get_bit(insn, 21);
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data = Multiply{
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.rm = rm, .rs = rs, .rn = rn, .rd = rd, .set = set, .acc = acc
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};
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// Multiply long
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} else if ((insn & 0x0F8000F0) == 0x00800090) {
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uint8_t rm = bit_range(insn, 0, 3);
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uint8_t rs = bit_range(insn, 8, 11);
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uint8_t rdlo = bit_range(insn, 12, 15);
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uint8_t rdhi = bit_range(insn, 16, 19);
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bool set = get_bit(insn, 20);
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bool acc = get_bit(insn, 21);
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bool uns = !get_bit(insn, 22);
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data = MultiplyLong{ .rm = rm,
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.rs = rs,
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.rdlo = rdlo,
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.rdhi = rdhi,
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.set = set,
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.acc = acc,
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.uns = uns };
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// Undefined
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} else if ((insn & 0x0E000010) == 0x06000010) {
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data = Undefined{};
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// Single data swap
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} else if ((insn & 0x0FB00FF0) == 0x01000090) {
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uint8_t rm = bit_range(insn, 0, 3);
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uint8_t rd = bit_range(insn, 12, 15);
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uint8_t rn = bit_range(insn, 16, 19);
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bool byte = get_bit(insn, 22);
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data = SingleDataSwap{ .rm = rm, .rd = rd, .rn = rn, .byte = byte };
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// Single data transfer
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} else if ((insn & 0x0C000000) == 0x04000000) {
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std::variant<uint16_t, Shift> offset;
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uint8_t rd = bit_range(insn, 12, 15);
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uint8_t rn = bit_range(insn, 16, 19);
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bool load = get_bit(insn, 20);
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bool write = get_bit(insn, 21);
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bool byte = get_bit(insn, 22);
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bool up = get_bit(insn, 23);
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bool pre = get_bit(insn, 24);
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bool imm = get_bit(insn, 25);
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if (imm) {
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// register specified shift amounts not available in single data
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// transfer (see Undefined)
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uint8_t rm = bit_range(insn, 0, 3);
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ShiftType shift_type =
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static_cast<ShiftType>(bit_range(insn, 5, 6));
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uint8_t operand = bit_range(insn, 7, 11);
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offset = Shift{ .rm = rm,
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.data = ShiftData{ .type = shift_type,
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.immediate = true,
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.operand = operand } };
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} else {
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offset = static_cast<uint16_t>(bit_range(insn, 0, 11));
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}
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data = SingleDataTransfer{ .offset = offset,
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.rd = rd,
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.rn = rn,
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.load = load,
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.write = write,
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.byte = byte,
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.up = up,
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.pre = pre };
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// Halfword transfer
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} else if ((insn & 0x0E000090) == 0x00000090) {
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uint8_t offset = bit_range(insn, 0, 3);
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bool half = get_bit(insn, 5);
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bool sign = get_bit(insn, 6);
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uint8_t rd = bit_range(insn, 12, 15);
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uint8_t rn = bit_range(insn, 16, 19);
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bool load = get_bit(insn, 20);
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bool write = get_bit(insn, 21);
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bool imm = get_bit(insn, 22);
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bool up = get_bit(insn, 23);
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bool pre = get_bit(insn, 24);
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offset |= (imm ? bit_range(insn, 8, 11) << 2 : 0);
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data = HalfwordTransfer{ .offset = offset,
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.half = half,
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.sign = sign,
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.rd = rd,
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.rn = rn,
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.load = load,
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.write = write,
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.imm = imm,
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.up = up,
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.pre = pre };
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// Block data transfer
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} else if ((insn & 0x0E000000) == 0x08000000) {
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uint16_t regs = bit_range(insn, 0, 15);
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uint8_t rn = bit_range(insn, 16, 19);
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bool load = get_bit(insn, 20);
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bool write = get_bit(insn, 21);
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bool s = get_bit(insn, 22);
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bool up = get_bit(insn, 23);
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bool pre = get_bit(insn, 24);
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data = BlockDataTransfer{ .regs = regs,
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.rn = rn,
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.load = load,
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.write = write,
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.s = s,
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.up = up,
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.pre = pre };
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// Data Processing
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} else if ((insn & 0x0C000000) == 0x00000000) {
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uint8_t rd = bit_range(insn, 12, 15);
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uint8_t rn = bit_range(insn, 16, 19);
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bool set = get_bit(insn, 20);
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OpCode opcode = static_cast<OpCode>(bit_range(insn, 21, 24));
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bool imm = get_bit(insn, 25);
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if ((opcode == OpCode::TST || opcode == OpCode::CMP) && !set) {
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data = PsrTransfer{ .operand = rd,
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.spsr = get_bit(insn, 22),
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.type = PsrTransfer::Type::Mrs,
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.imm = 0 };
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} else if ((opcode == OpCode::TEQ || opcode == OpCode::CMN) && !set) {
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uint32_t operand = 0;
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if (imm) {
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uint32_t immediate = bit_range(insn, 0, 7);
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uint8_t rotate = bit_range(insn, 8, 11);
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operand = std::rotr(immediate, rotate * 2);
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} else {
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operand = bit_range(insn, 0, 3);
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}
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data = PsrTransfer{ .operand = operand,
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.spsr = get_bit(insn, 22),
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.type = (get_bit(insn, 16)
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? PsrTransfer::Type::Msr
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: PsrTransfer::Type::Msr_flg),
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.imm = imm };
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} else {
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std::variant<Shift, uint32_t> operand;
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if (imm) {
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uint32_t immediate = bit_range(insn, 0, 7);
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uint8_t rotate = bit_range(insn, 8, 11);
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operand = std::rotr(immediate, rotate * 2);
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} else {
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uint8_t rm = bit_range(insn, 0, 3);
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bool reg = get_bit(insn, 4);
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ShiftType shift_type =
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static_cast<ShiftType>(bit_range(insn, 5, 6));
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uint8_t sh_operand = bit_range(insn, (reg ? 8 : 7), 11);
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operand = Shift{ .rm = rm,
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.data = ShiftData{ .type = shift_type,
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.immediate = !reg,
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.operand = sh_operand } };
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}
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data = DataProcessing{ .operand = operand,
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.rd = rd,
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.rn = rn,
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.set = set,
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.opcode = opcode };
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}
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// Software interrupt
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} else if ((insn & 0x0F000000) == 0x0F000000) {
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data = SoftwareInterrupt{};
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// Coprocessor data transfer
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} else if ((insn & 0x0E000000) == 0x0C000000) {
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uint8_t offset = bit_range(insn, 0, 7);
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uint8_t cpn = bit_range(insn, 8, 11);
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uint8_t crd = bit_range(insn, 12, 15);
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uint8_t rn = bit_range(insn, 16, 19);
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bool load = get_bit(insn, 20);
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bool write = get_bit(insn, 21);
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bool len = get_bit(insn, 22);
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bool up = get_bit(insn, 23);
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bool pre = get_bit(insn, 24);
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data = CoprocessorDataTransfer{ .offset = offset,
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.cpn = cpn,
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.crd = crd,
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.rn = rn,
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.load = load,
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.write = write,
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.len = len,
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.up = up,
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.pre = pre };
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// Coprocessor data operation
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} else if ((insn & 0x0F000010) == 0x0E000000) {
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uint8_t crm = bit_range(insn, 0, 3);
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uint8_t cp = bit_range(insn, 5, 7);
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uint8_t cpn = bit_range(insn, 8, 11);
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uint8_t crd = bit_range(insn, 12, 15);
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uint8_t crn = bit_range(insn, 16, 19);
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uint8_t cp_opc = bit_range(insn, 20, 23);
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data = CoprocessorDataOperation{ .crm = crm,
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.cp = cp,
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.cpn = cpn,
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.crd = crd,
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.crn = crn,
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.cp_opc = cp_opc };
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// Coprocessor register transfer
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} else if ((insn & 0x0F000010) == 0x0E000010) {
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uint8_t crm = bit_range(insn, 0, 3);
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uint8_t cp = bit_range(insn, 5, 7);
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uint8_t cpn = bit_range(insn, 8, 11);
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uint8_t rd = bit_range(insn, 12, 15);
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uint8_t crn = bit_range(insn, 16, 19);
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bool load = get_bit(insn, 20);
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uint8_t cp_opc = bit_range(insn, 21, 23);
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data = CoprocessorRegisterTransfer{ .crm = crm,
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.cp = cp,
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.cpn = cpn,
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.rd = rd,
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.crn = crn,
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.load = load,
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.cp_opc = cp_opc };
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} else {
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data = Undefined{};
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}
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}
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std::string
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Instruction::disassemble() {
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// goddamn this is gore
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// TODO: make this less ugly
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return std::visit(
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overloaded{
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[this](BranchAndExchange& data) {
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return fmt::format("BX{} R{:d}", condition, data.rn);
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},
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[this](Branch& data) {
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return fmt::format(
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"B{}{} 0x{:06X}", (data.link ? "L" : ""), condition, data.offset);
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},
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[this](Multiply& data) {
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if (data.acc) {
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return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
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condition,
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(data.set ? "S" : ""),
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data.rd,
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data.rm,
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data.rs,
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data.rn);
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} else {
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return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
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condition,
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(data.set ? "S" : ""),
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data.rd,
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data.rm,
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data.rs);
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}
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},
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[this](MultiplyLong& data) {
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return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
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(data.uns ? 'U' : 'S'),
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(data.acc ? "MLAL" : "MULL"),
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condition,
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(data.set ? "S" : ""),
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data.rdlo,
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data.rdhi,
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data.rm,
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data.rs);
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},
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[](Undefined) { return std::string("UND"); },
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[this](SingleDataSwap& data) {
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return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
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condition,
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(data.byte ? "B" : ""),
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data.rd,
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data.rm,
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data.rn);
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},
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[this](SingleDataTransfer& data) {
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std::string expression;
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std::string address;
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if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
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if (*offset == 0) {
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expression = "";
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} else {
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expression =
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fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
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}
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} else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
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// Shifts are always immediate in single data transfer
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expression = fmt::format(",{}R{:d},{} #{:d}",
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(data.up ? '+' : '-'),
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shift->rm,
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shift->data.type,
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shift->data.operand);
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}
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return fmt::format(
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"{}{}{}{} R{:d},[R{:d}{}]{}",
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(data.load ? "LDR" : "STR"),
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condition,
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(data.byte ? "B" : ""),
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(!data.pre && data.write ? "T" : ""),
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data.rd,
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data.rn,
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(data.pre ? expression : ""),
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(data.pre ? (data.write ? "!" : "") : expression));
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},
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[this](HalfwordTransfer& data) {
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std::string expression;
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if (data.imm) {
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if (data.offset == 0) {
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expression = "";
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} else {
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expression = fmt::format(
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",{}#{:d}", (data.up ? '+' : '-'), data.offset);
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}
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} else {
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expression =
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fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
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}
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return fmt::format(
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"{}{}{}{} R{:d},[R{:d}{}]{}",
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(data.load ? "LDR" : "STR"),
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condition,
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(data.sign ? "S" : ""),
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(data.half ? 'H' : 'B'),
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data.rd,
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data.rn,
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(data.pre ? expression : ""),
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(data.pre ? (data.write ? "!" : "") : expression));
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},
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[this](BlockDataTransfer& data) {
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std::string regs;
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for (uint8_t i = 0; i < 16; i++) {
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if (get_bit(data.regs, i))
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fmt::format_to(std::back_inserter(regs), "R{:d},", i);
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};
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regs.pop_back();
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return fmt::format("{}{}{}{} R{:d}{},{{{}}}{}",
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(data.load ? "LDM" : "STM"),
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condition,
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(data.up ? 'I' : 'D'),
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(data.pre ? 'B' : 'A'),
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data.rn,
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(data.write ? "!" : ""),
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regs,
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(data.s ? "^" : ""));
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},
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[this](PsrTransfer& data) {
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if (data.type == PsrTransfer::Type::Mrs) {
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return fmt::format("MRS{} R{:d},{}",
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condition,
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data.operand,
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(data.spsr ? "SPSR_all" : "CPSR_all"));
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} else {
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return fmt::format(
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"MSR{} {}_{},{}{}",
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condition,
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(data.spsr ? "SPSR" : "CPSR"),
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(data.type == PsrTransfer::Type::Msr_flg ? "flg" : "all"),
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(data.imm ? '#' : 'R'),
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data.operand);
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}
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},
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[this](DataProcessing& data) {
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std::string op_2;
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if (const uint32_t* operand =
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std::get_if<uint32_t>(&data.operand)) {
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op_2 = fmt::format("#{:d}", *operand);
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} else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
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op_2 = fmt::format("R{:d},{} {}{:d}",
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shift->rm,
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shift->data.type,
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(shift->data.immediate ? '#' : 'R'),
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shift->data.operand);
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}
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switch (data.opcode) {
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case OpCode::MOV:
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case OpCode::MVN:
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return fmt::format("{}{}{} R{:d},{}",
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data.opcode,
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condition,
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(data.set ? "S" : ""),
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data.rd,
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op_2);
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case OpCode::TST:
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case OpCode::TEQ:
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case OpCode::CMP:
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case OpCode::CMN:
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return fmt::format(
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"{}{} R{:d},{}", data.opcode, condition, data.rn, op_2);
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default:
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return fmt::format("{}{}{} R{:d},R{:d},{}",
|
||||
data.opcode,
|
||||
condition,
|
||||
(data.set ? "S" : ""),
|
||||
data.rd,
|
||||
data.rn,
|
||||
op_2);
|
||||
}
|
||||
},
|
||||
[this](SoftwareInterrupt) { return fmt::format("SWI{}", condition); },
|
||||
[this](CoprocessorDataTransfer& data) {
|
||||
std::string expression = fmt::format(",#{:d}", data.offset);
|
||||
return fmt::format(
|
||||
"{}{}{} p{:d},c{:d},[R{:d}{}]{}",
|
||||
(data.load ? "LDC" : "STC"),
|
||||
condition,
|
||||
(data.len ? "L" : ""),
|
||||
data.cpn,
|
||||
data.crd,
|
||||
data.rn,
|
||||
(data.pre ? expression : ""),
|
||||
(data.pre ? (data.write ? "!" : "") : expression));
|
||||
},
|
||||
[this](CoprocessorDataOperation& data) {
|
||||
return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
|
||||
condition,
|
||||
data.cpn,
|
||||
data.cp_opc,
|
||||
data.crd,
|
||||
data.crn,
|
||||
data.crm,
|
||||
data.cp);
|
||||
},
|
||||
[this](CoprocessorRegisterTransfer& data) {
|
||||
return fmt::format("{}{} p{},{},R{},c{},c{},{}",
|
||||
(data.load ? "MRC" : "MCR"),
|
||||
condition,
|
||||
data.cpn,
|
||||
data.cp_opc,
|
||||
data.rd,
|
||||
data.crn,
|
||||
data.crm,
|
||||
data.cp);
|
||||
},
|
||||
[](auto) { return std::string("unknown instruction"); } },
|
||||
data);
|
||||
}
|
||||
Reference in New Issue
Block a user