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refactor: reorganize everything

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Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2023-10-04 01:41:38 +05:30
parent 36d71a4ee2
commit e0f7f32699
28 changed files with 297 additions and 338 deletions
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18
src/bus.cc
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@@ -21,7 +21,7 @@ Bus::read_halfword(size_t address) {
if (address & 0b01)
glogger.warn("Reading a non aligned halfword address");
return memory->read(address) | memory->read(address + 1) << 8;
return read_byte(address) | read_byte(address + 1) << 8;
}
void
@@ -29,8 +29,8 @@ Bus::write_halfword(size_t address, uint16_t halfword) {
if (address & 0b01)
glogger.warn("Writing to a non aligned halfword address");
memory->write(address, halfword & 0xFF);
memory->write(address + 1, halfword >> 8 & 0xFF);
write_byte(address, halfword & 0xFF);
write_byte(address + 1, halfword >> 8 & 0xFF);
}
uint32_t
@@ -38,8 +38,8 @@ Bus::read_word(size_t address) {
if (address & 0b11)
glogger.warn("Reading a non aligned word address");
return memory->read(address) | memory->read(address + 1) << 8 |
memory->read(address + 2) << 16 | memory->read(address + 3) << 24;
return read_byte(address) | read_byte(address + 1) << 8 |
read_byte(address + 2) << 16 | read_byte(address + 3) << 24;
}
void
@@ -47,9 +47,9 @@ Bus::write_word(size_t address, uint32_t word) {
if (address & 0b11)
glogger.warn("Writing to a non aligned word address");
memory->write(address, word & 0xFF);
memory->write(address + 1, word >> 8 & 0xFF);
memory->write(address + 2, word >> 16 & 0xFF);
memory->write(address + 3, word >> 24 & 0xFF);
write_byte(address, word & 0xFF);
write_byte(address + 1, word >> 8 & 0xFF);
write_byte(address + 2, word >> 16 & 0xFF);
write_byte(address + 3, word >> 24 & 0xFF);
}
}

2
src/cpu/alu.cc
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@@ -1,4 +1,4 @@
#include "alu.hh"
#include "cpu/alu.hh"
#include "util/bits.hh"
namespace matar {

53
src/cpu/alu.hh
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@@ -1,53 +0,0 @@
#pragma once
#include <cstdint>
#include <fmt/ostream.h>
namespace matar {
enum class ShiftType {
LSL = 0b00,
LSR = 0b01,
ASR = 0b10,
ROR = 0b11
};
constexpr auto
stringify(ShiftType shift_type) {
#define CASE(type) \
case ShiftType::type: \
return #type;
switch (shift_type) {
CASE(LSL)
CASE(LSR)
CASE(ASR)
CASE(ROR)
}
#undef CASE
return "";
}
struct ShiftData {
ShiftType type;
bool immediate;
uint8_t operand;
};
struct Shift {
uint8_t rm;
ShiftData data;
};
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry);
uint32_t
sub(uint32_t a, uint32_t b, bool& carry, bool& overflow);
uint32_t
add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
uint32_t
sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
}

2
src/cpu/arm/disassembler.cc
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@@ -1,4 +1,4 @@
#include "instruction.hh"
#include "cpu/arm/instruction.hh"
#include "util/bits.hh"
namespace matar::arm {

4
src/cpu/arm/exec.cc
View File

@@ -1,10 +1,10 @@
#include "cpu/cpu-impl.hh"
#include "cpu/cpu.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar::arm {
void
Instruction::exec(CpuImpl& cpu) {
Instruction::exec(Cpu& cpu) {
if (!cpu.cpsr.condition(condition)) {
return;
}

2
src/cpu/arm/instruction.cc
View File

@@ -1,4 +1,4 @@
#include "instruction.hh"
#include "cpu/arm/instruction.hh"
#include "util/bits.hh"
#include <iterator>

230
src/cpu/arm/instruction.hh
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@@ -1,230 +0,0 @@
#pragma once
#include "cpu/alu.hh"
#include "cpu/psr.hh"
#include <cstdint>
#include <fmt/ostream.h>
#include <variant>
namespace matar {
class CpuImpl;
namespace arm {
// https://en.cppreference.com/w/cpp/utility/variant/visit
template<class... Ts>
struct overloaded : Ts... {
using Ts::operator()...;
};
template<class... Ts>
overloaded(Ts...) -> overloaded<Ts...>;
static constexpr size_t INSTRUCTION_SIZE = 4;
struct BranchAndExchange {
uint8_t rn;
};
struct Branch {
bool link;
uint32_t offset;
};
struct Multiply {
uint8_t rm;
uint8_t rs;
uint8_t rn;
uint8_t rd;
bool set;
bool acc;
};
struct MultiplyLong {
uint8_t rm;
uint8_t rs;
uint8_t rdlo;
uint8_t rdhi;
bool set;
bool acc;
bool uns;
};
struct SingleDataSwap {
uint8_t rm;
uint8_t rd;
uint8_t rn;
bool byte;
};
struct SingleDataTransfer {
std::variant<uint16_t, Shift> offset;
uint8_t rd;
uint8_t rn;
bool load;
bool write;
bool byte;
bool up;
bool pre;
};
struct HalfwordTransfer {
uint8_t offset;
bool half;
bool sign;
uint8_t rd;
uint8_t rn;
bool load;
bool write;
bool imm;
bool up;
bool pre;
};
struct BlockDataTransfer {
uint16_t regs;
uint8_t rn;
bool load;
bool write;
bool s;
bool up;
bool pre;
};
struct DataProcessing {
enum class OpCode {
AND = 0b0000,
EOR = 0b0001,
SUB = 0b0010,
RSB = 0b0011,
ADD = 0b0100,
ADC = 0b0101,
SBC = 0b0110,
RSC = 0b0111,
TST = 0b1000,
TEQ = 0b1001,
CMP = 0b1010,
CMN = 0b1011,
ORR = 0b1100,
MOV = 0b1101,
BIC = 0b1110,
MVN = 0b1111
};
std::variant<Shift, uint32_t> operand;
uint8_t rd;
uint8_t rn;
bool set;
OpCode opcode;
};
constexpr auto
stringify(DataProcessing::OpCode opcode) {
#define CASE(opcode) \
case DataProcessing::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(SUB)
CASE(RSB)
CASE(ADD)
CASE(ADC)
CASE(SBC)
CASE(RSC)
CASE(TST)
CASE(TEQ)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MOV)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return "";
}
struct PsrTransfer {
enum class Type {
Mrs,
Msr,
Msr_flg
};
uint32_t operand;
bool spsr;
Type type;
// ignored outside MSR_flg
bool imm;
};
struct CoprocessorDataTransfer {
uint8_t offset;
uint8_t cpn;
uint8_t crd;
uint8_t rn;
bool load;
bool write;
bool len;
bool up;
bool pre;
};
struct CoprocessorDataOperation {
uint8_t crm;
uint8_t cp;
uint8_t cpn;
uint8_t crd;
uint8_t crn;
uint8_t cp_opc;
};
struct CoprocessorRegisterTransfer {
uint8_t crm;
uint8_t cp;
uint8_t cpn;
uint8_t rd;
uint8_t crn;
bool load;
uint8_t cp_opc;
};
struct Undefined {};
struct SoftwareInterrupt {};
using InstructionData = std::variant<BranchAndExchange,
Branch,
Multiply,
MultiplyLong,
SingleDataSwap,
SingleDataTransfer,
HalfwordTransfer,
BlockDataTransfer,
DataProcessing,
PsrTransfer,
CoprocessorDataTransfer,
CoprocessorDataOperation,
CoprocessorRegisterTransfer,
Undefined,
SoftwareInterrupt>;
struct Instruction {
Instruction(uint32_t insn);
Instruction(Condition condition, InstructionData data)
: condition(condition)
, data(data){};
void exec(CpuImpl& cpu);
#ifdef DISASSEMBLER
std::string disassemble();
#endif
Condition condition;
InstructionData data;
};
}
}

160
src/cpu/cpu-impl.cc
View File

@@ -1,160 +0,0 @@
#include "cpu-impl.hh"
#include "cpu/arm/instruction.hh"
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include "util/log.hh"
#include <algorithm>
#include <cstdio>
#include <type_traits>
namespace matar {
CpuImpl::CpuImpl(const Bus& bus) noexcept
: bus(std::make_shared<Bus>(bus))
, gpr({ 0 })
, cpsr(0)
, spsr(0)
, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
, spsr_banked({ 0, 0, 0, 0, 0 })
, is_flushed(false) {
cpsr.set_mode(Mode::Supervisor);
cpsr.set_irq_disabled(true);
cpsr.set_fiq_disabled(true);
cpsr.set_state(State::Arm);
glogger.info("CPU successfully initialised");
// PC always points to two instructions ahead
// PC - 2 is the instruction being executed
pc += 2 * arm::INSTRUCTION_SIZE;
}
/* change modes */
void
CpuImpl::chg_mode(const Mode to) {
Mode from = cpsr.mode();
if (from == to)
return;
/* TODO: replace visible registers with view once I understand how to
* concatenate views */
#define STORE_BANKED(mode, MODE) \
std::copy(gpr.begin() + GPR_##MODE##_FIRST, \
gpr.begin() + gpr.size() - 1, \
gpr_banked.mode.begin())
switch (from) {
case Mode::Fiq:
STORE_BANKED(fiq, FIQ);
spsr_banked.fiq = spsr;
break;
case Mode::Supervisor:
STORE_BANKED(svc, SVC);
spsr_banked.svc = spsr;
break;
case Mode::Abort:
STORE_BANKED(abt, ABT);
spsr_banked.abt = spsr;
break;
case Mode::Irq:
STORE_BANKED(irq, IRQ);
spsr_banked.irq = spsr;
break;
case Mode::Undefined:
STORE_BANKED(und, UND);
spsr_banked.und = spsr;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#define RESTORE_BANKED(mode, MODE) \
std::copy(gpr_banked.mode.begin(), \
gpr_banked.mode.end(), \
gpr.begin() + GPR_##MODE##_FIRST)
switch (to) {
case Mode::Fiq:
RESTORE_BANKED(fiq, FIQ);
spsr = spsr_banked.fiq;
break;
case Mode::Supervisor:
RESTORE_BANKED(svc, SVC);
spsr = spsr_banked.svc;
break;
case Mode::Abort:
RESTORE_BANKED(abt, ABT);
spsr = spsr_banked.abt;
break;
case Mode::Irq:
RESTORE_BANKED(irq, IRQ);
spsr = spsr_banked.irq;
break;
case Mode::Undefined:
RESTORE_BANKED(und, UND);
spsr = spsr_banked.und;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#undef RESTORE_BANKED
cpsr.set_mode(to);
}
void
CpuImpl::step() {
// Current instruction is two instructions behind PC
uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
if (cpsr.state() == State::Arm) {
arm::Instruction instruction(bus->read_word(cur_pc));
#ifdef DISASSEMBLER
glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
#endif
instruction.exec(*this);
} else {
thumb::Instruction instruction(bus->read_halfword(cur_pc));
#ifdef DISASSEMBLER
glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble(cur_pc));
#endif
instruction.exec(*this);
}
// advance PC
{
size_t size = cpsr.state() == State::Arm ? arm::INSTRUCTION_SIZE
: thumb::INSTRUCTION_SIZE;
if (is_flushed) {
// if flushed, do not increment the PC, instead set it to two
// instructions ahead to account for flushed "fetch" and "decode"
// instructions
pc += 2 * size;
is_flushed = false;
} else {
// if not flushed continue like normal
pc += size;
}
}
}
}

70
src/cpu/cpu-impl.hh
View File

@@ -1,70 +0,0 @@
#pragma once
#include "arm/instruction.hh"
#include "bus.hh"
#include "cpu/psr.hh"
#include "thumb/instruction.hh"
#include <cstdint>
namespace matar {
class CpuImpl {
public:
CpuImpl(const Bus& bus) noexcept;
void step();
void chg_mode(const Mode to);
private:
friend void arm::Instruction::exec(CpuImpl& cpu);
friend void thumb::Instruction::exec(CpuImpl& cpu);
static constexpr uint8_t GPR_COUNT = 16;
static constexpr uint8_t GPR_FIQ_FIRST = 8;
static constexpr uint8_t GPR_SVC_FIRST = 13;
static constexpr uint8_t GPR_ABT_FIRST = 13;
static constexpr uint8_t GPR_IRQ_FIRST = 13;
static constexpr uint8_t GPR_UND_FIRST = 13;
static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
std::shared_ptr<Bus> bus;
std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
Psr cpsr; // current program status register
Psr spsr; // status program status register
static constexpr uint8_t SP_INDEX = 13;
static_assert(SP_INDEX < GPR_COUNT);
uint32_t& sp = gpr[SP_INDEX];
static constexpr uint8_t LR_INDEX = 14;
static_assert(LR_INDEX < GPR_COUNT);
uint32_t& lr = gpr[LR_INDEX];
static constexpr uint8_t PC_INDEX = 15;
static_assert(PC_INDEX < GPR_COUNT);
uint32_t& pc = gpr[PC_INDEX];
struct {
std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
// visible registers before the mode switch
std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
} gpr_banked; // banked general purpose registers
struct {
Psr fiq;
Psr svc;
Psr abt;
Psr irq;
Psr und;
} spsr_banked; // banked saved program status registers
bool is_flushed;
};
}

156
src/cpu/cpu.cc
View File

@@ -1,14 +1,160 @@
#include "cpu/cpu.hh"
#include "cpu-impl.hh"
#include "cpu/arm/instruction.hh"
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include "util/log.hh"
#include <algorithm>
#include <cstdio>
#include <type_traits>
namespace matar {
Cpu::Cpu(const Bus& bus) noexcept
: impl(std::make_unique<CpuImpl>(bus)){};
: bus(std::make_shared<Bus>(bus))
, gpr({ 0 })
, cpsr(0)
, spsr(0)
, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
, spsr_banked({ 0, 0, 0, 0, 0 })
, is_flushed(false) {
cpsr.set_mode(Mode::Supervisor);
cpsr.set_irq_disabled(true);
cpsr.set_fiq_disabled(true);
cpsr.set_state(State::Arm);
glogger.info("CPU successfully initialised");
Cpu::~Cpu() = default;
// PC always points to two instructions ahead
// PC - 2 is the instruction being executed
pc += 2 * arm::INSTRUCTION_SIZE;
}
/* change modes */
void
Cpu::chg_mode(const Mode to) {
Mode from = cpsr.mode();
if (from == to)
return;
/* TODO: replace visible registers with view once I understand how to
* concatenate views */
#define STORE_BANKED(mode, MODE) \
std::copy(gpr.begin() + GPR_##MODE##_FIRST, \
gpr.begin() + gpr.size() - 1, \
gpr_banked.mode.begin())
switch (from) {
case Mode::Fiq:
STORE_BANKED(fiq, FIQ);
spsr_banked.fiq = spsr;
break;
case Mode::Supervisor:
STORE_BANKED(svc, SVC);
spsr_banked.svc = spsr;
break;
case Mode::Abort:
STORE_BANKED(abt, ABT);
spsr_banked.abt = spsr;
break;
case Mode::Irq:
STORE_BANKED(irq, IRQ);
spsr_banked.irq = spsr;
break;
case Mode::Undefined:
STORE_BANKED(und, UND);
spsr_banked.und = spsr;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#define RESTORE_BANKED(mode, MODE) \
std::copy(gpr_banked.mode.begin(), \
gpr_banked.mode.end(), \
gpr.begin() + GPR_##MODE##_FIRST)
switch (to) {
case Mode::Fiq:
RESTORE_BANKED(fiq, FIQ);
spsr = spsr_banked.fiq;
break;
case Mode::Supervisor:
RESTORE_BANKED(svc, SVC);
spsr = spsr_banked.svc;
break;
case Mode::Abort:
RESTORE_BANKED(abt, ABT);
spsr = spsr_banked.abt;
break;
case Mode::Irq:
RESTORE_BANKED(irq, IRQ);
spsr = spsr_banked.irq;
break;
case Mode::Undefined:
RESTORE_BANKED(und, UND);
spsr = spsr_banked.und;
break;
case Mode::User:
case Mode::System:
STORE_BANKED(old, SYS_USR);
break;
}
#undef RESTORE_BANKED
cpsr.set_mode(to);
}
void
Cpu::step() {
impl->step();
};
// Current instruction is two instructions behind PC
uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
if (cpsr.state() == State::Arm) {
arm::Instruction instruction(bus->read_word(cur_pc));
#ifdef DISASSEMBLER
glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
#endif
instruction.exec(*this);
} else {
thumb::Instruction instruction(bus->read_halfword(cur_pc));
#ifdef DISASSEMBLER
glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble(cur_pc));
#endif
instruction.exec(*this);
}
// advance PC
{
size_t size = cpsr.state() == State::Arm ? arm::INSTRUCTION_SIZE
: thumb::INSTRUCTION_SIZE;
if (is_flushed) {
// if flushed, do not increment the PC, instead set it to two
// instructions ahead to account for flushed "fetch" and "decode"
// instructions
pc += 2 * size;
is_flushed = false;
} else {
// if not flushed continue like normal
pc += size;
}
}
}
}

1
src/cpu/meson.build
View File

@@ -1,5 +1,4 @@
lib_sources += files(
'cpu-impl.cc',
'cpu.cc',
'psr.cc',
'alu.cc'

2
src/cpu/psr.cc
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@@ -1,4 +1,4 @@
#include "psr.hh"
#include "cpu/psr.hh"
#include "util/bits.hh"
#include "util/log.hh"

123
src/cpu/psr.hh
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@@ -1,123 +0,0 @@
#pragma once
#include <cstdint>
#include <fmt/ostream.h>
namespace matar {
enum class Mode {
/* M[4:0] in PSR */
User = 0b10000,
Fiq = 0b10001,
Irq = 0b10010,
Supervisor = 0b10011,
Abort = 0b10111,
Undefined = 0b11011,
System = 0b11111,
};
enum class State {
Arm = 0,
Thumb = 1
};
enum class Condition {
EQ = 0b0000,
NE = 0b0001,
CS = 0b0010,
CC = 0b0011,
MI = 0b0100,
PL = 0b0101,
VS = 0b0110,
VC = 0b0111,
HI = 0b1000,
LS = 0b1001,
GE = 0b1010,
LT = 0b1011,
GT = 0b1100,
LE = 0b1101,
AL = 0b1110
};
constexpr auto
stringify(Condition cond) {
#define CASE(cond) \
case Condition::cond: \
return #cond;
switch (cond) {
CASE(EQ)
CASE(NE)
CASE(CS)
CASE(CC)
CASE(MI)
CASE(PL)
CASE(VS)
CASE(VC)
CASE(HI)
CASE(LS)
CASE(GE)
CASE(LT)
CASE(GT)
CASE(LE)
case Condition::AL: {
return "";
}
}
#undef CASE
return "";
}
class Psr {
public:
// clear the reserved bits i.e, [8:27]
Psr(uint32_t raw);
uint32_t raw() const;
void set_all(uint32_t raw);
// Mode : [4:0]
Mode mode() const;
void set_mode(Mode mode);
// State : [5]
State state() const;
void set_state(State state);
#define GET_SET_NTH_BIT_FUNCTIONS(name) \
bool name() const; \
void set_##name(bool val);
// FIQ disable : [6]
GET_SET_NTH_BIT_FUNCTIONS(fiq_disabled)
// IRQ disable : [7]
GET_SET_NTH_BIT_FUNCTIONS(irq_disabled)
// Reserved bits : [27:8]
// Overflow flag : [28]
GET_SET_NTH_BIT_FUNCTIONS(v)
// Carry flag : [29]
GET_SET_NTH_BIT_FUNCTIONS(c)
// Zero flag : [30]
GET_SET_NTH_BIT_FUNCTIONS(z)
// Negative flag : [30]
GET_SET_NTH_BIT_FUNCTIONS(n)
#undef GET_SET_NTH_BIT_FUNCTIONS
bool condition(Condition cond) const;
private:
static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
static constexpr uint32_t PSR_CLEAR_MODE = 0xFFFFFFE0;
uint32_t psr;
};
}

2
src/cpu/thumb/disassembler.cc
View File

@@ -1,4 +1,4 @@
#include "instruction.hh"
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
namespace matar::thumb {

5
src/cpu/thumb/exec.cc
View File

@@ -1,11 +1,10 @@
#include "cpu/cpu-impl.hh"
#include "instruction.hh"
#include "cpu/cpu.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar::thumb {
void
Instruction::exec(CpuImpl& cpu) {
Instruction::exec(Cpu& cpu) {
auto set_cc = [&cpu](bool c, bool v, bool n, bool z) {
cpu.cpsr.set_c(c);
cpu.cpsr.set_v(v);

2
src/cpu/thumb/instruction.cc
View File

@@ -1,4 +1,4 @@
#include "instruction.hh"
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include "util/log.hh"

291
src/cpu/thumb/instruction.hh
View File

@@ -1,291 +0,0 @@
#pragma once
#include "cpu/alu.hh"
#include "cpu/psr.hh"
#include <cstdint>
#include <fmt/ostream.h>
#include <variant>
namespace matar {
class CpuImpl;
namespace thumb {
// https://en.cppreference.com/w/cpp/utility/variant/visit
template<class... Ts>
struct overloaded : Ts... {
using Ts::operator()...;
};
template<class... Ts>
overloaded(Ts...) -> overloaded<Ts...>;
static constexpr size_t INSTRUCTION_SIZE = 2;
static constexpr uint8_t LO_GPR_COUNT = 8;
struct MoveShiftedRegister {
uint8_t rd;
uint8_t rs;
uint8_t offset;
ShiftType opcode;
};
struct AddSubtract {
enum class OpCode {
ADD = 0,
SUB = 1
};
uint8_t rd;
uint8_t rs;
uint8_t offset;
OpCode opcode;
bool imm;
};
constexpr auto
stringify(AddSubtract::OpCode opcode) {
#define CASE(opcode) \
case AddSubtract::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(ADD)
CASE(SUB)
}
#undef CASE
return "";
}
struct MovCmpAddSubImmediate {
enum class OpCode {
MOV = 0b00,
CMP = 0b01,
ADD = 0b10,
SUB = 0b11
};
uint8_t offset;
uint8_t rd;
OpCode opcode;
};
constexpr auto
stringify(MovCmpAddSubImmediate::OpCode opcode) {
#define CASE(opcode) \
case MovCmpAddSubImmediate::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(MOV)
CASE(CMP)
CASE(ADD)
CASE(SUB)
}
#undef CASE
return "";
}
struct AluOperations {
enum class OpCode {
AND = 0b0000,
EOR = 0b0001,
LSL = 0b0010,
LSR = 0b0011,
ASR = 0b0100,
ADC = 0b0101,
SBC = 0b0110,
ROR = 0b0111,
TST = 0b1000,
NEG = 0b1001,
CMP = 0b1010,
CMN = 0b1011,
ORR = 0b1100,
MUL = 0b1101,
BIC = 0b1110,
MVN = 0b1111
};
uint8_t rd;
uint8_t rs;
OpCode opcode;
};
constexpr auto
stringify(AluOperations::OpCode opcode) {
#define CASE(opcode) \
case AluOperations::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(LSL)
CASE(LSR)
CASE(ASR)
CASE(ADC)
CASE(SBC)
CASE(ROR)
CASE(TST)
CASE(NEG)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MUL)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return "";
}
struct HiRegisterOperations {
enum class OpCode {
ADD = 0b00,
CMP = 0b01,
MOV = 0b10,
BX = 0b11
};
uint8_t rd;
uint8_t rs;
OpCode opcode;
};
constexpr auto
stringify(HiRegisterOperations::OpCode opcode) {
#define CASE(opcode) \
case HiRegisterOperations::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(ADD)
CASE(CMP)
CASE(MOV)
CASE(BX)
}
#undef CASE
return "";
}
struct PcRelativeLoad {
uint16_t word;
uint8_t rd;
};
struct LoadStoreRegisterOffset {
uint8_t rd;
uint8_t rb;
uint8_t ro;
bool byte;
bool load;
};
struct LoadStoreSignExtendedHalfword {
uint8_t rd;
uint8_t rb;
uint8_t ro;
bool s;
bool h;
};
struct LoadStoreImmediateOffset {
uint8_t rd;
uint8_t rb;
uint8_t offset;
bool load;
bool byte;
};
struct LoadStoreHalfword {
uint8_t rd;
uint8_t rb;
uint8_t offset;
bool load;
};
struct SpRelativeLoad {
uint16_t word;
uint8_t rd;
bool load;
};
struct LoadAddress {
uint16_t word;
uint8_t rd;
bool sp;
};
struct AddOffsetStackPointer {
int16_t word;
};
struct PushPopRegister {
uint8_t regs;
bool pclr;
bool load;
};
struct MultipleLoad {
uint8_t regs;
uint8_t rb;
bool load;
};
struct ConditionalBranch {
int32_t offset;
Condition condition;
};
struct SoftwareInterrupt {
uint8_t vector;
};
struct UnconditionalBranch {
int32_t offset;
};
struct LongBranchWithLink {
uint16_t offset;
bool high;
};
using InstructionData = std::variant<MoveShiftedRegister,
AddSubtract,
MovCmpAddSubImmediate,
AluOperations,
HiRegisterOperations,
PcRelativeLoad,
LoadStoreRegisterOffset,
LoadStoreSignExtendedHalfword,
LoadStoreImmediateOffset,
LoadStoreHalfword,
SpRelativeLoad,
LoadAddress,
AddOffsetStackPointer,
PushPopRegister,
MultipleLoad,
ConditionalBranch,
SoftwareInterrupt,
UnconditionalBranch,
LongBranchWithLink>;
struct Instruction {
Instruction(uint16_t insn);
Instruction(InstructionData data)
: data(data) {}
void exec(CpuImpl& cpu);
#ifdef DISASSEMBLER
std::string disassemble(uint32_t pc = 0);
#endif
InstructionData data;
};
}
}

81
src/memory.cc
View File

@@ -34,64 +34,55 @@ Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
glogger.info("Cartridge Title: {}", header.title);
};
#define MATCHES(area) address >= area##_START&& address <= area##_END
uint8_t
Memory::read(size_t address) const {
if (MATCHES(BIOS)) {
return bios[address];
} else if (MATCHES(BOARD_WRAM)) {
return board_wram[address - BOARD_WRAM_START];
} else if (MATCHES(CHIP_WRAM)) {
return chip_wram[address - CHIP_WRAM_START];
} else if (MATCHES(PALETTE_RAM)) {
return palette_ram[address - PALETTE_RAM_START];
} else if (MATCHES(VRAM)) {
return vram[address - VRAM_START];
} else if (MATCHES(OAM_OBJ_ATTR)) {
return oam_obj_attr[address - OAM_OBJ_ATTR_START];
} else if (MATCHES(ROM_0)) {
return rom[address - ROM_0_START];
} else if (MATCHES(ROM_1)) {
return rom[address - ROM_1_START];
} else if (MATCHES(ROM_2)) {
return rom[address - ROM_2_START];
} else {
glogger.error("Invalid memory region accessed");
return 0xFF;
}
#define MATCHES(AREA, area) \
if (address >= AREA##_START && address < AREA##_START + area.size()) \
return area[address - AREA##_START];
MATCHES(BIOS, bios)
MATCHES(BOARD_WRAM, board_wram)
MATCHES(CHIP_WRAM, chip_wram)
MATCHES(PALETTE_RAM, palette_ram)
MATCHES(VRAM, vram)
MATCHES(OAM_OBJ_ATTR, oam_obj_attr)
MATCHES(ROM_0, rom)
MATCHES(ROM_1, rom)
MATCHES(ROM_2, rom)
glogger.error("Invalid memory region accessed");
return 0xFF;
#undef MATCHES
}
void
Memory::write(size_t address, uint8_t byte) {
if (MATCHES(BIOS)) {
bios[address] = byte;
} else if (MATCHES(BOARD_WRAM)) {
board_wram[address - BOARD_WRAM_START] = byte;
} else if (MATCHES(CHIP_WRAM)) {
chip_wram[address - CHIP_WRAM_START] = byte;
} else if (MATCHES(PALETTE_RAM)) {
palette_ram[address - PALETTE_RAM_START] = byte;
} else if (MATCHES(VRAM)) {
vram[address - VRAM_START] = byte;
} else if (MATCHES(OAM_OBJ_ATTR)) {
oam_obj_attr[address - OAM_OBJ_ATTR_START] = byte;
} else if (MATCHES(ROM_0)) {
rom[address - ROM_0_START] = byte;
} else if (MATCHES(ROM_1)) {
rom[address - ROM_1_START] = byte;
} else if (MATCHES(ROM_2)) {
rom[address - ROM_2_START] = byte;
} else {
glogger.error("Invalid memory region accessed");
#define MATCHES(AREA, area) \
if (address >= AREA##_START && address < AREA##_START + area.size()) { \
area[address - AREA##_START] = byte; \
return; \
}
MATCHES(BIOS, bios)
MATCHES(BOARD_WRAM, board_wram)
MATCHES(CHIP_WRAM, chip_wram)
MATCHES(PALETTE_RAM, palette_ram)
MATCHES(VRAM, vram)
MATCHES(OAM_OBJ_ATTR, oam_obj_attr)
MATCHES(ROM_0, rom)
MATCHES(ROM_1, rom)
MATCHES(ROM_2, rom)
glogger.error("Invalid memory region accessed");
#undef MATCHES
}
#undef MATCHES
void
Memory::parse_header() {
if (rom.size() < header.HEADER_SIZE) {
throw std::out_of_range(
"ROM is not large enough to even have a header");