refactor: reorganize everything

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

include/cpu/alu.hh

@@ -0,0 +1,53 @@
+#pragma once
+#include <cstdint>
+#include <fmt/ostream.h>
+
+namespace matar {
+enum class ShiftType {
+    LSL = 0b00,
+    LSR = 0b01,
+    ASR = 0b10,
+    ROR = 0b11
+};
+
+constexpr auto
+stringify(ShiftType shift_type) {
+#define CASE(type)                                                             \
+    case ShiftType::type:                                                      \
+        return #type;
+
+    switch (shift_type) {
+        CASE(LSL)
+        CASE(LSR)
+        CASE(ASR)
+        CASE(ROR)
+    }
+
+#undef CASE
+
+    return "";
+}
+
+struct ShiftData {
+    ShiftType type;
+    bool immediate;
+    uint8_t operand;
+};
+
+struct Shift {
+    uint8_t rm;
+    ShiftData data;
+};
+
+uint32_t
+eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry);
+
+uint32_t
+sub(uint32_t a, uint32_t b, bool& carry, bool& overflow);
+
+uint32_t
+add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
+
+uint32_t
+sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
+}

include/cpu/arm/instruction.hh

@@ -0,0 +1,230 @@
+#pragma once
+#include "cpu/alu.hh"
+#include "cpu/psr.hh"
+#include <cstdint>
+#include <fmt/ostream.h>
+#include <variant>
+
+namespace matar {
+class Cpu;
+
+namespace arm {
+
+// https://en.cppreference.com/w/cpp/utility/variant/visit
+template<class... Ts>
+struct overloaded : Ts... {
+    using Ts::operator()...;
+};
+template<class... Ts>
+overloaded(Ts...) -> overloaded<Ts...>;
+
+static constexpr size_t INSTRUCTION_SIZE = 4;
+
+struct BranchAndExchange {
+    uint8_t rn;
+};
+
+struct Branch {
+    bool link;
+    uint32_t offset;
+};
+
+struct Multiply {
+    uint8_t rm;
+    uint8_t rs;
+    uint8_t rn;
+    uint8_t rd;
+    bool set;
+    bool acc;
+};
+
+struct MultiplyLong {
+    uint8_t rm;
+    uint8_t rs;
+    uint8_t rdlo;
+    uint8_t rdhi;
+    bool set;
+    bool acc;
+    bool uns;
+};
+
+struct SingleDataSwap {
+    uint8_t rm;
+    uint8_t rd;
+    uint8_t rn;
+    bool byte;
+};
+
+struct SingleDataTransfer {
+    std::variant<uint16_t, Shift> offset;
+    uint8_t rd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool byte;
+    bool up;
+    bool pre;
+};
+
+struct HalfwordTransfer {
+    uint8_t offset;
+    bool half;
+    bool sign;
+    uint8_t rd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool imm;
+    bool up;
+    bool pre;
+};
+
+struct BlockDataTransfer {
+    uint16_t regs;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool s;
+    bool up;
+    bool pre;
+};
+
+struct DataProcessing {
+    enum class OpCode {
+        AND = 0b0000,
+        EOR = 0b0001,
+        SUB = 0b0010,
+        RSB = 0b0011,
+        ADD = 0b0100,
+        ADC = 0b0101,
+        SBC = 0b0110,
+        RSC = 0b0111,
+        TST = 0b1000,
+        TEQ = 0b1001,
+        CMP = 0b1010,
+        CMN = 0b1011,
+        ORR = 0b1100,
+        MOV = 0b1101,
+        BIC = 0b1110,
+        MVN = 0b1111
+    };
+
+    std::variant<Shift, uint32_t> operand;
+    uint8_t rd;
+    uint8_t rn;
+    bool set;
+    OpCode opcode;
+};
+
+constexpr auto
+stringify(DataProcessing::OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case DataProcessing::OpCode::opcode:                                       \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(SUB)
+        CASE(RSB)
+        CASE(ADD)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(RSC)
+        CASE(TST)
+        CASE(TEQ)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MOV)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+
+    return "";
+}
+
+struct PsrTransfer {
+    enum class Type {
+        Mrs,
+        Msr,
+        Msr_flg
+    };
+
+    uint32_t operand;
+    bool spsr;
+    Type type;
+    // ignored outside MSR_flg
+    bool imm;
+};
+
+struct CoprocessorDataTransfer {
+    uint8_t offset;
+    uint8_t cpn;
+    uint8_t crd;
+    uint8_t rn;
+    bool load;
+    bool write;
+    bool len;
+    bool up;
+    bool pre;
+};
+
+struct CoprocessorDataOperation {
+    uint8_t crm;
+    uint8_t cp;
+    uint8_t cpn;
+    uint8_t crd;
+    uint8_t crn;
+    uint8_t cp_opc;
+};
+
+struct CoprocessorRegisterTransfer {
+    uint8_t crm;
+    uint8_t cp;
+    uint8_t cpn;
+    uint8_t rd;
+    uint8_t crn;
+    bool load;
+    uint8_t cp_opc;
+};
+
+struct Undefined {};
+struct SoftwareInterrupt {};
+
+using InstructionData = std::variant<BranchAndExchange,
+                                     Branch,
+                                     Multiply,
+                                     MultiplyLong,
+                                     SingleDataSwap,
+                                     SingleDataTransfer,
+                                     HalfwordTransfer,
+                                     BlockDataTransfer,
+                                     DataProcessing,
+                                     PsrTransfer,
+                                     CoprocessorDataTransfer,
+                                     CoprocessorDataOperation,
+                                     CoprocessorRegisterTransfer,
+                                     Undefined,
+                                     SoftwareInterrupt>;
+
+struct Instruction {
+    Instruction(uint32_t insn);
+    Instruction(Condition condition, InstructionData data)
+      : condition(condition)
+      , data(data){};
+
+    void exec(Cpu& cpu);
+
+#ifdef DISASSEMBLER
+    std::string disassemble();
+#endif
+
+    Condition condition;
+    InstructionData data;
+};
+}
+}

include/cpu/arm/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh'
+)

include/cpu/cpu.hh

@@ -1,21 +1,70 @@
+#pragma once
+
+#include "arm/instruction.hh"
 #include "bus.hh"
+#include "cpu/psr.hh"
+#include "thumb/instruction.hh"
+
+#include <cstdint>
 
 namespace matar {
-class CpuImpl;
-
 class Cpu {
   public:
     Cpu(const Bus& bus) noexcept;
-    Cpu(const Cpu&)            = delete;
-    Cpu(Cpu&&)                 = delete;
-    Cpu& operator=(const Cpu&) = delete;
-    Cpu& operator=(Cpu&&)      = delete;
-
-    ~Cpu();
 
     void step();
+    void chg_mode(const Mode to);
 
   private:
-    std::unique_ptr<CpuImpl> impl;
+    friend void arm::Instruction::exec(Cpu& cpu);
+    friend void thumb::Instruction::exec(Cpu& cpu);
+
+    static constexpr uint8_t GPR_COUNT = 16;
+
+    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
+    static constexpr uint8_t GPR_SVC_FIRST     = 13;
+    static constexpr uint8_t GPR_ABT_FIRST     = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
+    static constexpr uint8_t GPR_UND_FIRST     = 13;
+    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+
+    Psr cpsr; // current program status register
+    Psr spsr; // status program status register
+
+    static constexpr uint8_t SP_INDEX = 13;
+    static_assert(SP_INDEX < GPR_COUNT);
+    uint32_t& sp = gpr[SP_INDEX];
+
+    static constexpr uint8_t LR_INDEX = 14;
+    static_assert(LR_INDEX < GPR_COUNT);
+    uint32_t& lr = gpr[LR_INDEX];
+
+    static constexpr uint8_t PC_INDEX = 15;
+    static_assert(PC_INDEX < GPR_COUNT);
+    uint32_t& pc = gpr[PC_INDEX];
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
+    } gpr_banked; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked; // banked saved program status registers
+
+    bool is_flushed;
 };
 }

include/cpu/meson.build

@@ -1,3 +1,8 @@
 headers += files(
+  'alu.hh',
   'cpu.hh',
-)
+  'psr.hh'
+)
+
+subdir('arm')
+subdir('thumb')

include/cpu/psr.hh

@@ -0,0 +1,123 @@
+#pragma once
+
+#include <cstdint>
+#include <fmt/ostream.h>
+
+namespace matar {
+enum class Mode {
+    /* M[4:0] in PSR */
+    User       = 0b10000,
+    Fiq        = 0b10001,
+    Irq        = 0b10010,
+    Supervisor = 0b10011,
+    Abort      = 0b10111,
+    Undefined  = 0b11011,
+    System     = 0b11111,
+};
+
+enum class State {
+    Arm   = 0,
+    Thumb = 1
+};
+
+enum class Condition {
+    EQ = 0b0000,
+    NE = 0b0001,
+    CS = 0b0010,
+    CC = 0b0011,
+    MI = 0b0100,
+    PL = 0b0101,
+    VS = 0b0110,
+    VC = 0b0111,
+    HI = 0b1000,
+    LS = 0b1001,
+    GE = 0b1010,
+    LT = 0b1011,
+    GT = 0b1100,
+    LE = 0b1101,
+    AL = 0b1110
+};
+
+constexpr auto
+stringify(Condition cond) {
+
+#define CASE(cond)                                                             \
+    case Condition::cond:                                                      \
+        return #cond;
+
+    switch (cond) {
+        CASE(EQ)
+        CASE(NE)
+        CASE(CS)
+        CASE(CC)
+        CASE(MI)
+        CASE(PL)
+        CASE(VS)
+        CASE(VC)
+        CASE(HI)
+        CASE(LS)
+        CASE(GE)
+        CASE(LT)
+        CASE(GT)
+        CASE(LE)
+        case Condition::AL: {
+            return "";
+        }
+    }
+
+#undef CASE
+
+    return "";
+}
+
+class Psr {
+  public:
+    // clear the reserved bits i.e, [8:27]
+    Psr(uint32_t raw);
+
+    uint32_t raw() const;
+    void set_all(uint32_t raw);
+
+    // Mode : [4:0]
+    Mode mode() const;
+    void set_mode(Mode mode);
+
+    // State : [5]
+    State state() const;
+    void set_state(State state);
+
+#define GET_SET_NTH_BIT_FUNCTIONS(name)                                        \
+    bool name() const;                                                         \
+    void set_##name(bool val);
+
+    // FIQ disable : [6]
+    GET_SET_NTH_BIT_FUNCTIONS(fiq_disabled)
+
+    // IRQ disable : [7]
+    GET_SET_NTH_BIT_FUNCTIONS(irq_disabled)
+
+    // Reserved bits : [27:8]
+
+    // Overflow flag : [28]
+    GET_SET_NTH_BIT_FUNCTIONS(v)
+
+    // Carry flag : [29]
+    GET_SET_NTH_BIT_FUNCTIONS(c)
+
+    // Zero flag : [30]
+    GET_SET_NTH_BIT_FUNCTIONS(z)
+
+    // Negative flag : [30]
+    GET_SET_NTH_BIT_FUNCTIONS(n)
+
+#undef GET_SET_NTH_BIT_FUNCTIONS
+
+    bool condition(Condition cond) const;
+
+  private:
+    static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
+    static constexpr uint32_t PSR_CLEAR_MODE     = 0xFFFFFFE0;
+
+    uint32_t psr;
+};
+}

include/cpu/thumb/instruction.hh

@@ -0,0 +1,291 @@
+#pragma once
+
+#include "cpu/alu.hh"
+#include "cpu/psr.hh"
+#include <cstdint>
+#include <fmt/ostream.h>
+#include <variant>
+
+namespace matar {
+class Cpu;
+
+namespace thumb {
+
+// https://en.cppreference.com/w/cpp/utility/variant/visit
+template<class... Ts>
+struct overloaded : Ts... {
+    using Ts::operator()...;
+};
+template<class... Ts>
+overloaded(Ts...) -> overloaded<Ts...>;
+
+static constexpr size_t INSTRUCTION_SIZE = 2;
+static constexpr uint8_t LO_GPR_COUNT    = 8;
+
+struct MoveShiftedRegister {
+    uint8_t rd;
+    uint8_t rs;
+    uint8_t offset;
+    ShiftType opcode;
+};
+
+struct AddSubtract {
+    enum class OpCode {
+        ADD = 0,
+        SUB = 1
+    };
+
+    uint8_t rd;
+    uint8_t rs;
+    uint8_t offset;
+    OpCode opcode;
+    bool imm;
+};
+
+constexpr auto
+stringify(AddSubtract::OpCode opcode) {
+#define CASE(opcode)                                                           \
+    case AddSubtract::OpCode::opcode:                                          \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(ADD)
+        CASE(SUB)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct MovCmpAddSubImmediate {
+    enum class OpCode {
+        MOV = 0b00,
+        CMP = 0b01,
+        ADD = 0b10,
+        SUB = 0b11
+    };
+
+    uint8_t offset;
+    uint8_t rd;
+    OpCode opcode;
+};
+
+constexpr auto
+stringify(MovCmpAddSubImmediate::OpCode opcode) {
+#define CASE(opcode)                                                           \
+    case MovCmpAddSubImmediate::OpCode::opcode:                                \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(MOV)
+        CASE(CMP)
+        CASE(ADD)
+        CASE(SUB)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct AluOperations {
+    enum class OpCode {
+        AND = 0b0000,
+        EOR = 0b0001,
+        LSL = 0b0010,
+        LSR = 0b0011,
+        ASR = 0b0100,
+        ADC = 0b0101,
+        SBC = 0b0110,
+        ROR = 0b0111,
+        TST = 0b1000,
+        NEG = 0b1001,
+        CMP = 0b1010,
+        CMN = 0b1011,
+        ORR = 0b1100,
+        MUL = 0b1101,
+        BIC = 0b1110,
+        MVN = 0b1111
+    };
+
+    uint8_t rd;
+    uint8_t rs;
+    OpCode opcode;
+};
+
+constexpr auto
+stringify(AluOperations::OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case AluOperations::OpCode::opcode:                                        \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(LSL)
+        CASE(LSR)
+        CASE(ASR)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(ROR)
+        CASE(TST)
+        CASE(NEG)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MUL)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct HiRegisterOperations {
+    enum class OpCode {
+        ADD = 0b00,
+        CMP = 0b01,
+        MOV = 0b10,
+        BX  = 0b11
+    };
+
+    uint8_t rd;
+    uint8_t rs;
+    OpCode opcode;
+};
+
+constexpr auto
+stringify(HiRegisterOperations::OpCode opcode) {
+#define CASE(opcode)                                                           \
+    case HiRegisterOperations::OpCode::opcode:                                 \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(ADD)
+        CASE(CMP)
+        CASE(MOV)
+        CASE(BX)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct PcRelativeLoad {
+    uint16_t word;
+    uint8_t rd;
+};
+
+struct LoadStoreRegisterOffset {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t ro;
+    bool byte;
+    bool load;
+};
+
+struct LoadStoreSignExtendedHalfword {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t ro;
+    bool s;
+    bool h;
+};
+
+struct LoadStoreImmediateOffset {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t offset;
+    bool load;
+    bool byte;
+};
+
+struct LoadStoreHalfword {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t offset;
+    bool load;
+};
+
+struct SpRelativeLoad {
+    uint16_t word;
+    uint8_t rd;
+    bool load;
+};
+
+struct LoadAddress {
+    uint16_t word;
+    uint8_t rd;
+    bool sp;
+};
+
+struct AddOffsetStackPointer {
+    int16_t word;
+};
+
+struct PushPopRegister {
+    uint8_t regs;
+    bool pclr;
+    bool load;
+};
+
+struct MultipleLoad {
+    uint8_t regs;
+    uint8_t rb;
+    bool load;
+};
+
+struct ConditionalBranch {
+    int32_t offset;
+    Condition condition;
+};
+
+struct SoftwareInterrupt {
+    uint8_t vector;
+};
+
+struct UnconditionalBranch {
+    int32_t offset;
+};
+
+struct LongBranchWithLink {
+    uint16_t offset;
+    bool high;
+};
+
+using InstructionData = std::variant<MoveShiftedRegister,
+                                     AddSubtract,
+                                     MovCmpAddSubImmediate,
+                                     AluOperations,
+                                     HiRegisterOperations,
+                                     PcRelativeLoad,
+                                     LoadStoreRegisterOffset,
+                                     LoadStoreSignExtendedHalfword,
+                                     LoadStoreImmediateOffset,
+                                     LoadStoreHalfword,
+                                     SpRelativeLoad,
+                                     LoadAddress,
+                                     AddOffsetStackPointer,
+                                     PushPopRegister,
+                                     MultipleLoad,
+                                     ConditionalBranch,
+                                     SoftwareInterrupt,
+                                     UnconditionalBranch,
+                                     LongBranchWithLink>;
+
+struct Instruction {
+    Instruction(uint16_t insn);
+    Instruction(InstructionData data)
+      : data(data) {}
+
+    void exec(Cpu& cpu);
+
+#ifdef DISASSEMBLER
+    std::string disassemble(uint32_t pc = 0);
+#endif
+
+    InstructionData data;
+};
+}
+}

include/cpu/thumb/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh'
+)