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bus (feat): add cycle accuracy

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Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2024-06-15 03:49:10 +05:30
parent cb75ebf8ef
commit c22333812e
9 changed files with 657 additions and 108 deletions
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3
include/cpu/alu.hh
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@@ -49,4 +49,7 @@ add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
uint32_t
sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
uint8_t
multiplier_array_cycles(uint32_t x, bool zeroes_only = false);
}

38
include/cpu/cpu.hh
View File

@@ -16,6 +16,23 @@ class Cpu {
void step();
void chg_mode(const Mode to);
bool is_flushed = false;
inline void flush_pipeline() {
is_flushed = true;
if (cpsr.state() == State::Arm) {
opcodes[0] = bus->read_word(pc, false);
advance_pc_arm();
opcodes[1] = bus->read_word(pc);
advance_pc_arm();
} else {
opcodes[0] = bus->read_halfword(pc, false);
advance_pc_thumb();
opcodes[1] = bus->read_halfword(pc);
advance_pc_thumb();
}
sequential = true;
};
private:
friend void arm::Instruction::exec(Cpu& cpu);
friend void thumb::Instruction::exec(Cpu& cpu);
@@ -66,26 +83,15 @@ class Cpu {
Psr und;
} spsr_banked = {}; // banked saved program status registers
inline void internal_cycle() { bus->internal_cycle(); }
// whether read is going to be sequential or not
bool sequential = true;
// raw instructions in the pipeline
std::array<uint32_t, 2> opcodes = {};
inline void advance_pc_arm() { pc += arm::INSTRUCTION_SIZE; };
inline void advance_pc_thumb() { pc += thumb::INSTRUCTION_SIZE; }
bool is_flushed = false;
inline void flush_pipeline() {
is_flushed = true;
if (cpsr.state() == State::Arm) {
opcodes[0] = bus->read_word(pc);
advance_pc_arm();
opcodes[1] = bus->read_word(pc);
advance_pc_arm();
} else {
opcodes[0] = bus->read_halfword(pc);
advance_pc_thumb();
opcodes[1] = bus->read_halfword(pc);
advance_pc_thumb();
}
};
};
}