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bus (feat): add cycle accuracy

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Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2024-06-15 03:49:10 +05:30
parent cb75ebf8ef
commit c22333812e
9 changed files with 657 additions and 108 deletions
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38
include/bus.hh
View File

@@ -5,6 +5,7 @@
#include <memory>
#include <optional>
#include <span>
#include <unordered_map>
#include <vector>
namespace matar {
@@ -22,14 +23,19 @@ class Bus {
static std::shared_ptr<Bus> init(std::array<uint8_t, BIOS_SIZE>&&,
std::vector<uint8_t>&&);
uint8_t read_byte(uint32_t);
void write_byte(uint32_t, uint8_t);
uint8_t read_byte(uint32_t, bool = true);
void write_byte(uint32_t, uint8_t, bool = true);
uint16_t read_halfword(uint32_t);
void write_halfword(uint32_t, uint16_t);
uint16_t read_halfword(uint32_t, bool = true);
void write_halfword(uint32_t, uint16_t, bool = true);
uint32_t read_word(uint32_t);
void write_word(uint32_t, uint32_t);
uint32_t read_word(uint32_t, bool = true);
void write_word(uint32_t, uint32_t, bool = true);
// not sure what else to do?
inline void internal_cycle() { cycles++; }
inline uint32_t get_cycles() { return cycles; }
private:
template<unsigned int>
@@ -38,9 +44,21 @@ class Bus {
template<unsigned int>
std::optional<std::span<uint8_t>> write(uint32_t);
uint32_t cycles = 0;
struct cycle_count {
uint8_t n16; // non sequential 8/16 bit width access
uint8_t n32; // non sequential 32 bit width access
uint8_t s16; // seuquential 8/16 bit width access
uint8_t s32; // sequential 32 bit width access
};
std::array<cycle_count, 0x10> cycle_map;
static constexpr decltype(cycle_map) init_cycle_count();
std::unique_ptr<IoDevices> io;
#define MEMORY_REGION(name, start) \
static constexpr uint32_t name##_START = start; \
static constexpr uint8_t name##_REGION = start >> 24 & 0xFF;
static constexpr uint8_t name##_REGION = start >> 24 & 0xF;
#define DECL_MEMORY(name, ident, start, end) \
MEMORY_REGION(name, start) \
@@ -70,12 +88,12 @@ class Bus {
MEMORY_REGION(ROM_1, 0x0A000000)
MEMORY_REGION(ROM_2, 0x0C000000)
MEMORY_REGION(IO, 0x04000000)
static constexpr uint32_t IO_END = 0x040003FE;
#undef MEMORY_REGION
std::vector<uint8_t> rom;
std::unique_ptr<IoDevices> io;
Header header;
void parse_header();
};

3
include/cpu/alu.hh
View File

@@ -49,4 +49,7 @@ add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
uint32_t
sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
uint8_t
multiplier_array_cycles(uint32_t x, bool zeroes_only = false);
}

38
include/cpu/cpu.hh
View File

@@ -16,6 +16,23 @@ class Cpu {
void step();
void chg_mode(const Mode to);
bool is_flushed = false;
inline void flush_pipeline() {
is_flushed = true;
if (cpsr.state() == State::Arm) {
opcodes[0] = bus->read_word(pc, false);
advance_pc_arm();
opcodes[1] = bus->read_word(pc);
advance_pc_arm();
} else {
opcodes[0] = bus->read_halfword(pc, false);
advance_pc_thumb();
opcodes[1] = bus->read_halfword(pc);
advance_pc_thumb();
}
sequential = true;
};
private:
friend void arm::Instruction::exec(Cpu& cpu);
friend void thumb::Instruction::exec(Cpu& cpu);
@@ -66,26 +83,15 @@ class Cpu {
Psr und;
} spsr_banked = {}; // banked saved program status registers
inline void internal_cycle() { bus->internal_cycle(); }
// whether read is going to be sequential or not
bool sequential = true;
// raw instructions in the pipeline
std::array<uint32_t, 2> opcodes = {};
inline void advance_pc_arm() { pc += arm::INSTRUCTION_SIZE; };
inline void advance_pc_thumb() { pc += thumb::INSTRUCTION_SIZE; }
bool is_flushed = false;
inline void flush_pipeline() {
is_flushed = true;
if (cpsr.state() == State::Arm) {
opcodes[0] = bus->read_word(pc);
advance_pc_arm();
opcodes[1] = bus->read_word(pc);
advance_pc_arm();
} else {
opcodes[0] = bus->read_halfword(pc);
advance_pc_thumb();
opcodes[1] = bus->read_halfword(pc);
advance_pc_thumb();
}
};
};
}