tests: [WIP] add unit tests for some of the instructions
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
@@ -116,27 +116,29 @@ Cpu::chg_mode(const Mode to) {
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}
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void
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Cpu::exec_arm(const ArmInstruction instruction) {
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auto cond = instruction.get_condition();
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auto data = instruction.get_data();
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Cpu::exec_arm(const arm::ArmInstruction instruction) {
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auto cond = instruction.condition;
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auto data = instruction.data;
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if (!cpsr.condition(cond)) {
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return;
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}
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auto pc_error = [](uint8_t r) {
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if (r == 15)
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if (r == PC_INDEX)
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log_error("Using PC (R15) as operand register");
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};
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auto pc_warn = [](uint8_t r) {
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if (r == 15)
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if (r == PC_INDEX)
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log_warn("Using PC (R15) as operand register");
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};
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using namespace arm;
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std::visit(
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overloaded{
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[this, pc_warn](ArmInstruction::BranchAndExchange& data) {
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[this, pc_warn](BranchAndExchange& data) {
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State state = static_cast<State>(data.rn & 1);
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pc_warn(data.rn);
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@@ -156,7 +158,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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// pc is affected so flush the pipeline
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is_flushed = true;
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},
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[this](ArmInstruction::Branch& data) {
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[this](Branch& data) {
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if (data.link)
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gpr[14] = pc - ARM_INSTRUCTION_SIZE;
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@@ -168,7 +170,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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// pc is affected so flush the pipeline
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is_flushed = true;
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},
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[this, pc_error](ArmInstruction::Multiply& data) {
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[this, pc_error](Multiply& data) {
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if (data.rd == data.rm)
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log_error("rd and rm are not distinct in {}",
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typeid(data).name());
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@@ -186,7 +188,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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cpsr.set_c(0);
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}
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},
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[this, pc_error](ArmInstruction::MultiplyLong& data) {
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[this, pc_error](MultiplyLong& data) {
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if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
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data.rdlo == data.rm)
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log_error("rdhi, rdlo and rm are not distinct in {}",
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@@ -226,8 +228,8 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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cpsr.set_v(0);
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}
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},
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[](ArmInstruction::Undefined) { log_warn("Undefined instruction"); },
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[this, pc_error](ArmInstruction::SingleDataSwap& data) {
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[](Undefined) { log_warn("Undefined instruction"); },
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[this, pc_error](SingleDataSwap& data) {
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pc_error(data.rm);
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pc_error(data.rn);
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pc_error(data.rd);
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@@ -240,7 +242,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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bus->write_word(gpr[data.rn], gpr[data.rm]);
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}
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},
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[this, pc_warn, pc_error](ArmInstruction::SingleDataTransfer& data) {
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[this, pc_warn, pc_error](SingleDataTransfer& data) {
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uint32_t offset = 0;
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uint32_t address = gpr[data.rn];
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@@ -316,7 +318,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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if (data.rd == PC_INDEX && data.load)
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is_flushed = true;
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},
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[this, pc_warn, pc_error](ArmInstruction::HalfwordTransfer& data) {
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[this, pc_warn, pc_error](HalfwordTransfer& data) {
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uint32_t address = gpr[data.rn];
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if (!data.pre && data.write)
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@@ -345,15 +347,16 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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gpr[data.rd] = bus->read_halfword(address);
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// sign extend the halfword
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if (get_bit(gpr[data.rd], PC_INDEX))
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gpr[data.rd] |= 0xFFFF0000;
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gpr[data.rd] =
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(static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
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// byte
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} else {
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gpr[data.rd] = bus->read_byte(address);
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// sign extend the byte
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if (get_bit(gpr[data.rd], 7))
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gpr[data.rd] |= 0xFFFFFF00;
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gpr[data.rd] =
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(static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
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}
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// unsigned halfword
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} else if (data.half) {
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@@ -379,7 +382,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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if (data.rd == PC_INDEX && data.load)
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is_flushed = true;
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},
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[this, pc_error](ArmInstruction::BlockDataTransfer& data) {
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[this, pc_error](BlockDataTransfer& data) {
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uint32_t address = gpr[data.rn];
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Mode mode = cpsr.mode();
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uint8_t alignment = 4; // word
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@@ -449,7 +452,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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// load back the original mode registers
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chg_mode(mode);
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},
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[this, pc_error](ArmInstruction::PsrTransfer& data) {
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[this, pc_error](PsrTransfer& data) {
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if (data.spsr && cpsr.mode() == Mode::User) {
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log_error("Accessing SPSR in User mode in {}",
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typeid(data).name());
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@@ -458,18 +461,18 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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Psr& psr = data.spsr ? spsr : cpsr;
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switch (data.type) {
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case ArmInstruction::PsrTransfer::Type::Mrs:
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case PsrTransfer::Type::Mrs:
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pc_error(data.operand);
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gpr[data.operand] = psr.raw();
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break;
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case ArmInstruction::PsrTransfer::Type::Msr:
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case PsrTransfer::Type::Msr:
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pc_error(data.operand);
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if (cpsr.mode() != Mode::User) {
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psr.set_all(gpr[data.operand]);
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break;
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}
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case ArmInstruction::PsrTransfer::Type::Msr_flg:
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case PsrTransfer::Type::Msr_flg:
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psr.set_n(get_bit(data.operand, 31));
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psr.set_z(get_bit(data.operand, 30));
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psr.set_c(get_bit(data.operand, 29));
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@@ -477,7 +480,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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break;
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}
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},
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[this, pc_error](ArmInstruction::DataProcessing& data) {
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[this, pc_error](DataProcessing& data) {
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uint32_t op_1 = gpr[data.rn];
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uint32_t op_2 = 0;
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@@ -671,7 +674,7 @@ Cpu::exec_arm(const ArmInstruction instruction) {
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is_flushed = true;
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}
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},
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[this](ArmInstruction::SoftwareInterrupt) {
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[this](SoftwareInterrupt) {
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chg_mode(Mode::Supervisor);
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pc = 0x08;
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spsr = cpsr;
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@@ -690,7 +693,7 @@ Cpu::step() {
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if (cpsr.state() == State::Arm) {
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debug(cur_pc);
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uint32_t x = bus->read_word(cur_pc);
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ArmInstruction instruction(x);
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arm::ArmInstruction instruction(x);
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log_info("{:#034b}", x);
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exec_arm(instruction);
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@@ -336,7 +336,8 @@ ArmInstruction::disassemble() {
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if (*offset == 0) {
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expression = "";
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} else {
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expression = fmt::format(",#{:d}", *offset);
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expression =
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fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
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}
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} else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
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// Shifts are always immediate in single data transfer
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@@ -365,7 +366,8 @@ ArmInstruction::disassemble() {
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if (data.offset == 0) {
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expression = "";
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} else {
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expression = fmt::format(",#{:d}", data.offset);
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expression = fmt::format(
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",{}#{:d}", (data.up ? '+' : '-'), data.offset);
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}
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} else {
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expression =
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