natto1784/matar
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

bus: send a weak ptr to io

Browse Source 
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2024-06-14 20:25:36 +05:30
parent d1df555a6a
commit bafd534671
8 changed files with 121 additions and 94 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
apps/target/main.cc
View File

@@ -87,12 +87,14 @@ main(int argc, const char* argv[]) {
matar::set_log_level(matar::LogLevel::Debug); matar::set_log_level(matar::LogLevel::Debug);
try { try {
std::shared_ptr<matar::Bus> bus( std::shared_ptr<matar::Bus> bus =
new matar::Bus(std::move(bios), std::move(rom))); matar::Bus::init(std::move(bios), std::move(rom));
matar::Cpu cpu(bus); matar::Cpu cpu(bus);
while (true) { while (true) {
cpu.step(); cpu.step();
std::this_thread::sleep_for(std::chrono::seconds(1)); // std::this_thread::sleep_for(std::chrono::milliseconds(10));
} }
} catch (const std::exception& e) { } catch (const std::exception& e) {
std::cerr << "Exception: " << e.what() << std::endl; std::cerr << "Exception: " << e.what() << std::endl;

41
include/bus.hh
View File

@@ -2,41 +2,51 @@
#include "header.hh" #include "header.hh"
#include "io/io.hh" #include "io/io.hh"
#include <memory>
#include <optional> #include <optional>
#include <span> #include <span>
#include <vector> #include <vector>
namespace matar { namespace matar {
class Bus { class Bus {
private:
struct Private {
explicit Private() = default;
};
public: public:
static constexpr uint32_t BIOS_SIZE = 1024 * 16; static constexpr uint32_t BIOS_SIZE = 1024 * 16;
Bus(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
uint8_t read_byte(uint32_t address); Bus(Private, std::array<uint8_t, BIOS_SIZE>&&, std::vector<uint8_t>&&);
void write_byte(uint32_t address, uint8_t byte);
uint16_t read_halfword(uint32_t address); static std::shared_ptr<Bus> init(std::array<uint8_t, BIOS_SIZE>&&,
void write_halfword(uint32_t address, uint16_t halfword); std::vector<uint8_t>&&);
uint32_t read_word(uint32_t address); uint8_t read_byte(uint32_t);
void write_word(uint32_t address, uint32_t word); void write_byte(uint32_t, uint8_t);
uint16_t read_halfword(uint32_t);
void write_halfword(uint32_t, uint16_t);
uint32_t read_word(uint32_t);
void write_word(uint32_t, uint32_t);
private: private:
template<unsigned int N> template<unsigned int>
std::optional<std::span<const uint8_t>> read(uint32_t address) const; std::optional<std::span<const uint8_t>> read(uint32_t) const;
template<unsigned int N> template<unsigned int>
std::optional<std::span<uint8_t>> write(uint32_t address); std::optional<std::span<uint8_t>> write(uint32_t);
#define MEMORY_REGION(name, start) \ #define MEMORY_REGION(name, start) \
static constexpr uint32_t name##_START = start; static constexpr uint32_t name##_START = start;
#define DECL_MEMORY(name, ident, start, end) \ #define DECL_MEMORY(name, ident, start, end) \
MEMORY_REGION(name, start) \ MEMORY_REGION(name, start) \
std::array<uint8_t, end - start + 1> ident; std::array<uint8_t, end - start + 1> ident = {};
MEMORY_REGION(BIOS, 0x00000000) MEMORY_REGION(BIOS, 0x00000000)
std::array<uint8_t, BIOS_SIZE> bios; std::array<uint8_t, BIOS_SIZE> bios = {};
// board working RAM // board working RAM
DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF) DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
@@ -61,9 +71,10 @@ class Bus {
#undef MEMORY_REGION #undef MEMORY_REGION
std::vector<uint8_t> rom; std::vector<uint8_t> rom;
std::unique_ptr<IoDevices> io;
Header header; Header header;
void parse_header(); void parse_header();
IoDevices io;
}; };
} }

8
include/cpu/cpu.hh
View File

@@ -30,10 +30,10 @@ class Cpu {
static constexpr uint8_t GPR_OLD_FIRST = 8; static constexpr uint8_t GPR_OLD_FIRST = 8;
std::shared_ptr<Bus> bus; std::shared_ptr<Bus> bus;
std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers std::array<uint32_t, GPR_COUNT> gpr = {}; // general purpose registers
Psr cpsr; // current program status register Psr cpsr = {}; // current program status register
Psr spsr; // status program status register Psr spsr = {}; // status program status register
static constexpr uint8_t SP_INDEX = 13; static constexpr uint8_t SP_INDEX = 13;
static_assert(SP_INDEX < GPR_COUNT); static_assert(SP_INDEX < GPR_COUNT);
@@ -56,7 +56,7 @@ class Cpu {
// visible registers before the mode switch // visible registers before the mode switch
std::array<uint32_t, GPR_COUNT - GPR_OLD_FIRST - 1> old; std::array<uint32_t, GPR_COUNT - GPR_OLD_FIRST - 1> old;
} gpr_banked; // banked general purpose registers } gpr_banked = {}; // banked general purpose registers
struct { struct {
Psr fiq; Psr fiq;

6
include/io/io.hh
View File

@@ -2,10 +2,14 @@
#include "lcd.hh" #include "lcd.hh"
#include "sound.hh" #include "sound.hh"
#include <cstdint> #include <cstdint>
#include <memory>
namespace matar { namespace matar {
class Bus;
class IoDevices { class IoDevices {
public: public:
IoDevices(std::weak_ptr<Bus>);
uint8_t read_byte(uint32_t) const; uint8_t read_byte(uint32_t) const;
void write_byte(uint32_t, uint8_t); void write_byte(uint32_t, uint8_t);
@@ -28,5 +32,7 @@ class IoDevices {
struct lcd lcd = {}; struct lcd lcd = {};
struct sound sound = {}; struct sound sound = {};
std::weak_ptr<Bus> bus;
}; };
} }

29
src/bus.cc
View File

@@ -7,13 +7,10 @@ namespace matar {
static constexpr uint32_t IO_START = 0x4000000; static constexpr uint32_t IO_START = 0x4000000;
static constexpr uint32_t IO_END = 0x40003FE; static constexpr uint32_t IO_END = 0x40003FE;
Bus::Bus(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom) Bus::Bus(Private,
std::array<uint8_t, BIOS_SIZE>&& bios,
std::vector<uint8_t>&& rom)
: bios(std::move(bios)) : bios(std::move(bios))
, board_wram({ 0 })
, chip_wram({ 0 })
, palette_ram({ 0 })
, vram({ 0 })
, oam_obj_attr({ 0 })
, rom(std::move(rom)) { , rom(std::move(rom)) {
std::string bios_hash = crypto::sha256(this->bios); std::string bios_hash = crypto::sha256(this->bios);
static constexpr std::string_view expected_hash = static constexpr std::string_view expected_hash =
@@ -33,6 +30,14 @@ Bus::Bus(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom)
glogger.info("Cartridge Title: {}", header.title); glogger.info("Cartridge Title: {}", header.title);
}; };
std::shared_ptr<Bus>
Bus::init(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom) {
auto self =
std::make_shared<Bus>(Private(), std::move(bios), std::move(rom));
self->io = std::make_unique<IoDevices>(self);
return self;
}
template<unsigned int N> template<unsigned int N>
std::optional<std::span<const uint8_t>> std::optional<std::span<const uint8_t>>
Bus::read(uint32_t address) const { Bus::read(uint32_t address) const {
@@ -78,7 +83,7 @@ Bus::write(uint32_t address) {
uint8_t uint8_t
Bus::read_byte(uint32_t address) { Bus::read_byte(uint32_t address) {
if (address >= IO_START && address <= IO_END) if (address >= IO_START && address <= IO_END)
return io.read_byte(address); return io->read_byte(address);
auto data = read<1>(address); auto data = read<1>(address);
return data.transform([](auto value) { return value[0]; }).value_or(0xFF); return data.transform([](auto value) { return value[0]; }).value_or(0xFF);
@@ -87,7 +92,7 @@ Bus::read_byte(uint32_t address) {
void void
Bus::write_byte(uint32_t address, uint8_t byte) { Bus::write_byte(uint32_t address, uint8_t byte) {
if (address >= IO_START && address <= IO_END) { if (address >= IO_START && address <= IO_END) {
io.write_byte(address, byte); io->write_byte(address, byte);
return; return;
} }
@@ -103,7 +108,7 @@ Bus::read_halfword(uint32_t address) {
glogger.warn("Reading a non aligned halfword address"); glogger.warn("Reading a non aligned halfword address");
if (address >= IO_START && address <= IO_END) if (address >= IO_START && address <= IO_END)
return io.read_halfword(address); return io->read_halfword(address);
return read<2>(address) return read<2>(address)
.transform([](auto value) { return value[0] | value[1] << 8; }) .transform([](auto value) { return value[0] | value[1] << 8; })
@@ -116,7 +121,7 @@ Bus::write_halfword(uint32_t address, uint16_t halfword) {
glogger.warn("Writing to a non aligned halfword address"); glogger.warn("Writing to a non aligned halfword address");
if (address >= IO_START && address <= IO_END) { if (address >= IO_START && address <= IO_END) {
io.write_halfword(address, halfword); io->write_halfword(address, halfword);
return; return;
} }
@@ -135,7 +140,7 @@ Bus::read_word(uint32_t address) {
glogger.warn("Reading a non aligned word address"); glogger.warn("Reading a non aligned word address");
if (address >= IO_START && address <= IO_END) if (address >= IO_START && address <= IO_END)
return io.read_word(address); return io->read_word(address);
return read<4>(address) return read<4>(address)
.transform([](auto value) { .transform([](auto value) {
@@ -150,7 +155,7 @@ Bus::write_word(uint32_t address, uint32_t word) {
glogger.warn("Writing to a non aligned word address"); glogger.warn("Writing to a non aligned word address");
if (address >= IO_START && address <= IO_END) { if (address >= IO_START && address <= IO_END) {
io.write_word(address, word); io->write_word(address, word);
return; return;
} }

3
src/io/io.cc
View File

@@ -86,6 +86,9 @@ ADDR HALTCNT = 0x4000301;
#undef ADDR #undef ADDR
IoDevices::IoDevices(std::weak_ptr<Bus> bus)
: bus(bus) {}
uint8_t uint8_t
IoDevices::read_byte(uint32_t address) const { IoDevices::read_byte(uint32_t address) const {
uint16_t halfword = read_halfword(address & ~1); uint16_t halfword = read_halfword(address & ~1);

115
tests/bus.cc
View File

@@ -8,11 +8,11 @@ using namespace matar;
class BusFixture { class BusFixture {
public: public:
BusFixture() BusFixture()
: bus(std::array<uint8_t, Bus::BIOS_SIZE>(), : bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
std::vector<uint8_t>(Header::HEADER_SIZE)) {} std::vector<uint8_t>(Header::HEADER_SIZE))) {}
protected: protected:
Bus bus; std::shared_ptr<Bus> bus;
}; };
TEST_CASE("bios", TAG) { TEST_CASE("bios", TAG) {
@@ -23,66 +23,67 @@ TEST_CASE("bios", TAG) {
bios[0x3FFF] = 0x48; bios[0x3FFF] = 0x48;
bios[0x2A56] = 0x10; bios[0x2A56] = 0x10;
Bus bus(std::move(bios), std::vector<uint8_t>(Header::HEADER_SIZE)); auto bus =
Bus::init(std::move(bios), std::vector<uint8_t>(Header::HEADER_SIZE));
CHECK(bus.read_byte(0) == 0xAC); CHECK(bus->read_byte(0) == 0xAC);
CHECK(bus.read_byte(0x3FFF) == 0x48); CHECK(bus->read_byte(0x3FFF) == 0x48);
CHECK(bus.read_byte(0x2A56) == 0x10); CHECK(bus->read_byte(0x2A56) == 0x10);
} }
TEST_CASE_METHOD(BusFixture, "board wram", TAG) { TEST_CASE_METHOD(BusFixture, "board wram", TAG) {
bus.write_byte(0x2000000, 0xAC); bus->write_byte(0x2000000, 0xAC);
CHECK(bus.read_byte(0x2000000) == 0xAC); CHECK(bus->read_byte(0x2000000) == 0xAC);
bus.write_byte(0x203FFFF, 0x48); bus->write_byte(0x203FFFF, 0x48);
CHECK(bus.read_byte(0x203FFFF) == 0x48); CHECK(bus->read_byte(0x203FFFF) == 0x48);
bus.write_byte(0x2022A56, 0x10); bus->write_byte(0x2022A56, 0x10);
CHECK(bus.read_byte(0x2022A56) == 0x10); CHECK(bus->read_byte(0x2022A56) == 0x10);
} }
TEST_CASE_METHOD(BusFixture, "chip wram", TAG) { TEST_CASE_METHOD(BusFixture, "chip wram", TAG) {
bus.write_byte(0x3000000, 0xAC); bus->write_byte(0x3000000, 0xAC);
CHECK(bus.read_byte(0x3000000) == 0xAC); CHECK(bus->read_byte(0x3000000) == 0xAC);
bus.write_byte(0x3007FFF, 0x48); bus->write_byte(0x3007FFF, 0x48);
CHECK(bus.read_byte(0x3007FFF) == 0x48); CHECK(bus->read_byte(0x3007FFF) == 0x48);
bus.write_byte(0x3002A56, 0x10); bus->write_byte(0x3002A56, 0x10);
CHECK(bus.read_byte(0x3002A56) == 0x10); CHECK(bus->read_byte(0x3002A56) == 0x10);
} }
TEST_CASE_METHOD(BusFixture, "palette ram", TAG) { TEST_CASE_METHOD(BusFixture, "palette ram", TAG) {
bus.write_byte(0x5000000, 0xAC); bus->write_byte(0x5000000, 0xAC);
CHECK(bus.read_byte(0x5000000) == 0xAC); CHECK(bus->read_byte(0x5000000) == 0xAC);
bus.write_byte(0x50003FF, 0x48); bus->write_byte(0x50003FF, 0x48);
CHECK(bus.read_byte(0x50003FF) == 0x48); CHECK(bus->read_byte(0x50003FF) == 0x48);
bus.write_byte(0x5000156, 0x10); bus->write_byte(0x5000156, 0x10);
CHECK(bus.read_byte(0x5000156) == 0x10); CHECK(bus->read_byte(0x5000156) == 0x10);
} }
TEST_CASE_METHOD(BusFixture, "video ram", TAG) { TEST_CASE_METHOD(BusFixture, "video ram", TAG) {
bus.write_byte(0x6000000, 0xAC); bus->write_byte(0x6000000, 0xAC);
CHECK(bus.read_byte(0x6000000) == 0xAC); CHECK(bus->read_byte(0x6000000) == 0xAC);
bus.write_byte(0x6017FFF, 0x48); bus->write_byte(0x6017FFF, 0x48);
CHECK(bus.read_byte(0x6017FFF) == 0x48); CHECK(bus->read_byte(0x6017FFF) == 0x48);
bus.write_byte(0x6012A56, 0x10); bus->write_byte(0x6012A56, 0x10);
CHECK(bus.read_byte(0x6012A56) == 0x10); CHECK(bus->read_byte(0x6012A56) == 0x10);
} }
TEST_CASE_METHOD(BusFixture, "oam obj ram", TAG) { TEST_CASE_METHOD(BusFixture, "oam obj ram", TAG) {
bus.write_byte(0x7000000, 0xAC); bus->write_byte(0x7000000, 0xAC);
CHECK(bus.read_byte(0x7000000) == 0xAC); CHECK(bus->read_byte(0x7000000) == 0xAC);
bus.write_byte(0x70003FF, 0x48); bus->write_byte(0x70003FF, 0x48);
CHECK(bus.read_byte(0x70003FF) == 0x48); CHECK(bus->read_byte(0x70003FF) == 0x48);
bus.write_byte(0x7000156, 0x10); bus->write_byte(0x7000156, 0x10);
CHECK(bus.read_byte(0x7000156) == 0x10); CHECK(bus->read_byte(0x7000156) == 0x10);
} }
TEST_CASE("rom", TAG) { TEST_CASE("rom", TAG) {
@@ -94,43 +95,43 @@ TEST_CASE("rom", TAG) {
rom[0x0EF0256] = 0x10; rom[0x0EF0256] = 0x10;
// 32 megabyte ROM // 32 megabyte ROM
Bus bus(std::array<uint8_t, Bus::BIOS_SIZE>(), std::move(rom)); auto bus = Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(), std::move(rom));
SECTION("ROM1") { SECTION("ROM1") {
CHECK(bus.read_byte(0x8000000) == 0xAC); CHECK(bus->read_byte(0x8000000) == 0xAC);
CHECK(bus.read_byte(0x9FFFFFF) == 0x48); CHECK(bus->read_byte(0x9FFFFFF) == 0x48);
CHECK(bus.read_byte(0x8EF0256) == 0x10); CHECK(bus->read_byte(0x8EF0256) == 0x10);
} }
SECTION("ROM2") { SECTION("ROM2") {
CHECK(bus.read_byte(0xA000000) == 0xAC); CHECK(bus->read_byte(0xA000000) == 0xAC);
CHECK(bus.read_byte(0xBFFFFFF) == 0x48); CHECK(bus->read_byte(0xBFFFFFF) == 0x48);
CHECK(bus.read_byte(0xAEF0256) == 0x10); CHECK(bus->read_byte(0xAEF0256) == 0x10);
} }
SECTION("ROM3") { SECTION("ROM3") {
CHECK(bus.read_byte(0xC000000) == 0xAC); CHECK(bus->read_byte(0xC000000) == 0xAC);
CHECK(bus.read_byte(0xDFFFFFF) == 0x48); CHECK(bus->read_byte(0xDFFFFFF) == 0x48);
CHECK(bus.read_byte(0xCEF0256) == 0x10); CHECK(bus->read_byte(0xCEF0256) == 0x10);
} }
} }
TEST_CASE_METHOD(BusFixture, "Halfword", TAG) { TEST_CASE_METHOD(BusFixture, "Halfword", TAG) {
CHECK(bus.read_halfword(0x202FED9) == 0); CHECK(bus->read_halfword(0x202FED9) == 0);
bus.write_halfword(0x202FED9, 0x1A4A); bus->write_halfword(0x202FED9, 0x1A4A);
CHECK(bus.read_halfword(0x202FED9) == 0x1A4A); CHECK(bus->read_halfword(0x202FED9) == 0x1A4A);
CHECK(bus.read_word(0x202FED9) == 0x1A4A); CHECK(bus->read_word(0x202FED9) == 0x1A4A);
CHECK(bus.read_byte(0x202FED9) == 0x4A); CHECK(bus->read_byte(0x202FED9) == 0x4A);
} }
TEST_CASE_METHOD(BusFixture, "Word", TAG) { TEST_CASE_METHOD(BusFixture, "Word", TAG) {
CHECK(bus.read_word(0x600EE34) == 0); CHECK(bus->read_word(0x600EE34) == 0);
bus.write_word(0x600EE34, 0x3ACC491D); bus->write_word(0x600EE34, 0x3ACC491D);
CHECK(bus.read_word(0x600EE34) == 0x3ACC491D); CHECK(bus->read_word(0x600EE34) == 0x3ACC491D);
CHECK(bus.read_halfword(0x600EE34) == 0x491D); CHECK(bus->read_halfword(0x600EE34) == 0x491D);
CHECK(bus.read_byte(0x600EE34) == 0x1D); CHECK(bus->read_byte(0x600EE34) == 0x1D);
} }
#undef TAG #undef TAG

5
tests/cpu/cpu-fixture.hh
View File

@@ -5,9 +5,8 @@ using namespace matar;
class CpuFixture { class CpuFixture {
public: public:
CpuFixture() CpuFixture()
: bus(std::shared_ptr<Bus>( : bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
new Bus(std::array<uint8_t, Bus::BIOS_SIZE>(), std::vector<uint8_t>(Header::HEADER_SIZE)))
std::vector<uint8_t>(Header::HEADER_SIZE))))
, cpu(bus) {} , cpu(bus) {}
protected: protected: