tests: add some exec tests
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
227
tests/cpu/arm/exec.cc
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227
tests/cpu/arm/exec.cc
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@@ -0,0 +1,227 @@
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#include "cpu/cpu.hh"
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#include "cpu/utility.hh"
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#include <bit>
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#include <catch2/catch_test_macros.hpp>
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#include <iostream>
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#include <limits>
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#include <random>
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// I could have written some public API but that wouldn't be the best practice,
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// so instead I will try to do my best to test these functions using memory
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// manipulation. We also use a fake PC to match the current instruction's
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// address.
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//
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// We are going to use some addresses for specific tasks
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// - (4 * 400) + 4 => Storing, then reading registers
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//
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// We are also going to keep some registers reserved for testing
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// - R0 is always zero
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// - R1 for reading PSR
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class CpuFixture {
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public:
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uint32_t fake_pc = 2 * ARM_INSTRUCTION_SIZE;
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CpuFixture()
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// BIOS is all zeroes so let's do what we can
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: memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
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std::vector<uint8_t>(192))
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, bus(memory)
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, cpu(bus) {}
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void write_register(uint8_t rd, uint8_t value, uint8_t rotate = 0) {
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// MOV
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uint32_t raw = 0b11100011101000000000000000000000;
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raw |= rd << 12;
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raw |= rotate << 8;
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raw |= value;
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execute(raw);
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}
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uint32_t read_register(uint8_t rd) {
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// use R0
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static constexpr uint16_t offset = MAX_FAKE_PC + ARM_INSTRUCTION_SIZE;
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uint32_t raw = 0b11100101100000000000000000000000;
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raw |= rd << 12;
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raw |= offset;
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execute(raw);
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return bus.read_word(offset + (rd == 15 ? ARM_INSTRUCTION_SIZE : 0));
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}
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Psr read_cpsr() {
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// use R1
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uint32_t raw = 0b11100001000011110001000000000000;
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execute(raw);
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return Psr(read_register(1));
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}
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void execute(uint32_t raw) {
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bus.write_word(fake_pc - 2 * ARM_INSTRUCTION_SIZE, raw);
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step();
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}
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private:
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static constexpr uint32_t MAX_FAKE_PC = 400 * ARM_INSTRUCTION_SIZE;
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Memory memory;
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void step() {
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cpu.step();
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fake_pc += ARM_INSTRUCTION_SIZE;
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if (fake_pc == MAX_FAKE_PC)
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fake_pc = 0;
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}
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protected:
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Bus bus;
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Cpu cpu;
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};
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#define TAG "arm execution"
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using namespace arm;
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TEST_CASE_METHOD(CpuFixture, "Test fixture", TAG) {
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std::random_device rd;
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std::mt19937 gen(rd());
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std::uniform_int_distribution<uint8_t> value_d;
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std::uniform_int_distribution<uint8_t> shift_d(0, (1 << 4) - 1);
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// R0 is reserved to be 0 so that it can be used as as offset
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write_register(0, 0);
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REQUIRE(read_register(0) == 0);
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for (uint8_t i = 1; i < 15; i++) {
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uint8_t value = value_d(gen);
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uint8_t shift = shift_d(gen);
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uint32_t amount = std::rotr(static_cast<uint32_t>(value), 2 * shift);
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write_register(i, value, shift);
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REQUIRE(read_register(i) == amount);
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}
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REQUIRE(read_cpsr().mode() == Mode::Supervisor);
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INFO("Fixture is OK");
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}
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TEST_CASE_METHOD(CpuFixture, "Branch and Exchange", TAG) {
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uint32_t raw = 0b11100001001011111111111100011010;
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write_register(10, 240);
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execute(raw);
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fake_pc = 240 + 2 * ARM_INSTRUCTION_SIZE;
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REQUIRE(read_register(15) == 240 + 2 * ARM_INSTRUCTION_SIZE);
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}
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// TODO write BX for when switching to thumb
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TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
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uint32_t raw = 0b11101011000000000000000000111100;
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uint32_t old_pc = fake_pc;
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execute(raw);
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fake_pc = old_pc + 240;
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// pipeline is flushed
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fake_pc += 2 * ARM_INSTRUCTION_SIZE;
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REQUIRE(read_register(15) == old_pc + 240 + 2 * ARM_INSTRUCTION_SIZE);
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REQUIRE(read_register(14) == old_pc - ARM_INSTRUCTION_SIZE);
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}
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TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
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uint32_t raw = 0b11100000001111011100101110011010;
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uint32_t result = 0;
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write_register(10, 230);
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write_register(11, 192);
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write_register(12, 37);
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execute(raw);
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result = 230 * 192 + 37;
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REQUIRE(read_register(13) == result);
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REQUIRE(read_cpsr().n() == (result >> 31 & 1));
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// when product is zero
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write_register(10, 230);
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write_register(11, 0);
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write_register(12, 0);
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execute(raw);
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REQUIRE(read_register(13) == 0);
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REQUIRE(read_cpsr().z() == true);
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}
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TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
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uint32_t raw = 0b11100000101111011100101110011010;
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uint64_t result = 0;
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write_register(10, 230, 3); // 2550136835
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write_register(11, 192, 12); // 49152
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write_register(12, 255, 9); // 4177920
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write_register(13, 11, 4); // 184549376
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result = 2550136835ull * 49152ull + (184549376ull << 32 | 4177920ull);
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execute(raw);
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REQUIRE(read_register(12) == (result & 0xFFFFFFFF));
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REQUIRE(read_register(13) == (result >> 32 & 0xFFFFFFFF));
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REQUIRE(read_cpsr().z() == false);
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REQUIRE(read_cpsr().n() == (result >> 63 & 1));
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// signed
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raw = 0b11100000111111011100101110011010;
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write_register(12, 255, 9); // 4177920
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write_register(13, 11, 4); // 184549376
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execute(raw);
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REQUIRE(read_register(12) == (result & 0xFFFFFFFF));
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REQUIRE(read_register(13) == (result >> 32 & 0xFFFFFFFF));
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REQUIRE(read_cpsr().z() == false);
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REQUIRE(read_cpsr().n() == (result >> 63 & 1));
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// 0 and no accumulation
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raw = 0b11100000110111011100101110011010;
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write_register(10, 0);
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execute(raw);
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REQUIRE(read_register(12) == 0);
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REQUIRE(read_register(13) == 0);
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REQUIRE(read_cpsr().z() == true);
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}
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TEST_CASE_METHOD(CpuFixture, "Single Data Swap", TAG) {
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write_register(6, 230, 3); // 2550136835
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write_register(9, 160, 0); // 160
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bus.write_word(read_register(9), 49152);
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SECTION("word") {
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uint32_t raw = 0b11100001000010010101000010010110;
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execute(raw);
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REQUIRE(read_register(5) == 49152);
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REQUIRE(bus.read_word(read_register(9)) == 2550136835);
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}
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SECTION("byte") {
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uint32_t raw = 0b11100001010010010101000010010110;
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execute(raw);
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REQUIRE(read_register(5) == (49152 & 0xFF));
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REQUIRE(bus.read_byte(read_register(9)) == (2550136835 & 0xFF));
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}
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}
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#undef TAG
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469
tests/cpu/arm/instruction.cc
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469
tests/cpu/arm/instruction.cc
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@@ -0,0 +1,469 @@
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#include "cpu/arm/instruction.hh"
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#include "cpu/utility.hh"
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#include <catch2/catch_test_macros.hpp>
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#define TAG "disassembler"
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using namespace arm;
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TEST_CASE("Branch and Exchange", TAG) {
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uint32_t raw = 0b11000001001011111111111100011010;
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Instruction instruction(raw);
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BranchAndExchange* bx = nullptr;
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REQUIRE((bx = std::get_if<BranchAndExchange>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::GT);
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REQUIRE(bx->rn == 10);
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REQUIRE(instruction.disassemble() == "BXGT R10");
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}
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TEST_CASE("Branch", TAG) {
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uint32_t raw = 0b11101011100001010111111111000011;
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Instruction instruction(raw);
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Branch* b = nullptr;
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REQUIRE((b = std::get_if<Branch>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::AL);
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// last 24 bits = 8748995
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// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
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// Also +8 since PC is two instructions ahead
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REQUIRE(b->offset == 0xFE15FF14);
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REQUIRE(b->link == true);
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REQUIRE(instruction.disassemble() == "BL 0xFE15FF14");
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b->link = false;
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REQUIRE(instruction.disassemble() == "B 0xFE15FF14");
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}
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TEST_CASE("Multiply", TAG) {
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uint32_t raw = 0b00000000001110101110111110010000;
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Instruction instruction(raw);
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Multiply* mul = nullptr;
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REQUIRE((mul = std::get_if<Multiply>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::EQ);
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REQUIRE(mul->rm == 0);
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REQUIRE(mul->rs == 15);
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REQUIRE(mul->rn == 14);
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REQUIRE(mul->rd == 10);
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REQUIRE(mul->acc == true);
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REQUIRE(mul->set == true);
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REQUIRE(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
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mul->acc = false;
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mul->set = false;
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REQUIRE(instruction.disassemble() == "MULEQ R10,R0,R15");
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}
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TEST_CASE("Multiply Long", TAG) {
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uint32_t raw = 0b00010000100111100111011010010010;
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Instruction instruction(raw);
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MultiplyLong* mull = nullptr;
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REQUIRE((mull = std::get_if<MultiplyLong>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::NE);
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REQUIRE(mull->rm == 2);
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REQUIRE(mull->rs == 6);
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REQUIRE(mull->rdlo == 7);
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REQUIRE(mull->rdhi == 14);
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REQUIRE(mull->acc == false);
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REQUIRE(mull->set == true);
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REQUIRE(mull->uns == true);
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REQUIRE(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
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mull->acc = true;
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REQUIRE(instruction.disassemble() == "UMLALNES R7,R14,R2,R6");
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mull->uns = false;
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mull->set = false;
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REQUIRE(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
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}
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TEST_CASE("Undefined", TAG) {
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// notice how this is the same as single data transfer except the shift
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// is now a register based shift
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uint32_t raw = 0b11100111101000101010111100010110;
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Instruction instruction(raw);
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REQUIRE(instruction.condition == Condition::AL);
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REQUIRE(instruction.disassemble() == "UND");
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}
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TEST_CASE("Single Data Swap", TAG) {
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uint32_t raw = 0b10100001000010010101000010010110;
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Instruction instruction(raw);
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SingleDataSwap* swp = nullptr;
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REQUIRE((swp = std::get_if<SingleDataSwap>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::GE);
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REQUIRE(swp->rm == 6);
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REQUIRE(swp->rd == 5);
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REQUIRE(swp->rn == 9);
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REQUIRE(swp->byte == false);
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REQUIRE(instruction.disassemble() == "SWPGE R5,R6,[R9]");
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swp->byte = true;
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REQUIRE(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
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}
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TEST_CASE("Single Data Transfer", TAG) {
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uint32_t raw = 0b11100111101000101010111100000110;
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Instruction instruction(raw);
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SingleDataTransfer* ldr = nullptr;
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Shift* shift = nullptr;
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REQUIRE((ldr = std::get_if<SingleDataTransfer>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::AL);
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REQUIRE((shift = std::get_if<Shift>(&ldr->offset)));
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REQUIRE(shift->rm == 6);
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REQUIRE(shift->data.immediate == true);
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REQUIRE(shift->data.type == ShiftType::LSL);
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REQUIRE(shift->data.operand == 30);
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REQUIRE(ldr->rd == 10);
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REQUIRE(ldr->rn == 2);
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REQUIRE(ldr->load == false);
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REQUIRE(ldr->write == true);
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REQUIRE(ldr->byte == false);
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REQUIRE(ldr->up == true);
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REQUIRE(ldr->pre == true);
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ldr->load = true;
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ldr->byte = true;
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ldr->write = false;
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shift->data.type = ShiftType::ROR;
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REQUIRE(instruction.disassemble() == "LDRB R10,[R2,+R6,ROR #30]");
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ldr->up = false;
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ldr->pre = false;
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REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-R6,ROR #30");
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ldr->offset = static_cast<uint16_t>(9023);
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REQUIRE(instruction.disassemble() == "LDRB R10,[R2],-#9023");
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ldr->pre = true;
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REQUIRE(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
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}
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TEST_CASE("Halfword Transfer", TAG) {
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uint32_t raw = 0b00110001101011110010000010110110;
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Instruction instruction(raw);
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HalfwordTransfer* ldr = nullptr;
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REQUIRE((ldr = std::get_if<HalfwordTransfer>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::CC);
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// offset is not immediate
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REQUIRE(ldr->imm == 0);
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// hence this offset is a register number (rm)
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REQUIRE(ldr->offset == 6);
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REQUIRE(ldr->half == true);
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REQUIRE(ldr->sign == false);
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REQUIRE(ldr->rd == 2);
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REQUIRE(ldr->rn == 15);
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REQUIRE(ldr->load == false);
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REQUIRE(ldr->write == true);
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REQUIRE(ldr->up == true);
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REQUIRE(ldr->pre == true);
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REQUIRE(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
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ldr->pre = false;
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ldr->load = true;
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ldr->sign = true;
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ldr->up = false;
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REQUIRE(instruction.disassemble() == "LDRCCSH R2,[R15],-R6");
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ldr->half = false;
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REQUIRE(instruction.disassemble() == "LDRCCSB R2,[R15],-R6");
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ldr->load = false;
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// not a register anymore
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ldr->imm = 1;
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ldr->offset = 90;
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REQUIRE(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
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}
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TEST_CASE("Block Data Transfer", TAG) {
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uint32_t raw = 0b10011001010101110100000101101101;
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Instruction instruction(raw);
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BlockDataTransfer* ldm = nullptr;
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REQUIRE((ldm = std::get_if<BlockDataTransfer>(&instruction.data)));
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REQUIRE(instruction.condition == Condition::LS);
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{
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uint16_t regs = 0;
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regs |= 1 << 0;
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regs |= 1 << 2;
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regs |= 1 << 3;
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regs |= 1 << 5;
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regs |= 1 << 6;
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regs |= 1 << 8;
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regs |= 1 << 14;
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REQUIRE(ldm->regs == regs);
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}
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REQUIRE(ldm->rn == 7);
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REQUIRE(ldm->load == true);
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REQUIRE(ldm->write == false);
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REQUIRE(ldm->s == true);
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REQUIRE(ldm->up == false);
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REQUIRE(ldm->pre == true);
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REQUIRE(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
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ldm->write = true;
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ldm->s = false;
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ldm->up = true;
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REQUIRE(instruction.disassemble() == "LDMLSIB R7!,{R0,R2,R3,R5,R6,R8,R14}");
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ldm->regs &= ~(1 << 6);
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ldm->regs &= ~(1 << 3);
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ldm->regs &= ~(1 << 8);
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ldm->load = false;
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ldm->pre = false;
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|
||||
REQUIRE(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
|
||||
}
|
||||
|
||||
TEST_CASE("PSR Transfer", TAG) {
|
||||
PsrTransfer* msr = nullptr;
|
||||
|
||||
SECTION("MRS") {
|
||||
uint32_t raw = 0b01000001010011111010000000000000;
|
||||
Instruction instruction(raw);
|
||||
PsrTransfer* mrs = nullptr;
|
||||
|
||||
REQUIRE((mrs = std::get_if<PsrTransfer>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::MI);
|
||||
|
||||
REQUIRE(mrs->type == PsrTransfer::Type::Mrs);
|
||||
// Operand is a register in the case of MRS (PSR -> Register)
|
||||
REQUIRE(mrs->operand == 10);
|
||||
REQUIRE(mrs->spsr == true);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "MRSMI R10,SPSR_all");
|
||||
}
|
||||
|
||||
SECTION("MSR") {
|
||||
uint32_t raw = 0b11100001001010011111000000001000;
|
||||
Instruction instruction(raw);
|
||||
PsrTransfer* msr = nullptr;
|
||||
|
||||
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::AL);
|
||||
|
||||
REQUIRE(msr->type == PsrTransfer::Type::Msr);
|
||||
// Operand is a register in the case of MSR (Register -> PSR)
|
||||
REQUIRE(msr->operand == 8);
|
||||
REQUIRE(msr->spsr == false);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "MSR CPSR_all,R8");
|
||||
}
|
||||
|
||||
SECTION("MSR_flg with register operand") {
|
||||
uint32_t raw = 0b01100001001010001111000000001000;
|
||||
Instruction instruction(raw);
|
||||
|
||||
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::VS);
|
||||
|
||||
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
|
||||
REQUIRE(msr->imm == 0);
|
||||
REQUIRE(msr->operand == 8);
|
||||
REQUIRE(msr->spsr == false);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "MSRVS CPSR_flg,R8");
|
||||
}
|
||||
|
||||
SECTION("MSR_flg with immediate operand") {
|
||||
uint32_t raw = 0b11100011011010001111011101101000;
|
||||
Instruction instruction(raw);
|
||||
|
||||
REQUIRE((msr = std::get_if<PsrTransfer>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::AL);
|
||||
|
||||
REQUIRE(msr->type == PsrTransfer::Type::Msr_flg);
|
||||
REQUIRE(msr->imm == 1);
|
||||
|
||||
// 104 (32 bits) rotated by 2 * 7
|
||||
REQUIRE(msr->operand == 27262976);
|
||||
REQUIRE(msr->spsr == true);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "MSR SPSR_flg,#27262976");
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("Data Processing", TAG) {
|
||||
uint32_t raw = 0b11100000000111100111101101100001;
|
||||
Instruction instruction(raw);
|
||||
DataProcessing* alu = nullptr;
|
||||
Shift* shift = nullptr;
|
||||
|
||||
REQUIRE((alu = std::get_if<DataProcessing>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::AL);
|
||||
|
||||
// operand 2 is a shifted register
|
||||
REQUIRE((shift = std::get_if<Shift>(&alu->operand)));
|
||||
REQUIRE(shift->rm == 1);
|
||||
REQUIRE(shift->data.immediate == true);
|
||||
REQUIRE(shift->data.type == ShiftType::ROR);
|
||||
REQUIRE(shift->data.operand == 22);
|
||||
|
||||
REQUIRE(alu->rd == 7);
|
||||
REQUIRE(alu->rn == 14);
|
||||
REQUIRE(alu->set == true);
|
||||
REQUIRE(alu->opcode == OpCode::AND);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
|
||||
|
||||
shift->data.immediate = false;
|
||||
shift->data.operand = 2;
|
||||
alu->set = false;
|
||||
|
||||
REQUIRE(instruction.disassemble() == "AND R7,R14,R1,ROR R2");
|
||||
|
||||
alu->operand = static_cast<uint32_t>(3300012);
|
||||
REQUIRE(instruction.disassemble() == "AND R7,R14,#3300012");
|
||||
|
||||
SECTION("set-only operations") {
|
||||
alu->set = true;
|
||||
|
||||
alu->opcode = OpCode::TST;
|
||||
REQUIRE(instruction.disassemble() == "TST R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::TEQ;
|
||||
REQUIRE(instruction.disassemble() == "TEQ R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::CMP;
|
||||
REQUIRE(instruction.disassemble() == "CMP R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::CMN;
|
||||
REQUIRE(instruction.disassemble() == "CMN R14,#3300012");
|
||||
}
|
||||
|
||||
SECTION("destination operations") {
|
||||
alu->opcode = OpCode::EOR;
|
||||
REQUIRE(instruction.disassemble() == "EOR R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::SUB;
|
||||
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::RSB;
|
||||
REQUIRE(instruction.disassemble() == "RSB R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::SUB;
|
||||
REQUIRE(instruction.disassemble() == "SUB R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::ADC;
|
||||
REQUIRE(instruction.disassemble() == "ADC R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::SBC;
|
||||
REQUIRE(instruction.disassemble() == "SBC R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::RSC;
|
||||
REQUIRE(instruction.disassemble() == "RSC R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::ORR;
|
||||
REQUIRE(instruction.disassemble() == "ORR R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::MOV;
|
||||
REQUIRE(instruction.disassemble() == "MOV R7,#3300012");
|
||||
|
||||
alu->opcode = OpCode::BIC;
|
||||
REQUIRE(instruction.disassemble() == "BIC R7,R14,#3300012");
|
||||
|
||||
alu->opcode = OpCode::MVN;
|
||||
REQUIRE(instruction.disassemble() == "MVN R7,#3300012");
|
||||
}
|
||||
}
|
||||
|
||||
TEST_CASE("Coprocessor Data Transfer", TAG) {
|
||||
uint32_t raw = 0b10101101101001011111000101000110;
|
||||
Instruction instruction(raw);
|
||||
CoprocessorDataTransfer* ldc = nullptr;
|
||||
|
||||
REQUIRE((ldc = std::get_if<CoprocessorDataTransfer>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::GE);
|
||||
|
||||
REQUIRE(ldc->offset == 70);
|
||||
REQUIRE(ldc->cpn == 1);
|
||||
REQUIRE(ldc->crd == 15);
|
||||
REQUIRE(ldc->rn == 5);
|
||||
REQUIRE(ldc->load == false);
|
||||
REQUIRE(ldc->write == true);
|
||||
REQUIRE(ldc->len == false);
|
||||
REQUIRE(ldc->up == true);
|
||||
REQUIRE(ldc->pre == true);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
|
||||
|
||||
ldc->load = true;
|
||||
ldc->pre = false;
|
||||
ldc->write = false;
|
||||
ldc->len = true;
|
||||
|
||||
REQUIRE(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
|
||||
}
|
||||
|
||||
TEST_CASE("Coprocessor Operand Operation", TAG) {
|
||||
uint32_t raw = 0b11101110101001011111000101000110;
|
||||
Instruction instruction(raw);
|
||||
CoprocessorDataOperation* cdp = nullptr;
|
||||
|
||||
REQUIRE((cdp = std::get_if<CoprocessorDataOperation>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::AL);
|
||||
|
||||
REQUIRE(cdp->crm == 6);
|
||||
REQUIRE(cdp->cp == 2);
|
||||
REQUIRE(cdp->cpn == 1);
|
||||
REQUIRE(cdp->crd == 15);
|
||||
REQUIRE(cdp->crn == 5);
|
||||
REQUIRE(cdp->cp_opc == 10);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
|
||||
}
|
||||
|
||||
TEST_CASE("Coprocessor Register Transfer", TAG) {
|
||||
uint32_t raw = 0b11101110101001011111000101010110;
|
||||
Instruction instruction(raw);
|
||||
CoprocessorRegisterTransfer* mrc = nullptr;
|
||||
|
||||
REQUIRE(
|
||||
(mrc = std::get_if<CoprocessorRegisterTransfer>(&instruction.data)));
|
||||
REQUIRE(instruction.condition == Condition::AL);
|
||||
|
||||
REQUIRE(mrc->crm == 6);
|
||||
REQUIRE(mrc->cp == 2);
|
||||
REQUIRE(mrc->cpn == 1);
|
||||
REQUIRE(mrc->rd == 15);
|
||||
REQUIRE(mrc->crn == 5);
|
||||
REQUIRE(mrc->load == false);
|
||||
REQUIRE(mrc->cp_opc == 5);
|
||||
|
||||
REQUIRE(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
|
||||
}
|
||||
|
||||
TEST_CASE("Software Interrupt", TAG) {
|
||||
uint32_t raw = 0b00001111101010101010101010101010;
|
||||
Instruction instruction(raw);
|
||||
|
||||
REQUIRE(instruction.condition == Condition::EQ);
|
||||
REQUIRE(instruction.disassemble() == "SWIEQ");
|
||||
}
|
||||
|
||||
#undef TAG
|
||||
4
tests/cpu/arm/meson.build
Normal file
4
tests/cpu/arm/meson.build
Normal file
@@ -0,0 +1,4 @@
|
||||
tests_sources += files(
|
||||
'instruction.cc',
|
||||
'exec.cc'
|
||||
)
|
||||
Reference in New Issue
Block a user