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refactor: replace fmt ostreams with stringify

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Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2023-09-27 01:24:32 +05:30
parent ed01ed80cd
commit b55f6ee16b
11 changed files with 87 additions and 116 deletions
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20
src/cpu/alu.cc
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@@ -48,24 +48,4 @@ eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
return eval;
}
std::ostream&
operator<<(std::ostream& os, const ShiftType shift_type) {
#define CASE(type) \
case ShiftType::type: \
os << #type; \
break;
switch (shift_type) {
CASE(LSL)
CASE(LSR)
CASE(ASR)
CASE(ROR)
}
#undef CASE
return os;
}
}

27
src/cpu/alu.hh
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@@ -10,6 +10,24 @@ enum class ShiftType {
ROR = 0b11
};
constexpr auto
stringify(ShiftType shift_type) {
#define CASE(type) \
case ShiftType::type: \
return #type;
switch (shift_type) {
CASE(LSL)
CASE(LSR)
CASE(ASR)
CASE(ROR)
}
#undef CASE
return "";
}
struct ShiftData {
ShiftType type;
bool immediate;
@@ -23,13 +41,4 @@ struct Shift {
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const ShiftType cond);
}
namespace fmt {
template<>
struct formatter<matar::ShiftType> : ostream_formatter {};
}

2
src/cpu/arm/exec.cc
View File

@@ -4,7 +4,7 @@
namespace matar {
void
CpuImpl::exec_arm(const arm::Instruction instruction) {
CpuImpl::exec(const arm::Instruction instruction) {
Condition cond = instruction.condition;
arm::InstructionData data = instruction.data;

32
src/cpu/arm/instruction.cc
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@@ -4,7 +4,6 @@
namespace matar {
namespace arm {
Instruction::Instruction(uint32_t insn)
: condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
// Branch and exhcange
@@ -500,36 +499,5 @@ Instruction::disassemble() {
data);
}
std::ostream&
operator<<(std::ostream& os, const DataProcessing::OpCode opcode) {
#define CASE(opcode) \
case DataProcessing::OpCode::opcode: \
os << #opcode; \
break;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(SUB)
CASE(RSB)
CASE(ADD)
CASE(ADC)
CASE(SBC)
CASE(RSC)
CASE(TST)
CASE(TEQ)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MOV)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return os;
}
}
}

40
src/cpu/arm/instruction.hh
View File

@@ -8,6 +8,7 @@
namespace matar {
namespace arm {
// https://en.cppreference.com/w/cpp/utility/variant/visit
template<class... Ts>
struct overloaded : Ts... {
using Ts::operator()...;
@@ -113,6 +114,37 @@ struct DataProcessing {
OpCode opcode;
};
constexpr auto
stringify(DataProcessing::OpCode opcode) {
#define CASE(opcode) \
case DataProcessing::OpCode::opcode: \
return #opcode;
switch (opcode) {
CASE(AND)
CASE(EOR)
CASE(SUB)
CASE(RSB)
CASE(ADD)
CASE(ADC)
CASE(SBC)
CASE(RSC)
CASE(TST)
CASE(TEQ)
CASE(CMP)
CASE(CMN)
CASE(ORR)
CASE(MOV)
CASE(BIC)
CASE(MVN)
}
#undef CASE
return "";
}
struct PsrTransfer {
enum class Type {
Mrs,
@@ -188,13 +220,5 @@ struct Instruction {
std::string disassemble();
};
std::ostream&
operator<<(std::ostream& os, const DataProcessing::OpCode cond);
}
}
namespace fmt {
template<>
struct formatter<matar::arm::DataProcessing::OpCode> : ostream_formatter {};
}

2
src/cpu/cpu-impl.cc
View File

@@ -123,7 +123,7 @@ CpuImpl::step() {
arm::Instruction instruction(x);
glogger.info("{:#034b}", x);
exec_arm(instruction);
arm(instruction);
glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());

2
src/cpu/cpu-impl.hh
View File

@@ -13,7 +13,7 @@ class CpuImpl {
void step();
void chg_mode(const Mode to);
void exec_arm(const arm::Instruction instruction);
void exec(const arm::Instruction instruction);
static constexpr uint8_t GPR_COUNT = 16;

33
src/cpu/psr.cc
View File

@@ -96,37 +96,4 @@ Psr::condition(Condition cond) const {
return false;
}
std::ostream&
operator<<(std::ostream& os, const Condition cond) {
#define CASE(cond) \
case Condition::cond: \
os << #cond; \
break;
switch (cond) {
CASE(EQ)
CASE(NE)
CASE(CS)
CASE(CC)
CASE(MI)
CASE(PL)
CASE(VS)
CASE(VC)
CASE(HI)
CASE(LS)
CASE(GE)
CASE(LT)
CASE(GT)
CASE(LE)
case Condition::AL: {
// empty
}
}
#undef CASE
return os;
}
}

41
src/cpu/psr.hh
View File

@@ -38,6 +38,38 @@ enum class Condition {
AL = 0b1110
};
constexpr auto
stringify(Condition cond) {
#define CASE(cond) \
case Condition::cond: \
return #cond;
switch (cond) {
CASE(EQ)
CASE(NE)
CASE(CS)
CASE(CC)
CASE(MI)
CASE(PL)
CASE(VS)
CASE(VC)
CASE(HI)
CASE(LS)
CASE(GE)
CASE(LT)
CASE(GT)
CASE(LE)
case Condition::AL: {
// empty
}
}
#undef CASE
return "";
}
class Psr {
public:
// clear the reserved bits i.e, [8:27]
@@ -88,13 +120,4 @@ class Psr {
uint32_t psr;
};
// https://fmt.dev/dev/api.html#std-ostream-support
std::ostream&
operator<<(std::ostream& os, const Condition cond);
}
namespace fmt {
template<>
struct formatter<matar::Condition> : ostream_formatter {};
}

2
src/util/log.hh
View File

@@ -80,4 +80,4 @@ class Logger {
extern logging::Logger glogger;
#define debug(x) glogger.debug("{} = {}", #x, x);
#define dbg(x) glogger.debug("{} = {}", #x, x);

2
tests/cpu/arm/exec.cc
View File

@@ -15,7 +15,7 @@ class CpuFixture {
protected:
void exec(arm::InstructionData data, Condition condition = Condition::AL) {
arm::Instruction instruction(condition, data);
cpu.exec_arm(instruction);
cpu.exec(instruction);
}
void reset(uint32_t value = 0) {