cpu/{arm|thumb}(chore): change how branch disassembly happens

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

tests/cpu/thumb/exec.cc

@@ -1,6 +1,5 @@
 #include "cpu/cpu-fixture.hh"
 #include "cpu/thumb/instruction.hh"
-#include "util/bits.hh"
 #include <catch2/catch_test_macros.hpp>
 
 using namespace matar;
@@ -531,8 +530,9 @@ TEST_CASE_METHOD(CpuFixture, "PC Relative Load", TAG) {
     InstructionData data = PcRelativeLoad{ .word = 0x578, .rd = 0 };
 
     setr(15, 0x3003FD5);
-    // 0x3003FD5 + 0x578
-    bus.write_word(0x300454D, 489753492);
+    // setting bit 0 for 0x3003FD5, we get 0x3003FD4
+    // 0x3003FD4 + 0x578
+    bus.write_word(0x300454C, 489753492);
 
     CHECK(getr(0) == 0);
     exec(data);

tests/cpu/thumb/instruction.cc

@@ -412,7 +412,8 @@ TEST_CASE("Conditional Branch", TAG) {
     CHECK(b->condition == Condition::LS);
 
 #ifdef DISASSEMBLER
-    // (-76 << 1) + PC (0) + 4
+    // take prefetch into account
+    // offset + 4 = -152 + 4
     CHECK(instruction.disassemble() == "BLS #-148");
 #endif
 }
@@ -439,7 +440,8 @@ TEST_CASE("Unconditional Branch") {
     REQUIRE(b->offset == -410);
 
 #ifdef DISASSEMBLER
-    // (2147483443 << 1) + PC(0) + 4
+    // take prefetch into account
+    // offset + 4 = -410 + 4
     CHECK(instruction.disassemble() == "B #-406");
 #endif
 }