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cpu/{arm|thumb}(chore): change how branch disassembly happens

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Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2024-06-11 23:03:44 +05:30
parent 0062ad424b
commit ac92f43b28
11 changed files with 41 additions and 36 deletions
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13
tests/cpu/arm/exec.cc
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@@ -24,18 +24,25 @@ TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
InstructionData data = Branch{ .link = false, .offset = 3489748 };
Branch* branch = std::get_if<Branch>(&data);
// set PC to 48
setr(15, 48);
exec(data);
CHECK(getr(15) == 3489748);
// 48 + offset
CHECK(getr(15) == 3489796);
CHECK(getr(14) == 0);
// with link
reset();
setr(15, 48);
branch->link = true;
exec(data);
CHECK(getr(15) == 3489748);
CHECK(getr(14) == 0 + INSTRUCTION_SIZE);
// 48 + offset
CHECK(getr(15) == 3489796);
// pc was set to 48
CHECK(getr(14) == 48 - INSTRUCTION_SIZE);
}
TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {

9
tests/cpu/arm/instruction.cc
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@@ -31,15 +31,16 @@ TEST_CASE("Branch", TAG) {
// last 24 bits = 8748995
// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
// Also +8 since PC is two instructions ahead
CHECK(b->offset == 0xFE15FF14);
CHECK(b->offset == static_cast<int32_t>(0xfe15ff0c));
CHECK(b->link == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "BL 0xFE15FF14");
// take prefetch into account
// offset + 8 = 0xfe15ff0c + 8 = -0x1ea00e4 + 8
CHECK(instruction.disassemble() == "BL -0x1ea00ec");
b->link = false;
CHECK(instruction.disassemble() == "B 0xFE15FF14");
CHECK(instruction.disassemble() == "B -0x1ea00ec");
#endif
}

6
tests/cpu/thumb/exec.cc
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@@ -1,6 +1,5 @@
#include "cpu/cpu-fixture.hh"
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include <catch2/catch_test_macros.hpp>
using namespace matar;
@@ -531,8 +530,9 @@ TEST_CASE_METHOD(CpuFixture, "PC Relative Load", TAG) {
InstructionData data = PcRelativeLoad{ .word = 0x578, .rd = 0 };
setr(15, 0x3003FD5);
// 0x3003FD5 + 0x578
bus.write_word(0x300454D, 489753492);
// setting bit 0 for 0x3003FD5, we get 0x3003FD4
// 0x3003FD4 + 0x578
bus.write_word(0x300454C, 489753492);
CHECK(getr(0) == 0);
exec(data);

6
tests/cpu/thumb/instruction.cc
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@@ -412,7 +412,8 @@ TEST_CASE("Conditional Branch", TAG) {
CHECK(b->condition == Condition::LS);
#ifdef DISASSEMBLER
// (-76 << 1) + PC (0) + 4
// take prefetch into account
// offset + 4 = -152 + 4
CHECK(instruction.disassemble() == "BLS #-148");
#endif
}
@@ -439,7 +440,8 @@ TEST_CASE("Unconditional Branch") {
REQUIRE(b->offset == -410);
#ifdef DISASSEMBLER
// (2147483443 << 1) + PC(0) + 4
// take prefetch into account
// offset + 4 = -410 + 4
CHECK(instruction.disassemble() == "B #-406");
#endif
}