add a basic structure for disassembler + executor
Instructions added Branch and Exchange (BX) Branch and Link (B) Multiply and Accumulate (MUL, MLA) Multiply Long and Accumulate (SMULL, SMLAL, UMULL, UMLAL) Single data swap (SWP) [WIP] Halfword Transfer (STRH, LDRH) Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
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@@ -1,5 +1,6 @@
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#include "psr.hh"
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#include "util/bits.hh"
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#include "util/log.hh"
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Psr::Psr(uint32_t raw) {
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psr = raw & PSR_CLEAR_RESERVED;
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@@ -16,9 +17,9 @@ Psr::set_mode(Mode mode) {
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psr |= static_cast<uint32_t>(mode);
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}
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bool
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State
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Psr::state() const {
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return get_nth_bit(psr, 5);
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return static_cast<State>(get_nth_bit(psr, 5));
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}
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void
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@@ -47,3 +48,39 @@ GET_SET_NTH_BIT_FUNCTIONS(z, 30);
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GET_SET_NTH_BIT_FUNCTIONS(n, 31);
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#undef GET_SET_NTH_BIT_FUNCTIONS
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bool
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Psr::condition(Condition cond) const {
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switch (cond) {
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case Condition::EQ:
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return z();
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case Condition::NE:
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return !z();
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case Condition::CS:
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return c();
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case Condition::CC:
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return !c();
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case Condition::MI:
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return n();
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case Condition::PL:
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return !n();
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case Condition::VS:
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return v();
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case Condition::VC:
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return !v();
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case Condition::HI:
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return c() && !z();
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case Condition::LS:
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return !c() || z();
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case Condition::GE:
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return n() == v();
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case Condition::LT:
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return n() != v();
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case Condition::GT:
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return !z() && (n() == v());
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case Condition::LE:
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return z() || (n() != v());
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case Condition::AL:
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return true;
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}
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}
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