add a basic structure for disassembler + executor

Instructions added
Branch and Exchange (BX)
Branch and Link (B)
Multiply and Accumulate (MUL, MLA)
Multiply Long and Accumulate (SMULL, SMLAL, UMULL, UMLAL)
Single data swap (SWP)
[WIP] Halfword Transfer (STRH, LDRH)

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

src/cpu/arm/insruction.hh

@@ -1,43 +0,0 @@
-enum class Condition {
-    EQ = 0b0000,
-    NE = 0b0001,
-    CS = 0b0010,
-    CC = 0b0011,
-    MI = 0b0100,
-    PL = 0b0101,
-    VS = 0b0110,
-    VC = 0b0111,
-    HI = 0b1000,
-    LS = 0b1001,
-    GE = 0b1010,
-    LT = 0b1011,
-    GT = 0b1100,
-    LE = 0b1101,
-    AL = 0b1110
-};
-
-enum class OpCode {
-    AND = 0b0000,
-    EOR = 0b0001,
-    SUB = 0b0010,
-    RSB = 0b0011,
-    ADD = 0b0100,
-    ADC = 0b0101,
-    SBC = 0b0110,
-    RSC = 0b0111,
-    TST = 0b1000,
-    TEQ = 0b1001,
-    CMP = 0b1010,
-    CMN = 0b1011,
-    ORR = 0b1100,
-    MOV = 0b1101,
-    BIC = 0b1110,
-    MVN = 0b1111
-};
-
-enum class ShiftType {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11
-};

src/cpu/arm/meson.build

@@ -1,2 +0,0 @@
-lib_sources += files(
-)