[UNTESTED] complete initial disassembler structure for ARM
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
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@@ -14,14 +14,14 @@ class Cpu {
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void step();
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private:
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static constexpr size_t GPR_COUNT = 16;
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static constexpr uint8_t GPR_COUNT = 16;
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static constexpr size_t GPR_FIQ_FIRST = 8;
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static constexpr size_t GPR_SVC_FIRST = 13;
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static constexpr size_t GPR_ABT_FIRST = 13;
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static constexpr size_t GPR_IRQ_FIRST = 13;
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static constexpr size_t GPR_UND_FIRST = 13;
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static constexpr size_t GPR_SYS_USR_FIRST = 8;
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static constexpr uint8_t GPR_FIQ_FIRST = 8;
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static constexpr uint8_t GPR_SVC_FIRST = 13;
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static constexpr uint8_t GPR_ABT_FIRST = 13;
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static constexpr uint8_t GPR_IRQ_FIRST = 13;
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static constexpr uint8_t GPR_UND_FIRST = 13;
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static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
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std::shared_ptr<Bus> bus;
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std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
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@@ -29,7 +29,13 @@ class Cpu {
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Psr cpsr; // current program status register
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Psr spsr; // status program status register
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uint32_t& pc = gpr[15];
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static constexpr uint8_t PC_INDEX = 15;
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uint32_t& pc = gpr[PC_INDEX];
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bool is_flushed;
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void chg_mode(const Mode to);
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void exec_arm(const ArmInstruction instruction);
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struct {
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std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
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@@ -49,7 +55,4 @@ class Cpu {
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Psr irq;
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Psr und;
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} spsr_banked; // banked saved program status registers
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void chg_mode(const Mode to);
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void exec_arm(const ArmInstruction instruction);
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};
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