[UNTESTED] complete initial disassembler structure for ARM

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

include/cpu/cpu.hh

@@ -14,14 +14,14 @@ class Cpu {
     void step();
 
   private:
-    static constexpr size_t GPR_COUNT = 16;
+    static constexpr uint8_t GPR_COUNT = 16;
 
-    static constexpr size_t GPR_FIQ_FIRST     = 8;
-    static constexpr size_t GPR_SVC_FIRST     = 13;
-    static constexpr size_t GPR_ABT_FIRST     = 13;
-    static constexpr size_t GPR_IRQ_FIRST     = 13;
-    static constexpr size_t GPR_UND_FIRST     = 13;
-    static constexpr size_t GPR_SYS_USR_FIRST = 8;
+    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
+    static constexpr uint8_t GPR_SVC_FIRST     = 13;
+    static constexpr uint8_t GPR_ABT_FIRST     = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
+    static constexpr uint8_t GPR_UND_FIRST     = 13;
+    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
 
     std::shared_ptr<Bus> bus;
     std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
@@ -29,7 +29,13 @@ class Cpu {
     Psr cpsr; // current program status register
     Psr spsr; // status program status register
 
-    uint32_t& pc = gpr[15];
+    static constexpr uint8_t PC_INDEX = 15;
+    uint32_t& pc                      = gpr[PC_INDEX];
+
+    bool is_flushed;
+
+    void chg_mode(const Mode to);
+    void exec_arm(const ArmInstruction instruction);
 
     struct {
         std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
@@ -49,7 +55,4 @@ class Cpu {
         Psr irq;
         Psr und;
     } spsr_banked; // banked saved program status registers
-
-    void chg_mode(const Mode to);
-    void exec_arm(const ArmInstruction instruction);
 };

include/cpu/instruction.hh

@@ -79,6 +79,38 @@ class ArmInstruction {
         bool pre;
     };
 
+    struct BlockDataTransfer {
+        uint16_t regs;
+        uint8_t rn;
+        bool load;
+        bool write;
+        bool s;
+        bool up;
+        bool pre;
+    };
+
+    struct DataProcessing {
+        std::variant<Shift, uint32_t> operand;
+        uint8_t rd;
+        uint8_t rn;
+        bool set;
+        OpCode opcode;
+    };
+
+    struct PsrTransfer {
+        enum class Type {
+            Mrs,
+            Msr,
+            Msr_flg
+        };
+
+        uint32_t operand;
+        bool spsr;
+        Type type;
+        // ignored outside MSR_flg
+        bool imm;
+    };
+
     struct CoprocessorDataTransfer {
         uint8_t offset;
         uint8_t cpn;
@@ -120,6 +152,9 @@ class ArmInstruction {
                                          SingleDataSwap,
                                          SingleDataTransfer,
                                          HalfwordTransfer,
+                                         BlockDataTransfer,
+                                         DataProcessing,
+                                         PsrTransfer,
                                          CoprocessorDataTransfer,
                                          CoprocessorDataOperation,
                                          CoprocessorRegisterTransfer,

include/cpu/psr.hh

@@ -8,6 +8,9 @@ class Psr {
     // clear the reserved bits i.e, [8:27]
     Psr(uint32_t raw);
 
+    uint32_t raw() const;
+    void set_all(uint32_t raw);
+
     // Mode : [4:0]
     Mode mode() const;
     void set_mode(Mode mode);
@@ -45,8 +48,8 @@ class Psr {
     bool condition(Condition cond) const;
 
   private:
-    static constexpr uint32_t PSR_CLEAR_RESERVED = 0xf00000ff;
-    static constexpr uint32_t PSR_CLEAR_MODE     = 0x0b00000;
+    static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
+    static constexpr uint32_t PSR_CLEAR_MODE     = 0xFFFFFFE0;
 
     uint32_t psr;
 };

include/cpu/utility.hh

@@ -65,6 +65,12 @@ enum class OpCode {
     MVN = 0b1111
 };
 
+// https://fmt.dev/dev/api.html#std-ostream-support
+std::ostream&
+operator<<(std::ostream& os, const OpCode cond);
+template<>
+struct fmt::formatter<OpCode> : ostream_formatter {};
+
 enum class ShiftType {
     LSL = 0b00,
     LSR = 0b01,