bus: separate out read/write that count cycles
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
@@ -132,7 +132,7 @@ Cpu::step() {
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arm::Instruction instruction(opcodes[0]);
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opcodes[0] = opcodes[1];
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opcodes[1] = bus->read_word(pc, sequential);
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opcodes[1] = bus->read_word(pc, next_access);
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#ifdef DISASSEMBLER
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glogger.info("0x{:08X} : {}",
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@@ -151,7 +151,7 @@ Cpu::step() {
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thumb::Instruction instruction(opcodes[0]);
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opcodes[0] = opcodes[1];
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opcodes[1] = bus->read_halfword(pc, sequential);
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opcodes[1] = bus->read_halfword(pc, next_access);
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#ifdef DISASSEMBLER
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glogger.info("0x{:08X} : {}",
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@@ -168,4 +168,24 @@ Cpu::step() {
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advance_pc_thumb();
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}
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}
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void
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Cpu::flush_pipeline() {
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// halfword align
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rst_bit(pc, 0);
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if (cpsr.state() == State::Arm) {
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// word align
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rst_bit(pc, 1);
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opcodes[0] = bus->read_word(pc, CpuAccess::NonSequential);
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advance_pc_arm();
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opcodes[1] = bus->read_word(pc, CpuAccess::Sequential);
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advance_pc_arm();
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} else {
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opcodes[0] = bus->read_halfword(pc, CpuAccess::NonSequential);
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advance_pc_thumb();
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opcodes[1] = bus->read_halfword(pc, CpuAccess::Sequential);
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advance_pc_thumb();
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}
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next_access = CpuAccess::Sequential;
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};
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}
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