restructure: get rid of cpu/utility

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

src/cpu/arm/exec.cc

@@ -7,7 +7,7 @@ using namespace logger;
 namespace matar {
 void
 CpuImpl::exec_arm(const arm::Instruction instruction) {
-    arm::Condition cond       = instruction.condition;
+    Condition cond            = instruction.condition;
     arm::InstructionData data = instruction.data;
 
     debug(cpsr.condition(cond));
@@ -387,6 +387,8 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             }
         },
         [this, pc_error](DataProcessing& data) {
+            using OpCode = DataProcessing::OpCode;
+
             uint32_t op_1 = gpr[data.rn];
             uint32_t op_2 = 0;
 

src/cpu/arm/instruction.cc

@@ -1,5 +1,4 @@
 #include "instruction.hh"
-#include "cpu/utility.hh"
 #include "util/bits.hh"
 #include <iterator>
 
@@ -153,6 +152,8 @@ Instruction::Instruction(uint32_t insn)
 
         // Data Processing
     } else if ((insn & 0x0C000000) == 0x00000000) {
+        using OpCode = DataProcessing::OpCode;
+
         uint8_t rd    = bit_range(insn, 12, 15);
         uint8_t rn    = bit_range(insn, 16, 19);
         bool set      = get_bit(insn, 20);
@@ -420,6 +421,8 @@ Instruction::disassemble() {
             }
         },
         [this](DataProcessing& data) {
+            using OpCode = DataProcessing::OpCode;
+
             std::string op_2;
 
             if (const uint32_t* operand =
@@ -496,5 +499,37 @@ Instruction::disassemble() {
         [](auto) { return std::string("unknown instruction"); } },
       data);
 }
+
+std::ostream&
+operator<<(std::ostream& os, const DataProcessing::OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case DataProcessing::OpCode::opcode:                                       \
+        os << #opcode;                                                         \
+        break;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(SUB)
+        CASE(RSB)
+        CASE(ADD)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(RSC)
+        CASE(TST)
+        CASE(TEQ)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MOV)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+
+    return os;
+}
 }
 }

src/cpu/arm/instruction.hh

@@ -1,8 +1,13 @@
 #pragma once
-#include "cpu/utility.hh"
+#include "cpu/alu.hh"
+#include "cpu/psr.hh"
 #include <cstdint>
+#include <fmt/ostream.h>
 #include <variant>
 
+namespace matar {
+namespace arm {
+
 template<class... Ts>
 struct overloaded : Ts... {
     using Ts::operator()...;
@@ -10,8 +15,6 @@ struct overloaded : Ts... {
 template<class... Ts>
 overloaded(Ts...) -> overloaded<Ts...>;
 
-namespace matar {
-namespace arm {
 static constexpr size_t INSTRUCTION_SIZE = 4;
 
 struct BranchAndExchange {
@@ -84,6 +87,25 @@ struct BlockDataTransfer {
 };
 
 struct DataProcessing {
+    enum class OpCode {
+        AND = 0b0000,
+        EOR = 0b0001,
+        SUB = 0b0010,
+        RSB = 0b0011,
+        ADD = 0b0100,
+        ADC = 0b0101,
+        SBC = 0b0110,
+        RSC = 0b0111,
+        TST = 0b1000,
+        TEQ = 0b1001,
+        CMP = 0b1010,
+        CMN = 0b1011,
+        ORR = 0b1100,
+        MOV = 0b1101,
+        BIC = 0b1110,
+        MVN = 0b1111
+    };
+
     std::variant<Shift, uint32_t> operand;
     uint8_t rd;
     uint8_t rn;
@@ -166,5 +188,13 @@ struct Instruction {
 
     std::string disassemble();
 };
+
+std::ostream&
+operator<<(std::ostream& os, const DataProcessing::OpCode cond);
 }
 }
+
+namespace fmt {
+template<>
+struct formatter<matar::arm::DataProcessing::OpCode> : ostream_formatter {};
+}