[UNTESTED] refactor how instructions are parsed

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

include/cpu/cpu.hh

@@ -1 +0,0 @@
-../../src/cpu/cpu.hh

include/cpu/cpu.hh

@@ -0,0 +1,55 @@
+#pragma once
+
+#include "bus.hh"
+#include "instruction.hh"
+#include "psr.hh"
+
+#include <cstdint>
+
+using std::size_t;
+
+class Cpu {
+  public:
+    Cpu(Bus& bus);
+    void step();
+
+  private:
+    static constexpr size_t GPR_COUNT = 16;
+
+    static constexpr size_t GPR_FIQ_FIRST     = 8;
+    static constexpr size_t GPR_SVC_FIRST     = 13;
+    static constexpr size_t GPR_ABT_FIRST     = 13;
+    static constexpr size_t GPR_IRQ_FIRST     = 13;
+    static constexpr size_t GPR_UND_FIRST     = 13;
+    static constexpr size_t GPR_SYS_USR_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+
+    Psr cpsr; // current program status register
+    Psr spsr; // status program status register
+
+    uint32_t& pc = gpr[15];
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
+    } gpr_banked; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked; // banked saved program status registers
+
+    void chg_mode(const Mode to);
+    void exec_arm(const ArmInstruction instruction);
+};

include/cpu/instruction.hh

@@ -0,0 +1 @@
+../../src/cpu/instruction.hh

include/cpu/meson.build

@@ -1,5 +1,6 @@
 headers += files(
   'cpu.hh',
+  'instruction.hh',
   'psr.hh',
   'utility.hh'
 )

include/cpu/utility.hh

@@ -1,79 +0,0 @@
-#pragma once
-
-#include <fmt/ostream.h>
-#include <ostream>
-
-static constexpr size_t ARM_INSTRUCTION_SIZE   = 4;
-static constexpr size_t THUMB_INSTRUCTION_SIZE = 2;
-
-enum class Mode {
-    /* M[4:0] in PSR */
-    User       = 0b10000,
-    Fiq        = 0b10001,
-    Irq        = 0b10010,
-    Supervisor = 0b10011,
-    Abort      = 0b10111,
-    Undefined  = 0b11011,
-    System     = 0b11111,
-};
-
-enum class State {
-    Arm   = 0,
-    Thumb = 1
-};
-
-enum class Condition {
-    EQ = 0b0000,
-    NE = 0b0001,
-    CS = 0b0010,
-    CC = 0b0011,
-    MI = 0b0100,
-    PL = 0b0101,
-    VS = 0b0110,
-    VC = 0b0111,
-    HI = 0b1000,
-    LS = 0b1001,
-    GE = 0b1010,
-    LT = 0b1011,
-    GT = 0b1100,
-    LE = 0b1101,
-    AL = 0b1110
-};
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const Condition cond);
-template<>
-struct fmt::formatter<Condition> : ostream_formatter {};
-
-enum class OpCode {
-    AND = 0b0000,
-    EOR = 0b0001,
-    SUB = 0b0010,
-    RSB = 0b0011,
-    ADD = 0b0100,
-    ADC = 0b0101,
-    SBC = 0b0110,
-    RSC = 0b0111,
-    TST = 0b1000,
-    TEQ = 0b1001,
-    CMP = 0b1010,
-    CMN = 0b1011,
-    ORR = 0b1100,
-    MOV = 0b1101,
-    BIC = 0b1110,
-    MVN = 0b1111
-};
-
-enum class ShiftType {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11
-};
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const ShiftType cond);
-template<>
-struct fmt::formatter<ShiftType> : ostream_formatter {};

include/cpu/utility.hh

@@ -0,0 +1 @@
+../../src/cpu/utility.hh