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initialise a memory structure or smth

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Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2023-09-11 10:23:46 +05:30
parent 84c68a4e00
commit 332f0b87d6
26 changed files with 763 additions and 163 deletions
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104
src/cpu/cpu.hh
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@@ -7,71 +7,57 @@
using std::size_t;
static constexpr size_t GPR_VISIBLE_COUNT = 16;
static constexpr size_t GPR_FIQ_BANKED_FIRST = 8;
static constexpr size_t GPR_FIQ_BANKED_COUNT = 7;
static constexpr size_t GPR_SVC_BANKED_FIRST = 13;
static constexpr size_t GPR_SVC_BANKED_COUNT = 2;
static constexpr size_t GPR_ABT_BANKED_FIRST = 13;
static constexpr size_t GPR_ABT_BANKED_COUNT = 2;
static constexpr size_t GPR_IRQ_BANKED_FIRST = 13;
static constexpr size_t GPR_IRQ_BANKED_COUNT = 2;
static constexpr size_t GPR_UND_BANKED_FIRST = 13;
static constexpr size_t GPR_UND_BANKED_COUNT = 2;
static constexpr size_t GPR_SYS_USR_BANKED_FIRST = 8;
static constexpr size_t GPR_SYS_USR_BANKED_COUNT = 7;
struct _GprBanked {
uint32_t fiq[GPR_FIQ_BANKED_COUNT];
uint32_t svc[GPR_SVC_BANKED_COUNT];
uint32_t abt[GPR_ABT_BANKED_COUNT];
uint32_t irq[GPR_IRQ_BANKED_COUNT];
uint32_t und[GPR_UND_BANKED_COUNT];
/* visible registers before the mode switch */
uint32_t old[GPR_SYS_USR_BANKED_COUNT];
};
typedef struct _GprBanked GprBanked;
struct _SpsrBanked {
Psr fiq;
Psr svc;
Psr abt;
Psr irq;
Psr und;
};
typedef struct _SpsrBanked SpsrBanked;
class Cpu {
public:
Cpu(Bus bus);
private:
static constexpr size_t GPR_FIQ_BANKED_FIRST = 8;
static constexpr size_t GPR_FIQ_BANKED_COUNT = 7;
static constexpr size_t GPR_SVC_BANKED_FIRST = 13;
static constexpr size_t GPR_SVC_BANKED_COUNT = 2;
static constexpr size_t GPR_ABT_BANKED_FIRST = 13;
static constexpr size_t GPR_ABT_BANKED_COUNT = 2;
static constexpr size_t GPR_IRQ_BANKED_FIRST = 13;
static constexpr size_t GPR_IRQ_BANKED_COUNT = 2;
static constexpr size_t GPR_UND_BANKED_FIRST = 13;
static constexpr size_t GPR_UND_BANKED_COUNT = 2;
static constexpr size_t GPR_SYS_USR_BANKED_FIRST = 8;
static constexpr size_t GPR_SYS_USR_BANKED_COUNT = 7;
static constexpr size_t GPR_VISIBLE_COUNT = 16;
uint32_t gpr[GPR_VISIBLE_COUNT]; // general purpose registers
GprBanked gpr_banked; // banked general purpose registers
SpsrBanked spsr_banked; // banked saved program status registers
Psr cpsr; // current program status register
Psr spsr; // status program status register
Bus bus;
struct {
uint32_t fiq[GPR_FIQ_BANKED_COUNT];
uint32_t svc[GPR_SVC_BANKED_COUNT];
uint32_t abt[GPR_ABT_BANKED_COUNT];
uint32_t irq[GPR_IRQ_BANKED_COUNT];
uint32_t und[GPR_UND_BANKED_COUNT];
// visible registers before the mode switch
uint32_t old[GPR_SYS_USR_BANKED_COUNT];
} gpr_banked; // banked general purpose registers
struct {
Psr fiq;
Psr svc;
Psr abt;
Psr irq;
Psr und;
} spsr_banked; // banked saved program status registers
void chg_mode(Mode from, Mode to);
uint32_t& operator[](size_t idx);
const uint32_t& operator[](size_t idx) const;
public:
Cpu(Bus bus)
: gpr(0)
, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
, spsr_banked({ 0, 0, 0, 0, 0 })
, cpsr(0)
, spsr(0)
, bus(bus) {
cpsr.set_mode(Mode::System);
cpsr.set_irq_disabled(true);
cpsr.set_fiq_disabled(true);
cpsr.set_state(State::Arm);
}
uint32_t& operator[](uint8_t idx);
const uint32_t& operator[](uint8_t idx) const;
};