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massive instruction rewrite

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So, I ended up moving exec methods from Instruction to Cpu for
encapsulating cycle emulation, and this has caused me lots of pain since
I had to rewrite a shit ton of tests which are not even useful or
comprehensible, i do no know why i put myself through this

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2024-06-20 06:07:00 +05:30
parent 7d3996526f
commit 1c96f418eb
12 changed files with 775 additions and 486 deletions
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161
tests/cpu/arm/exec.cc
View File

@@ -15,9 +15,16 @@ TEST_CASE_METHOD(CpuFixture, "Branch and Exchange", TAG) {
setr(3, 342800);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3);
CHECK(getr(15) == 342800);
INFO(getr(15));
INFO(getr(15));
INFO(getr(15));
INFO(getr(15));
// +8 cuz pipeline flush
CHECK(getr(15) == 342808);
}
TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
@@ -27,10 +34,13 @@ TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
// set PC to 48
setr(15, 48);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3);
// 48 + offset
CHECK(getr(15) == 3489796);
// +8 cuz pipeline flush
CHECK(getr(15) == 3489804);
CHECK(getr(14) == 0);
// with link
@@ -40,7 +50,8 @@ TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
exec(data);
// 48 + offset
CHECK(getr(15) == 3489796);
// +8 cuz pipeline flush
CHECK(getr(15) == 3489804);
// pc was set to 48
CHECK(getr(14) == 48 - INSTRUCTION_SIZE);
}
@@ -53,11 +64,13 @@ TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
setr(10, 234912349);
setr(11, 124897);
setr(3, 99999);
setr(3, 99999); // m = 3 since [32:24] bits are 0
{
uint32_t result = 234912349ull * 124897ull & 0xFFFFFFFF;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 4); // S + mI
CHECK(getr(5) == result);
}
@@ -66,7 +79,9 @@ TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
{
uint32_t result = (234912349ull * 124897ull + 99999ull) & 0xFFFFFFFF;
multiply->acc = true;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 5); // S + mI + I
CHECK(getr(5) == result);
}
@@ -105,12 +120,14 @@ TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
MultiplyLong* multiply_long = std::get_if<MultiplyLong>(&data);
setr(10, 234912349);
setr(11, 124897);
setr(11, 124897); // m = 3
// unsigned
{
uint64_t result = 234912349ull * 124897ull;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 5); // S + (m+1)I
CHECK(getr(3) == bit_range(result, 0, 31));
CHECK(getr(5) == bit_range(result, 32, 63));
@@ -121,7 +138,9 @@ TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
int64_t result = 234912349ll * -124897ll;
setr(11, getr(11) * -1);
multiply_long->uns = false;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 5); // S + (m+1)I
CHECK(getr(3) == static_cast<uint32_t>(bit_range(result, 0, 31)));
CHECK(getr(5) == static_cast<uint32_t>(bit_range(result, 32, 63)));
@@ -136,7 +155,9 @@ TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
234912349ll * -124897ll + (99999ll | -444333391ll << 32);
multiply_long->acc = true;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 6); // S + (m+2)I
CHECK(getr(3) == static_cast<uint32_t>(bit_range(result, 0, 31)));
CHECK(getr(5) == static_cast<uint32_t>(bit_range(result, 32, 63)));
@@ -185,7 +206,9 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Swap", TAG) {
bus->write_word(getr(9), 3241011111);
SECTION("word") {
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 4); // S + 2N + I
CHECK(getr(4) == 3241011111);
CHECK(bus->read_word(getr(9)) == static_cast<uint32_t>(-259039045));
@@ -227,7 +250,9 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
{
// 0x31E + 0x3000004
bus->write_word(0x30031E4, 95995);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I
CHECK(getr(5) == 95995);
setr(5, 0);
@@ -305,7 +330,9 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
{
data_transfer->load = false;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 2N for store
CHECK(bus->read_word(0x30042CB) == 61119);
// 0x30042CB - 0xDA1
@@ -315,13 +342,15 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
// r15 as rn
{
data_transfer->rn = 15;
setr(15, 0x300352A);
setr(15, 0x300352C); // word aligned
exec(data);
CHECK(bus->read_word(0x300352A) == 61119);
// 0x300352A - 0xDA1
CHECK(getr(15) == 0x3002789);
CHECK(bus->read_word(0x300352C) == 61119);
// 0x300352C - 0xDA1
// +4 cuz PC advanced
// and then word aligned
CHECK(getr(15) == 0x300278C);
// cleanup
data_transfer->rn = 7;
@@ -334,13 +363,12 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
exec(data);
CHECK(bus->read_word(0x300352A + INSTRUCTION_SIZE) == 444444);
CHECK(bus->read_word(0x300352A) == 444444 + 4);
// 0x300352A - 0xDA1
CHECK(getr(7) == 0x3002789 + INSTRUCTION_SIZE);
CHECK(getr(7) == 0x3002789);
// cleanup
data_transfer->rd = 5;
setr(7, getr(7) - INSTRUCTION_SIZE);
}
// byte
@@ -355,6 +383,29 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
// 0x3002789 - 0xDA1
CHECK(getr(7) == 0x30019E8);
}
// r15 as rd with load
{
data_transfer->rd = 15;
data_transfer->load = true;
setr(15, 0);
bus->write_byte(0x30019E8, 0xE2);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() ==
cycles + 5); // 2S + 2N + I for load with rd=15
// +8 cuz pipeline flushed then word aligned
// so +6
CHECK(getr(15) == 0xE8);
// 0x30019E8 - 0xDA1
CHECK(getr(7) == 0x3000C47);
// cleanup
data_transfer->rd = 5;
}
}
TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
@@ -378,7 +429,10 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
{
// 0x300611E + 0x384
bus->write_word(0x30064A2, 3948123487);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I
CHECK(getr(11) == (3948123487 & 0xFFFF));
}
@@ -436,7 +490,9 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
{
hw_transfer->load = false;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 2N
CHECK(bus->read_halfword(0x3005FD0) == (6111909 & 0xFFFF));
// 0x3005FD0 - 0xA7
@@ -446,14 +502,15 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
// r15 as rn
{
hw_transfer->rn = 15;
setr(15, 0x3005F29);
setr(15, 0x3005F28); // word aligned
exec(data);
CHECK(bus->read_halfword(0x3005F29 - 2 * INSTRUCTION_SIZE) ==
(6111909 & 0xFFFF));
// 0x3005F29 - 0xA7
CHECK(getr(15) == 0x3005E82 - 2 * INSTRUCTION_SIZE);
CHECK(bus->read_halfword(0x3005F28) == (6111909 & 0xFFFF));
// 0x3005F28 - 0xA7
// +4 cuz PC advanced
// and then word aligned
CHECK(getr(15) == 0x3005E84);
// cleanup
hw_transfer->rn = 10;
@@ -466,13 +523,12 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
exec(data);
CHECK(bus->read_halfword(0x3005F29 + INSTRUCTION_SIZE) == 224);
CHECK(bus->read_halfword(0x3005F29) == 224 + 4);
// 0x3005F29 - 0xA7
CHECK(getr(10) == 0x3005E82 + INSTRUCTION_SIZE);
CHECK(getr(10) == 0x3005E82);
// cleanup
hw_transfer->rd = 11;
setr(10, getr(10) - INSTRUCTION_SIZE);
}
// signed halfword
@@ -499,6 +555,28 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
// 0x3005DDB - 0xA7
CHECK(getr(10) == 0x3005D34);
}
// r15 as rd with load
{
hw_transfer->rd = 15;
hw_transfer->load = true;
setr(15, 0);
bus->write_byte(0x3005D34, 56);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() ==
cycles + 5); // 2S + 2N + I for load with rd=15
// +8 cuz pipeline flushed then word aligned
CHECK(getr(15) == static_cast<uint32_t>(56 + 8));
// 0x3005D34 - 0xA7
CHECK(getr(10) == 0x3005C8D);
// cleanup
hw_transfer->rd = 11;
}
}
TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
@@ -542,7 +620,10 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
CHECK(getr(12) == 0);
CHECK(getr(13) == 989231);
CHECK(getr(14) == 0);
CHECK(getr(15) == 6);
// setting r15 as 6, flushes the pipeline causing it to go 6 + 8
// i.e, 14. word aligning this, gives us 12
CHECK(getr(15) == 12);
for (uint8_t i = 0; i < 16; i++) {
setr(i, 0);
@@ -550,7 +631,9 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
};
setr(10, address);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 11); // (n+1)S + 2N + I
checker(address);
// with write
@@ -610,23 +693,30 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
setr(8, 131313333);
setr(11, 131);
setr(13, 989231);
setr(15, 6);
setr(15, 4); // word align
auto checker = [this]() {
// we will count the number of steps to count PC advances
uint8_t steps = 0;
auto checker = [this, &steps]() {
CHECK(bus->read_word(address + alignment) == 237164);
CHECK(bus->read_word(address + alignment * 2) == 679785111);
CHECK(bus->read_word(address + alignment * 3) == 905895898);
CHECK(bus->read_word(address + alignment * 4) == 131313333);
CHECK(bus->read_word(address + alignment * 5) == 131);
CHECK(bus->read_word(address + alignment * 6) == 989231);
CHECK(bus->read_word(address + alignment * 7) == 6);
CHECK(bus->read_word(address + alignment * 7) ==
4 + (4 * (steps - 1)));
for (uint8_t i = 1; i < 8; i++)
bus->write_word(address + alignment * i, 0);
};
setr(10, address); // base
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 8); // 2N + (n-1)S
steps++;
checker();
// decrement
@@ -635,6 +725,7 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
// adjust rn
setr(10, address + alignment * 8);
exec(data);
steps++;
checker();
// post increment
@@ -643,6 +734,7 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
// adjust rn
setr(10, address + alignment);
exec(data);
steps++;
checker();
// post decrement
@@ -650,12 +742,14 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
// adjust rn
setr(10, address + alignment * 7);
exec(data);
steps++;
checker();
// with s bit
cpu.chg_mode(Mode::Fiq);
block_transfer->s = true;
exec(data);
steps++;
// User's R13 is different (unset at this point)
CHECK(bus->read_word(address + alignment * 6) == 0);
}
@@ -674,7 +768,9 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
setr(12, 12389398);
CHECK(psr().raw() != getr(12));
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(psr().raw() == getr(12));
psr_transfer->spsr = true;
@@ -691,7 +787,9 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
setr(12, 16556u << 8);
CHECK(psr().raw() != getr(12));
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(psr().raw() == getr(12));
psr_transfer->spsr = true;
@@ -708,7 +806,9 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
setr(12, 1490352945);
// go to the reserved bits
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(psr().n() == get_bit(1490352945, 31));
CHECK(psr().z() == get_bit(1490352945, 30));
CHECK(psr().c() == get_bit(1490352945, 29));
@@ -719,6 +819,7 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
psr_transfer->imm = true;
psr_transfer->spsr = true;
exec(data);
CHECK(psr().n() == get_bit(1490352945, 31));
CHECK(psr(true).n() == get_bit(9933394, 31));
CHECK(psr(true).z() == get_bit(9933394, 30));
CHECK(psr(true).c() == get_bit(9933394, 29));
@@ -750,7 +851,9 @@ TEST_CASE_METHOD(CpuFixture, "Data Processing", TAG) {
{
// rm
setr(3, 1596);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
// -28717 & 12768
CHECK(getr(5) == 448);
}
@@ -767,7 +870,11 @@ TEST_CASE_METHOD(CpuFixture, "Data Processing", TAG) {
setr(3, 1596);
// rs
setr(12, 2);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 1S + 1I
// -28717 & 6384
CHECK(getr(5) == 2256);
}
@@ -1063,10 +1170,12 @@ TEST_CASE_METHOD(CpuFixture, "Data Processing", TAG) {
processing->rd = 15;
setr(15, 0);
CHECK(psr(true).raw() != psr().raw());
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
// ~54924809
CHECK(getr(15) == static_cast<uint32_t>(-54924810));
// ~54924809 + 8 (for flush) and then word adjust
CHECK(getr(15) == static_cast<uint32_t>(-54924804));
// flags are not set
flags(false, false, false, false);

47
tests/cpu/cpu-fixture.cc
View File

@@ -2,6 +2,7 @@
Psr
CpuFixture::psr(bool spsr) {
uint32_t pc = getr(15);
Psr psr(0);
Cpu tmp = cpu;
arm::Instruction instruction(
@@ -11,17 +12,19 @@ CpuFixture::psr(bool spsr) {
.type = arm::PsrTransfer::Type::Mrs,
.imm = false });
instruction.exec(tmp);
tmp.exec(instruction);
psr.set_all(getr_(0, tmp));
// reset pc
setr(15, pc);
return psr;
}
void
CpuFixture::set_psr(Psr psr, bool spsr) {
// R0
uint32_t pc = getr(15);
uint32_t old = getr(0);
setr(0, psr.raw());
arm::Instruction instruction(
@@ -31,22 +34,23 @@ CpuFixture::set_psr(Psr psr, bool spsr) {
.type = arm::PsrTransfer::Type::Msr,
.imm = false });
instruction.exec(cpu);
cpu.exec(instruction);
setr(0, old);
// reset PC
setr(15, pc);
}
// We need these workarounds to just use the public API and not private
// fields. Assuming that these work correctly is necessary. Besides, all that
// matters is that the public API is correct.
uint32_t
CpuFixture::getr_(uint8_t r, Cpu& cpu) {
uint32_t addr = 0x02000000;
uint8_t offset = r == 15 ? 4 : 0;
uint32_t word = bus->read_word(addr + offset);
Cpu tmp = cpu;
uint32_t ret = 0xFFFFFFFF;
uint8_t base = r ? 0 : 1;
CpuFixture::getr_(uint8_t r, Cpu tmp) {
uint32_t addr = 0x02000000;
uint32_t word = bus->read_word(addr);
uint32_t ret = 0xFFFFFFFF;
uint8_t base = r ? 0 : 1;
// set R0/R1 = addr
arm::Instruction zero(
@@ -69,16 +73,14 @@ CpuFixture::getr_(uint8_t r, Cpu& cpu) {
.up = true,
.pre = true });
zero.exec(tmp);
get.exec(tmp);
addr += offset;
tmp.exec(zero);
tmp.exec(get);
ret = bus->read_word(addr);
bus->write_word(addr, word);
return ret;
return ret - (r == 15 ? 4 : 0); // +4 for rd = 15 in str
}
void
@@ -86,11 +88,12 @@ CpuFixture::setr_(uint8_t r, uint32_t value, Cpu& cpu) {
// set register
arm::Instruction set(
Condition::AL,
arm::DataProcessing{ .operand = value,
.rd = r,
.rn = 0,
.set = false,
.opcode = arm::DataProcessing::OpCode::MOV });
arm::DataProcessing{
.operand = (r == 15 ? value - 8 : value), // account for pipeline flush
.rd = r,
.rn = 0,
.set = false,
.opcode = arm::DataProcessing::OpCode::MOV });
set.exec(cpu);
cpu.exec(set);
}

39
tests/cpu/cpu-fixture.hh
View File

@@ -11,20 +11,49 @@ class CpuFixture {
protected:
void exec(arm::InstructionData data, Condition condition = Condition::AL) {
// hack to account for one fetch cycle
bus->internal_cycle();
arm::Instruction instruction(condition, data);
instruction.exec(cpu);
cpu.exec(instruction);
}
void exec(thumb::InstructionData data) {
// hack to account for one fetch cycle
bus->internal_cycle();
thumb::Instruction instruction(data);
instruction.exec(cpu);
cpu.exec(instruction);
}
void reset(uint32_t value = 0) { setr(15, value + 8); }
uint32_t getr(uint8_t r) { return getr_(r, cpu); }
uint32_t getr(uint8_t r) {
uint32_t pc = 0;
void setr(uint8_t r, uint32_t value) { setr_(r, value, cpu); }
if (r != 15)
pc = getr_(15, cpu);
uint32_t ret = getr_(r, cpu);
if (r == 15)
pc = ret;
// undo PC advance
setr_(15, pc, cpu);
return ret;
}
void setr(uint8_t r, uint32_t value) {
uint32_t pc = getr_(15, cpu);
setr_(r, value, cpu);
// undo PC advance when r != 15
// when r is 15, setr_ takes account of pipeline flush
if (r != 15)
setr_(15, pc, cpu);
}
Psr psr(bool spsr = false);
@@ -35,7 +64,7 @@ class CpuFixture {
private:
// hack to get a register
uint32_t getr_(uint8_t r, Cpu& cpu);
uint32_t getr_(uint8_t r, Cpu tmp);
// hack to set a register
void setr_(uint8_t r, uint32_t value, Cpu& cpu);

203
tests/cpu/thumb/exec.cc
View File

@@ -18,7 +18,9 @@ TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
setr(3, 0);
setr(5, 6687);
// LSL
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(3) == 219119616);
setr(5, 0);
@@ -32,7 +34,11 @@ TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
move->opcode = ShiftType::LSR;
setr(5, -1827489745);
// LSR
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(3) == 75301);
CHECK(!psr().n());
@@ -47,7 +53,11 @@ TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
setr(5, -1827489745);
move->opcode = ShiftType::ASR;
// ASR
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(psr().n());
CHECK(getr(3) == 4294911525);
@@ -71,7 +81,10 @@ TEST_CASE_METHOD(CpuFixture, "Add/Subtract", TAG) {
SECTION("ADD") {
// register
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(5) == 377761225);
add->imm = true;
@@ -94,7 +107,11 @@ TEST_CASE_METHOD(CpuFixture, "Add/Subtract", TAG) {
add->opcode = AddSubtract::OpCode::SUB;
setr(2, -((1u << 31) - 1));
add->offset = 4;
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(5) == 2147483645);
CHECK(psr().v());
@@ -122,7 +139,10 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
MovCmpAddSubImmediate* move = std::get_if<MovCmpAddSubImmediate>(&data);
SECTION("MOV") {
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(5) == 251);
move->offset = 0;
@@ -136,7 +156,11 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
setr(5, 251);
move->opcode = MovCmpAddSubImmediate::OpCode::CMP;
CHECK(!psr().z());
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(5) == 251);
CHECK(psr().z());
@@ -152,7 +176,11 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
move->opcode = MovCmpAddSubImmediate::OpCode::ADD;
setr(5, (1u << 31) - 1);
// immediate and overflow
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(5) == 2147483898);
CHECK(psr().v());
@@ -168,7 +196,11 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
setr(5, 251);
move->opcode = MovCmpAddSubImmediate::OpCode::SUB;
CHECK(!psr().z());
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(5) == 0);
CHECK(psr().z());
@@ -190,8 +222,11 @@ TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
setr(3, -991);
SECTION("AND") {
uint32_t cycles = bus->get_cycles();
// 328940001 & -991
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(1) == 328939553);
CHECK(!psr().n());
@@ -221,8 +256,12 @@ TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
SECTION("LSL") {
setr(3, 3);
alu->opcode = AluOperations::OpCode::LSL;
uint32_t cycles = bus->get_cycles();
// 328940001 << 3
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 1S + 1I (shift)
CHECK(getr(1) == 2631520008);
CHECK(psr().n());
@@ -410,8 +449,12 @@ TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
SECTION("MUL") {
alu->opcode = AluOperations::OpCode::MUL;
uint32_t cycles = bus->get_cycles();
// 328940001 * -991 (lower 32 bits) (-325979540991 & 0xFFFFFFFF)
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + mI (m = 2 for -991)
CHECK(getr(1) == 437973505);
setr(3, 0);
@@ -462,19 +505,22 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
};
HiRegisterOperations* hi = std::get_if<HiRegisterOperations>(&data);
setr(15, 3452948950);
setr(15, 3452948948);
setr(5, 958656720);
SECTION("ADD") {
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(getr(5) == 116638374);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(5) == 116638372);
// hi + hi
hi->rd = 14;
hi->rs = 15;
setr(14, 42589);
exec(data);
CHECK(getr(14) == 3452991539);
CHECK(getr(14) == 3452991537);
}
SECTION("CMP") {
@@ -500,7 +546,7 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
hi->opcode = HiRegisterOperations::OpCode::MOV;
exec(data);
CHECK(getr(5) == 3452948950);
CHECK(getr(5) == 3452948948);
}
SECTION("BX") {
@@ -509,8 +555,13 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
SECTION("Arm") {
setr(10, 2189988);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(getr(15) == 2189988);
CHECK(bus->get_cycles() == cycles + 3); // 2S + N cycles
// +4 for pipeline flush
CHECK(getr(15) == 2189988 + 4);
// switched to arm
CHECK(psr().state() == State::Arm);
}
@@ -518,7 +569,9 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
SECTION("Thumb") {
setr(10, 2189989);
exec(data);
CHECK(getr(15) == 2189988);
// +4 for pipeline flush
CHECK(getr(15) == 2189988 + 4);
// switched to thumb
CHECK(psr().state() == State::Thumb);
@@ -535,7 +588,11 @@ TEST_CASE_METHOD(CpuFixture, "PC Relative Load", TAG) {
bus->write_word(0x300454C, 489753492);
CHECK(getr(0) == 0);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
CHECK(getr(0) == 489753492);
}
@@ -552,7 +609,11 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store with Register Offset", TAG) {
SECTION("store") {
// 0x3003000 + 0x332
CHECK(bus->read_word(0x3003332) == 0);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
CHECK(bus->read_word(0x3003332) == 389524259);
// byte
@@ -565,7 +626,11 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store with Register Offset", TAG) {
SECTION("load") {
load->load = true;
bus->write_word(0x3003332, 11123489);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
CHECK(getr(3) == 11123489);
// byte
@@ -589,21 +654,27 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store Sign Extended Byte/Halfword", TAG) {
SECTION("SH = 00") {
// 0x3003000 + 0x332
CHECK(bus->read_word(0x3003332) == 0);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
CHECK(bus->read_word(0x3003332) == 43811);
}
SECTION("SH = 01") {
load->h = true;
bus->write_word(0x3003332, 11123489);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
CHECK(getr(3) == 47905);
}
SECTION("SH = 10") {
load->s = true;
bus->write_word(0x3003332, 34521594);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
// sign extended 250 byte (0xFA)
CHECK(getr(3) == 4294967290);
}
@@ -613,7 +684,9 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store Sign Extended Byte/Halfword", TAG) {
load->h = true;
bus->write_word(0x3003332, 11123489);
// sign extended 47905 halfword (0xBB21)
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
CHECK(getr(3) == 4294949665);
}
}
@@ -631,7 +704,9 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store with Immediate Offset", TAG) {
SECTION("store") {
// 0x30066A + 0x6E
CHECK(bus->read_word(0x30066D8) == 0);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
CHECK(bus->read_word(0x30066D8) == 389524259);
// byte
@@ -644,7 +719,9 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store with Immediate Offset", TAG) {
SECTION("load") {
load->load = true;
bus->write_word(0x30066D8, 11123489);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
CHECK(getr(3) == 11123489);
// byte
@@ -665,14 +742,18 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store Halfword", TAG) {
SECTION("store") {
// 0x300666A + 0x6E
CHECK(bus->read_word(0x30066D8) == 0);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
CHECK(bus->read_word(0x30066D8) == 43811);
}
SECTION("load") {
load->load = true;
bus->write_word(0x30066D8, 11123489);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
CHECK(getr(3) == 47905);
}
}
@@ -689,14 +770,18 @@ TEST_CASE_METHOD(CpuFixture, "SP Relative Load", TAG) {
SECTION("store") {
// 0x3004A8A + 0x328
CHECK(bus->read_word(0x3004DB2) == 0);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
CHECK(bus->read_word(0x3004DB2) == 2349505744);
}
SECTION("load") {
load->load = true;
bus->write_word(0x3004DB2, 11123489);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
CHECK(getr(1) == 11123489);
}
}
@@ -711,8 +796,11 @@ TEST_CASE_METHOD(CpuFixture, "Load Address", TAG) {
setr(13, 69879977);
SECTION("PC") {
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(getr(1) == 337293);
CHECK(bus->get_cycles() == cycles + 1); // 1S
// word align 337293
CHECK(getr(1) == 337292);
}
SECTION("SP") {
@@ -730,7 +818,9 @@ TEST_CASE_METHOD(CpuFixture, "Add Offset to Stack Pointer", TAG) {
setr(13, 69879977);
SECTION("positive") {
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(13) == 69880450);
}
@@ -772,7 +862,9 @@ TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
setr(13, address + alignment * 5);
SECTION("without LR") {
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 6); // 2N + (n-1)S, n = 5
checker();
CHECK(getr(13) == address);
}
@@ -783,7 +875,10 @@ TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
setr(14, 999304);
// add another word on stack (top + 4)
setr(13, address + alignment * 6);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 7); // 2N + nS, n = 5
CHECK(bus->read_word(address + alignment * 5) == 999304);
checker();
@@ -819,19 +914,25 @@ TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
// set stack pointer to bottom of stack
setr(13, address);
SECTION("without SP") {
SECTION("without PC") {
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 7); // nS + N + I, n = 5
checker();
CHECK(getr(13) == address + alignment * 5);
}
SECTION("with SP") {
SECTION("with PC") {
push->pclr = true;
// populate next address
bus->write_word(address + alignment * 5, 93333912);
exec(data);
CHECK(getr(15) == 93333912);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 10); //(n+2)S + 2N + I, n = 5
// +4 for flushed pipeline
CHECK(getr(15) == 93333912 + 4);
checker();
CHECK(getr(13) == address + alignment * 6);
}
@@ -858,7 +959,9 @@ TEST_CASE_METHOD(CpuFixture, "Multiple Load/Store", TAG) {
// base
setr(2, address);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 6); //(n-1)S + 2N, n = 5
CHECK(bus->read_word(address) == 237164);
CHECK(bus->read_word(address + alignment) == address);
@@ -883,7 +986,10 @@ TEST_CASE_METHOD(CpuFixture, "Multiple Load/Store", TAG) {
// base
setr(2, address);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 7); // nS + N + 1, n = 5
CHECK(getr(0) == 237164);
CHECK(getr(1) == 0);
CHECK(getr(2) == address + alignment * 5); // write back
@@ -900,72 +1006,93 @@ TEST_CASE_METHOD(CpuFixture, "Conditional Branch", TAG) {
ConditionalBranch{ .offset = -192, .condition = Condition::EQ };
ConditionalBranch* branch = std::get_if<ConditionalBranch>(&data);
Psr cpsr = psr();
cpsr.set_state(State::Thumb);
setr(15, 4589344);
SECTION("z") {
Psr cpsr = psr();
uint32_t cycles = bus->get_cycles();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
CHECK(bus->get_cycles() == cycles + 1); // 1S
// +2 for pc advance
CHECK(getr(15) == 4589344 + 2);
cpsr.set_z(true);
set_psr(cpsr);
cycles = bus->get_cycles();
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
// +4 for pipeline flush
CHECK(getr(15) == 4589156);
}
SECTION("c") {
branch->condition = Condition::CS;
Psr cpsr = psr();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
// +2 for pc advance
CHECK(getr(15) == 4589346);
cpsr.set_c(true);
set_psr(cpsr);
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
// +4 for pipeline flush
CHECK(getr(15) == 4589156);
}
SECTION("n") {
branch->condition = Condition::MI;
Psr cpsr = psr();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
// +2 for pc advance
CHECK(getr(15) == 4589346);
cpsr.set_n(true);
set_psr(cpsr);
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
// +4 for pipeline flush
CHECK(getr(15) == 4589156);
}
SECTION("v") {
branch->condition = Condition::VS;
Psr cpsr = psr();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
// +2 for pc advance
CHECK(getr(15) == 4589346);
cpsr.set_v(true);
set_psr(cpsr);
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
// +4 for pipeline flush
CHECK(getr(15) == 4589156);
}
}
TEST_CASE_METHOD(CpuFixture, "Software Interrupt", TAG) {
InstructionData data = SoftwareInterrupt{ .vector = 33 };
InstructionData data = SoftwareInterrupt{ .vector = 32 };
setr(15, 4492);
uint32_t cycles = bus->get_cycles();
// condition is true
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
CHECK(psr().raw() == psr(true).raw());
CHECK(getr(14) == 4490);
CHECK(getr(15) == 33);
// +4 for flushed pipeline
CHECK(getr(15) == 36);
CHECK(psr().state() == State::Arm);
CHECK(psr().mode() == Mode::Supervisor);
}
@@ -974,23 +1101,39 @@ TEST_CASE_METHOD(CpuFixture, "Unconditional Branch", TAG) {
InstructionData data = UnconditionalBranch{ .offset = -920 };
setr(15, 4589344);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(getr(15) == 4588424);
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
// +4 for flushed pipeline
CHECK(getr(15) == 4588428);
}
TEST_CASE_METHOD(CpuFixture, "Long Branch With Link", TAG) {
InstructionData data = LongBranchWithLink{ .offset = 3262, .high = false };
InstructionData data =
LongBranchWithLink{ .offset = 0b10010111110, .low = false };
LongBranchWithLink* branch = std::get_if<LongBranchWithLink>(&data);
// high
setr(15, 4589344);
uint32_t cycles = bus->get_cycles();
exec(data);
CHECK(getr(14) == 2881312);
CHECK(bus->get_cycles() == cycles + 1); // 1S
CHECK(getr(14) == 1173280);
// low
branch->high = true;
branch->low = true;
cycles = bus->get_cycles();
exec(data);
CHECK(bus->get_cycles() == cycles + 3); // 2S + N
// +2 for advancing thumb, then -2 to get the next instruciton of current
// executing instruction, then set bit 0
CHECK(getr(14) == 4589343);
CHECK(getr(15) == 2884574);
// 1175712 + 4 for flushed pipeline
CHECK(getr(15) == 1175712);
}

12
tests/cpu/thumb/instruction.cc
View File

@@ -447,20 +447,20 @@ TEST_CASE("Unconditional Branch") {
}
TEST_CASE("Long Branch with link") {
uint16_t raw = 0b1111010011101100;
uint16_t raw = 0b1111110011101100;
Instruction instruction(raw);
LongBranchWithLink* bl = nullptr;
REQUIRE((bl = std::get_if<LongBranchWithLink>(&instruction.data)));
// 1260 << 1
CHECK(bl->offset == 2520);
CHECK(bl->high == false);
CHECK(bl->offset == 1260);
CHECK(bl->low == true);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "BL #2520");
CHECK(instruction.disassemble() == "BL #1260");
bl->high = true;
CHECK(instruction.disassemble() == "BLH #2520");
bl->low = false;
CHECK(instruction.disassemble() == "BLH #1260");
#endif
}