massive instruction rewrite
So, I ended up moving exec methods from Instruction to Cpu for encapsulating cycle emulation, and this has caused me lots of pain since I had to rewrite a shit ton of tests which are not even useful or comprehensible, i do no know why i put myself through this Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
@@ -1,21 +1,25 @@
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#include "bus.hh"
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#include "cpu/cpu.hh"
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#include "util/bits.hh"
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#include "util/log.hh"
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namespace matar::arm {
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namespace matar {
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void
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Instruction::exec(Cpu& cpu) {
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if (!cpu.cpsr.condition(condition)) {
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Cpu::exec(arm::Instruction& instruction) {
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bool is_flushed = false;
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if (!cpsr.condition(instruction.condition)) {
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advance_pc_arm();
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return;
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}
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auto pc_error = [cpu](uint8_t r) {
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if (r == cpu.PC_INDEX)
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auto pc_error = [](uint8_t r) {
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if (r == PC_INDEX)
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glogger.error("Using PC (R15) as operand register");
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};
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auto pc_warn = [cpu](uint8_t r) {
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if (r == cpu.PC_INDEX)
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auto pc_warn = [](uint8_t r) {
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if (r == PC_INDEX)
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glogger.warn("Using PC (R15) as operand register");
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};
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@@ -23,7 +27,7 @@ Instruction::exec(Cpu& cpu) {
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std::visit(
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overloaded{
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[&cpu, pc_warn](BranchAndExchange& data) {
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[this, pc_warn, &is_flushed](BranchAndExchange& data) {
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/*
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S -> reading instruction in step()
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N -> fetch from the new address in branch
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@@ -32,30 +36,30 @@ Instruction::exec(Cpu& cpu) {
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1S done, S+N taken care of by flush_pipeline()
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*/
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uint32_t addr = cpu.gpr[data.rn];
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uint32_t addr = gpr[data.rn];
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State state = static_cast<State>(get_bit(addr, 0));
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pc_warn(data.rn);
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if (state != cpu.cpsr.state())
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if (state != cpsr.state())
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glogger.info_bold("State changed");
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// set state
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cpu.cpsr.set_state(state);
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cpsr.set_state(state);
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// copy to PC
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cpu.pc = addr;
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pc = addr;
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// ignore [1:0] bits for arm and 0 bit for thumb
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rst_bit(cpu.pc, 0);
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rst_bit(pc, 0);
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if (state == State::Arm)
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rst_bit(cpu.pc, 1);
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rst_bit(pc, 1);
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// PC is affected so flush the pipeline
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cpu.is_flushed = true;
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is_flushed = true;
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},
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[&cpu](Branch& data) {
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[this, &is_flushed](Branch& data) {
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/*
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S -> reading instruction in step()
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N -> fetch from the new address in branch
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@@ -65,14 +69,14 @@ Instruction::exec(Cpu& cpu) {
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*/
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if (data.link)
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cpu.gpr[14] = cpu.pc - INSTRUCTION_SIZE;
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gpr[14] = pc - INSTRUCTION_SIZE;
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cpu.pc += data.offset;
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pc += data.offset;
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// pc is affected so flush the pipeline
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cpu.is_flushed = true;
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is_flushed = true;
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},
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[&cpu, pc_error](Multiply& data) {
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[this, pc_error](Multiply& data) {
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/*
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S -> reading instruction in step()
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mI -> m internal cycles
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@@ -95,36 +99,34 @@ Instruction::exec(Cpu& cpu) {
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pc_error(data.rd);
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// mI
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for (int i = 0; i < multiplier_array_cycles(cpu.gpr[data.rs]); i++)
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cpu.internal_cycle();
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for (int i = 0; i < multiplier_array_cycles(gpr[data.rs]); i++)
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internal_cycle();
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cpu.gpr[data.rd] = cpu.gpr[data.rm] * cpu.gpr[data.rs];
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gpr[data.rd] = gpr[data.rm] * gpr[data.rs];
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if (data.acc) {
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cpu.gpr[data.rd] += cpu.gpr[data.rn];
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gpr[data.rd] += gpr[data.rn];
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// 1I
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cpu.internal_cycle();
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internal_cycle();
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}
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if (data.set) {
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cpu.cpsr.set_z(cpu.gpr[data.rd] == 0);
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cpu.cpsr.set_n(get_bit(cpu.gpr[data.rd], 31));
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cpu.cpsr.set_c(0);
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cpsr.set_z(gpr[data.rd] == 0);
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cpsr.set_n(get_bit(gpr[data.rd], 31));
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cpsr.set_c(0);
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}
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},
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[&cpu, pc_error](MultiplyLong& data) {
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[this, pc_error](MultiplyLong& data) {
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/*
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S -> reading instruction in step()
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(m+1)I -> m + 1 internal cycles
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I -> only when accumulating
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let v = data at rn
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let v = data at rs
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m = 1 if bits [32:8] of v are all zeroes (or all ones if signed)
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m = 2 [32:16]
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m = 3 [32:24]
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m = 4 otherwise
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Total = S + mI or S + (m+1)I
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Total = S + (m+1)I or S + (m+2)I
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*/
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@@ -140,56 +142,54 @@ Instruction::exec(Cpu& cpu) {
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// 1I
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if (data.acc)
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cpu.internal_cycle();
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internal_cycle();
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// m+1 internal cycles
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for (int i = 0;
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i <= multiplier_array_cycles(cpu.gpr[data.rs], data.uns);
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i <= multiplier_array_cycles(gpr[data.rs], data.uns);
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i++)
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cpu.internal_cycle();
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internal_cycle();
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if (data.uns) {
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auto cast = [](uint32_t x) -> uint64_t {
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return static_cast<uint64_t>(x);
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};
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uint64_t eval =
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cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
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(data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
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cast(cpu.gpr[data.rdlo])
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: 0);
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uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
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(data.acc ? (cast(gpr[data.rdhi]) << 32) |
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cast(gpr[data.rdlo])
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: 0);
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cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
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cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
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gpr[data.rdlo] = bit_range(eval, 0, 31);
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gpr[data.rdhi] = bit_range(eval, 32, 63);
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} else {
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auto cast = [](uint32_t x) -> int64_t {
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return static_cast<int64_t>(static_cast<int32_t>(x));
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};
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int64_t eval = cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
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(data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
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cast(cpu.gpr[data.rdlo])
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int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
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(data.acc ? (cast(gpr[data.rdhi]) << 32) |
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cast(gpr[data.rdlo])
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: 0);
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cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
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cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
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gpr[data.rdlo] = bit_range(eval, 0, 31);
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gpr[data.rdhi] = bit_range(eval, 32, 63);
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}
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if (data.set) {
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cpu.cpsr.set_z(cpu.gpr[data.rdhi] == 0 &&
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cpu.gpr[data.rdlo] == 0);
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cpu.cpsr.set_n(get_bit(cpu.gpr[data.rdhi], 31));
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cpu.cpsr.set_c(0);
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cpu.cpsr.set_v(0);
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cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
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cpsr.set_n(get_bit(gpr[data.rdhi], 31));
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cpsr.set_c(0);
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cpsr.set_v(0);
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}
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},
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[](Undefined) {
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// this should be 2S + N + I, should i flush the pipeline? i dont
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// know. TODO: study
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// this should be 2S + N + I, should i flush the pipeline? i
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// dont know. TODO: study
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glogger.warn("Undefined instruction");
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},
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[&cpu, pc_error](SingleDataSwap& data) {
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[this, pc_error](SingleDataSwap& data) {
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/*
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N -> reading instruction in step()
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N -> unrelated read
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@@ -203,23 +203,22 @@ Instruction::exec(Cpu& cpu) {
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pc_error(data.rd);
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if (data.byte) {
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cpu.gpr[data.rd] = cpu.bus->read_byte(cpu.gpr[data.rn],
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CpuAccess::NonSequential);
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cpu.bus->write_byte(cpu.gpr[data.rn],
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cpu.gpr[data.rm] & 0xFF,
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CpuAccess::Sequential);
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gpr[data.rd] =
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bus->read_byte(gpr[data.rn], CpuAccess::NonSequential);
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bus->write_byte(
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gpr[data.rn], gpr[data.rm] & 0xFF, CpuAccess::Sequential);
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} else {
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cpu.gpr[data.rd] = cpu.bus->read_word(cpu.gpr[data.rn],
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CpuAccess::NonSequential);
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cpu.bus->write_word(
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cpu.gpr[data.rn], cpu.gpr[data.rm], CpuAccess::Sequential);
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gpr[data.rd] =
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bus->read_word(gpr[data.rn], CpuAccess::NonSequential);
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bus->write_word(
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gpr[data.rn], gpr[data.rm], CpuAccess::Sequential);
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}
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cpu.internal_cycle();
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internal_cycle();
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// last write address is unrelated to next
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cpu.next_access = CpuAccess::NonSequential;
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next_access = CpuAccess::NonSequential;
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},
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[&cpu, pc_warn, pc_error](SingleDataTransfer& data) {
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[this, pc_warn, pc_error, &is_flushed](SingleDataTransfer& data) {
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/*
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Load
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====
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@@ -236,13 +235,13 @@ Instruction::exec(Cpu& cpu) {
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Total = 2N
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*/
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uint32_t offset = 0;
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uint32_t address = cpu.gpr[data.rn];
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uint32_t address = gpr[data.rn];
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if (!data.pre && data.write)
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glogger.warn("Write-back enabled with post-indexing in {}",
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typeid(data).name());
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if (data.rn == cpu.PC_INDEX && data.write)
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if (data.rn == PC_INDEX && data.write)
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glogger.warn("Write-back enabled with base register as PC {}",
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typeid(data).name());
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@@ -256,18 +255,18 @@ Instruction::exec(Cpu& cpu) {
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} else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
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uint8_t amount =
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(shift->data.immediate ? shift->data.operand
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: cpu.gpr[shift->data.operand] & 0xFF);
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: gpr[shift->data.operand] & 0xFF);
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bool carry = cpu.cpsr.c();
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bool carry = cpsr.c();
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if (!shift->data.immediate)
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pc_error(shift->data.operand);
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pc_error(shift->rm);
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offset = eval_shift(
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shift->data.type, cpu.gpr[shift->rm], amount, carry);
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offset =
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eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
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cpu.cpsr.set_c(carry);
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cpsr.set_c(carry);
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}
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if (data.pre)
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@@ -277,46 +276,47 @@ Instruction::exec(Cpu& cpu) {
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if (data.load) {
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// byte
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if (data.byte)
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cpu.gpr[data.rd] =
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cpu.bus->read_byte(address, CpuAccess::NonSequential);
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gpr[data.rd] =
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bus->read_byte(address, CpuAccess::NonSequential);
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// word
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else
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cpu.gpr[data.rd] =
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cpu.bus->read_word(address, CpuAccess::NonSequential);
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gpr[data.rd] =
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bus->read_word(address, CpuAccess::NonSequential);
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// N + S
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if (data.rd == cpu.PC_INDEX)
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cpu.is_flushed = true;
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if (data.rd == PC_INDEX)
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is_flushed = true;
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// I
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cpu.internal_cycle();
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internal_cycle();
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// store
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} else {
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// take PC into consideration
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if (data.rd == cpu.PC_INDEX)
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address += INSTRUCTION_SIZE;
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uint32_t value = gpr[data.rd];
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if (data.rd == PC_INDEX)
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value += INSTRUCTION_SIZE;
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// byte
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if (data.byte)
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cpu.bus->write_byte(address,
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cpu.gpr[data.rd] & 0xFF,
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CpuAccess::NonSequential);
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bus->write_byte(
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address, value & 0xFF, CpuAccess::NonSequential);
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// word
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else
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cpu.bus->write_word(
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address, cpu.gpr[data.rd], CpuAccess::NonSequential);
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bus->write_word(address, value, CpuAccess::NonSequential);
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}
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if (!data.pre)
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address += (data.up ? offset : -offset);
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if (!data.pre || data.write)
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cpu.gpr[data.rn] = address;
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gpr[data.rn] = address;
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// last read/write is unrelated, this will be overwriten if flushed
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cpu.next_access = CpuAccess::NonSequential;
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// last read/write is unrelated, this will be overwriten if
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// flushed
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next_access = CpuAccess::NonSequential;
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},
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[&cpu, pc_warn, pc_error](HalfwordTransfer& data) {
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[this, pc_warn, pc_error, &is_flushed](HalfwordTransfer& data) {
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/*
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Load
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====
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@@ -332,7 +332,7 @@ Instruction::exec(Cpu& cpu) {
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N -> write at target
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Total = 2N
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*/
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uint32_t address = cpu.gpr[data.rn];
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uint32_t address = gpr[data.rn];
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uint32_t offset = 0;
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if (!data.pre && data.write)
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@@ -348,15 +348,11 @@ Instruction::exec(Cpu& cpu) {
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// offset is register number (4 bits) when not an immediate
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if (!data.imm) {
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pc_error(data.offset);
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offset = cpu.gpr[data.offset];
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offset = gpr[data.offset];
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} else {
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offset = data.offset;
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}
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// PC is always two instructions ahead
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if (data.rn == cpu.PC_INDEX)
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address -= 2 * INSTRUCTION_SIZE;
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if (data.pre)
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address += (data.up ? offset : -offset);
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@@ -366,56 +362,59 @@ Instruction::exec(Cpu& cpu) {
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if (data.sign) {
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// halfword
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if (data.half) {
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cpu.gpr[data.rd] = cpu.bus->read_halfword(
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address, CpuAccess::NonSequential);
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gpr[data.rd] =
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bus->read_halfword(address, CpuAccess::NonSequential);
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// sign extend the halfword
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cpu.gpr[data.rd] =
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(static_cast<int32_t>(cpu.gpr[data.rd]) << 16) >> 16;
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gpr[data.rd] =
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(static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
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// byte
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} else {
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cpu.gpr[data.rd] =
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cpu.bus->read_byte(address, CpuAccess::NonSequential);
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gpr[data.rd] =
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bus->read_byte(address, CpuAccess::NonSequential);
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// sign extend the byte
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cpu.gpr[data.rd] =
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(static_cast<int32_t>(cpu.gpr[data.rd]) << 24) >> 24;
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gpr[data.rd] =
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(static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
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}
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// unsigned halfword
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} else if (data.half) {
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cpu.gpr[data.rd] =
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cpu.bus->read_halfword(address, CpuAccess::NonSequential);
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gpr[data.rd] =
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bus->read_halfword(address, CpuAccess::NonSequential);
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}
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// I
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cpu.internal_cycle();
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internal_cycle();
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if (data.rd == cpu.PC_INDEX)
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cpu.is_flushed = true;
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if (data.rd == PC_INDEX)
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is_flushed = true;
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// store
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} else {
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uint32_t value = gpr[data.rd];
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// take PC into consideration
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if (data.rd == cpu.PC_INDEX)
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address += INSTRUCTION_SIZE;
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if (data.rd == PC_INDEX)
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value += INSTRUCTION_SIZE;
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// halfword
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if (data.half)
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cpu.bus->write_halfword(
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address, cpu.gpr[data.rd], CpuAccess::NonSequential);
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bus->write_halfword(
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address, value & 0xFFFF, CpuAccess::NonSequential);
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}
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if (!data.pre)
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address += (data.up ? offset : -offset);
|
||||
|
||||
if (!data.pre || data.write)
|
||||
cpu.gpr[data.rn] = address;
|
||||
gpr[data.rn] = address;
|
||||
|
||||
// last read/write is unrelated, this will be overwriten if flushed
|
||||
cpu.next_access = CpuAccess::NonSequential;
|
||||
// last read/write is unrelated, this will be overwriten if
|
||||
// flushed
|
||||
next_access = CpuAccess::NonSequential;
|
||||
},
|
||||
[&cpu, pc_error](BlockDataTransfer& data) {
|
||||
[this, pc_error, &is_flushed](BlockDataTransfer& data) {
|
||||
/*
|
||||
Load
|
||||
====
|
||||
@@ -423,8 +422,8 @@ Instruction::exec(Cpu& cpu) {
|
||||
N -> unrelated read from target
|
||||
(n-1) S -> next n - 1 related reads from target
|
||||
I -> stored in register
|
||||
N+S -> if PC is written - taken care of by flush_pipeline()
|
||||
Total = nS + N + I or (n+1)S + 2N + I
|
||||
N+S -> if PC is written - taken care of by
|
||||
flush_pipeline() Total = nS + N + I or (n+1)S + 2N + I
|
||||
|
||||
Store
|
||||
=====
|
||||
@@ -436,22 +435,22 @@ Instruction::exec(Cpu& cpu) {
|
||||
|
||||
static constexpr uint8_t alignment = 4; // word
|
||||
|
||||
uint32_t address = cpu.gpr[data.rn];
|
||||
Mode mode = cpu.cpsr.mode();
|
||||
uint32_t address = gpr[data.rn];
|
||||
Mode mode = cpsr.mode();
|
||||
int8_t i = 0;
|
||||
CpuAccess access = CpuAccess::NonSequential;
|
||||
|
||||
pc_error(data.rn);
|
||||
|
||||
if (cpu.cpsr.mode() == Mode::User && data.s) {
|
||||
if (cpsr.mode() == Mode::User && data.s) {
|
||||
glogger.error("Bit S is set outside priviliged modes in block "
|
||||
"data transfer");
|
||||
}
|
||||
|
||||
// we just change modes to load user registers
|
||||
if ((!get_bit(data.regs, cpu.PC_INDEX) && data.s) ||
|
||||
if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
|
||||
(!data.load && data.s)) {
|
||||
cpu.chg_mode(Mode::User);
|
||||
chg_mode(Mode::User);
|
||||
|
||||
if (data.write) {
|
||||
glogger.error("Write-back enable for user bank registers "
|
||||
@@ -464,27 +463,27 @@ Instruction::exec(Cpu& cpu) {
|
||||
address += (data.up ? alignment : -alignment);
|
||||
|
||||
if (data.load) {
|
||||
if (get_bit(data.regs, cpu.PC_INDEX)) {
|
||||
cpu.is_flushed = true;
|
||||
if (get_bit(data.regs, PC_INDEX)) {
|
||||
is_flushed = true;
|
||||
|
||||
// current mode's cpu.spsr is already loaded when it was
|
||||
// current mode's spsr is already loaded when it was
|
||||
// switched
|
||||
if (data.s)
|
||||
cpu.spsr = cpu.cpsr;
|
||||
spsr = cpsr;
|
||||
}
|
||||
|
||||
if (data.up) {
|
||||
for (i = 0; i < cpu.GPR_COUNT; i++) {
|
||||
for (i = 0; i < GPR_COUNT; i++) {
|
||||
if (get_bit(data.regs, i)) {
|
||||
cpu.gpr[i] = cpu.bus->read_word(address, access);
|
||||
gpr[i] = bus->read_word(address, access);
|
||||
address += alignment;
|
||||
access = CpuAccess::Sequential;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (i = cpu.GPR_COUNT - 1; i >= 0; i--) {
|
||||
for (i = GPR_COUNT - 1; i >= 0; i--) {
|
||||
if (get_bit(data.regs, i)) {
|
||||
cpu.gpr[i] = cpu.bus->read_word(address, access);
|
||||
gpr[i] = bus->read_word(address, access);
|
||||
address -= alignment;
|
||||
access = CpuAccess::Sequential;
|
||||
}
|
||||
@@ -492,20 +491,20 @@ Instruction::exec(Cpu& cpu) {
|
||||
}
|
||||
|
||||
// I
|
||||
cpu.internal_cycle();
|
||||
internal_cycle();
|
||||
} else {
|
||||
if (data.up) {
|
||||
for (i = 0; i < cpu.GPR_COUNT; i++) {
|
||||
for (i = 0; i < GPR_COUNT; i++) {
|
||||
if (get_bit(data.regs, i)) {
|
||||
cpu.bus->write_word(address, cpu.gpr[i], access);
|
||||
bus->write_word(address, gpr[i], access);
|
||||
address += alignment;
|
||||
access = CpuAccess::Sequential;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (i = cpu.GPR_COUNT - 1; i >= 0; i--) {
|
||||
for (i = GPR_COUNT - 1; i >= 0; i--) {
|
||||
if (get_bit(data.regs, i)) {
|
||||
cpu.bus->write_word(address, cpu.gpr[i], access);
|
||||
bus->write_word(address, gpr[i], access);
|
||||
address -= alignment;
|
||||
access = CpuAccess::Sequential;
|
||||
}
|
||||
@@ -518,47 +517,48 @@ Instruction::exec(Cpu& cpu) {
|
||||
address += (data.up ? -alignment : alignment);
|
||||
|
||||
if (!data.pre || data.write)
|
||||
cpu.gpr[data.rn] = address;
|
||||
gpr[data.rn] = address;
|
||||
|
||||
// load back the original mode registers
|
||||
cpu.chg_mode(mode);
|
||||
chg_mode(mode);
|
||||
|
||||
// last read/write is unrelated, this will be overwriten if flushed
|
||||
cpu.next_access = CpuAccess::NonSequential;
|
||||
// last read/write is unrelated, this will be overwriten if
|
||||
// flushed
|
||||
next_access = CpuAccess::NonSequential;
|
||||
},
|
||||
[&cpu, pc_error](PsrTransfer& data) {
|
||||
[this, pc_error](PsrTransfer& data) {
|
||||
/*
|
||||
S -> prefetched instruction in step()
|
||||
Total = 1S cycle
|
||||
*/
|
||||
|
||||
if (data.spsr && cpu.cpsr.mode() == Mode::User) {
|
||||
glogger.error("Accessing CPU.SPSR in User mode in {}",
|
||||
if (data.spsr && cpsr.mode() == Mode::User) {
|
||||
glogger.error("Accessing SPSR in User mode in {}",
|
||||
typeid(data).name());
|
||||
}
|
||||
|
||||
Psr& psr = data.spsr ? cpu.spsr : cpu.cpsr;
|
||||
Psr& psr = data.spsr ? spsr : cpsr;
|
||||
|
||||
switch (data.type) {
|
||||
case PsrTransfer::Type::Mrs:
|
||||
pc_error(data.operand);
|
||||
cpu.gpr[data.operand] = psr.raw();
|
||||
gpr[data.operand] = psr.raw();
|
||||
break;
|
||||
case PsrTransfer::Type::Msr:
|
||||
pc_error(data.operand);
|
||||
|
||||
if (cpu.cpsr.mode() != Mode::User) {
|
||||
if (cpsr.mode() != Mode::User) {
|
||||
if (!data.spsr) {
|
||||
Psr tmp = Psr(cpu.gpr[data.operand]);
|
||||
cpu.chg_mode(tmp.mode());
|
||||
Psr tmp = Psr(gpr[data.operand]);
|
||||
chg_mode(tmp.mode());
|
||||
}
|
||||
|
||||
psr.set_all(cpu.gpr[data.operand]);
|
||||
psr.set_all(gpr[data.operand]);
|
||||
}
|
||||
break;
|
||||
case PsrTransfer::Type::Msr_flg:
|
||||
uint32_t operand =
|
||||
(data.imm ? data.operand : cpu.gpr[data.operand]);
|
||||
(data.imm ? data.operand : gpr[data.operand]);
|
||||
psr.set_n(get_bit(operand, 31));
|
||||
psr.set_z(get_bit(operand, 30));
|
||||
psr.set_c(get_bit(operand, 29));
|
||||
@@ -566,7 +566,7 @@ Instruction::exec(Cpu& cpu) {
|
||||
break;
|
||||
}
|
||||
},
|
||||
[&cpu, pc_error](DataProcessing& data) {
|
||||
[this, pc_error, &is_flushed](DataProcessing& data) {
|
||||
/*
|
||||
Always
|
||||
======
|
||||
@@ -587,7 +587,7 @@ Instruction::exec(Cpu& cpu) {
|
||||
|
||||
using OpCode = DataProcessing::OpCode;
|
||||
|
||||
uint32_t op_1 = cpu.gpr[data.rn];
|
||||
uint32_t op_1 = gpr[data.rn];
|
||||
uint32_t op_2 = 0;
|
||||
|
||||
uint32_t result = 0;
|
||||
@@ -598,30 +598,30 @@ Instruction::exec(Cpu& cpu) {
|
||||
} else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
|
||||
uint8_t amount =
|
||||
(shift->data.immediate ? shift->data.operand
|
||||
: cpu.gpr[shift->data.operand] & 0xFF);
|
||||
: gpr[shift->data.operand] & 0xFF);
|
||||
|
||||
bool carry = cpu.cpsr.c();
|
||||
bool carry = cpsr.c();
|
||||
|
||||
if (!shift->data.immediate)
|
||||
pc_error(shift->data.operand);
|
||||
pc_error(shift->rm);
|
||||
|
||||
op_2 = eval_shift(
|
||||
shift->data.type, cpu.gpr[shift->rm], amount, carry);
|
||||
op_2 =
|
||||
eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
|
||||
|
||||
cpu.cpsr.set_c(carry);
|
||||
cpsr.set_c(carry);
|
||||
|
||||
// PC is 12 bytes ahead when shifting
|
||||
if (data.rn == cpu.PC_INDEX)
|
||||
if (data.rn == PC_INDEX)
|
||||
op_1 += INSTRUCTION_SIZE;
|
||||
|
||||
// 1I when register specified shift
|
||||
if (shift->data.operand)
|
||||
cpu.internal_cycle();
|
||||
if (!shift->data.immediate)
|
||||
internal_cycle();
|
||||
}
|
||||
|
||||
bool overflow = cpu.cpsr.v();
|
||||
bool carry = cpu.cpsr.c();
|
||||
bool overflow = cpsr.v();
|
||||
bool carry = cpsr.c();
|
||||
|
||||
switch (data.opcode) {
|
||||
case OpCode::AND:
|
||||
@@ -667,19 +667,19 @@ Instruction::exec(Cpu& cpu) {
|
||||
break;
|
||||
}
|
||||
|
||||
auto set_conditions = [&cpu, carry, overflow, result]() {
|
||||
cpu.cpsr.set_c(carry);
|
||||
cpu.cpsr.set_v(overflow);
|
||||
cpu.cpsr.set_n(get_bit(result, 31));
|
||||
cpu.cpsr.set_z(result == 0);
|
||||
auto set_conditions = [this, carry, overflow, result]() {
|
||||
cpsr.set_c(carry);
|
||||
cpsr.set_v(overflow);
|
||||
cpsr.set_n(get_bit(result, 31));
|
||||
cpsr.set_z(result == 0);
|
||||
};
|
||||
|
||||
if (data.set) {
|
||||
if (data.rd == cpu.PC_INDEX) {
|
||||
if (cpu.cpsr.mode() == Mode::User)
|
||||
if (data.rd == PC_INDEX) {
|
||||
if (cpsr.mode() == Mode::User)
|
||||
glogger.error("Running {} in User mode",
|
||||
typeid(data).name());
|
||||
cpu.spsr = cpu.cpsr;
|
||||
spsr = cpsr;
|
||||
} else {
|
||||
set_conditions();
|
||||
}
|
||||
@@ -689,19 +689,29 @@ Instruction::exec(Cpu& cpu) {
|
||||
data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
|
||||
set_conditions();
|
||||
} else {
|
||||
cpu.gpr[data.rd] = result;
|
||||
if (data.rd == cpu.PC_INDEX || data.opcode == OpCode::MVN)
|
||||
cpu.is_flushed = true;
|
||||
gpr[data.rd] = result;
|
||||
if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
|
||||
is_flushed = true;
|
||||
}
|
||||
},
|
||||
[&cpu](SoftwareInterrupt) {
|
||||
cpu.chg_mode(Mode::Supervisor);
|
||||
cpu.pc = 0x08;
|
||||
cpu.spsr = cpu.cpsr;
|
||||
[this, &is_flushed](SoftwareInterrupt) {
|
||||
chg_mode(Mode::Supervisor);
|
||||
pc = 0x00;
|
||||
spsr = cpsr;
|
||||
is_flushed = true;
|
||||
},
|
||||
[](auto& data) {
|
||||
glogger.error("Unimplemented {} instruction", typeid(data).name());
|
||||
} },
|
||||
data);
|
||||
instruction.data);
|
||||
|
||||
if (is_flushed) {
|
||||
opcodes[0] = bus->read_word(pc, CpuAccess::NonSequential);
|
||||
advance_pc_arm();
|
||||
opcodes[1] = bus->read_word(pc, CpuAccess::Sequential);
|
||||
advance_pc_arm();
|
||||
next_access = CpuAccess::Sequential;
|
||||
} else
|
||||
advance_pc_arm();
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user