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memory: bus and rom should not be writeable

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so fix tests and shit

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
This commit is contained in:
Amneesh Singh
2023-10-05 00:21:18 +05:30
parent e0f7f32699
commit 174008f60c
8 changed files with 255 additions and 252 deletions
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20
src/cpu/arm/exec.cc
View File

@@ -282,17 +282,18 @@ Instruction::exec(Cpu& cpu) {
cpu.is_flushed = true;
},
[&cpu, pc_error](BlockDataTransfer& data) {
uint32_t address = cpu.gpr[data.rn];
Mode mode = cpu.cpsr.mode();
uint8_t alignment = 4; // word
uint8_t i = 0;
uint8_t n_regs = std::popcount(data.regs);
static constexpr uint8_t alignment = 4; // word
uint32_t address = cpu.gpr[data.rn];
Mode mode = cpu.cpsr.mode();
uint8_t i = 0;
uint8_t n_regs = std::popcount(data.regs);
pc_error(data.rn);
if (cpu.cpsr.mode() == Mode::User && data.s) {
glogger.error("Bit S is set outside priviliged modes in {}",
typeid(data).name());
glogger.error("Bit S is set outside priviliged modes in block "
"data transfer");
}
// we just change modes to load user registers
@@ -301,9 +302,8 @@ Instruction::exec(Cpu& cpu) {
cpu.chg_mode(Mode::User);
if (data.write) {
glogger.error(
"Write-back enable for user bank registers in {}",
typeid(data).name());
glogger.error("Write-back enable for user bank registers "
"in block data transfer");
}
}

16
src/cpu/thumb/exec.cc
View File

@@ -286,47 +286,51 @@ Instruction::exec(Cpu& cpu) {
},
[&cpu](AddOffsetStackPointer& data) { cpu.sp += data.word; },
[&cpu](PushPopRegister& data) {
static constexpr uint8_t alignment = 4;
if (data.load) {
for (uint8_t i = 0; i < 8; i++) {
if (get_bit(data.regs, i)) {
cpu.gpr[i] = cpu.bus->read_word(cpu.sp);
cpu.sp += 4;
cpu.sp += alignment;
}
}
if (data.pclr) {
cpu.pc = cpu.bus->read_word(cpu.sp);
cpu.sp += 4;
cpu.sp += alignment;
cpu.is_flushed = true;
}
} else {
if (data.pclr) {
cpu.sp -= 4;
cpu.sp -= alignment;
cpu.bus->write_word(cpu.sp, cpu.lr);
}
for (int8_t i = 7; i >= 0; i--) {
if (get_bit(data.regs, i)) {
cpu.sp -= 4;
cpu.sp -= alignment;
cpu.bus->write_word(cpu.sp, cpu.gpr[i]);
}
}
}
},
[&cpu](MultipleLoad& data) {
static constexpr uint8_t alignment = 4;
uint32_t rb = cpu.gpr[data.rb];
if (data.load) {
for (uint8_t i = 0; i < 8; i++) {
if (get_bit(data.regs, i)) {
cpu.gpr[i] = cpu.bus->read_word(rb);
rb += 4;
rb += alignment;
}
}
} else {
for (int8_t i = 7; i >= 0; i--) {
if (get_bit(data.regs, i)) {
rb -= 4;
rb -= alignment;
cpu.bus->write_word(rb, cpu.gpr[i]);
}
}

6
src/memory.cc
View File

@@ -64,23 +64,17 @@ Memory::write(size_t address, uint8_t byte) {
return; \
}
MATCHES(BIOS, bios)
MATCHES(BOARD_WRAM, board_wram)
MATCHES(CHIP_WRAM, chip_wram)
MATCHES(PALETTE_RAM, palette_ram)
MATCHES(VRAM, vram)
MATCHES(OAM_OBJ_ATTR, oam_obj_attr)
MATCHES(ROM_0, rom)
MATCHES(ROM_1, rom)
MATCHES(ROM_2, rom)
glogger.error("Invalid memory region accessed");
#undef MATCHES
}
#undef MATCHES
void
Memory::parse_header() {
if (rom.size() < header.HEADER_SIZE) {