cpu/{arm|thumb}(chore): change how branch disassembly happens
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
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@@ -24,18 +24,25 @@ TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
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InstructionData data = Branch{ .link = false, .offset = 3489748 };
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Branch* branch = std::get_if<Branch>(&data);
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// set PC to 48
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setr(15, 48);
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exec(data);
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CHECK(getr(15) == 3489748);
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// 48 + offset
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CHECK(getr(15) == 3489796);
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CHECK(getr(14) == 0);
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// with link
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reset();
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setr(15, 48);
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branch->link = true;
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exec(data);
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CHECK(getr(15) == 3489748);
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CHECK(getr(14) == 0 + INSTRUCTION_SIZE);
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// 48 + offset
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CHECK(getr(15) == 3489796);
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// pc was set to 48
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CHECK(getr(14) == 48 - INSTRUCTION_SIZE);
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}
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TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
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@@ -31,15 +31,16 @@ TEST_CASE("Branch", TAG) {
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// last 24 bits = 8748995
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// (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
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// Also +8 since PC is two instructions ahead
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CHECK(b->offset == 0xFE15FF14);
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CHECK(b->offset == static_cast<int32_t>(0xfe15ff0c));
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CHECK(b->link == true);
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#ifdef DISASSEMBLER
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CHECK(instruction.disassemble() == "BL 0xFE15FF14");
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// take prefetch into account
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// offset + 8 = 0xfe15ff0c + 8 = -0x1ea00e4 + 8
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CHECK(instruction.disassemble() == "BL -0x1ea00ec");
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b->link = false;
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CHECK(instruction.disassemble() == "B 0xFE15FF14");
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CHECK(instruction.disassemble() == "B -0x1ea00ec");
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#endif
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}
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@@ -412,7 +412,8 @@ TEST_CASE("Conditional Branch", TAG) {
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CHECK(b->condition == Condition::LS);
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#ifdef DISASSEMBLER
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// (-76 << 1) + PC (0) + 4
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// take prefetch into account
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// offset + 4 = -152 + 4
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CHECK(instruction.disassemble() == "BLS #-148");
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#endif
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}
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@@ -439,7 +440,8 @@ TEST_CASE("Unconditional Branch") {
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REQUIRE(b->offset == -410);
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#ifdef DISASSEMBLER
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// (2147483443 << 1) + PC(0) + 4
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// take prefetch into account
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// offset + 4 = -410 + 4
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CHECK(instruction.disassemble() == "B #-406");
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#endif
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}
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