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natto1784:master natto1784:thumb natto1784:tests natto1784:build-system natto1784:test-public-api

4 Commits
thumb ... 36d71a4ee2

Author SHA1 Message Date
Amneesh Singh
36d71a4ee2 thumb: add execution of instructions 
also arm: fix some instructions

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
 2023-09-30 01:31:09 +05:30
Amneesh Singh
03dbb7052f nix: bump 
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
 2023-09-30 01:30:44 +05:30
Amneesh Singh
0f09874929 cpu: get rid of the test workaround 
now can we remove the pimpl?

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
 2023-09-27 22:43:50 +05:30
Amneesh Singh
03ebc6378a clang: make linter happy 
Signed-off-by: Amneesh Singh <natto@weirdnatto.in>
 2023-09-27 17:36:25 +05:30
28 changed files with 2199 additions and 585 deletions
Expand all files Collapse all files

6
flake.lock generated
View File

@@ -20,11 +20,11 @@
},
"nixpkgs": {
"locked": {
"lastModified": 1695318763,
"narHash": "sha256-FHVPDRP2AfvsxAdc+AsgFJevMz5VBmnZglFUMlxBkcY=",
"lastModified": 1695806987,
"narHash": "sha256-fX5kGs66NZIxCMcpAGIpxuftajHL8Hil1vjHmjjl118=",
"owner": "nixos",
"repo": "nixpkgs",
"rev": "e12483116b3b51a185a33a272bf351e357ba9a99",
"rev": "f3dab3509afca932f3f4fd0908957709bb1c1f57",
"type": "github"
},
"original": {

5
meson.build
View File

@@ -24,11 +24,6 @@ else
error(compiler.get_id() + ' ' + compiler.version() + 'does not meet the compiler requirements')
endif
if compiler.has_argument('-fexperimental-library')
add_global_arguments('-fexperimental-library', language: 'cpp')
else
error(compiler.get_id() + ' ' + compiler.version() + 'does not support -fexperimental-library')
endif
'''
subdir('include')

2
nix/matar-clang.nix
View File

@@ -19,7 +19,7 @@
packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
devShells.matar-clang = pkgs.callPackage ./shell.nix {
inherit libraries stdenv;
tools = with pkgs; [ clang-tools_16 ];
tools = with pkgs; [ (clang-tools_16.override { enableLibcxx = true; }) ];
};
};
}

41
src/cpu/alu.cc
View File

@@ -3,7 +3,7 @@
namespace matar {
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry) {
uint32_t eval = 0;
switch (shift_type) {
@@ -48,4 +48,43 @@ eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
return eval;
}
uint32_t
sub(uint32_t a, uint32_t b, bool& carry, bool& overflow) {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint32_t result = a - b;
carry = b <= a;
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result;
}
uint32_t
add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint64_t result = a + b + c;
carry = get_bit(result, 32);
overflow = s1 == s2 && s2 != get_bit(result, 31);
return result & 0xFFFFFFFF;
}
uint32_t
sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint64_t result = a - b - !c;
carry = get_bit(result, 32);
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result & 0xFFFFFFFF;
}
}

11
src/cpu/alu.hh
View File

@@ -40,5 +40,14 @@ struct Shift {
};
uint32_t
eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry);
uint32_t
sub(uint32_t a, uint32_t b, bool& carry, bool& overflow);
uint32_t
add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
uint32_t
sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
}

311
src/cpu/arm/exec.cc
View File

@@ -2,23 +2,20 @@
#include "util/bits.hh"
#include "util/log.hh"
namespace matar {
namespace matar::arm {
void
CpuImpl::exec(const arm::Instruction instruction) {
Condition cond = instruction.condition;
arm::InstructionData data = instruction.data;
if (!cpsr.condition(cond)) {
Instruction::exec(CpuImpl& cpu) {
if (!cpu.cpsr.condition(condition)) {
return;
}
auto pc_error = [](uint8_t r) {
if (r == PC_INDEX)
auto pc_error = [cpu](uint8_t r) {
if (r == cpu.PC_INDEX)
glogger.error("Using PC (R15) as operand register");
};
auto pc_warn = [](uint8_t r) {
if (r == PC_INDEX)
auto pc_warn = [cpu](uint8_t r) {
if (r == cpu.PC_INDEX)
glogger.warn("Using PC (R15) as operand register");
};
@@ -26,38 +23,39 @@ CpuImpl::exec(const arm::Instruction instruction) {
std::visit(
overloaded{
[this, pc_warn](BranchAndExchange& data) {
[&cpu, pc_warn](BranchAndExchange& data) {
State state = static_cast<State>(data.rn & 1);
pc_warn(data.rn);
// set state
cpsr.set_state(state);
cpu.cpsr.set_state(state);
// copy to PC
pc = gpr[data.rn];
cpu.pc = cpu.gpr[data.rn];
// ignore [1:0] bits for arm and 0 bit for thumb
rst_bit(pc, 0);
rst_bit(cpu.pc, 0);
if (state == State::Arm)
rst_bit(pc, 1);
rst_bit(cpu.pc, 1);
// pc is affected so flush the pipeline
is_flushed = true;
cpu.is_flushed = true;
},
[this](Branch& data) {
[&cpu](Branch& data) {
if (data.link)
gpr[14] = pc - INSTRUCTION_SIZE;
cpu.gpr[14] = cpu.pc - INSTRUCTION_SIZE;
// data.offset accounts for two instructions ahead when
// disassembling, so need to adjust
pc = static_cast<int32_t>(pc) - 2 * INSTRUCTION_SIZE + data.offset;
cpu.pc =
static_cast<int32_t>(cpu.pc) - 2 * INSTRUCTION_SIZE + data.offset;
// pc is affected so flush the pipeline
is_flushed = true;
cpu.is_flushed = true;
},
[this, pc_error](Multiply& data) {
[&cpu, pc_error](Multiply& data) {
if (data.rd == data.rm)
glogger.error("rd and rm are not distinct in {}",
typeid(data).name());
@@ -66,16 +64,16 @@ CpuImpl::exec(const arm::Instruction instruction) {
pc_error(data.rd);
pc_error(data.rd);
gpr[data.rd] =
gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
cpu.gpr[data.rd] = cpu.gpr[data.rm] * cpu.gpr[data.rs] +
(data.acc ? cpu.gpr[data.rn] : 0);
if (data.set) {
cpsr.set_z(gpr[data.rd] == 0);
cpsr.set_n(get_bit(gpr[data.rd], 31));
cpsr.set_c(0);
cpu.cpsr.set_z(cpu.gpr[data.rd] == 0);
cpu.cpsr.set_n(get_bit(cpu.gpr[data.rd], 31));
cpu.cpsr.set_c(0);
}
},
[this, pc_error](MultiplyLong& data) {
[&cpu, pc_error](MultiplyLong& data) {
if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
data.rdlo == data.rm)
glogger.error("rdhi, rdlo and rm are not distinct in {}",
@@ -91,58 +89,60 @@ CpuImpl::exec(const arm::Instruction instruction) {
return static_cast<uint64_t>(x);
};
uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
(data.acc ? (cast(gpr[data.rdhi]) << 32) |
cast(gpr[data.rdlo])
: 0);
uint64_t eval =
cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
(data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
cast(cpu.gpr[data.rdlo])
: 0);
gpr[data.rdlo] = bit_range(eval, 0, 31);
gpr[data.rdhi] = bit_range(eval, 32, 63);
cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
} else {
auto cast = [](uint32_t x) -> int64_t {
return static_cast<int64_t>(static_cast<int32_t>(x));
};
int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
(data.acc ? (cast(gpr[data.rdhi]) << 32) |
cast(gpr[data.rdlo])
int64_t eval = cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
(data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
cast(cpu.gpr[data.rdlo])
: 0);
gpr[data.rdlo] = bit_range(eval, 0, 31);
gpr[data.rdhi] = bit_range(eval, 32, 63);
cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
}
if (data.set) {
cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
cpsr.set_n(get_bit(gpr[data.rdhi], 31));
cpsr.set_c(0);
cpsr.set_v(0);
cpu.cpsr.set_z(cpu.gpr[data.rdhi] == 0 &&
cpu.gpr[data.rdlo] == 0);
cpu.cpsr.set_n(get_bit(cpu.gpr[data.rdhi], 31));
cpu.cpsr.set_c(0);
cpu.cpsr.set_v(0);
}
},
[](Undefined) { glogger.warn("Undefined instruction"); },
[this, pc_error](SingleDataSwap& data) {
[&cpu, pc_error](SingleDataSwap& data) {
pc_error(data.rm);
pc_error(data.rn);
pc_error(data.rd);
if (data.byte) {
gpr[data.rd] = bus->read_byte(gpr[data.rn]);
bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
cpu.gpr[data.rd] = cpu.bus->read_byte(cpu.gpr[data.rn]);
cpu.bus->write_byte(cpu.gpr[data.rn], cpu.gpr[data.rm] & 0xFF);
} else {
gpr[data.rd] = bus->read_word(gpr[data.rn]);
bus->write_word(gpr[data.rn], gpr[data.rm]);
cpu.gpr[data.rd] = cpu.bus->read_word(cpu.gpr[data.rn]);
cpu.bus->write_word(cpu.gpr[data.rn], cpu.gpr[data.rm]);
}
},
[this, pc_warn, pc_error](SingleDataTransfer& data) {
[&cpu, pc_warn, pc_error](SingleDataTransfer& data) {
uint32_t offset = 0;
uint32_t address = gpr[data.rn];
uint32_t address = cpu.gpr[data.rn];
if (!data.pre && data.write)
glogger.warn("Write-back enabled with post-indexing in {}",
typeid(data).name());
if (data.rn == PC_INDEX && data.write)
if (data.rn == cpu.PC_INDEX && data.write)
glogger.warn("Write-back enabled with base register as PC {}",
typeid(data).name());
@@ -156,22 +156,22 @@ CpuImpl::exec(const arm::Instruction instruction) {
} else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
uint8_t amount =
(shift->data.immediate ? shift->data.operand
: gpr[shift->data.operand] & 0xFF);
: cpu.gpr[shift->data.operand] & 0xFF);
bool carry = cpsr.c();
bool carry = cpu.cpsr.c();
if (!shift->data.immediate)
pc_error(shift->data.operand);
pc_error(shift->rm);
offset =
eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
offset = eval_shift(
shift->data.type, cpu.gpr[shift->rm], amount, carry);
cpsr.set_c(carry);
cpu.cpsr.set_c(carry);
}
// PC is always two instructions ahead
if (data.rn == PC_INDEX)
if (data.rn == cpu.PC_INDEX)
address -= 2 * INSTRUCTION_SIZE;
if (data.pre)
@@ -181,35 +181,35 @@ CpuImpl::exec(const arm::Instruction instruction) {
if (data.load) {
// byte
if (data.byte)
gpr[data.rd] = bus->read_byte(address);
cpu.gpr[data.rd] = cpu.bus->read_byte(address);
// word
else
gpr[data.rd] = bus->read_word(address);
cpu.gpr[data.rd] = cpu.bus->read_word(address);
// store
} else {
// take PC into consideration
if (data.rd == PC_INDEX)
if (data.rd == cpu.PC_INDEX)
address += INSTRUCTION_SIZE;
// byte
if (data.byte)
bus->write_byte(address, gpr[data.rd] & 0xFF);
cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
// word
else
bus->write_word(address, gpr[data.rd]);
cpu.bus->write_word(address, cpu.gpr[data.rd]);
}
if (!data.pre)
address += (data.up ? offset : -offset);
if (!data.pre || data.write)
gpr[data.rn] = address;
cpu.gpr[data.rn] = address;
if (data.rd == PC_INDEX && data.load)
is_flushed = true;
if (data.rd == cpu.PC_INDEX && data.load)
cpu.is_flushed = true;
},
[this, pc_warn, pc_error](HalfwordTransfer& data) {
uint32_t address = gpr[data.rn];
[&cpu, pc_warn, pc_error](HalfwordTransfer& data) {
uint32_t address = cpu.gpr[data.rn];
uint32_t offset = 0;
if (!data.pre && data.write)
@@ -225,13 +225,13 @@ CpuImpl::exec(const arm::Instruction instruction) {
// offset is register number (4 bits) when not an immediate
if (!data.imm) {
pc_error(data.offset);
offset = gpr[data.offset];
offset = cpu.gpr[data.offset];
} else {
offset = data.offset;
}
// PC is always two instructions ahead
if (data.rn == PC_INDEX)
if (data.rn == cpu.PC_INDEX)
address -= 2 * INSTRUCTION_SIZE;
if (data.pre)
@@ -243,62 +243,62 @@ CpuImpl::exec(const arm::Instruction instruction) {
if (data.sign) {
// halfword
if (data.half) {
gpr[data.rd] = bus->read_halfword(address);
cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
// sign extend the halfword
gpr[data.rd] =
(static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
cpu.gpr[data.rd] =
(static_cast<int32_t>(cpu.gpr[data.rd]) << 16) >> 16;
// byte
} else {
gpr[data.rd] = bus->read_byte(address);
cpu.gpr[data.rd] = cpu.bus->read_byte(address);
// sign extend the byte
gpr[data.rd] =
(static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
cpu.gpr[data.rd] =
(static_cast<int32_t>(cpu.gpr[data.rd]) << 24) >> 24;
}
// unsigned halfword
} else if (data.half) {
gpr[data.rd] = bus->read_halfword(address);
cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
}
// store
} else {
// take PC into consideration
if (data.rd == PC_INDEX)
if (data.rd == cpu.PC_INDEX)
address += INSTRUCTION_SIZE;
// halfword
if (data.half)
bus->write_halfword(address, gpr[data.rd]);
cpu.bus->write_halfword(address, cpu.gpr[data.rd]);
}
if (!data.pre)
address += (data.up ? offset : -offset);
if (!data.pre || data.write)
gpr[data.rn] = address;
cpu.gpr[data.rn] = address;
if (data.rd == PC_INDEX && data.load)
is_flushed = true;
if (data.rd == cpu.PC_INDEX && data.load)
cpu.is_flushed = true;
},
[this, pc_error](BlockDataTransfer& data) {
uint32_t address = gpr[data.rn];
Mode mode = cpsr.mode();
[&cpu, pc_error](BlockDataTransfer& data) {
uint32_t address = cpu.gpr[data.rn];
Mode mode = cpu.cpsr.mode();
uint8_t alignment = 4; // word
uint8_t i = 0;
uint8_t n_regs = std::popcount(data.regs);
pc_error(data.rn);
if (cpsr.mode() == Mode::User && data.s) {
if (cpu.cpsr.mode() == Mode::User && data.s) {
glogger.error("Bit S is set outside priviliged modes in {}",
typeid(data).name());
}
// we just change modes to load user registers
if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
if ((!get_bit(data.regs, cpu.PC_INDEX) && data.s) ||
(!data.load && data.s)) {
chg_mode(Mode::User);
cpu.chg_mode(Mode::User);
if (data.write) {
glogger.error(
@@ -307,6 +307,7 @@ CpuImpl::exec(const arm::Instruction instruction) {
}
}
// TODO: clean this shit
// account for decrement
if (!data.up)
address -= (n_regs - 1) * alignment;
@@ -315,22 +316,22 @@ CpuImpl::exec(const arm::Instruction instruction) {
address += (data.up ? alignment : -alignment);
if (data.load) {
if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
// current mode's spsr is already loaded when it was
if (get_bit(data.regs, cpu.PC_INDEX) && data.s && data.load) {
// current mode's cpu.spsr is already loaded when it was
// switched
spsr = cpsr;
cpu.spsr = cpu.cpsr;
}
for (i = 0; i < GPR_COUNT; i++) {
for (i = 0; i < cpu.GPR_COUNT; i++) {
if (get_bit(data.regs, i)) {
gpr[i] = bus->read_word(address);
cpu.gpr[i] = cpu.bus->read_word(address);
address += alignment;
}
}
} else {
for (i = 0; i < GPR_COUNT; i++) {
for (i = 0; i < cpu.GPR_COUNT; i++) {
if (get_bit(data.regs, i)) {
bus->write_word(address, gpr[i]);
cpu.bus->write_word(address, cpu.gpr[i]);
address += alignment;
}
}
@@ -346,37 +347,37 @@ CpuImpl::exec(const arm::Instruction instruction) {
address -= alignment;
if (!data.pre || data.write)
gpr[data.rn] = address;
cpu.gpr[data.rn] = address;
if (data.load && get_bit(data.regs, PC_INDEX))
is_flushed = true;
if (data.load && get_bit(data.regs, cpu.PC_INDEX))
cpu.is_flushed = true;
// load back the original mode registers
chg_mode(mode);
cpu.chg_mode(mode);
},
[this, pc_error](PsrTransfer& data) {
if (data.spsr && cpsr.mode() == Mode::User) {
glogger.error("Accessing SPSR in User mode in {}",
[&cpu, pc_error](PsrTransfer& data) {
if (data.spsr && cpu.cpsr.mode() == Mode::User) {
glogger.error("Accessing CPU.SPSR in User mode in {}",
typeid(data).name());
}
Psr& psr = data.spsr ? spsr : cpsr;
Psr& psr = data.spsr ? cpu.spsr : cpu.cpsr;
switch (data.type) {
case PsrTransfer::Type::Mrs:
pc_error(data.operand);
gpr[data.operand] = psr.raw();
cpu.gpr[data.operand] = psr.raw();
break;
case PsrTransfer::Type::Msr:
pc_error(data.operand);
if (cpsr.mode() != Mode::User) {
psr.set_all(gpr[data.operand]);
if (cpu.cpsr.mode() != Mode::User) {
psr.set_all(cpu.gpr[data.operand]);
}
break;
case PsrTransfer::Type::Msr_flg:
uint32_t operand =
(data.imm ? data.operand : gpr[data.operand]);
(data.imm ? data.operand : cpu.gpr[data.operand]);
psr.set_n(get_bit(operand, 31));
psr.set_z(get_bit(operand, 30));
psr.set_c(get_bit(operand, 29));
@@ -384,10 +385,10 @@ CpuImpl::exec(const arm::Instruction instruction) {
break;
}
},
[this, pc_error](DataProcessing& data) {
[&cpu, pc_error](DataProcessing& data) {
using OpCode = DataProcessing::OpCode;
uint32_t op_1 = gpr[data.rn];
uint32_t op_1 = cpu.gpr[data.rn];
uint32_t op_2 = 0;
uint32_t result = 0;
@@ -398,64 +399,26 @@ CpuImpl::exec(const arm::Instruction instruction) {
} else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
uint8_t amount =
(shift->data.immediate ? shift->data.operand
: gpr[shift->data.operand] & 0xFF);
: cpu.gpr[shift->data.operand] & 0xFF);
bool carry = cpsr.c();
bool carry = cpu.cpsr.c();
if (!shift->data.immediate)
pc_error(shift->data.operand);
pc_error(shift->rm);
op_2 =
eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
op_2 = eval_shift(
shift->data.type, cpu.gpr[shift->rm], amount, carry);
cpsr.set_c(carry);
cpu.cpsr.set_c(carry);
// PC is 12 bytes ahead when shifting
if (data.rn == PC_INDEX)
if (data.rn == cpu.PC_INDEX)
op_1 += INSTRUCTION_SIZE;
}
bool overflow = cpsr.v();
bool carry = cpsr.c();
auto sub = [&carry, &overflow](uint32_t a, uint32_t b) -> uint32_t {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint32_t result = a - b;
carry = b <= a;
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result;
};
auto add = [&carry, &overflow](
uint32_t a, uint32_t b, bool c = 0) -> uint32_t {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
// 33 bits
uint64_t result_ = a + b + c;
uint32_t result = result_ & 0xFFFFFFFF;
carry = get_bit(result_, 32);
overflow = s1 == s2 && s2 != get_bit(result, 31);
return result;
};
auto sbc = [&carry,
&overflow](uint32_t a, uint32_t b, bool c) -> uint32_t {
bool s1 = get_bit(a, 31);
bool s2 = get_bit(b, 31);
uint64_t result_ = a - b + c - 1;
uint32_t result = result_ & 0xFFFFFFFF;
carry = get_bit(result_, 32);
overflow = s1 != s2 && s2 == get_bit(result, 31);
return result;
};
bool overflow = cpu.cpsr.v();
bool carry = cpu.cpsr.c();
switch (data.opcode) {
case OpCode::AND:
@@ -469,23 +432,23 @@ CpuImpl::exec(const arm::Instruction instruction) {
break;
case OpCode::SUB:
case OpCode::CMP:
result = sub(op_1, op_2);
result = sub(op_1, op_2, carry, overflow);
break;
case OpCode::RSB:
result = sub(op_2, op_1);
result = sub(op_2, op_1, carry, overflow);
break;
case OpCode::ADD:
case OpCode::CMN:
result = add(op_1, op_2);
result = add(op_1, op_2, carry, overflow);
break;
case OpCode::ADC:
result = add(op_1, op_2, carry);
result = add(op_1, op_2, carry, overflow, carry);
break;
case OpCode::SBC:
result = sbc(op_1, op_2, carry);
result = sbc(op_1, op_2, carry, overflow, carry);
break;
case OpCode::RSC:
result = sbc(op_2, op_1, carry);
result = sbc(op_2, op_1, carry, overflow, carry);
break;
case OpCode::ORR:
result = op_1 | op_2;
@@ -501,19 +464,19 @@ CpuImpl::exec(const arm::Instruction instruction) {
break;
}
auto set_conditions = [this, carry, overflow, result]() {
cpsr.set_c(carry);
cpsr.set_v(overflow);
cpsr.set_n(get_bit(result, 31));
cpsr.set_z(result == 0);
auto set_conditions = [&cpu, carry, overflow, result]() {
cpu.cpsr.set_c(carry);
cpu.cpsr.set_v(overflow);
cpu.cpsr.set_n(get_bit(result, 31));
cpu.cpsr.set_z(result == 0);
};
if (data.set) {
if (data.rd == PC_INDEX) {
if (cpsr.mode() == Mode::User)
if (data.rd == cpu.PC_INDEX) {
if (cpu.cpsr.mode() == Mode::User)
glogger.error("Running {} in User mode",
typeid(data).name());
spsr = cpsr;
cpu.spsr = cpu.cpsr;
} else {
set_conditions();
}
@@ -523,15 +486,15 @@ CpuImpl::exec(const arm::Instruction instruction) {
data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
set_conditions();
} else {
gpr[data.rd] = result;
if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
is_flushed = true;
cpu.gpr[data.rd] = result;
if (data.rd == cpu.PC_INDEX || data.opcode == OpCode::MVN)
cpu.is_flushed = true;
}
},
[this](SoftwareInterrupt) {
chg_mode(Mode::Supervisor);
pc = 0x08;
spsr = cpsr;
[&cpu](SoftwareInterrupt) {
cpu.chg_mode(Mode::Supervisor);
cpu.pc = 0x08;
cpu.spsr = cpu.cpsr;
},
[](auto& data) {
glogger.error("Unimplemented {} instruction", typeid(data).name());

16
src/cpu/arm/instruction.hh
View File

@@ -5,7 +5,10 @@
#include <fmt/ostream.h>
#include <variant>
namespace matar::arm {
namespace matar {
class CpuImpl;
namespace arm {
// https://en.cppreference.com/w/cpp/utility/variant/visit
template<class... Ts>
@@ -209,16 +212,19 @@ using InstructionData = std::variant<BranchAndExchange,
SoftwareInterrupt>;
struct Instruction {
Condition condition;
InstructionData data;
Instruction(uint32_t insn);
Instruction(Condition condition, InstructionData data) noexcept
Instruction(Condition condition, InstructionData data)
: condition(condition)
, data(data){};
void exec(CpuImpl& cpu);
#ifdef DISASSEMBLER
std::string disassemble();
#endif
Condition condition;
InstructionData data;
};
}
}

33
src/cpu/cpu-impl.cc
View File

@@ -1,4 +1,6 @@
#include "cpu-impl.hh"
#include "cpu/arm/instruction.hh"
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include "util/log.hh"
#include <algorithm>
@@ -11,9 +13,9 @@ CpuImpl::CpuImpl(const Bus& bus) noexcept
, gpr({ 0 })
, cpsr(0)
, spsr(0)
, is_flushed(false)
, gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
, spsr_banked({ 0, 0, 0, 0, 0 }) {
, spsr_banked({ 0, 0, 0, 0, 0 })
, is_flushed(false) {
cpsr.set_mode(Mode::Supervisor);
cpsr.set_irq_disabled(true);
cpsr.set_fiq_disabled(true);
@@ -120,25 +122,38 @@ CpuImpl::step() {
uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
if (cpsr.state() == State::Arm) {
uint32_t x = bus->read_word(cur_pc);
arm::Instruction instruction(x);
exec(instruction);
arm::Instruction instruction(bus->read_word(cur_pc));
#ifdef DISASSEMBLER
glogger.info("{:#034b}", x);
glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
#endif
instruction.exec(*this);
} else {
thumb::Instruction instruction(bus->read_halfword(cur_pc));
#ifdef DISASSEMBLER
glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble(cur_pc));
#endif
instruction.exec(*this);
}
// advance PC
{
size_t size = cpsr.state() == State::Arm ? arm::INSTRUCTION_SIZE
: thumb::INSTRUCTION_SIZE;
if (is_flushed) {
// if flushed, do not increment the PC, instead set it to two
// instructions ahead to account for flushed "fetch" and "decode"
// instructions
pc += 2 * arm::INSTRUCTION_SIZE;
pc += 2 * size;
is_flushed = false;
} else {
// if not flushed continue like normal
pc += arm::INSTRUCTION_SIZE;
pc += size;
}
}
}

22
src/cpu/cpu-impl.hh
View File

@@ -1,8 +1,9 @@
#pragma once
#include "arm/instruction.hh"
#include "bus.hh"
#include "cpu/arm/instruction.hh"
#include "cpu/psr.hh"
#include "thumb/instruction.hh"
#include <cstdint>
@@ -13,12 +14,10 @@ class CpuImpl {
void step();
void chg_mode(const Mode to);
void exec(const arm::Instruction instruction);
// TODO: get rid of this
#ifndef MATAR_CPU_TESTS
private:
#endif
friend void arm::Instruction::exec(CpuImpl& cpu);
friend void thumb::Instruction::exec(CpuImpl& cpu);
static constexpr uint8_t GPR_COUNT = 16;
@@ -35,13 +34,18 @@ class CpuImpl {
Psr cpsr; // current program status register
Psr spsr; // status program status register
static constexpr uint8_t SP_INDEX = 13;
static_assert(SP_INDEX < GPR_COUNT);
uint32_t& sp = gpr[SP_INDEX];
static constexpr uint8_t LR_INDEX = 14;
static_assert(LR_INDEX < GPR_COUNT);
uint32_t& lr = gpr[LR_INDEX];
static constexpr uint8_t PC_INDEX = 15;
static_assert(PC_INDEX < GPR_COUNT);
uint32_t& pc = gpr[PC_INDEX];
bool is_flushed;
struct {
std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
@@ -60,5 +64,7 @@ class CpuImpl {
Psr irq;
Psr und;
} spsr_banked; // banked saved program status registers
bool is_flushed;
};
}

4
src/cpu/psr.cc
View File

@@ -13,7 +13,7 @@ Psr::raw() const {
void
Psr::set_all(uint32_t raw) {
psr = raw & ~PSR_CLEAR_RESERVED;
psr = raw;
}
Mode
@@ -91,7 +91,7 @@ Psr::condition(Condition cond) const {
case Condition::LE:
return z() || (n() != v());
case Condition::AL:
return true && state() == State::Arm;
return true;
}
return false;

2
src/cpu/psr.hh
View File

@@ -61,7 +61,7 @@ stringify(Condition cond) {
CASE(GT)
CASE(LE)
case Condition::AL: {
// empty
return "";
}
}

26
src/cpu/thumb/disassembler.cc
View File

@@ -3,7 +3,7 @@
namespace matar::thumb {
std::string
Instruction::disassemble() {
Instruction::disassemble(uint32_t pc) {
return std::visit(
overloaded{
[](MoveShiftedRegister& data) {
@@ -90,8 +90,7 @@ Instruction::disassemble() {
data.word);
},
[](AddOffsetStackPointer& data) {
return fmt::format(
"ADD SP,#{}{:d}", (data.sign ? '-' : '+'), data.word);
return fmt::format("ADD SP,#{:d}", data.word);
},
[](PushPopRegister& data) {
std::string regs;
@@ -130,19 +129,24 @@ Instruction::disassemble() {
return fmt::format(
"{} R{}!,{{{}}}", (data.load ? "LDMIA" : "STMIA"), data.rb, regs);
},
[](SoftwareInterrupt) { return std::string("SWI"); },
[](ConditionalBranch& data) {
return fmt::format("B{} {:d}",
stringify(data.condition),
data.offset);
[](SoftwareInterrupt& data) {
return fmt::format("SWI {:d}", data.vector);
},
[](UnconditionalBranch& data) {
return fmt::format("B {:d}", data.offset);
[pc](ConditionalBranch& data) {
return fmt::format(
"B{} #{:d}",
stringify(data.condition),
static_cast<int32_t>(data.offset + pc + 2 * INSTRUCTION_SIZE));
},
[pc](UnconditionalBranch& data) {
return fmt::format(
"B #{:d}",
static_cast<int32_t>(data.offset + pc + 2 * INSTRUCTION_SIZE));
},
[](LongBranchWithLink& data) {
// duh this manual be empty for H = 0
return fmt::format(
"BL{} {:d}", (data.high ? "H" : ""), data.offset);
"BL{} #{:d}", (data.high ? "H" : ""), data.offset);
},
[](auto) { return std::string("unknown instruction"); } },
data);

384
src/cpu/thumb/exec.cc Normal file
View File

@@ -0,0 +1,384 @@
#include "cpu/cpu-impl.hh"
#include "instruction.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar::thumb {
void
Instruction::exec(CpuImpl& cpu) {
auto set_cc = [&cpu](bool c, bool v, bool n, bool z) {
cpu.cpsr.set_c(c);
cpu.cpsr.set_v(v);
cpu.cpsr.set_n(n);
cpu.cpsr.set_z(z);
};
std::visit(
overloaded{
[&cpu, set_cc](MoveShiftedRegister& data) {
if (data.opcode == ShiftType::ROR)
glogger.error("Invalid opcode in {}", typeid(data).name());
bool carry = cpu.cpsr.c();
uint32_t shifted =
eval_shift(data.opcode, cpu.gpr[data.rs], data.offset, carry);
cpu.gpr[data.rd] = shifted;
set_cc(carry, cpu.cpsr.v(), get_bit(shifted, 31), shifted == 0);
},
[&cpu, set_cc](AddSubtract& data) {
uint32_t offset =
data.imm ? static_cast<uint32_t>(static_cast<int8_t>(data.offset))
: cpu.gpr[data.offset];
uint32_t result = 0;
bool carry = cpu.cpsr.c();
bool overflow = cpu.cpsr.v();
switch (data.opcode) {
case AddSubtract::OpCode::ADD:
result = add(cpu.gpr[data.rs], offset, carry, overflow);
break;
case AddSubtract::OpCode::SUB:
result = sub(cpu.gpr[data.rs], offset, carry, overflow);
break;
}
cpu.gpr[data.rd] = result;
set_cc(carry, overflow, get_bit(result, 31), result == 0);
},
[&cpu, set_cc](MovCmpAddSubImmediate& data) {
uint32_t result = 0;
bool carry = cpu.cpsr.c();
bool overflow = cpu.cpsr.v();
switch (data.opcode) {
case MovCmpAddSubImmediate::OpCode::MOV:
result = data.offset;
carry = 0;
break;
case MovCmpAddSubImmediate::OpCode::ADD:
result =
add(cpu.gpr[data.rd], data.offset, carry, overflow);
break;
case MovCmpAddSubImmediate::OpCode::SUB:
case MovCmpAddSubImmediate::OpCode::CMP:
result =
sub(cpu.gpr[data.rd], data.offset, carry, overflow);
break;
}
set_cc(carry, overflow, get_bit(result, 31), result == 0);
if (data.opcode != MovCmpAddSubImmediate::OpCode::CMP)
cpu.gpr[data.rd] = result;
},
[&cpu, set_cc](AluOperations& data) {
uint32_t op_1 = cpu.gpr[data.rd];
uint32_t op_2 = cpu.gpr[data.rs];
uint32_t result = 0;
bool carry = cpu.cpsr.c();
bool overflow = cpu.cpsr.v();
switch (data.opcode) {
case AluOperations::OpCode::AND:
case AluOperations::OpCode::TST:
result = op_1 & op_2;
break;
case AluOperations::OpCode::EOR:
result = op_1 ^ op_2;
break;
case AluOperations::OpCode::LSL:
result = eval_shift(ShiftType::LSL, op_1, op_2, carry);
break;
case AluOperations::OpCode::LSR:
result = eval_shift(ShiftType::LSR, op_1, op_2, carry);
break;
case AluOperations::OpCode::ASR:
result = eval_shift(ShiftType::ASR, op_1, op_2, carry);
break;
case AluOperations::OpCode::ADC:
result = add(op_1, op_2, carry, overflow, carry);
break;
case AluOperations::OpCode::SBC:
result = sbc(op_1, op_2, carry, overflow, carry);
break;
case AluOperations::OpCode::ROR:
result = eval_shift(ShiftType::ROR, op_1, op_2, carry);
break;
case AluOperations::OpCode::NEG:
result = -op_2;
break;
case AluOperations::OpCode::CMP:
result = sub(op_1, op_2, carry, overflow);
break;
case AluOperations::OpCode::CMN:
result = add(op_1, op_2, carry, overflow);
break;
case AluOperations::OpCode::ORR:
result = op_1 | op_2;
break;
case AluOperations::OpCode::MUL:
result = op_1 * op_2;
break;
case AluOperations::OpCode::BIC:
result = op_1 & ~op_2;
break;
case AluOperations::OpCode::MVN:
result = ~op_2;
break;
}
if (data.opcode != AluOperations::OpCode::TST &&
data.opcode != AluOperations::OpCode::CMP &&
data.opcode != AluOperations::OpCode::CMN)
cpu.gpr[data.rd] = result;
set_cc(carry, overflow, get_bit(result, 31), result == 0);
},
[&cpu, set_cc](HiRegisterOperations& data) {
uint32_t op_1 = cpu.gpr[data.rd];
uint32_t op_2 = cpu.gpr[data.rs];
bool carry = cpu.cpsr.c();
bool overflow = cpu.cpsr.v();
// PC is already current + 4, so dont need to do that
if (data.rd == cpu.PC_INDEX)
rst_bit(op_1, 0);
if (data.rs == cpu.PC_INDEX)
rst_bit(op_2, 0);
switch (data.opcode) {
case HiRegisterOperations::OpCode::ADD: {
cpu.gpr[data.rd] = add(op_1, op_2, carry, overflow);
if (data.rd == cpu.PC_INDEX)
cpu.is_flushed = true;
} break;
case HiRegisterOperations::OpCode::CMP: {
uint32_t result = sub(op_1, op_2, carry, overflow);
set_cc(carry, overflow, get_bit(result, 31), result == 0);
} break;
case HiRegisterOperations::OpCode::MOV: {
cpu.gpr[data.rd] = op_2;
if (data.rd == cpu.PC_INDEX)
cpu.is_flushed = true;
} break;
case HiRegisterOperations::OpCode::BX: {
State state = static_cast<State>(op_2 & 1);
// set state
cpu.cpsr.set_state(state);
// copy to PC
cpu.pc = op_2;
// ignore [1:0] bits for arm and 0 bit for thumb
rst_bit(cpu.pc, 0);
if (state == State::Arm)
rst_bit(cpu.pc, 1);
// pc is affected so flush the pipeline
cpu.is_flushed = true;
} break;
}
},
[&cpu](PcRelativeLoad& data) {
uint32_t pc = cpu.pc;
rst_bit(pc, 1);
cpu.gpr[data.rd] = cpu.bus->read_word(pc + data.word);
},
[&cpu](LoadStoreRegisterOffset& data) {
uint32_t address = cpu.gpr[data.rb] + cpu.gpr[data.ro];
if (data.load) {
if (data.byte) {
cpu.gpr[data.rd] = cpu.bus->read_byte(address);
} else {
cpu.gpr[data.rd] = cpu.bus->read_word(address);
}
} else {
if (data.byte) {
cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
} else {
cpu.bus->write_word(address, cpu.gpr[data.rd]);
}
}
},
[&cpu](LoadStoreSignExtendedHalfword& data) {
uint32_t address = cpu.gpr[data.rb] + cpu.gpr[data.ro];
switch (data.s << 1 | data.h) {
case 0b00:
cpu.bus->write_halfword(address, cpu.gpr[data.rd] & 0xFFFF);
break;
case 0b01:
cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
break;
case 0b10:
// sign extend and load the byte
cpu.gpr[data.rd] =
(static_cast<int32_t>(cpu.bus->read_byte(address))
<< 24) >>
24;
break;
case 0b11:
// sign extend the halfword
cpu.gpr[data.rd] =
(static_cast<int32_t>(cpu.bus->read_halfword(address))
<< 16) >>
16;
break;
// unreachable
default: {
}
}
},
[&cpu](LoadStoreImmediateOffset& data) {
uint32_t address = cpu.gpr[data.rb] + data.offset;
if (data.load) {
if (data.byte) {
cpu.gpr[data.rd] = cpu.bus->read_byte(address);
} else {
cpu.gpr[data.rd] = cpu.bus->read_word(address);
}
} else {
if (data.byte) {
cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
} else {
cpu.bus->write_word(address, cpu.gpr[data.rd]);
}
}
},
[&cpu](LoadStoreHalfword& data) {
uint32_t address = cpu.gpr[data.rb] + data.offset;
if (data.load) {
cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
} else {
cpu.bus->write_halfword(address, cpu.gpr[data.rd] & 0xFFFF);
}
},
[&cpu](SpRelativeLoad& data) {
uint32_t address = cpu.sp + data.word;
if (data.load) {
cpu.gpr[data.rd] = cpu.bus->read_word(address);
} else {
cpu.bus->write_word(address, cpu.gpr[data.rd]);
}
},
[&cpu](LoadAddress& data) {
if (data.sp) {
cpu.gpr[data.rd] = cpu.sp + data.word;
} else {
// PC is already current + 4, so dont need to do that
// force bit 1 to 0
cpu.gpr[data.rd] = (cpu.pc & ~(1 << 1)) + data.word;
}
},
[&cpu](AddOffsetStackPointer& data) { cpu.sp += data.word; },
[&cpu](PushPopRegister& data) {
if (data.load) {
for (uint8_t i = 0; i < 8; i++) {
if (get_bit(data.regs, i)) {
cpu.gpr[i] = cpu.bus->read_word(cpu.sp);
cpu.sp += 4;
}
}
if (data.pclr) {
cpu.pc = cpu.bus->read_word(cpu.sp);
cpu.sp += 4;
cpu.is_flushed = true;
}
} else {
if (data.pclr) {
cpu.sp -= 4;
cpu.bus->write_word(cpu.sp, cpu.lr);
}
for (int8_t i = 7; i >= 0; i--) {
if (get_bit(data.regs, i)) {
cpu.sp -= 4;
cpu.bus->write_word(cpu.sp, cpu.gpr[i]);
}
}
}
},
[&cpu](MultipleLoad& data) {
uint32_t rb = cpu.gpr[data.rb];
if (data.load) {
for (uint8_t i = 0; i < 8; i++) {
if (get_bit(data.regs, i)) {
cpu.gpr[i] = cpu.bus->read_word(rb);
rb += 4;
}
}
} else {
for (int8_t i = 7; i >= 0; i--) {
if (get_bit(data.regs, i)) {
rb -= 4;
cpu.bus->write_word(rb, cpu.gpr[i]);
}
}
}
cpu.gpr[data.rb] = rb;
},
[&cpu](ConditionalBranch& data) {
if (data.condition == Condition::AL)
glogger.warn("Condition 1110 (AL) is undefined");
if (!cpu.cpsr.condition(data.condition))
return;
cpu.pc += data.offset;
cpu.is_flushed = true;
},
[&cpu](SoftwareInterrupt& data) {
// next instruction is one instruction behind PC
cpu.lr = cpu.pc - INSTRUCTION_SIZE;
cpu.spsr = cpu.cpsr;
cpu.pc = data.vector;
cpu.cpsr.set_state(State::Arm);
cpu.chg_mode(Mode::Supervisor);
cpu.is_flushed = true;
},
[&cpu](UnconditionalBranch& data) {
cpu.pc += data.offset;
cpu.is_flushed = true;
},
[&cpu](LongBranchWithLink& data) {
// 12 bit integer
int32_t offset = data.offset;
if (data.high) {
uint32_t old_pc = cpu.pc;
cpu.pc = cpu.lr + offset;
cpu.lr = (old_pc - INSTRUCTION_SIZE) | 1;
cpu.is_flushed = true;
} else {
// 12 + 11 = 23 bit
offset <<= 11;
// sign extend
offset = (offset << 9) >> 9;
cpu.lr = cpu.pc + offset;
}
},
[](auto& data) {
glogger.error("Unknown thumb format : {}", typeid(data).name());
} },
data);
}
}

78
src/cpu/thumb/instruction.cc
View File

@@ -1,5 +1,6 @@
#include "instruction.hh"
#include "util/bits.hh"
#include "util/log.hh"
namespace matar::thumb {
Instruction::Instruction(uint16_t insn) {
@@ -55,16 +56,20 @@ Instruction::Instruction(uint16_t insn) {
HiRegisterOperations::OpCode opcode =
static_cast<HiRegisterOperations::OpCode>(bit_range(insn, 8, 9));
if (opcode == HiRegisterOperations::OpCode::BX && hi_1)
glogger.warn("H1 set with BX");
rd += (hi_1 ? LO_GPR_COUNT : 0);
rs += (hi_2 ? LO_GPR_COUNT : 0);
data = HiRegisterOperations{ .rd = rd, .rs = rs, .opcode = opcode };
// Format 6: PC-relative load
} else if ((insn & 0xF800) == 0x4800) {
uint8_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
uint16_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
data = PcRelativeLoad{ .word = word, .rd = rd };
data =
PcRelativeLoad{ .word = static_cast<uint16_t>(word << 2), .rd = rd };
// Format 7: Load/store with register offset
} else if ((insn & 0xF200) == 0x5000) {
@@ -91,13 +96,16 @@ Instruction::Instruction(uint16_t insn) {
};
// Format 9: Load/store with immediate offset
} else if ((insn & 0xF000) == 0x6000) {
} else if ((insn & 0xE000) == 0x6000) {
uint8_t rd = bit_range(insn, 0, 2);
uint8_t rb = bit_range(insn, 3, 5);
uint8_t offset = bit_range(insn, 6, 10);
bool load = get_bit(insn, 11);
bool byte = get_bit(insn, 12);
if (!byte)
offset <<= 2;
data = LoadStoreImmediateOffset{
.rd = rd, .rb = rb, .offset = offset, .load = load, .byte = byte
};
@@ -109,40 +117,43 @@ Instruction::Instruction(uint16_t insn) {
uint8_t offset = bit_range(insn, 6, 10);
bool load = get_bit(insn, 11);
offset <<= 1;
data = LoadStoreHalfword{
.rd = rd, .rb = rb, .offset = offset, .load = load
};
// Format 11: SP-relative load/store
} else if ((insn & 0xF000) == 0x9000) {
uint8_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
bool load = get_bit(insn, 11);
uint16_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
bool load = get_bit(insn, 11);
word <<= 2;
data = SpRelativeLoad{ .word = word, .rd = rd, .load = load };
// Format 12: Load address
} else if ((insn & 0xF000) == 0xA000) {
uint8_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
bool sp = get_bit(insn, 11);
uint16_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
bool sp = get_bit(insn, 11);
data = LoadAddress{ .word = word, .rd = rd, .sp = sp };
// Format 12: Load address
} else if ((insn & 0xF000) == 0xA000) {
uint8_t word = bit_range(insn, 0, 7);
uint8_t rd = bit_range(insn, 8, 10);
bool sp = get_bit(insn, 11);
word <<= 2;
data = LoadAddress{ .word = word, .rd = rd, .sp = sp };
// Format 13: Add offset to stack pointer
} else if ((insn & 0xFF00) == 0xB000) {
uint8_t word = bit_range(insn, 0, 6);
int16_t word = static_cast<int16_t>(bit_range(insn, 0, 6));
bool sign = get_bit(insn, 7);
data = AddOffsetStackPointer{ .word = word, .sign = sign };
word <<= 2;
word = static_cast<int16_t>(word * (sign ? -1 : 1));
data = AddOffsetStackPointer{
.word = word,
};
// Format 14: Push/pop registers
} else if ((insn & 0xF600) == 0xB400) {
@@ -162,30 +173,41 @@ Instruction::Instruction(uint16_t insn) {
// Format 17: Software interrupt
} else if ((insn & 0xFF00) == 0xDF00) {
data = SoftwareInterrupt{};
uint8_t vector = bit_range(insn, 0, 7);
data = SoftwareInterrupt{ .vector = vector };
// Format 16: Conditional branch
} else if ((insn & 0xF000) == 0xD000) {
uint16_t offset = bit_range(insn, 0, 7);
int32_t offset = bit_range(insn, 0, 7);
Condition condition = static_cast<Condition>(bit_range(insn, 8, 11));
data = ConditionalBranch{ .offset = static_cast<uint16_t>(offset << 1),
.condition = condition };
offset <<= 1;
// sign extend the 9 bit integer
offset = (offset << 23) >> 23;
data = ConditionalBranch{ .offset = offset, .condition = condition };
// Format 18: Unconditional branch
} else if ((insn & 0xF800) == 0xE000) {
uint16_t offset = bit_range(insn, 0, 10);
int32_t offset = bit_range(insn, 0, 10);
data =
UnconditionalBranch{ .offset = static_cast<uint16_t>(offset << 1) };
offset <<= 1;
// sign extend the 12 bit integer
offset = (offset << 20) >> 20;
data = UnconditionalBranch{ .offset = offset };
// Format 19: Long branch with link
} else if ((insn & 0xF000) == 0xF000) {
uint16_t offset = bit_range(insn, 0, 10);
bool high = get_bit(insn, 11);
data = LongBranchWithLink{ .offset = static_cast<uint16_t>(offset << 1),
.high = high };
offset <<= 1;
data = LongBranchWithLink{ .offset = offset, .high = high };
}
}
}

33
src/cpu/thumb/instruction.hh
View File

@@ -6,7 +6,10 @@
#include <fmt/ostream.h>
#include <variant>
namespace matar::thumb {
namespace matar {
class CpuImpl;
namespace thumb {
// https://en.cppreference.com/w/cpp/utility/variant/visit
template<class... Ts>
@@ -170,7 +173,7 @@ stringify(HiRegisterOperations::OpCode opcode) {
}
struct PcRelativeLoad {
uint8_t word;
uint16_t word;
uint8_t rd;
};
@@ -206,20 +209,19 @@ struct LoadStoreHalfword {
};
struct SpRelativeLoad {
uint8_t word;
uint16_t word;
uint8_t rd;
bool load;
};
struct LoadAddress {
uint8_t word;
uint16_t word;
uint8_t rd;
bool sp;
};
struct AddOffsetStackPointer {
uint8_t word;
bool sign;
int16_t word;
};
struct PushPopRegister {
@@ -235,14 +237,16 @@ struct MultipleLoad {
};
struct ConditionalBranch {
uint16_t offset;
int32_t offset;
Condition condition;
};
struct SoftwareInterrupt {};
struct SoftwareInterrupt {
uint8_t vector;
};
struct UnconditionalBranch {
uint16_t offset;
int32_t offset;
};
struct LongBranchWithLink {
@@ -271,12 +275,17 @@ using InstructionData = std::variant<MoveShiftedRegister,
LongBranchWithLink>;
struct Instruction {
InstructionData data;
Instruction(uint16_t insn);
Instruction(InstructionData data)
: data(data) {}
void exec(CpuImpl& cpu);
#ifdef DISASSEMBLER
std::string disassemble();
std::string disassemble(uint32_t pc = 0);
#endif
InstructionData data;
};
}
}

3
src/cpu/thumb/meson.build
View File

@@ -1,5 +1,6 @@
lib_sources += files(
'instruction.cc'
'instruction.cc',
'exec.cc'
)
if get_option('disassembler')

4
tests/bus.cc
View File

@@ -1,7 +1,7 @@
#include "bus.hh"
#include <catch2/catch_test_macros.hpp>
static constexpr auto TAG = "[bus]";
#define TAG "[bus]"
using namespace matar;
@@ -41,3 +41,5 @@ TEST_CASE_METHOD(BusFixture, "Word", TAG) {
CHECK(bus.read_halfword(100724276) == 0x491D);
CHECK(bus.read_byte(100724276) == 0x1D);
}
#undef TAG

560
tests/cpu/arm/exec.cc
View File

File diff suppressed because it is too large Load Diff

4
tests/cpu/arm/instruction.cc
View File

@@ -1,7 +1,7 @@
#include "cpu/arm/instruction.hh"
#include <catch2/catch_test_macros.hpp>
static constexpr auto TAG = "[arm][disassembly]";
#define TAG "[arm][disassembly]"
using namespace matar;
using namespace arm;
@@ -505,3 +505,5 @@ TEST_CASE("Software Interrupt", TAG) {
CHECK(instruction.disassemble() == "SWIEQ");
#endif
}
#undef TAG

96
tests/cpu/cpu-fixture.cc Normal file
View File

@@ -0,0 +1,96 @@
#include "cpu-fixture.hh"
Psr
CpuFixture::psr(bool spsr) {
Psr psr(0);
CpuImpl tmp = cpu;
arm::Instruction instruction(
Condition::AL,
arm::PsrTransfer{ .operand = 0,
.spsr = spsr,
.type = arm::PsrTransfer::Type::Mrs,
.imm = false });
instruction.exec(tmp);
psr.set_all(getr_(0, tmp));
return psr;
}
void
CpuFixture::set_psr(Psr psr, bool spsr) {
// R0
uint32_t old = getr(0);
setr(0, psr.raw());
arm::Instruction instruction(
Condition::AL,
arm::PsrTransfer{ .operand = 0,
.spsr = spsr,
.type = arm::PsrTransfer::Type::Msr,
.imm = false });
instruction.exec(cpu);
setr(0, old);
}
// We need these workarounds to just use the public API and not private
// fields. Assuming that these work correctly is necessary. Besides, all that
// matters is that the public API is correct.
uint32_t
CpuFixture::getr_(uint8_t r, CpuImpl& cpu) {
size_t addr = 13000;
size_t offset = r == 15 ? 4 : 0;
uint32_t word = bus.read_word(addr + offset);
CpuImpl tmp = cpu;
uint32_t ret = 0xFFFFFFFF;
uint8_t base = r ? 0 : 1;
// set R0/R1 = 0
arm::Instruction zero(
Condition::AL,
arm::DataProcessing{ .operand = 0u,
.rd = base,
.rn = 0,
.set = false,
.opcode = arm::DataProcessing::OpCode::MOV });
// get register
arm::Instruction get(
Condition::AL,
arm::SingleDataTransfer{ .offset = static_cast<uint16_t>(addr),
.rd = r,
.rn = base,
.load = false,
.write = false,
.byte = false,
.up = true,
.pre = true });
zero.exec(tmp);
get.exec(tmp);
addr += offset;
ret = bus.read_word(addr);
bus.write_word(addr, word);
return ret;
}
void
CpuFixture::setr_(uint8_t r, uint32_t value, CpuImpl& cpu) {
// set register
arm::Instruction set(
Condition::AL,
arm::DataProcessing{ .operand = value,
.rd = r,
.rn = 0,
.set = false,
.opcode = arm::DataProcessing::OpCode::MOV });
set.exec(cpu);
}

42
tests/cpu/cpu-fixture.hh Normal file
View File

@@ -0,0 +1,42 @@
#include "cpu/cpu-impl.hh"
using namespace matar;
class CpuFixture {
public:
CpuFixture()
: bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
std::vector<uint8_t>(Header::HEADER_SIZE)))
, cpu(bus) {}
protected:
void exec(arm::InstructionData data, Condition condition = Condition::AL) {
arm::Instruction instruction(condition, data);
instruction.exec(cpu);
}
void exec(thumb::InstructionData data) {
thumb::Instruction instruction(data);
instruction.exec(cpu);
}
void reset(uint32_t value = 0) { setr(15, value + 8); }
uint32_t getr(uint8_t r) { return getr_(r, cpu); }
void setr(uint8_t r, uint32_t value) { setr_(r, value, cpu); }
Psr psr(bool spsr = false);
void set_psr(Psr psr, bool spsr = false);
Bus bus;
CpuImpl cpu;
private:
// hack to get a register
uint32_t getr_(uint8_t r, CpuImpl& cpu);
// hack to set a register
void setr_(uint8_t r, uint32_t value, CpuImpl& cpu);
};

4
tests/cpu/meson.build
View File

@@ -1,2 +1,6 @@
tests_sources += files(
'cpu-fixture.cc'
)
subdir('arm')
subdir('thumb')

990
tests/cpu/thumb/exec.cc Normal file
View File

@@ -0,0 +1,990 @@
#include "cpu/cpu-fixture.hh"
#include "cpu/cpu-impl.hh"
#include "cpu/thumb/instruction.hh"
#include "util/bits.hh"
#include <catch2/catch_test_macros.hpp>
using namespace matar;
#define TAG "[thumb][execution]"
using namespace thumb;
TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
InstructionData data = MoveShiftedRegister{
.rd = 3, .rs = 5, .offset = 15, .opcode = ShiftType::LSL
};
MoveShiftedRegister* move = std::get_if<MoveShiftedRegister>(&data);
SECTION("LSL") {
setr(3, 0);
setr(5, 6687);
// LSL
exec(data);
CHECK(getr(3) == 219119616);
setr(5, 0);
// zero
exec(data);
CHECK(getr(3) == 0);
CHECK(psr().z());
}
SECTION("LSR") {
move->opcode = ShiftType::LSR;
setr(5, -1827489745);
// LSR
exec(data);
CHECK(getr(3) == 75301);
CHECK(!psr().n());
setr(5, 4444);
// zero flag
exec(data);
CHECK(getr(3) == 0);
CHECK(psr().z());
}
SECTION("ASR") {
setr(5, -1827489745);
move->opcode = ShiftType::ASR;
// ASR
exec(data);
CHECK(psr().n());
CHECK(getr(3) == 4294911525);
setr(5, 500);
// zero flag
exec(data);
CHECK(getr(3) == 0);
CHECK(psr().z());
}
}
TEST_CASE_METHOD(CpuFixture, "Add/Subtract", TAG) {
InstructionData data = AddSubtract{ .rd = 5,
.rs = 2,
.offset = 7,
.opcode = AddSubtract::OpCode::ADD,
.imm = false };
AddSubtract* add = std::get_if<AddSubtract>(&data);
setr(2, 378427891);
setr(7, -666666);
SECTION("ADD") {
// register
exec(data);
CHECK(getr(5) == 377761225);
add->imm = true;
setr(2, (1u << 31) - 1);
// immediate and overflow
exec(data);
CHECK(getr(5) == 2147483654);
CHECK(psr().v());
setr(2, -7);
// zero
exec(data);
CHECK(getr(5) == 0);
CHECK(psr().z());
}
add->imm = true;
SECTION("SUB") {
add->opcode = AddSubtract::OpCode::SUB;
setr(2, -((1u << 31) - 1));
add->offset = 4;
exec(data);
CHECK(getr(5) == 2147483645);
CHECK(psr().v());
setr(2, ~0u);
add->offset = -4;
// carry
exec(data);
CHECK(getr(5) == 3);
CHECK(psr().c());
setr(2, 0);
add->offset = 0;
// zero
exec(data);
CHECK(getr(5) == 0);
CHECK(psr().z());
}
}
TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
InstructionData data = MovCmpAddSubImmediate{
.offset = 251, .rd = 5, .opcode = MovCmpAddSubImmediate::OpCode::MOV
};
MovCmpAddSubImmediate* move = std::get_if<MovCmpAddSubImmediate>(&data);
SECTION("MOV") {
exec(data);
CHECK(getr(5) == 251);
move->offset = 0;
// zero
exec(data);
CHECK(getr(5) == 0);
CHECK(psr().z());
}
SECTION("CMP") {
setr(5, 251);
move->opcode = MovCmpAddSubImmediate::OpCode::CMP;
CHECK(!psr().z());
exec(data);
CHECK(getr(5) == 251);
CHECK(psr().z());
// overflow
setr(5, -((1u << 31) - 1));
CHECK(!psr().v());
exec(data);
CHECK(getr(5) == 2147483649);
CHECK(psr().v());
}
SECTION("ADD") {
move->opcode = MovCmpAddSubImmediate::OpCode::ADD;
setr(5, (1u << 31) - 1);
// immediate and overflow
exec(data);
CHECK(getr(5) == 2147483898);
CHECK(psr().v());
setr(5, -251);
// zero
exec(data);
CHECK(getr(5) == 0);
CHECK(psr().z());
}
SECTION("SUB") {
// same as CMP but loaded
setr(5, 251);
move->opcode = MovCmpAddSubImmediate::OpCode::SUB;
CHECK(!psr().z());
exec(data);
CHECK(getr(5) == 0);
CHECK(psr().z());
// overflow
setr(5, -((1u << 31) - 1));
CHECK(!psr().v());
exec(data);
CHECK(getr(5) == 2147483398);
CHECK(psr().v());
}
}
TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
InstructionData data =
AluOperations{ .rd = 1, .rs = 3, .opcode = AluOperations::OpCode::AND };
AluOperations* alu = std::get_if<AluOperations>(&data);
setr(1, 328940001);
setr(3, -991);
SECTION("AND") {
// 328940001 & -991
exec(data);
CHECK(getr(1) == 328939553);
CHECK(!psr().n());
setr(3, 0);
CHECK(!psr().z());
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("EOR") {
alu->opcode = AluOperations::OpCode::EOR;
// 328940001 ^ -991
exec(data);
CHECK(getr(1) == 3966027200);
CHECK(psr().n());
setr(3, 3966027200);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
CHECK(!psr().n());
}
SECTION("LSL") {
setr(3, 3);
alu->opcode = AluOperations::OpCode::LSL;
// 328940001 << 3
exec(data);
CHECK(getr(1) == 2631520008);
CHECK(psr().n());
setr(1, 0);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("LSR") {
alu->opcode = AluOperations::OpCode::LSR;
setr(3, 991);
// 328940001 >> 991
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
setr(1, -83885328);
setr(3, 5);
// -83885328 >> 5
exec(data);
CHECK(getr(1) == 131596311);
CHECK(!psr().z());
CHECK(!psr().n());
}
SECTION("ASR") {
alu->opcode = AluOperations::OpCode::ASR;
setr(3, 991);
// 328940001 >> 991
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
setr(1, -83885328);
setr(3, 5);
// -83885328 >> 5
exec(data);
CHECK(getr(1) == 4292345879);
CHECK(!psr().z());
CHECK(psr().n());
}
SECTION("ADC") {
alu->opcode = AluOperations::OpCode::ADC;
setr(3, (1u << 31) - 1);
Psr cpsr = psr();
cpsr.set_c(true);
set_psr(cpsr);
// 2147483647 + 328940001 + 1
exec(data);
CHECK(getr(1) == 2476423649);
CHECK(psr().v());
CHECK(psr().n());
CHECK(!psr().c());
setr(3, -328940001);
setr(1, 328940001);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("SBC") {
alu->opcode = AluOperations::OpCode::SBC;
setr(3, -((1u << 31) - 1));
Psr cpsr = psr();
cpsr.set_c(false);
set_psr(cpsr);
// 328940001 - -2147483647 - 1
exec(data);
CHECK(getr(1) == 2476423647);
CHECK(psr().v());
CHECK(psr().n());
CHECK(!psr().c());
setr(1, -34892);
setr(3, -34893);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("ROR") {
setr(3, 993);
alu->opcode = AluOperations::OpCode::ROR;
// 328940001 ROR 993
exec(data);
CHECK(getr(1) == 2311953648);
CHECK(psr().n());
CHECK(psr().c());
setr(1, 0);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("TST") {
alu->opcode = AluOperations::OpCode::TST;
// 328940001 & -991
exec(data);
// no change
CHECK(getr(1) == 328940001);
setr(3, 0);
CHECK(!psr().z());
// zero
exec(data);
CHECK(getr(1) == 328940001);
CHECK(psr().z());
}
SECTION("NEG") {
alu->opcode = AluOperations::OpCode::NEG;
// -(-991)
exec(data);
CHECK(getr(1) == 991);
setr(3, 0);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("CMP") {
alu->opcode = AluOperations::OpCode::CMP;
setr(3, -((1u << 31) - 1));
// 328940001 - -2147483647
exec(data);
// no change
CHECK(getr(1) == 328940001);
CHECK(psr().v());
CHECK(psr().n());
CHECK(!psr().c());
setr(1, -34892);
setr(3, -34892);
// zero
exec(data);
// no change (-34892)
CHECK(getr(1) == 4294932404);
CHECK(psr().z());
}
SECTION("CMN") {
alu->opcode = AluOperations::OpCode::CMN;
setr(3, (1u << 31) - 1);
// 2147483647 + 328940001
exec(data);
CHECK(getr(1) == 328940001);
CHECK(psr().v());
CHECK(psr().n());
CHECK(!psr().c());
setr(3, -328940001);
setr(1, 328940001);
// zero
exec(data);
CHECK(getr(1) == 328940001);
CHECK(psr().z());
}
SECTION("ORR") {
alu->opcode = AluOperations::OpCode::ORR;
// 328940001 | -991
exec(data);
CHECK(getr(1) == 4294966753);
CHECK(psr().n());
setr(1, 0);
setr(3, 0);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("MUL") {
alu->opcode = AluOperations::OpCode::MUL;
// 328940001 * -991 (lower 32 bits) (-325979540991 & 0xFFFFFFFF)
exec(data);
CHECK(getr(1) == 437973505);
setr(3, 0);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("BIC") {
alu->opcode = AluOperations::OpCode::BIC;
// 328940001 & ~ -991
exec(data);
CHECK(getr(1) == 448);
CHECK(!psr().n());
setr(3, ~0u);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
SECTION("MVN") {
alu->opcode = AluOperations::OpCode::MVN;
//~ -991
exec(data);
CHECK(getr(1) == 990);
CHECK(!psr().n());
setr(3, 24358);
// negative
exec(data);
CHECK(getr(1) == 4294942937);
CHECK(psr().n());
setr(3, ~0u);
// zero
exec(data);
CHECK(getr(1) == 0);
CHECK(psr().z());
}
}
TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
InstructionData data = HiRegisterOperations{
.rd = 5, .rs = 15, .opcode = HiRegisterOperations::OpCode::ADD
};
HiRegisterOperations* hi = std::get_if<HiRegisterOperations>(&data);
setr(15, 3452948950);
setr(5, 958656720);
SECTION("ADD") {
exec(data);
CHECK(getr(5) == 116638374);
// hi + hi
hi->rd = 14;
hi->rs = 15;
setr(14, 42589);
exec(data);
CHECK(getr(14) == 3452991539);
}
SECTION("CMP") {
hi->opcode = HiRegisterOperations::OpCode::CMP;
exec(data);
// no change
CHECK(getr(5) == 958656720);
CHECK(!psr().n());
CHECK(!psr().c());
CHECK(!psr().v());
CHECK(!psr().z());
setr(15, 958656720);
// zero
exec(data);
// no change
CHECK(getr(5) == 958656720);
CHECK(psr().z());
}
SECTION("MOV") {
hi->opcode = HiRegisterOperations::OpCode::MOV;
exec(data);
CHECK(getr(5) == 3452948950);
}
SECTION("BX") {
hi->opcode = HiRegisterOperations::OpCode::BX;
hi->rs = 10;
SECTION("Arm") {
setr(10, 2189988);
exec(data);
CHECK(getr(15) == 2189988);
// switched to arm
CHECK(psr().state() == State::Arm);
}
SECTION("Thumb") {
setr(10, 2189989);
exec(data);
CHECK(getr(15) == 2189988);
// switched to thumb
CHECK(psr().state() == State::Thumb);
}
}
}
TEST_CASE_METHOD(CpuFixture, "PC Relative Load", TAG) {
InstructionData data = PcRelativeLoad{ .word = 380, .rd = 0 };
setr(15, 13804);
// 13804 + 380
bus.write_word(14184, 489753492);
CHECK(getr(0) == 0);
exec(data);
CHECK(getr(0) == 489753492);
}
TEST_CASE_METHOD(CpuFixture, "Load/Store with Register Offset", TAG) {
InstructionData data = LoadStoreRegisterOffset{
.rd = 3, .rb = 0, .ro = 7, .byte = false, .load = false
};
LoadStoreRegisterOffset* load = std::get_if<LoadStoreRegisterOffset>(&data);
setr(7, 9910);
setr(0, 1034);
setr(3, 389524259);
SECTION("store") {
// 9910 + 1034
CHECK(bus.read_word(10944) == 0);
exec(data);
CHECK(bus.read_word(10944) == 389524259);
// byte
load->byte = true;
bus.write_word(10944, 0);
exec(data);
CHECK(bus.read_word(10944) == 35);
}
SECTION("load") {
load->load = true;
bus.write_word(10944, 11123489);
exec(data);
CHECK(getr(3) == 11123489);
// byte
load->byte = true;
exec(data);
CHECK(getr(3) == 33);
}
}
TEST_CASE_METHOD(CpuFixture, "Load/Store Sign Extended Byte/Halfword", TAG) {
InstructionData data = LoadStoreSignExtendedHalfword{
.rd = 3, .rb = 0, .ro = 7, .s = false, .h = false
};
LoadStoreSignExtendedHalfword* load =
std::get_if<LoadStoreSignExtendedHalfword>(&data);
setr(7, 9910);
setr(0, 1034);
setr(3, 389524259);
SECTION("SH = 00") {
// 9910 + 1034
CHECK(bus.read_word(10944) == 0);
exec(data);
CHECK(bus.read_word(10944) == 43811);
}
SECTION("SH = 01") {
load->h = true;
bus.write_word(10944, 11123489);
exec(data);
CHECK(getr(3) == 47905);
}
SECTION("SH = 10") {
load->s = true;
bus.write_word(10944, 34521594);
exec(data);
// sign extended 250 byte (0xFA)
CHECK(getr(3) == 4294967290);
}
SECTION("SH = 11") {
load->s = true;
load->h = true;
bus.write_word(10944, 11123489);
// sign extended 47905 halfword (0xBB21)
exec(data);
CHECK(getr(3) == 4294949665);
}
}
TEST_CASE_METHOD(CpuFixture, "Load/Store with Immediate Offset", TAG) {
InstructionData data = LoadStoreImmediateOffset{
.rd = 3, .rb = 0, .offset = 110, .load = false, .byte = false
};
LoadStoreImmediateOffset* load =
std::get_if<LoadStoreImmediateOffset>(&data);
setr(0, 1034);
setr(3, 389524259);
SECTION("store") {
// 110 + 1034
CHECK(bus.read_word(1144) == 0);
exec(data);
CHECK(bus.read_word(1144) == 389524259);
// byte
load->byte = true;
bus.write_word(1144, 0);
exec(data);
CHECK(bus.read_word(1144) == 35);
}
SECTION("load") {
load->load = true;
bus.write_word(1144, 11123489);
exec(data);
CHECK(getr(3) == 11123489);
// byte
load->byte = true;
exec(data);
CHECK(getr(3) == 33);
}
}
TEST_CASE_METHOD(CpuFixture, "Load/Store Halfword", TAG) {
InstructionData data =
LoadStoreHalfword{ .rd = 3, .rb = 0, .offset = 110, .load = false };
LoadStoreHalfword* load = std::get_if<LoadStoreHalfword>(&data);
setr(0, 1034);
setr(3, 389524259);
SECTION("store") {
// 110 + 1034
CHECK(bus.read_word(1144) == 0);
exec(data);
CHECK(bus.read_word(1144) == 43811);
}
SECTION("load") {
load->load = true;
bus.write_word(1144, 11123489);
exec(data);
CHECK(getr(3) == 47905);
}
}
TEST_CASE_METHOD(CpuFixture, "SP Relative Load", TAG) {
InstructionData data =
SpRelativeLoad{ .word = 808, .rd = 1, .load = false };
SpRelativeLoad* load = std::get_if<SpRelativeLoad>(&data);
setr(1, 2349505744);
// sp
setr(13, 336);
SECTION("store") {
// 110 + 1034
CHECK(bus.read_word(1144) == 0);
exec(data);
CHECK(bus.read_word(1144) == 2349505744);
}
SECTION("load") {
load->load = true;
bus.write_word(1144, 11123489);
exec(data);
CHECK(getr(1) == 11123489);
}
}
TEST_CASE_METHOD(CpuFixture, "Load Address", TAG) {
InstructionData data = LoadAddress{ .word = 808, .rd = 1, .sp = false };
LoadAddress* load = std::get_if<LoadAddress>(&data);
// pc
setr(15, 336485);
// sp
setr(13, 69879977);
SECTION("PC") {
exec(data);
CHECK(getr(1) == 337293);
}
SECTION("SP") {
load->sp = true;
exec(data);
CHECK(getr(1) == 69880785);
}
}
TEST_CASE_METHOD(CpuFixture, "Add Offset to Stack Pointer", TAG) {
InstructionData data = AddOffsetStackPointer{ .word = 473 };
AddOffsetStackPointer* add = std::get_if<AddOffsetStackPointer>(&data);
// sp
setr(13, 69879977);
SECTION("positive") {
exec(data);
CHECK(getr(13) == 69880450);
}
SECTION("negative") {
add->word = -473;
exec(data);
CHECK(getr(13) == 69879504);
}
}
TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
InstructionData data =
PushPopRegister{ .regs = 0b11010011, .pclr = false, .load = false };
PushPopRegister* push = std::get_if<PushPopRegister>(&data);
// registers = 0, 1, 4, 6, 7
SECTION("push (store)") {
// populate registers
setr(0, 237164);
setr(1, 679785111);
setr(4, 905895898);
setr(6, 131313333);
setr(7, 131);
auto checker = [this]() {
// address
CHECK(bus.read_word(5548) == 237164);
CHECK(bus.read_word(5552) == 679785111);
CHECK(bus.read_word(5556) == 905895898);
CHECK(bus.read_word(5560) == 131313333);
CHECK(bus.read_word(5564) == 131);
};
// set stack pointer to top of stack
setr(13, 5568);
SECTION("without LR") {
exec(data);
checker();
CHECK(getr(13) == 5548);
}
SECTION("with LR") {
push->pclr = true;
// populate lr
setr(14, 999304);
// add another word on stack (5568 + 4)
setr(13, 5572);
exec(data);
CHECK(bus.read_word(5568) == 999304);
checker();
CHECK(getr(13) == 5548);
}
}
SECTION("pop (load)") {
push->load = true;
// populate memory
bus.write_word(5548, 237164);
bus.write_word(5552, 679785111);
bus.write_word(5556, 905895898);
bus.write_word(5560, 131313333);
bus.write_word(5564, 131);
auto checker = [this]() {
CHECK(getr(0) == 237164);
CHECK(getr(1) == 679785111);
CHECK(getr(2) == 0);
CHECK(getr(3) == 0);
CHECK(getr(4) == 905895898);
CHECK(getr(5) == 0);
CHECK(getr(6) == 131313333);
CHECK(getr(7) == 131);
for (uint8_t i = 0; i < 8; i++) {
setr(i, 0);
}
};
// set stack pointer to bottom of stack
setr(13, 5548);
SECTION("without SP") {
exec(data);
checker();
CHECK(getr(13) == 5568);
}
SECTION("with SP") {
push->pclr = true;
// populate next address
bus.write_word(5568, 93333912);
exec(data);
CHECK(getr(15) == 93333912);
checker();
CHECK(getr(13) == 5572);
}
}
}
TEST_CASE_METHOD(CpuFixture, "Multiple Load/Store", TAG) {
InstructionData data =
MultipleLoad{ .regs = 0b11010101, .rb = 2, .load = false };
MultipleLoad* push = std::get_if<MultipleLoad>(&data);
// registers = 0, 1, 4, 6, 7
SECTION("push (store)") {
// populate registers
setr(0, 237164);
setr(4, 905895898);
setr(6, 131313333);
setr(7, 131);
// set R2 (base) to top of stack
setr(2, 5568);
exec(data);
CHECK(bus.read_word(5548) == 237164);
CHECK(bus.read_word(5552) == 5568);
CHECK(bus.read_word(5556) == 905895898);
CHECK(bus.read_word(5560) == 131313333);
CHECK(bus.read_word(5564) == 131);
// write back
CHECK(getr(2) == 5548);
}
SECTION("pop (load)") {
push->load = true;
// populate memory
bus.write_word(5548, 237164);
bus.write_word(5552, 679785111);
bus.write_word(5556, 905895898);
bus.write_word(5560, 131313333);
bus.write_word(5564, 131);
// base
setr(2, 5548);
exec(data);
CHECK(getr(0) == 237164);
CHECK(getr(1) == 0);
CHECK(getr(2) == 5568); // write back
CHECK(getr(3) == 0);
CHECK(getr(4) == 905895898);
CHECK(getr(5) == 0);
CHECK(getr(6) == 131313333);
CHECK(getr(7) == 131);
}
}
TEST_CASE_METHOD(CpuFixture, "Conditional Branch", TAG) {
InstructionData data =
ConditionalBranch{ .offset = -192, .condition = Condition::EQ };
ConditionalBranch* branch = std::get_if<ConditionalBranch>(&data);
setr(15, 4589344);
SECTION("z") {
Psr cpsr = psr();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
cpsr.set_z(true);
set_psr(cpsr);
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
}
SECTION("c") {
branch->condition = Condition::CS;
Psr cpsr = psr();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
cpsr.set_c(true);
set_psr(cpsr);
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
}
SECTION("n") {
branch->condition = Condition::MI;
Psr cpsr = psr();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
cpsr.set_n(true);
set_psr(cpsr);
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
}
SECTION("v") {
branch->condition = Condition::VS;
Psr cpsr = psr();
// condition is false
exec(data);
CHECK(getr(15) == 4589344);
cpsr.set_v(true);
set_psr(cpsr);
// condition is true
exec(data);
CHECK(getr(15) == 4589152);
}
}
TEST_CASE_METHOD(CpuFixture, "Software Interrupt", TAG) {
InstructionData data = SoftwareInterrupt{ .vector = 33 };
setr(15, 4492);
exec(data);
CHECK(psr().raw() == psr(true).raw());
CHECK(getr(14) == 4490);
CHECK(getr(15) == 33);
CHECK(psr().state() == State::Arm);
CHECK(psr().mode() == Mode::Supervisor);
}
TEST_CASE_METHOD(CpuFixture, "Unconditional Branch", TAG) {
InstructionData data = UnconditionalBranch{ .offset = -920 };
setr(15, 4589344);
exec(data);
CHECK(getr(15) == 4588424);
}
TEST_CASE_METHOD(CpuFixture, "Long Branch With Link", TAG) {
InstructionData data = LongBranchWithLink{ .offset = 3262, .high = false };
LongBranchWithLink* branch = std::get_if<LongBranchWithLink>(&data);
// high
setr(15, 4589344);
exec(data);
CHECK(getr(14) == 2881312);
// low
branch->high = true;
exec(data);
CHECK(getr(14) == 4589343);
CHECK(getr(15) == 2884574);
}

92
tests/cpu/thumb/instruction.cc
View File

@@ -1,7 +1,7 @@
#include "cpu/thumb/instruction.hh"
#include <catch2/catch_test_macros.hpp>
static constexpr auto TAG = "[thumb][disassembly]";
#define TAG "[thumb][disassembly]"
using namespace matar;
using namespace thumb;
@@ -178,11 +178,12 @@ TEST_CASE("PC Relative Load", TAG) {
PcRelativeLoad* ldr = nullptr;
REQUIRE((ldr = std::get_if<PcRelativeLoad>(&instruction.data)));
CHECK(ldr->word == 230);
// 230 << 2
CHECK(ldr->word == 920);
CHECK(ldr->rd == 2);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "LDR R2,[PC,#230]");
CHECK(instruction.disassemble() == "LDR R2,[PC,#920]");
#endif
}
@@ -247,21 +248,32 @@ TEST_CASE("Load/Store with Immediate Offset", TAG) {
REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
CHECK(ldr->rd == 5);
CHECK(ldr->rb == 3);
CHECK(ldr->offset == 22);
// 22 << 4 when byte == false
CHECK(ldr->offset == 88);
CHECK(ldr->byte == false);
CHECK(ldr->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STR R5,[R3,#22]");
CHECK(instruction.disassemble() == "STR R5,[R3,#88]");
ldr->byte = true;
ldr->load = true;
CHECK(instruction.disassemble() == "LDR R5,[R3,#88]");
#endif
// byte
raw = 0b0111010110011101;
instruction = Instruction(raw);
INFO(instruction.data.index());
REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
CHECK(ldr->byte == true);
CHECK(ldr->offset == 22);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STRB R5,[R3,#22]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDRB R5,[R3,#22]");
ldr->byte = false;
CHECK(instruction.disassemble() == "LDR R5,[R3,#22]");
#endif
}
@@ -273,14 +285,15 @@ TEST_CASE("Load/Store Halfword", TAG) {
REQUIRE((ldr = std::get_if<LoadStoreHalfword>(&instruction.data)));
CHECK(ldr->rd == 5);
CHECK(ldr->rb == 3);
CHECK(ldr->offset == 26);
// 26 << 1
CHECK(ldr->offset == 52);
CHECK(ldr->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STRH R5,[R3,#26]");
CHECK(instruction.disassemble() == "STRH R5,[R3,#52]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDRH R5,[R3,#26]");
CHECK(instruction.disassemble() == "LDRH R5,[R3,#52]");
#endif
}
@@ -291,14 +304,15 @@ TEST_CASE("SP-Relative Load/Store", TAG) {
REQUIRE((ldr = std::get_if<SpRelativeLoad>(&instruction.data)));
CHECK(ldr->rd == 4);
CHECK(ldr->word == 157);
// 157 << 2
CHECK(ldr->word == 628);
CHECK(ldr->load == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "STR R4,[SP,#157]");
CHECK(instruction.disassemble() == "STR R4,[SP,#628]");
ldr->load = true;
CHECK(instruction.disassemble() == "LDR R4,[SP,#157]");
CHECK(instruction.disassemble() == "LDR R4,[SP,#628]");
#endif
}
@@ -308,15 +322,16 @@ TEST_CASE("Load Adress", TAG) {
LoadAddress* add = nullptr;
REQUIRE((add = std::get_if<LoadAddress>(&instruction.data)));
CHECK(add->word == 143);
// 143 << 2
CHECK(add->word == 572);
CHECK(add->rd == 1);
CHECK(add->sp == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ADD R1,PC,#143");
CHECK(instruction.disassemble() == "ADD R1,PC,#572");
add->sp = true;
CHECK(instruction.disassemble() == "ADD R1,SP,#143");
CHECK(instruction.disassemble() == "ADD R1,SP,#572");
#endif
}
@@ -326,14 +341,21 @@ TEST_CASE("Add Offset to Stack Pointer", TAG) {
AddOffsetStackPointer* add = nullptr;
REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
CHECK(add->word == 37);
CHECK(add->sign == false);
// 37 << 2
CHECK(add->word == 148);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ADD SP,#+37");
CHECK(instruction.disassemble() == "ADD SP,#148");
#endif
add->sign = true;
CHECK(instruction.disassemble() == "ADD SP,#-37");
raw = 0b1011000010100101;
instruction = Instruction(raw);
REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
CHECK(add->word == -148);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "ADD SP,#-148");
#endif
}
@@ -380,17 +402,18 @@ TEST_CASE("Multiple Load/Store", TAG) {
}
TEST_CASE("Conditional Branch", TAG) {
uint16_t raw = 0b1101100101110100;
uint16_t raw = 0b1101100110110100;
Instruction instruction(raw);
ConditionalBranch* b = nullptr;
REQUIRE((b = std::get_if<ConditionalBranch>(&instruction.data)));
// 116 << 2
CHECK(b->offset == 232);
// (-76 << 1)
CHECK(b->offset == -152);
CHECK(b->condition == Condition::LS);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "BLS 232");
// (-76 << 1) + PC (0) + 4
CHECK(instruction.disassemble() == "BLS #-148");
#endif
}
@@ -402,7 +425,7 @@ TEST_CASE("SoftwareInterrupt") {
REQUIRE((swi = std::get_if<SoftwareInterrupt>(&instruction.data)));
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "SWI");
CHECK(instruction.disassemble() == "SWI 51");
#endif
}
@@ -412,11 +435,12 @@ TEST_CASE("Unconditional Branch") {
UnconditionalBranch* b = nullptr;
REQUIRE((b = std::get_if<UnconditionalBranch>(&instruction.data)));
// 1843 << 2
REQUIRE(b->offset == 3686);
// (2147483443 << 1)
REQUIRE(b->offset == -410);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "B 3686");
// (2147483443 << 1) + PC(0) + 4
CHECK(instruction.disassemble() == "B #-406");
#endif
}
@@ -431,9 +455,11 @@ TEST_CASE("Long Branch with link") {
CHECK(bl->high == false);
#ifdef DISASSEMBLER
CHECK(instruction.disassemble() == "BL 2520");
CHECK(instruction.disassemble() == "BL #2520");
bl->high = true;
CHECK(instruction.disassemble() == "BLH 2520");
CHECK(instruction.disassemble() == "BLH #2520");
#endif
}
#undef TAG

3
tests/cpu/thumb/meson.build
View File

@@ -1,3 +1,4 @@
tests_sources += files(
'instruction.cc'
'instruction.cc',
'exec.cc'
)

4
tests/memory.cc
View File

@@ -1,7 +1,7 @@
#include "memory.hh"
#include <catch2/catch_test_macros.hpp>
static constexpr auto TAG = "[memory]";
#define TAG "[memory]"
using namespace matar;
@@ -119,3 +119,5 @@ TEST_CASE("rom", TAG) {
CHECK(memory.read(0xCEF0256) == 0x10);
}
}
#undef TAG

4
tests/util/bits.cc
View File

@@ -1,7 +1,7 @@
#include "util/bits.hh"
#include <catch2/catch_test_macros.hpp>
static constexpr auto TAG = "[util][bits]";
#define TAG "[util][bits]"
TEST_CASE("8 bits", TAG) {
uint8_t num = 45;
@@ -104,3 +104,5 @@ TEST_CASE("64 bits", TAG) {
// 0b011010001
CHECK(bit_range(num, 39, 47) == 209);
}
#undef TAG

4
tests/util/crypto.cc
View File

@@ -1,7 +1,7 @@
#include "util/crypto.hh"
#include <catch2/catch_test_macros.hpp>
static constexpr auto TAG = "[util][crypto]";
#define TAG "[util][crypto]"
TEST_CASE("sha256 matar", TAG) {
std::array<uint8_t, 5> data = { 'm', 'a', 't', 'a', 'r' };
@@ -19,3 +19,5 @@ TEST_CASE("sha256 forgis", TAG) {
CHECK(crypto::sha256(data) ==
"cfddca2ce2673f355518cbe2df2a8522693c54723a469e8b36a4f68b90d2b759");
}
#undef TAG