cpu/arm: fix MSR by changing modes

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

.gitignore

@@ -3,5 +3,5 @@ result
 build/
 .cache/
 *~
-#*#
+\#*\#
 .#*

README.md

@@ -5,18 +5,21 @@ But if you are curious (probably not), read ahead
 # Dependencies
 ## Tested toolchains
 
-- LLVM 16.0.6
+- LLVM 18.1.7
-- GCC 12.3.0
+- GCC 14.1.0
 
-In theory, any toolchain supporting at least the C++20 standard should work.
+In theory, any toolchain supporting at least the c++23 standard should work.
 I am using LLVM's clang and libcxx as the primary toolchain.
 
 ## Static libraries
 
-| Name   | Version   | Required? |
+| Name   | Version | Required? | Purpose   |
-|:------:|:----------|:---------:|
+|:------:|:--------|:---------:|:---------:|
-| fmt    | >= 10.1.1 | yes       |
+| catch2 | >= 3.4  | no        | for tests |
-| catch2 | >= 3.4    | for tests |
 
 This goes without saying but using a different toolchain to compile these libraries before linking probably won't work.
-I will add meson wrap support once LLVM 17 is out, since I want to get rid of fmt.
+
+-----
+
+# LOG
+- June 11, 2024: After almost an year, I have come back to this silly abandoned project, will probably complete it soon.

apps/target/main.cc

@@ -7,8 +7,7 @@
 #include <fstream>
 #include <iostream>
 #include <memory>
-#include <ostream>
+#include <thread>
-#include <unistd.h>
 #include <vector>
 
 // NOLINTBEGIN
@@ -93,7 +92,7 @@ main(int argc, const char* argv[]) {
         matar::Cpu cpu(bus);
         while (true) {
             cpu.step();
-            sleep(2);
+            std::this_thread::sleep_for(std::chrono::seconds(1));
         }
     } catch (const std::exception& e) {
         std::cerr << "Exception: " << e.what() << std::endl;

flake.lock

@@ -5,11 +5,11 @@
         "nixpkgs-lib": "nixpkgs-lib"
       },
       "locked": {
-        "lastModified": 1693611461,
+        "lastModified": 1717285511,
-        "narHash": "sha256-aPODl8vAgGQ0ZYFIRisxYG5MOGSkIczvu2Cd8Gb9+1Y=",
+        "narHash": "sha256-iKzJcpdXih14qYVcZ9QC9XuZYnPc6T8YImb6dX166kw=",
         "owner": "hercules-ci",
         "repo": "flake-parts",
-        "rev": "7f53fdb7bdc5bb237da7fefef12d099e4fd611ca",
+        "rev": "2a55567fcf15b1b1c7ed712a2c6fadaec7412ea8",
         "type": "github"
       },
       "original": {
@@ -20,11 +20,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1695318763,
+        "lastModified": 1717868076,
-        "narHash": "sha256-FHVPDRP2AfvsxAdc+AsgFJevMz5VBmnZglFUMlxBkcY=",
+        "narHash": "sha256-c83Y9t815Wa34khrux81j8K8ET94ESmCuwORSKm2bQY=",
         "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "e12483116b3b51a185a33a272bf351e357ba9a99",
+        "rev": "cd18e2ae9ab8e2a0a8d715b60c91b54c0ac35ff9",
         "type": "github"
       },
       "original": {
@@ -36,20 +36,14 @@
     },
     "nixpkgs-lib": {
       "locked": {
-        "dir": "lib",
+        "lastModified": 1717284937,
-        "lastModified": 1693471703,
+        "narHash": "sha256-lIbdfCsf8LMFloheeE6N31+BMIeixqyQWbSr2vk79EQ=",
-        "narHash": "sha256-0l03ZBL8P1P6z8MaSDS/MvuU8E75rVxe5eE1N6gxeTo=",
+        "type": "tarball",
-        "owner": "NixOS",
+        "url": "https://github.com/NixOS/nixpkgs/archive/eb9ceca17df2ea50a250b6b27f7bf6ab0186f198.tar.gz"
-        "repo": "nixpkgs",
-        "rev": "3e52e76b70d5508f3cec70b882a29199f4d1ee85",
-        "type": "github"
       },
       "original": {
-        "dir": "lib",
+        "type": "tarball",
-        "owner": "NixOS",
+        "url": "https://github.com/NixOS/nixpkgs/archive/eb9ceca17df2ea50a250b6b27f7bf6ab0186f198.tar.gz"
-        "ref": "nixos-unstable",
-        "repo": "nixpkgs",
-        "type": "github"
       }
     },
     "root": {

flake.nix

@@ -26,7 +26,7 @@
             ".hh"
             ".cc"
             ".build"
-            "meson_options.txt"
+            ".options"
           ];
         in
         rec {

include/bus.hh

@@ -1,6 +1,7 @@
 #pragma once
 
 #include "memory.hh"
+#include "io/io.hh"
 #include <memory>
 
 namespace matar {
@@ -8,16 +9,17 @@ class Bus {
   public:
     Bus(const Memory& memory);
 
-    uint8_t read_byte(size_t address);
+    uint8_t read_byte(uint32_t address);
-    void write_byte(size_t address, uint8_t byte);
+    void write_byte(uint32_t address, uint8_t byte);
 
-    uint16_t read_halfword(size_t address);
+    uint16_t read_halfword(uint32_t address);
-    void write_halfword(size_t address, uint16_t halfword);
+    void write_halfword(uint32_t address, uint16_t halfword);
 
-    uint32_t read_word(size_t address);
+    uint32_t read_word(uint32_t address);
-    void write_word(size_t address, uint32_t word);
+    void write_word(uint32_t address, uint32_t word);
 
   private:
+    IoDevices io;
     std::shared_ptr<Memory> memory;
 };
 }

include/cpu/alu.hh

@@ -0,0 +1,52 @@
+#pragma once
+#include <cstdint>
+
+namespace matar {
+enum class ShiftType {
+    LSL = 0b00,
+    LSR = 0b01,
+    ASR = 0b10,
+    ROR = 0b11
+};
+
+constexpr auto
+stringify(ShiftType shift_type) {
+#define CASE(type)                                                             \
+    case ShiftType::type:                                                      \
+        return #type;
+
+    switch (shift_type) {
+        CASE(LSL)
+        CASE(LSR)
+        CASE(ASR)
+        CASE(ROR)
+    }
+
+#undef CASE
+
+    return "";
+}
+
+struct ShiftData {
+    ShiftType type;
+    bool immediate;
+    uint8_t operand;
+};
+
+struct Shift {
+    uint8_t rm;
+    ShiftData data;
+};
+
+uint32_t
+eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry);
+
+uint32_t
+sub(uint32_t a, uint32_t b, bool& carry, bool& overflow);
+
+uint32_t
+add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
+
+uint32_t
+sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
+}

include/cpu/arm/instruction.hh

@@ -2,12 +2,15 @@
 #include "cpu/alu.hh"
 #include "cpu/psr.hh"
 #include <cstdint>
-#include <fmt/ostream.h>
+#include <string>
 #include <variant>
 
 namespace matar {
+class Cpu;
+
 namespace arm {
 
+// https://en.cppreference.com/w/cpp/utility/variant/visit
 template<class... Ts>
 struct overloaded : Ts... {
     using Ts::operator()...;
@@ -23,7 +26,7 @@ struct BranchAndExchange {
 
 struct Branch {
     bool link;
-    uint32_t offset;
+    int32_t offset;
 };
 
 struct Multiply {
@@ -113,6 +116,37 @@ struct DataProcessing {
     OpCode opcode;
 };
 
+constexpr auto
+stringify(DataProcessing::OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case DataProcessing::OpCode::opcode:                                       \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(SUB)
+        CASE(RSB)
+        CASE(ADD)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(RSC)
+        CASE(TST)
+        CASE(TEQ)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MOV)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+
+    return "";
+}
+
 struct PsrTransfer {
     enum class Type {
         Mrs,
@@ -178,23 +212,19 @@ using InstructionData = std::variant<BranchAndExchange,
                                      SoftwareInterrupt>;
 
 struct Instruction {
+    Instruction(uint32_t insn);
+    Instruction(Condition condition, InstructionData data)
+      : condition(condition)
+      , data(data) {};
+
+    void exec(Cpu& cpu);
+
+#ifdef DISASSEMBLER
+    std::string disassemble();
+#endif
+
     Condition condition;
     InstructionData data;
-
-    Instruction(uint32_t insn);
-    Instruction(Condition condition, InstructionData data) noexcept
-      : condition(condition)
-      , data(data){};
-
-    std::string disassemble();
 };
-
-std::ostream&
-operator<<(std::ostream& os, const DataProcessing::OpCode cond);
 }
 }
-
-namespace fmt {
-template<>
-struct formatter<matar::arm::DataProcessing::OpCode> : ostream_formatter {};
-}

include/cpu/arm/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh'
+)

include/cpu/cpu.hh

@@ -1,21 +1,70 @@
+#pragma once
+
+#include "arm/instruction.hh"
 #include "bus.hh"
+#include "cpu/psr.hh"
+#include "thumb/instruction.hh"
+
+#include <cstdint>
 
 namespace matar {
-class CpuImpl;
-
 class Cpu {
   public:
     Cpu(const Bus& bus) noexcept;
-    Cpu(const Cpu&)            = delete;
-    Cpu(Cpu&&)                 = delete;
-    Cpu& operator=(const Cpu&) = delete;
-    Cpu& operator=(Cpu&&)      = delete;
-
-    ~Cpu();
 
     void step();
+    void chg_mode(const Mode to);
 
   private:
-    std::unique_ptr<CpuImpl> impl;
+    friend void arm::Instruction::exec(Cpu& cpu);
+    friend void thumb::Instruction::exec(Cpu& cpu);
+
+    static constexpr uint8_t GPR_COUNT = 16;
+
+    static constexpr uint8_t GPR_FIQ_FIRST = 8;
+    static constexpr uint8_t GPR_SVC_FIRST = 13;
+    static constexpr uint8_t GPR_ABT_FIRST = 13;
+    static constexpr uint8_t GPR_IRQ_FIRST = 13;
+    static constexpr uint8_t GPR_UND_FIRST = 13;
+    static constexpr uint8_t GPR_OLD_FIRST = 8;
+
+    std::shared_ptr<Bus> bus;
+    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+
+    Psr cpsr; // current program status register
+    Psr spsr; // status program status register
+
+    static constexpr uint8_t SP_INDEX = 13;
+    static_assert(SP_INDEX < GPR_COUNT);
+    uint32_t& sp = gpr[SP_INDEX];
+
+    static constexpr uint8_t LR_INDEX = 14;
+    static_assert(LR_INDEX < GPR_COUNT);
+    uint32_t& lr = gpr[LR_INDEX];
+
+    static constexpr uint8_t PC_INDEX = 15;
+    static_assert(PC_INDEX < GPR_COUNT);
+    uint32_t& pc = gpr[PC_INDEX];
+
+    struct {
+        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
+        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
+        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
+        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
+        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
+
+        // visible registers before the mode switch
+        std::array<uint32_t, GPR_COUNT - GPR_OLD_FIRST - 1> old;
+    } gpr_banked; // banked general purpose registers
+
+    struct {
+        Psr fiq;
+        Psr svc;
+        Psr abt;
+        Psr irq;
+        Psr und;
+    } spsr_banked; // banked saved program status registers
+
+    bool is_flushed;
 };
 }

include/cpu/meson.build

@@ -1,3 +1,8 @@
 headers += files(
+  'alu.hh',
   'cpu.hh',
+  'psr.hh'
 )
+
+subdir('arm')
+subdir('thumb')

include/cpu/psr.hh

@@ -1,7 +1,6 @@
 #pragma once
 
 #include <cstdint>
-#include <fmt/ostream.h>
 
 namespace matar {
 enum class Mode {
@@ -38,6 +37,38 @@ enum class Condition {
     AL = 0b1110
 };
 
+constexpr auto
+stringify(Condition cond) {
+
+#define CASE(cond)                                                             \
+    case Condition::cond:                                                      \
+        return #cond;
+
+    switch (cond) {
+        CASE(EQ)
+        CASE(NE)
+        CASE(CS)
+        CASE(CC)
+        CASE(MI)
+        CASE(PL)
+        CASE(VS)
+        CASE(VC)
+        CASE(HI)
+        CASE(LS)
+        CASE(GE)
+        CASE(LT)
+        CASE(GT)
+        CASE(LE)
+        case Condition::AL: {
+            return "";
+        }
+    }
+
+#undef CASE
+
+    return "";
+}
+
 class Psr {
   public:
     // clear the reserved bits i.e, [8:27]
@@ -84,17 +115,7 @@ class Psr {
 
   private:
     static constexpr uint32_t PSR_CLEAR_RESERVED = 0xF00000FF;
-    static constexpr uint32_t PSR_CLEAR_MODE     = 0xFFFFFFE0;
 
     uint32_t psr;
 };
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const Condition cond);
-}
-
-namespace fmt {
-template<>
-struct formatter<matar::Condition> : ostream_formatter {};
 }

include/cpu/thumb/instruction.hh

@@ -0,0 +1,291 @@
+#pragma once
+
+#include "cpu/alu.hh"
+#include "cpu/psr.hh"
+#include <cstdint>
+#include <string>
+#include <variant>
+
+namespace matar {
+class Cpu;
+
+namespace thumb {
+
+// https://en.cppreference.com/w/cpp/utility/variant/visit
+template<class... Ts>
+struct overloaded : Ts... {
+    using Ts::operator()...;
+};
+template<class... Ts>
+overloaded(Ts...) -> overloaded<Ts...>;
+
+static constexpr size_t INSTRUCTION_SIZE = 2;
+static constexpr uint8_t LO_GPR_COUNT    = 8;
+
+struct MoveShiftedRegister {
+    uint8_t rd;
+    uint8_t rs;
+    uint8_t offset;
+    ShiftType opcode;
+};
+
+struct AddSubtract {
+    enum class OpCode {
+        ADD = 0,
+        SUB = 1
+    };
+
+    uint8_t rd;
+    uint8_t rs;
+    uint8_t offset;
+    OpCode opcode;
+    bool imm;
+};
+
+constexpr auto
+stringify(AddSubtract::OpCode opcode) {
+#define CASE(opcode)                                                           \
+    case AddSubtract::OpCode::opcode:                                          \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(ADD)
+        CASE(SUB)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct MovCmpAddSubImmediate {
+    enum class OpCode {
+        MOV = 0b00,
+        CMP = 0b01,
+        ADD = 0b10,
+        SUB = 0b11
+    };
+
+    uint8_t offset;
+    uint8_t rd;
+    OpCode opcode;
+};
+
+constexpr auto
+stringify(MovCmpAddSubImmediate::OpCode opcode) {
+#define CASE(opcode)                                                           \
+    case MovCmpAddSubImmediate::OpCode::opcode:                                \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(MOV)
+        CASE(CMP)
+        CASE(ADD)
+        CASE(SUB)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct AluOperations {
+    enum class OpCode {
+        AND = 0b0000,
+        EOR = 0b0001,
+        LSL = 0b0010,
+        LSR = 0b0011,
+        ASR = 0b0100,
+        ADC = 0b0101,
+        SBC = 0b0110,
+        ROR = 0b0111,
+        TST = 0b1000,
+        NEG = 0b1001,
+        CMP = 0b1010,
+        CMN = 0b1011,
+        ORR = 0b1100,
+        MUL = 0b1101,
+        BIC = 0b1110,
+        MVN = 0b1111
+    };
+
+    uint8_t rd;
+    uint8_t rs;
+    OpCode opcode;
+};
+
+constexpr auto
+stringify(AluOperations::OpCode opcode) {
+
+#define CASE(opcode)                                                           \
+    case AluOperations::OpCode::opcode:                                        \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(AND)
+        CASE(EOR)
+        CASE(LSL)
+        CASE(LSR)
+        CASE(ASR)
+        CASE(ADC)
+        CASE(SBC)
+        CASE(ROR)
+        CASE(TST)
+        CASE(NEG)
+        CASE(CMP)
+        CASE(CMN)
+        CASE(ORR)
+        CASE(MUL)
+        CASE(BIC)
+        CASE(MVN)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct HiRegisterOperations {
+    enum class OpCode {
+        ADD = 0b00,
+        CMP = 0b01,
+        MOV = 0b10,
+        BX  = 0b11
+    };
+
+    uint8_t rd;
+    uint8_t rs;
+    OpCode opcode;
+};
+
+constexpr auto
+stringify(HiRegisterOperations::OpCode opcode) {
+#define CASE(opcode)                                                           \
+    case HiRegisterOperations::OpCode::opcode:                                 \
+        return #opcode;
+
+    switch (opcode) {
+        CASE(ADD)
+        CASE(CMP)
+        CASE(MOV)
+        CASE(BX)
+    }
+
+#undef CASE
+    return "";
+}
+
+struct PcRelativeLoad {
+    uint16_t word;
+    uint8_t rd;
+};
+
+struct LoadStoreRegisterOffset {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t ro;
+    bool byte;
+    bool load;
+};
+
+struct LoadStoreSignExtendedHalfword {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t ro;
+    bool s;
+    bool h;
+};
+
+struct LoadStoreImmediateOffset {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t offset;
+    bool load;
+    bool byte;
+};
+
+struct LoadStoreHalfword {
+    uint8_t rd;
+    uint8_t rb;
+    uint8_t offset;
+    bool load;
+};
+
+struct SpRelativeLoad {
+    uint16_t word;
+    uint8_t rd;
+    bool load;
+};
+
+struct LoadAddress {
+    uint16_t word;
+    uint8_t rd;
+    bool sp;
+};
+
+struct AddOffsetStackPointer {
+    int16_t word;
+};
+
+struct PushPopRegister {
+    uint8_t regs;
+    bool pclr;
+    bool load;
+};
+
+struct MultipleLoad {
+    uint8_t regs;
+    uint8_t rb;
+    bool load;
+};
+
+struct ConditionalBranch {
+    int32_t offset;
+    Condition condition;
+};
+
+struct SoftwareInterrupt {
+    uint8_t vector;
+};
+
+struct UnconditionalBranch {
+    int32_t offset;
+};
+
+struct LongBranchWithLink {
+    uint16_t offset;
+    bool high;
+};
+
+using InstructionData = std::variant<MoveShiftedRegister,
+                                     AddSubtract,
+                                     MovCmpAddSubImmediate,
+                                     AluOperations,
+                                     HiRegisterOperations,
+                                     PcRelativeLoad,
+                                     LoadStoreRegisterOffset,
+                                     LoadStoreSignExtendedHalfword,
+                                     LoadStoreImmediateOffset,
+                                     LoadStoreHalfword,
+                                     SpRelativeLoad,
+                                     LoadAddress,
+                                     AddOffsetStackPointer,
+                                     PushPopRegister,
+                                     MultipleLoad,
+                                     ConditionalBranch,
+                                     SoftwareInterrupt,
+                                     UnconditionalBranch,
+                                     LongBranchWithLink>;
+
+struct Instruction {
+    Instruction(uint16_t insn);
+    Instruction(InstructionData data)
+      : data(data) {}
+
+    void exec(Cpu& cpu);
+
+#ifdef DISASSEMBLER
+    std::string disassemble();
+#endif
+
+    InstructionData data;
+};
+}
+}

include/cpu/thumb/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'instruction.hh'
+)

include/io/io.hh

@@ -0,0 +1,32 @@
+#pragma once
+#include "lcd.hh"
+#include "sound.hh"
+#include <cstdint>
+
+namespace matar {
+class IoDevices {
+  public:
+    uint8_t read_byte(uint32_t) const;
+    void write_byte(uint32_t, uint8_t);
+
+    uint32_t read_word(uint32_t) const;
+    void write_word(uint32_t, uint32_t);
+
+    uint16_t read_halfword(uint32_t) const;
+    void write_halfword(uint32_t, uint16_t);
+
+  private:
+    struct {
+        using u16 = uint16_t;
+        bool post_boot_flag;
+        bool interrupt_master_enabler;
+        u16 interrupt_enable;
+        u16 interrupt_request_flags;
+        u16 waitstate_control;
+        bool low_power_mode;
+    } system = {};
+
+    struct lcd lcd     = {};
+    struct sound sound = {};
+};
+}

include/io/lcd.hh

@@ -0,0 +1,84 @@
+#include <cstdint>
+
+// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
+
+/*
+  4000000h  2    R/W  DISPCNT   LCD Control
+  4000002h  2    R/W  -         Undocumented - Green Swap
+  4000004h  2    R/W  DISPSTAT  General LCD Status (STAT,LYC)
+  4000006h  2    R    VCOUNT    Vertical Counter (LY)
+  4000008h  2    R/W  BG0CNT    BG0 Control
+  400000Ah  2    R/W  BG1CNT    BG1 Control
+  400000Ch  2    R/W  BG2CNT    BG2 Control
+  400000Eh  2    R/W  BG3CNT    BG3 Control
+  4000010h  2    W    BG0HOFS   BG0 X-Offset
+  4000012h  2    W    BG0VOFS   BG0 Y-Offset
+  4000014h  2    W    BG1HOFS   BG1 X-Offset
+  4000016h  2    W    BG1VOFS   BG1 Y-Offset
+  4000018h  2    W    BG2HOFS   BG2 X-Offset
+  400001Ah  2    W    BG2VOFS   BG2 Y-Offset
+  400001Ch  2    W    BG3HOFS   BG3 X-Offset
+  400001Eh  2    W    BG3VOFS   BG3 Y-Offset
+  4000020h  2    W    BG2PA     BG2 Rotation/Scaling Parameter A (dx)
+  4000022h  2    W    BG2PB     BG2 Rotation/Scaling Parameter B (dmx)
+  4000024h  2    W    BG2PC     BG2 Rotation/Scaling Parameter C (dy)
+  4000026h  2    W    BG2PD     BG2 Rotation/Scaling Parameter D (dmy)
+  4000028h  4    W    BG2X      BG2 Reference Point X-Coordinate
+  400002Ch  4    W    BG2Y      BG2 Reference Point Y-Coordinate
+  4000030h  2    W    BG3PA     BG3 Rotation/Scaling Parameter A (dx)
+  4000032h  2    W    BG3PB     BG3 Rotation/Scaling Parameter B (dmx)
+  4000034h  2    W    BG3PC     BG3 Rotation/Scaling Parameter C (dy)
+  4000036h  2    W    BG3PD     BG3 Rotation/Scaling Parameter D (dmy)
+  4000038h  4    W    BG3X      BG3 Reference Point X-Coordinate
+  400003Ch  4    W    BG3Y      BG3 Reference Point Y-Coordinate
+  4000040h  2    W    WIN0H     Window 0 Horizontal Dimensions
+  4000042h  2    W    WIN1H     Window 1 Horizontal Dimensions
+  4000044h  2    W    WIN0V     Window 0 Vertical Dimensions
+  4000046h  2    W    WIN1V     Window 1 Vertical Dimensions
+  4000048h  2    R/W  WININ     Inside of Window 0 and 1
+  400004Ah  2    R/W  WINOUT    Inside of OBJ Window & Outside of Windows
+  400004Ch  2    W    MOSAIC    Mosaic Size
+  400004Eh       -    -         Not used
+  4000050h  2    R/W  BLDCNT    Color Special Effects Selection
+  4000052h  2    R/W  BLDALPHA  Alpha Blending Coefficients
+  4000054h  2    W    BLDY      Brightness (Fade-In/Out) Coefficient
+  4000056h       -    -         Not used
+*/
+
+struct lcd {
+    using u16 = uint16_t;
+
+    u16 lcd_control;
+    u16 general_lcd_status;
+    u16 vertical_counter;
+    u16 bg0_control;
+    u16 bg1_control;
+    u16 bg2_control;
+    u16 bg3_control;
+    u16 bg0_x_offset;
+    u16 bg0_y_offset;
+    u16 bg1_x_offset;
+    u16 bg1_y_offset;
+    u16 bg2_x_offset;
+    u16 bg2_y_offset;
+    u16 bg3_x_offset;
+    u16 bg3_y_offset;
+    u16 bg2_rot_scaling_parameters[4];
+    u16 bg2_reference_x[2];
+    u16 bg2_reference_y[2];
+    u16 bg3_rot_scaling_parameters[4];
+    u16 bg3_reference_x[2];
+    u16 bg3_reference_y[2];
+    u16 win0_horizontal_dimensions;
+    u16 win1_horizontal_dimensions;
+    u16 win0_vertical_dimensions;
+    u16 win1_vertical_dimensions;
+    u16 inside_win_0_1;
+    u16 outside_win;
+    u16 mosaic_size;
+    u16 color_special_effects_selection;
+    u16 alpha_blending_coefficients;
+    u16 brightness_coefficient;
+};
+
+// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

include/io/meson.build

@@ -0,0 +1,3 @@
+headers += files(
+  'io.hh'
+)

include/io/sound.hh

@@ -0,0 +1,66 @@
+#include <cstdint>
+
+// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
+
+/*
+  4000060h  2  R/W  SOUND1CNT_L Channel 1 Sweep register       (NR10)
+  4000062h  2  R/W  SOUND1CNT_H Channel 1 Duty/Length/Envelope (NR11, NR12)
+  4000064h  2  R/W  SOUND1CNT_X Channel 1 Frequency/Control    (NR13, NR14)
+  4000066h     -    -           Not used
+  4000068h  2  R/W  SOUND2CNT_L Channel 2 Duty/Length/Envelope (NR21, NR22)
+  400006Ah     -    -           Not used
+  400006Ch  2  R/W  SOUND2CNT_H Channel 2 Frequency/Control    (NR23, NR24)
+  400006Eh     -    -           Not used
+  4000070h  2  R/W  SOUND3CNT_L Channel 3 Stop/Wave RAM select (NR30)
+  4000072h  2  R/W  SOUND3CNT_H Channel 3 Length/Volume        (NR31, NR32)
+  4000074h  2  R/W  SOUND3CNT_X Channel 3 Frequency/Control    (NR33, NR34)
+  4000076h     -    -           Not used
+  4000078h  2  R/W  SOUND4CNT_L Channel 4 Length/Envelope      (NR41, NR42)
+  400007Ah     -    -           Not used
+  400007Ch  2  R/W  SOUND4CNT_H Channel 4 Frequency/Control    (NR43, NR44)
+  400007Eh     -    -           Not used
+  4000080h  2  R/W  SOUNDCNT_L  Control Stereo/Volume/Enable   (NR50, NR51)
+  4000082h  2  R/W  SOUNDCNT_H  Control Mixing/DMA Control
+  4000084h  2  R/W  SOUNDCNT_X  Control Sound on/off           (NR52)
+  4000086h     -    -           Not used
+  4000088h  2  BIOS SOUNDBIAS   Sound PWM Control
+  400008Ah  ..   -    -         Not used
+  4000090h 2x10h R/W  WAVE_RAM  Channel 3 Wave Pattern RAM (2 banks!!)
+  40000A0h  4    W    FIFO_A    Channel A FIFO, Data 0-3
+  40000A4h  4    W    FIFO_B    Channel B FIFO, Data 0-3
+*/
+
+struct sound{
+    using u16 = uint16_t;
+
+    // channel 1
+    u16 ch1_sweep;
+    u16 ch1_duty_length_env;
+    u16 ch1_freq_control;
+
+    // channel 2
+    u16 ch2_duty_length_env;
+    u16 ch2_freq_control;
+
+    // channel 3
+    u16 ch3_stop_wave_ram_select;
+    u16 ch3_length_volume;
+    u16 ch3_freq_control;
+    u16 ch3_wave_pattern[8];
+
+    // channel 4
+    u16 ch4_length_env;
+    u16 ch4_freq_control;
+
+    // control
+    u16 ctrl_stereo_volume;
+    u16 ctrl_mixing;
+    u16 ctrl_sound_on_off;
+    u16 pwm_control;
+
+    // fifo
+    u16 fifo_a[2];
+    u16 fifo_b[2];
+};
+
+// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

include/memory.hh

@@ -10,25 +10,23 @@
 namespace matar {
 class Memory {
   public:
-    static constexpr size_t BIOS_SIZE = 1024 * 16;
+    static constexpr uint32_t BIOS_SIZE = 1024 * 16;
 
     Memory(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
 
-    uint8_t read(size_t address) const;
+    uint8_t read(uint32_t address) const;
-    void write(size_t address, uint8_t byte);
+    void write(uint32_t address, uint8_t byte);
 
   private:
-#define MEMORY_REGION(name, start, end)                                        \
+#define MEMORY_REGION(name, start)                                             \
-    static constexpr size_t name##_START = start;                              \
+    static constexpr uint32_t name##_START = start;
-    static constexpr size_t name##_END   = end;
 
 #define DECL_MEMORY(name, ident, start, end)                                   \
-    MEMORY_REGION(name, start, end)                                            \
+    MEMORY_REGION(name, start)                                                 \
-    std::array<uint8_t, name##_END - name##_START + 1> ident;
+    std::array<uint8_t, end - start + 1> ident;
 
-    MEMORY_REGION(BIOS, 0x00000000, 0x00003FFF)
+    MEMORY_REGION(BIOS, 0x00000000)
     std::array<uint8_t, BIOS_SIZE> bios;
-    static_assert(BIOS_END - BIOS_START + 1 == BIOS_SIZE);
 
     // board working RAM
     DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
@@ -47,13 +45,12 @@ class Memory {
 
 #undef DECL_MEMORY
 
-    MEMORY_REGION(ROM_0, 0x08000000, 0x09FFFFFF)
+    MEMORY_REGION(ROM_0, 0x08000000)
-    MEMORY_REGION(ROM_1, 0x0A000000, 0x0BFFFFFF)
+    MEMORY_REGION(ROM_1, 0x0A000000)
-    MEMORY_REGION(ROM_2, 0x0C000000, 0x0DFFFFFF)
+    MEMORY_REGION(ROM_2, 0x0C000000)
 
 #undef MEMORY_REGION
-
+    std::unordered_map<uint32_t, uint8_t> invalid_mem;
-    std::unordered_map<size_t, uint8_t> invalid_mem;
     std::vector<uint8_t> rom;
     Header header;
     void parse_header();

include/meson.build

@@ -8,5 +8,6 @@ inc = include_directories('.')
 
 subdir('cpu')
 subdir('util')
+subdir('io')
 
 install_headers(headers, subdir: meson.project_name(), preserve_path: true)

meson.build

@@ -4,33 +4,11 @@ project('matar', 'cpp',
   default_options : ['warning_level=3',
                      'werror=true',
                      'optimization=3',
-                     'cpp_std=c++20',
+                     'cpp_std=c++23',
                      'default_library=static'])
 
 compiler = meson.get_compiler('cpp')
 
-'''
-TODO: use <print> and <format> instead of libfmt once LLVM 17 is out
-
-if compiler.has_argument('-std=c++2c')
-  add_global_arguments('-std=c++2c', language: 'cpp')
-elif compiler.has_argument('-std=c++23')
-  add_global_arguments('-std=c++23', language: 'cpp')
-elif compiler.has_argument('-std=c++2b')
-  add_global_arguments('-std=c++2b', language: 'cpp')
-elif compiler.has_argument('-std=c++20')
-  add_global_arguments('-std=c++20', language: 'cpp')
-else
-  error(compiler.get_id() + ' ' + compiler.version() + 'does not meet the compiler requirements')
-endif
-
-if compiler.has_argument('-fexperimental-library')
-  add_global_arguments('-fexperimental-library', language: 'cpp')
-else
-  error(compiler.get_id() + ' ' + compiler.version() + 'does not support -fexperimental-library')
-endif
-'''
-
 subdir('include')
 subdir('src')
 subdir('apps')

meson.options

@@ -0,0 +1,2 @@
+option('tests', type : 'boolean', value : true, description: 'enable tests')
+option('disassembler', type: 'boolean', value: true, description: 'enable disassembler')

meson_options.txt

@@ -1 +0,0 @@
-option('tests', type : 'boolean', value : true, description: 'enable tests')

nix/matar-clang.nix

@@ -1,17 +1,10 @@
 { ... }: {
   perSystem = { pkgs, src, ... }:
     let
-      llvm = pkgs.llvmPackages_16;
+      llvm = pkgs.llvmPackages_18;
       stdenv = llvm.libcxxStdenv;
 
       libraries = with pkgs; [
-        ((pkgs.fmt.override {
-          inherit stdenv;
-          enableShared = false;
-        }).overrideAttrs (oa: {
-          cmakeFlags = oa.cmakeFlags ++ [ "-DFMT_TEST=off" ];
-        })).dev
-
         (catch2_3.override { inherit stdenv; }).out
       ];
     in
@@ -19,7 +12,7 @@
       packages.matar-clang = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
       devShells.matar-clang = pkgs.callPackage ./shell.nix {
         inherit libraries stdenv;
-        tools = with pkgs; [ clang-tools_16 ];
+        tools = with pkgs; [ (clang-tools_18.override { enableLibcxx = true; }) ];
       };
     };
 }

nix/matar.nix

@@ -1,13 +1,14 @@
 { ... }: {
   perSystem = { pkgs, src, ... }:
     let
+      stdenv = pkgs.gcc14Stdenv;
+
       libraries = with pkgs; [
-        (pkgs.fmt.override { enableShared = false; }).dev
+        (catch2_3.override { inherit stdenv; }).out
-        catch2_3.out
       ];
     in
     {
-      packages.matar = pkgs.callPackage ./build.nix { inherit src libraries; };
+      packages.matar = pkgs.callPackage ./build.nix { inherit src libraries stdenv; };
-      devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries; };
+      devShells.matar = pkgs.callPackage ./shell.nix { inherit libraries stdenv; };
     };
 }

src/bus.cc

@@ -3,53 +3,81 @@
 #include <memory>
 
 namespace matar {
+
+static constexpr uint32_t IO_START = 0x4000000;
+static constexpr uint32_t IO_END   = 0x40003FE;
+
 Bus::Bus(const Memory& memory)
   : memory(std::make_shared<Memory>(memory)) {}
 
 uint8_t
-Bus::read_byte(size_t address) {
+Bus::read_byte(uint32_t address) {
+    if (address >= IO_START && address <= IO_END)
+        return io.read_byte(address);
+
     return memory->read(address);
 }
 
 void
-Bus::write_byte(size_t address, uint8_t byte) {
+Bus::write_byte(uint32_t address, uint8_t byte) {
+    if (address >= IO_START && address <= IO_END) {
+        io.write_byte(address, byte);
+        return;
+    }
+
     memory->write(address, byte);
 }
 
 uint16_t
-Bus::read_halfword(size_t address) {
+Bus::read_halfword(uint32_t address) {
     if (address & 0b01)
         glogger.warn("Reading a non aligned halfword address");
 
-    return memory->read(address) | memory->read(address + 1) << 8;
+    if (address >= IO_START && address <= IO_END)
+        return io.read_halfword(address);
+
+    return read_byte(address) | read_byte(address + 1) << 8;
 }
 
 void
-Bus::write_halfword(size_t address, uint16_t halfword) {
+Bus::write_halfword(uint32_t address, uint16_t halfword) {
     if (address & 0b01)
         glogger.warn("Writing to a non aligned halfword address");
 
-    memory->write(address, halfword & 0xFF);
+    if (address >= IO_START && address <= IO_END) {
-    memory->write(address + 1, halfword >> 8 & 0xFF);
+        io.write_halfword(address, halfword);
+        return;
+    }
+
+    write_byte(address, halfword & 0xFF);
+    write_byte(address + 1, halfword >> 8 & 0xFF);
 }
 
 uint32_t
-Bus::read_word(size_t address) {
+Bus::read_word(uint32_t address) {
     if (address & 0b11)
         glogger.warn("Reading a non aligned word address");
 
-    return memory->read(address) | memory->read(address + 1) << 8 |
+    if (address >= IO_START && address <= IO_END)
-           memory->read(address + 2) << 16 | memory->read(address + 3) << 24;
+        return io.read_word(address);
+
+    return read_byte(address) | read_byte(address + 1) << 8 |
+           read_byte(address + 2) << 16 | read_byte(address + 3) << 24;
 }
 
 void
-Bus::write_word(size_t address, uint32_t word) {
+Bus::write_word(uint32_t address, uint32_t word) {
     if (address & 0b11)
         glogger.warn("Writing to a non aligned word address");
 
-    memory->write(address, word & 0xFF);
+    if (address >= IO_START && address <= IO_END) {
-    memory->write(address + 1, word >> 8 & 0xFF);
+        io.write_word(address, word);
-    memory->write(address + 2, word >> 16 & 0xFF);
+        return;
-    memory->write(address + 3, word >> 24 & 0xFF);
+    }
+
+    write_byte(address, word & 0xFF);
+    write_byte(address + 1, word >> 8 & 0xFF);
+    write_byte(address + 2, word >> 16 & 0xFF);
+    write_byte(address + 3, word >> 24 & 0xFF);
 }
 }

src/cpu/alu.cc

@@ -1,9 +1,10 @@
-#include "alu.hh"
+#include "cpu/alu.hh"
 #include "util/bits.hh"
+#include <bit>
 
 namespace matar {
 uint32_t
-eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
+eval_shift(ShiftType shift_type, uint32_t value, uint32_t amount, bool& carry) {
     uint32_t eval = 0;
 
     switch (shift_type) {
@@ -49,23 +50,42 @@ eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry) {
     return eval;
 }
 
-std::ostream&
+uint32_t
-operator<<(std::ostream& os, const ShiftType shift_type) {
+sub(uint32_t a, uint32_t b, bool& carry, bool& overflow) {
+    bool s1 = get_bit(a, 31);
+    bool s2 = get_bit(b, 31);
 
-#define CASE(type)                                                             \
+    uint32_t result = a - b;
-    case ShiftType::type:                                                      \
-        os << #type;                                                           \
-        break;
 
-    switch (shift_type) {
+    carry    = a >= b;
-        CASE(LSL)
+    overflow = s1 != s2 && s2 == get_bit(result, 31);
-        CASE(LSR)
-        CASE(ASR)
-        CASE(ROR)
-    }
 
-#undef CASE
+    return result;
+}
 
-    return os;
+uint32_t
+add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
+    bool s1 = get_bit(a, 31);
+    bool s2 = get_bit(b, 31);
+
+    uint64_t result = a + b + c;
+
+    carry    = get_bit(result, 32);
+    overflow = s1 == s2 && s2 != get_bit(result, 31);
+
+    return result & 0xFFFFFFFF;
+}
+
+uint32_t
+sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
+    bool s1 = get_bit(a, 31);
+    bool s2 = get_bit(b, 31);
+
+    uint64_t result = a - b - !c;
+
+    carry    = get_bit(result, 32);
+    overflow = s1 != s2 && s2 == get_bit(result, 31);
+
+    return result & 0xFFFFFFFF;
 }
 }

src/cpu/alu.hh

@@ -1,35 +0,0 @@
-#pragma once
-#include <cstdint>
-#include <fmt/ostream.h>
-
-namespace matar {
-enum class ShiftType {
-    LSL = 0b00,
-    LSR = 0b01,
-    ASR = 0b10,
-    ROR = 0b11
-};
-
-struct ShiftData {
-    ShiftType type;
-    bool immediate;
-    uint8_t operand;
-};
-
-struct Shift {
-    uint8_t rm;
-    ShiftData data;
-};
-
-uint32_t
-eval_shift(ShiftType shift_type, uint32_t value, uint8_t amount, bool& carry);
-
-// https://fmt.dev/dev/api.html#std-ostream-support
-std::ostream&
-operator<<(std::ostream& os, const ShiftType cond);
-}
-
-namespace fmt {
-template<>
-struct formatter<matar::ShiftType> : ostream_formatter {};
-}

src/cpu/arm/disassembler.cc

@@ -0,0 +1,237 @@
+#include "cpu/arm/instruction.hh"
+#include "util/bits.hh"
+#include <format>
+
+namespace matar::arm {
+std::string
+Instruction::disassemble() {
+    auto condition = stringify(this->condition);
+
+    return std::visit(
+      overloaded{
+        [condition](BranchAndExchange& data) {
+            return std::format("BX{} R{:d}", condition, data.rn);
+        },
+        [condition](Branch& data) {
+            return std::format(
+              "B{}{} {:#06x}",
+              (data.link ? "L" : ""),
+              condition,
+              static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
+        },
+        [condition](Multiply& data) {
+            if (data.acc) {
+                return std::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
+                                   condition,
+                                   (data.set ? "S" : ""),
+                                   data.rd,
+                                   data.rm,
+                                   data.rs,
+                                   data.rn);
+            } else {
+                return std::format("MUL{}{} R{:d},R{:d},R{:d}",
+                                   condition,
+                                   (data.set ? "S" : ""),
+                                   data.rd,
+                                   data.rm,
+                                   data.rs);
+            }
+        },
+        [condition](MultiplyLong& data) {
+            return std::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
+                               (data.uns ? 'U' : 'S'),
+                               (data.acc ? "MLAL" : "MULL"),
+                               condition,
+                               (data.set ? "S" : ""),
+                               data.rdlo,
+                               data.rdhi,
+                               data.rm,
+                               data.rs);
+        },
+        [](Undefined) { return std::string("UND"); },
+        [condition](SingleDataSwap& data) {
+            return std::format("SWP{}{} R{:d},R{:d},[R{:d}]",
+                               condition,
+                               (data.byte ? "B" : ""),
+                               data.rd,
+                               data.rm,
+                               data.rn);
+        },
+        [condition](SingleDataTransfer& data) {
+            std::string expression;
+            std::string address;
+
+            if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
+                if (*offset == 0) {
+                    expression = "";
+                } else {
+                    expression =
+                      std::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
+                }
+            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
+                // Shifts are always immediate in single data transfer
+                expression = std::format(",{}R{:d},{} #{:d}",
+                                         (data.up ? '+' : '-'),
+                                         shift->rm,
+                                         stringify(shift->data.type),
+                                         shift->data.operand);
+            }
+
+            return std::format(
+              "{}{}{}{} R{:d},[R{:d}{}]{}",
+              (data.load ? "LDR" : "STR"),
+              condition,
+              (data.byte ? "B" : ""),
+              (!data.pre && data.write ? "T" : ""),
+              data.rd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [condition](HalfwordTransfer& data) {
+            std::string expression;
+
+            if (data.imm) {
+                if (data.offset == 0) {
+                    expression = "";
+                } else {
+                    expression = std::format(
+                      ",{}#{:d}", (data.up ? '+' : '-'), data.offset);
+                }
+            } else {
+                expression =
+                  std::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
+            }
+
+            return std::format(
+              "{}{}{}{} R{:d},[R{:d}{}]{}",
+              (data.load ? "LDR" : "STR"),
+              condition,
+              (data.sign ? "S" : ""),
+              (data.half ? 'H' : 'B'),
+              data.rd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [condition](BlockDataTransfer& data) {
+            std::string regs;
+
+            for (uint8_t i = 0; i < 16; i++) {
+                if (get_bit(data.regs, i))
+                    std::format_to(std::back_inserter(regs), "R{:d},", i);
+            };
+
+            regs.pop_back();
+
+            return std::format("{}{}{}{} R{:d}{},{{{}}}{}",
+                               (data.load ? "LDM" : "STM"),
+                               condition,
+                               (data.up ? 'I' : 'D'),
+                               (data.pre ? 'B' : 'A'),
+                               data.rn,
+                               (data.write ? "!" : ""),
+                               regs,
+                               (data.s ? "^" : ""));
+        },
+        [condition](PsrTransfer& data) {
+            if (data.type == PsrTransfer::Type::Mrs) {
+                return std::format("MRS{} R{:d},{}",
+                                   condition,
+                                   data.operand,
+                                   (data.spsr ? "SPSR_all" : "CPSR_all"));
+            } else {
+                return std::format(
+                  "MSR{} {}_{},{}{}",
+                  condition,
+                  (data.spsr ? "SPSR" : "CPSR"),
+                  (data.type == PsrTransfer::Type::Msr_flg ? "flg" : "all"),
+                  (data.imm ? '#' : 'R'),
+                  data.operand);
+            }
+        },
+        [condition](DataProcessing& data) {
+            using OpCode = DataProcessing::OpCode;
+
+            std::string op_2;
+
+            if (const uint32_t* operand =
+                  std::get_if<uint32_t>(&data.operand)) {
+                op_2 = std::format("#{:d}", *operand);
+            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
+                op_2 = std::format("R{:d},{} {}{:d}",
+                                   shift->rm,
+                                   stringify(shift->data.type),
+                                   (shift->data.immediate ? '#' : 'R'),
+                                   shift->data.operand);
+            }
+
+            switch (data.opcode) {
+                case OpCode::MOV:
+                case OpCode::MVN:
+                    return std::format("{}{}{} R{:d},{}",
+                                       stringify(data.opcode),
+                                       condition,
+                                       (data.set ? "S" : ""),
+                                       data.rd,
+                                       op_2);
+                case OpCode::TST:
+                case OpCode::TEQ:
+                case OpCode::CMP:
+                case OpCode::CMN:
+                    return std::format("{}{} R{:d},{}",
+                                       stringify(data.opcode),
+                                       condition,
+                                       data.rn,
+                                       op_2);
+                default:
+                    return std::format("{}{}{} R{:d},R{:d},{}",
+                                       stringify(data.opcode),
+                                       condition,
+                                       (data.set ? "S" : ""),
+                                       data.rd,
+                                       data.rn,
+                                       op_2);
+            }
+        },
+        [condition](SoftwareInterrupt) {
+            return std::format("SWI{}", condition);
+        },
+        [condition](CoprocessorDataTransfer& data) {
+            std::string expression = std::format(",#{:d}", data.offset);
+            return std::format(
+              "{}{}{} p{:d},c{:d},[R{:d}{}]{}",
+              (data.load ? "LDC" : "STC"),
+              condition,
+              (data.len ? "L" : ""),
+              data.cpn,
+              data.crd,
+              data.rn,
+              (data.pre ? expression : ""),
+              (data.pre ? (data.write ? "!" : "") : expression));
+        },
+        [condition](CoprocessorDataOperation& data) {
+            return std::format("CDP{} p{},{},c{},c{},c{},{}",
+                               condition,
+                               data.cpn,
+                               data.cp_opc,
+                               data.crd,
+                               data.crn,
+                               data.crm,
+                               data.cp);
+        },
+        [condition](CoprocessorRegisterTransfer& data) {
+            return std::format("{}{} p{},{},R{},c{},c{},{}",
+                               (data.load ? "MRC" : "MCR"),
+                               condition,
+                               data.cpn,
+                               data.cp_opc,
+                               data.rd,
+                               data.crn,
+                               data.crm,
+                               data.cp);
+        },
+        [](auto) { return std::string("unknown instruction"); } },
+      data);
+}
+}

src/cpu/arm/exec.cc

@@ -1,24 +1,21 @@
-#include "cpu/cpu-impl.hh"
+#include "cpu/cpu.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
-namespace matar {
+namespace matar::arm {
 void
-CpuImpl::exec_arm(const arm::Instruction instruction) {
+Instruction::exec(Cpu& cpu) {
-    Condition cond            = instruction.condition;
+    if (!cpu.cpsr.condition(condition)) {
-    arm::InstructionData data = instruction.data;
-
-    if (!cpsr.condition(cond)) {
         return;
     }
 
-    auto pc_error = [](uint8_t r) {
+    auto pc_error = [cpu](uint8_t r) {
-        if (r == PC_INDEX)
+        if (r == cpu.PC_INDEX)
             glogger.error("Using PC (R15) as operand register");
     };
 
-    auto pc_warn = [](uint8_t r) {
+    auto pc_warn = [cpu](uint8_t r) {
-        if (r == PC_INDEX)
+        if (r == cpu.PC_INDEX)
             glogger.warn("Using PC (R15) as operand register");
     };
 
@@ -26,38 +23,40 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
 
     std::visit(
       overloaded{
-        [this, pc_warn](BranchAndExchange& data) {
+        [&cpu, pc_warn](BranchAndExchange& data) {
-            State state = static_cast<State>(data.rn & 1);
+            uint32_t addr = cpu.gpr[data.rn];
+            State state   = static_cast<State>(get_bit(addr, 0));
 
             pc_warn(data.rn);
 
+            if (state != cpu.cpsr.state())
+                glogger.info_bold("State changed");
+
             // set state
-            cpsr.set_state(state);
+            cpu.cpsr.set_state(state);
 
             // copy to PC
-            pc = gpr[data.rn];
+            cpu.pc = addr;
 
             // ignore [1:0] bits for arm and 0 bit for thumb
-            rst_bit(pc, 0);
+            rst_bit(cpu.pc, 0);
 
             if (state == State::Arm)
-                rst_bit(pc, 1);
+                rst_bit(cpu.pc, 1);
 
-            // pc is affected so flush the pipeline
+            // PC is affected so flush the pipeline
-            is_flushed = true;
+            cpu.is_flushed = true;
         },
-        [this](Branch& data) {
+        [&cpu](Branch& data) {
             if (data.link)
-                gpr[14] = pc - INSTRUCTION_SIZE;
+                cpu.gpr[14] = cpu.pc - INSTRUCTION_SIZE;
 
-            // data.offset accounts for two instructions ahead when
+            cpu.pc += data.offset;
-            // disassembling, so need to adjust
-            pc = static_cast<int32_t>(pc) - 2 * INSTRUCTION_SIZE + data.offset;
 
             // pc is affected so flush the pipeline
-            is_flushed = true;
+            cpu.is_flushed = true;
         },
-        [this, pc_error](Multiply& data) {
+        [&cpu, pc_error](Multiply& data) {
             if (data.rd == data.rm)
                 glogger.error("rd and rm are not distinct in {}",
                               typeid(data).name());
@@ -66,16 +65,16 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             pc_error(data.rd);
             pc_error(data.rd);
 
-            gpr[data.rd] =
+            cpu.gpr[data.rd] = cpu.gpr[data.rm] * cpu.gpr[data.rs] +
-              gpr[data.rm] * gpr[data.rs] + (data.acc ? gpr[data.rn] : 0);
+                               (data.acc ? cpu.gpr[data.rn] : 0);
 
             if (data.set) {
-                cpsr.set_z(gpr[data.rd] == 0);
+                cpu.cpsr.set_z(cpu.gpr[data.rd] == 0);
-                cpsr.set_n(get_bit(gpr[data.rd], 31));
+                cpu.cpsr.set_n(get_bit(cpu.gpr[data.rd], 31));
-                cpsr.set_c(0);
+                cpu.cpsr.set_c(0);
             }
         },
-        [this, pc_error](MultiplyLong& data) {
+        [&cpu, pc_error](MultiplyLong& data) {
             if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
                 data.rdlo == data.rm)
                 glogger.error("rdhi, rdlo and rm are not distinct in {}",
@@ -91,58 +90,60 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                     return static_cast<uint64_t>(x);
                 };
 
-                uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                uint64_t eval =
-                                (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                  cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
-                                              cast(gpr[data.rdlo])
+                  (data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
+                                cast(cpu.gpr[data.rdlo])
                             : 0);
 
-                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
-                gpr[data.rdhi] = bit_range(eval, 32, 63);
+                cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
 
             } else {
                 auto cast = [](uint32_t x) -> int64_t {
                     return static_cast<int64_t>(static_cast<int32_t>(x));
                 };
 
-                int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
+                int64_t eval = cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
-                               (data.acc ? (cast(gpr[data.rdhi]) << 32) |
+                               (data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
-                                             cast(gpr[data.rdlo])
+                                             cast(cpu.gpr[data.rdlo])
                                          : 0);
 
-                gpr[data.rdlo] = bit_range(eval, 0, 31);
+                cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
-                gpr[data.rdhi] = bit_range(eval, 32, 63);
+                cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
             }
 
             if (data.set) {
-                cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
+                cpu.cpsr.set_z(cpu.gpr[data.rdhi] == 0 &&
-                cpsr.set_n(get_bit(gpr[data.rdhi], 31));
+                               cpu.gpr[data.rdlo] == 0);
-                cpsr.set_c(0);
+                cpu.cpsr.set_n(get_bit(cpu.gpr[data.rdhi], 31));
-                cpsr.set_v(0);
+                cpu.cpsr.set_c(0);
+                cpu.cpsr.set_v(0);
             }
         },
         [](Undefined) { glogger.warn("Undefined instruction"); },
-        [this, pc_error](SingleDataSwap& data) {
+        [&cpu, pc_error](SingleDataSwap& data) {
             pc_error(data.rm);
             pc_error(data.rn);
             pc_error(data.rd);
 
             if (data.byte) {
-                gpr[data.rd] = bus->read_byte(gpr[data.rn]);
+                cpu.gpr[data.rd] = cpu.bus->read_byte(cpu.gpr[data.rn]);
-                bus->write_byte(gpr[data.rn], gpr[data.rm] & 0xFF);
+                cpu.bus->write_byte(cpu.gpr[data.rn], cpu.gpr[data.rm] & 0xFF);
             } else {
-                gpr[data.rd] = bus->read_word(gpr[data.rn]);
+                cpu.gpr[data.rd] = cpu.bus->read_word(cpu.gpr[data.rn]);
-                bus->write_word(gpr[data.rn], gpr[data.rm]);
+                cpu.bus->write_word(cpu.gpr[data.rn], cpu.gpr[data.rm]);
             }
         },
-        [this, pc_warn, pc_error](SingleDataTransfer& data) {
+        [&cpu, pc_warn, pc_error](SingleDataTransfer& data) {
             uint32_t offset  = 0;
-            uint32_t address = gpr[data.rn];
+            uint32_t address = cpu.gpr[data.rn];
 
             if (!data.pre && data.write)
                 glogger.warn("Write-back enabled with post-indexing in {}",
                              typeid(data).name());
 
-            if (data.rn == PC_INDEX && data.write)
+            if (data.rn == cpu.PC_INDEX && data.write)
                 glogger.warn("Write-back enabled with base register as PC {}",
                              typeid(data).name());
 
@@ -156,24 +157,20 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
                 uint8_t amount =
                   (shift->data.immediate ? shift->data.operand
-                                         : gpr[shift->data.operand] & 0xFF);
+                                         : cpu.gpr[shift->data.operand] & 0xFF);
 
-                bool carry = cpsr.c();
+                bool carry = cpu.cpsr.c();
 
                 if (!shift->data.immediate)
                     pc_error(shift->data.operand);
                 pc_error(shift->rm);
 
-                offset =
+                offset = eval_shift(
-                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+                  shift->data.type, cpu.gpr[shift->rm], amount, carry);
 
-                cpsr.set_c(carry);
+                cpu.cpsr.set_c(carry);
             }
 
-            // PC is always two instructions ahead
-            if (data.rn == PC_INDEX)
-                address -= 2 * INSTRUCTION_SIZE;
-
             if (data.pre)
                 address += (data.up ? offset : -offset);
 
@@ -181,35 +178,35 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             if (data.load) {
                 // byte
                 if (data.byte)
-                    gpr[data.rd] = bus->read_byte(address);
+                    cpu.gpr[data.rd] = cpu.bus->read_byte(address);
                 // word
                 else
-                    gpr[data.rd] = bus->read_word(address);
+                    cpu.gpr[data.rd] = cpu.bus->read_word(address);
                 // store
             } else {
                 // take PC into consideration
-                if (data.rd == PC_INDEX)
+                if (data.rd == cpu.PC_INDEX)
                     address += INSTRUCTION_SIZE;
 
                 // byte
                 if (data.byte)
-                    bus->write_byte(address, gpr[data.rd] & 0xFF);
+                    cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
                 // word
                 else
-                    bus->write_word(address, gpr[data.rd]);
+                    cpu.bus->write_word(address, cpu.gpr[data.rd]);
             }
 
             if (!data.pre)
                 address += (data.up ? offset : -offset);
 
             if (!data.pre || data.write)
-                gpr[data.rn] = address;
+                cpu.gpr[data.rn] = address;
 
-            if (data.rd == PC_INDEX && data.load)
+            if (data.rd == cpu.PC_INDEX && data.load)
-                is_flushed = true;
+                cpu.is_flushed = true;
         },
-        [this, pc_warn, pc_error](HalfwordTransfer& data) {
+        [&cpu, pc_warn, pc_error](HalfwordTransfer& data) {
-            uint32_t address = gpr[data.rn];
+            uint32_t address = cpu.gpr[data.rn];
             uint32_t offset  = 0;
 
             if (!data.pre && data.write)
@@ -225,13 +222,13 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             // offset is register number (4 bits) when not an immediate
             if (!data.imm) {
                 pc_error(data.offset);
-                offset = gpr[data.offset];
+                offset = cpu.gpr[data.offset];
             } else {
                 offset = data.offset;
             }
 
             // PC is always two instructions ahead
-            if (data.rn == PC_INDEX)
+            if (data.rn == cpu.PC_INDEX)
                 address -= 2 * INSTRUCTION_SIZE;
 
             if (data.pre)
@@ -243,140 +240,154 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                 if (data.sign) {
                     // halfword
                     if (data.half) {
-                        gpr[data.rd] = bus->read_halfword(address);
+                        cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
 
                         // sign extend the halfword
-                        gpr[data.rd] =
+                        cpu.gpr[data.rd] =
-                          (static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
+                          (static_cast<int32_t>(cpu.gpr[data.rd]) << 16) >> 16;
 
                         // byte
                     } else {
-                        gpr[data.rd] = bus->read_byte(address);
+                        cpu.gpr[data.rd] = cpu.bus->read_byte(address);
 
                         // sign extend the byte
-                        gpr[data.rd] =
+                        cpu.gpr[data.rd] =
-                          (static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
+                          (static_cast<int32_t>(cpu.gpr[data.rd]) << 24) >> 24;
                     }
                     // unsigned halfword
                 } else if (data.half) {
-                    gpr[data.rd] = bus->read_halfword(address);
+                    cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
                 }
                 // store
             } else {
                 // take PC into consideration
-                if (data.rd == PC_INDEX)
+                if (data.rd == cpu.PC_INDEX)
                     address += INSTRUCTION_SIZE;
 
                 // halfword
                 if (data.half)
-                    bus->write_halfword(address, gpr[data.rd]);
+                    cpu.bus->write_halfword(address, cpu.gpr[data.rd]);
             }
 
             if (!data.pre)
                 address += (data.up ? offset : -offset);
 
             if (!data.pre || data.write)
-                gpr[data.rn] = address;
+                cpu.gpr[data.rn] = address;
 
-            if (data.rd == PC_INDEX && data.load)
+            if (data.rd == cpu.PC_INDEX && data.load)
-                is_flushed = true;
+                cpu.is_flushed = true;
         },
-        [this, pc_error](BlockDataTransfer& data) {
+        [&cpu, pc_error](BlockDataTransfer& data) {
-            uint32_t address  = gpr[data.rn];
+            static constexpr uint8_t alignment = 4; // word
-            Mode mode         = cpsr.mode();
+
-            uint8_t alignment = 4; // word
+            uint32_t address = cpu.gpr[data.rn];
-            uint8_t i         = 0;
+            Mode mode        = cpu.cpsr.mode();
-            uint8_t n_regs    = std::popcount(data.regs);
+            int8_t i        = 0;
 
             pc_error(data.rn);
 
-            if (cpsr.mode() == Mode::User && data.s) {
+            if (cpu.cpsr.mode() == Mode::User && data.s) {
-                glogger.error("Bit S is set outside priviliged modes in {}",
+                glogger.error("Bit S is set outside priviliged modes in block "
-                              typeid(data).name());
+                              "data transfer");
             }
 
             // we just change modes to load user registers
-            if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
+            if ((!get_bit(data.regs, cpu.PC_INDEX) && data.s) ||
                 (!data.load && data.s)) {
-                chg_mode(Mode::User);
+                cpu.chg_mode(Mode::User);
 
                 if (data.write) {
-                    glogger.error(
+                    glogger.error("Write-back enable for user bank registers "
-                      "Write-back enable for user bank registers in {}",
+                                  "in block data transfer");
-                      typeid(data).name());
                 }
             }
 
-            // account for decrement
+            // increment beforehand
-            if (!data.up)
-                address -= (n_regs - 1) * alignment;
-
             if (data.pre)
                 address += (data.up ? alignment : -alignment);
 
             if (data.load) {
-                if (get_bit(data.regs, PC_INDEX) && data.s && data.load) {
+                if (get_bit(data.regs, cpu.PC_INDEX) && data.s && data.load) {
-                    // current mode's spsr is already loaded when it was
+                    // current mode's cpu.spsr is already loaded when it was
                     // switched
-                    spsr = cpsr;
+                    cpu.spsr = cpu.cpsr;
                 }
 
-                for (i = 0; i < GPR_COUNT; i++) {
+                if (data.up) {
+                    for (i = 0; i < cpu.GPR_COUNT; i++) {
                         if (get_bit(data.regs, i)) {
-                        gpr[i] = bus->read_word(address);
+                            cpu.gpr[i] = cpu.bus->read_word(address);
                             address += alignment;
                         }
                     }
                 } else {
-                for (i = 0; i < GPR_COUNT; i++) {
+                    for (i = cpu.GPR_COUNT - 1; i >= 0; i--) {
                         if (get_bit(data.regs, i)) {
-                        bus->write_word(address, gpr[i]);
+                            cpu.gpr[i] = cpu.bus->read_word(address);
+                            address -= alignment;
+                        }
+                    }
+                }
+            } else {
+                if (data.up) {
+                    for (i = 0; i < cpu.GPR_COUNT; i++) {
+                        if (get_bit(data.regs, i)) {
+                            cpu.bus->write_word(address, cpu.gpr[i]);
                             address += alignment;
                         }
                     }
+                } else {
+                    for (i = cpu.GPR_COUNT - 1; i >= 0; i--) {
+                        if (get_bit(data.regs, i)) {
+                            cpu.bus->write_word(address, cpu.gpr[i]);
+                            address -= alignment;
+                        }
+                    }
+                }
             }
 
-            if (!data.pre)
+            // fix increment
-                address += (data.up ? alignment : -alignment);
+            if (data.pre)
-
+                address += (data.up ? -alignment : alignment);
-            // reset back to original address + offset if incremented earlier
-            if (data.up)
-                address -= n_regs * alignment;
-            else
-                address -= alignment;
 
             if (!data.pre || data.write)
-                gpr[data.rn] = address;
+                cpu.gpr[data.rn] = address;
 
-            if (data.load && get_bit(data.regs, PC_INDEX))
+            if (data.load && get_bit(data.regs, cpu.PC_INDEX))
-                is_flushed = true;
+                cpu.is_flushed = true;
 
             // load back the original mode registers
-            chg_mode(mode);
+            cpu.chg_mode(mode);
         },
-        [this, pc_error](PsrTransfer& data) {
+        [&cpu, pc_error](PsrTransfer& data) {
-            if (data.spsr && cpsr.mode() == Mode::User) {
+            if (data.spsr && cpu.cpsr.mode() == Mode::User) {
-                glogger.error("Accessing SPSR in User mode in {}",
+                glogger.error("Accessing CPU.SPSR in User mode in {}",
                               typeid(data).name());
             }
 
-            Psr& psr = data.spsr ? spsr : cpsr;
+            Psr& psr = data.spsr ? cpu.spsr : cpu.cpsr;
 
             switch (data.type) {
                 case PsrTransfer::Type::Mrs:
                     pc_error(data.operand);
-                    gpr[data.operand] = psr.raw();
+                    cpu.gpr[data.operand] = psr.raw();
                     break;
                 case PsrTransfer::Type::Msr:
                     pc_error(data.operand);
 
-                    if (cpsr.mode() != Mode::User) {
+                    if (cpu.cpsr.mode() != Mode::User) {
-                        psr.set_all(gpr[data.operand]);
+                        if (!data.spsr) {
+                            Psr tmp = Psr(cpu.gpr[data.operand]);
+                            cpu.chg_mode(tmp.mode());
+                        }
+
+                        psr.set_all(cpu.gpr[data.operand]);
                     }
                     break;
                 case PsrTransfer::Type::Msr_flg:
                     uint32_t operand =
-                      (data.imm ? data.operand : gpr[data.operand]);
+                      (data.imm ? data.operand : cpu.gpr[data.operand]);
                     psr.set_n(get_bit(operand, 31));
                     psr.set_z(get_bit(operand, 30));
                     psr.set_c(get_bit(operand, 29));
@@ -384,10 +395,10 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                     break;
             }
         },
-        [this, pc_error](DataProcessing& data) {
+        [&cpu, pc_error](DataProcessing& data) {
             using OpCode = DataProcessing::OpCode;
 
-            uint32_t op_1 = gpr[data.rn];
+            uint32_t op_1 = cpu.gpr[data.rn];
             uint32_t op_2 = 0;
 
             uint32_t result = 0;
@@ -398,64 +409,26 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
             } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
                 uint8_t amount =
                   (shift->data.immediate ? shift->data.operand
-                                         : gpr[shift->data.operand] & 0xFF);
+                                         : cpu.gpr[shift->data.operand] & 0xFF);
 
-                bool carry = cpsr.c();
+                bool carry = cpu.cpsr.c();
 
                 if (!shift->data.immediate)
                     pc_error(shift->data.operand);
                 pc_error(shift->rm);
 
-                op_2 =
+                op_2 = eval_shift(
-                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
+                  shift->data.type, cpu.gpr[shift->rm], amount, carry);
 
-                cpsr.set_c(carry);
+                cpu.cpsr.set_c(carry);
 
                 // PC is 12 bytes ahead when shifting
-                if (data.rn == PC_INDEX)
+                if (data.rn == cpu.PC_INDEX)
                     op_1 += INSTRUCTION_SIZE;
             }
 
-            bool overflow = cpsr.v();
+            bool overflow = cpu.cpsr.v();
-            bool carry    = cpsr.c();
+            bool carry    = cpu.cpsr.c();
-
-            auto sub = [&carry, &overflow](uint32_t a, uint32_t b) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                uint32_t result = a - b;
-
-                carry    = b <= a;
-                overflow = s1 != s2 && s2 == get_bit(result, 31);
-                return result;
-            };
-
-            auto add = [&carry, &overflow](
-                         uint32_t a, uint32_t b, bool c = 0) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                // 33 bits
-                uint64_t result_ = a + b + c;
-                uint32_t result  = result_ & 0xFFFFFFFF;
-
-                carry    = get_bit(result_, 32);
-                overflow = s1 == s2 && s2 != get_bit(result, 31);
-                return result;
-            };
-
-            auto sbc = [&carry,
-                        &overflow](uint32_t a, uint32_t b, bool c) -> uint32_t {
-                bool s1 = get_bit(a, 31);
-                bool s2 = get_bit(b, 31);
-
-                uint64_t result_ = a - b + c - 1;
-                uint32_t result  = result_ & 0xFFFFFFFF;
-
-                carry    = get_bit(result_, 32);
-                overflow = s1 != s2 && s2 == get_bit(result, 31);
-                return result;
-            };
 
             switch (data.opcode) {
                 case OpCode::AND:
@@ -469,23 +442,23 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                     break;
                 case OpCode::SUB:
                 case OpCode::CMP:
-                    result = sub(op_1, op_2);
+                    result = sub(op_1, op_2, carry, overflow);
                     break;
                 case OpCode::RSB:
-                    result = sub(op_2, op_1);
+                    result = sub(op_2, op_1, carry, overflow);
                     break;
                 case OpCode::ADD:
                 case OpCode::CMN:
-                    result = add(op_1, op_2);
+                    result = add(op_1, op_2, carry, overflow);
                     break;
                 case OpCode::ADC:
-                    result = add(op_1, op_2, carry);
+                    result = add(op_1, op_2, carry, overflow, carry);
                     break;
                 case OpCode::SBC:
-                    result = sbc(op_1, op_2, carry);
+                    result = sbc(op_1, op_2, carry, overflow, carry);
                     break;
                 case OpCode::RSC:
-                    result = sbc(op_2, op_1, carry);
+                    result = sbc(op_2, op_1, carry, overflow, carry);
                     break;
                 case OpCode::ORR:
                     result = op_1 | op_2;
@@ -501,19 +474,19 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                     break;
             }
 
-            auto set_conditions = [this, carry, overflow, result]() {
+            auto set_conditions = [&cpu, carry, overflow, result]() {
-                cpsr.set_c(carry);
+                cpu.cpsr.set_c(carry);
-                cpsr.set_v(overflow);
+                cpu.cpsr.set_v(overflow);
-                cpsr.set_n(get_bit(result, 31));
+                cpu.cpsr.set_n(get_bit(result, 31));
-                cpsr.set_z(result == 0);
+                cpu.cpsr.set_z(result == 0);
             };
 
             if (data.set) {
-                if (data.rd == PC_INDEX) {
+                if (data.rd == cpu.PC_INDEX) {
-                    if (cpsr.mode() == Mode::User)
+                    if (cpu.cpsr.mode() == Mode::User)
                         glogger.error("Running {} in User mode",
                                       typeid(data).name());
-                    spsr = cpsr;
+                    cpu.spsr = cpu.cpsr;
                 } else {
                     set_conditions();
                 }
@@ -523,15 +496,15 @@ CpuImpl::exec_arm(const arm::Instruction instruction) {
                 data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
                 set_conditions();
             } else {
-                gpr[data.rd] = result;
+                cpu.gpr[data.rd] = result;
-                if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
+                if (data.rd == cpu.PC_INDEX || data.opcode == OpCode::MVN)
-                    is_flushed = true;
+                    cpu.is_flushed = true;
             }
         },
-        [this](SoftwareInterrupt) {
+        [&cpu](SoftwareInterrupt) {
-            chg_mode(Mode::Supervisor);
+            cpu.chg_mode(Mode::Supervisor);
-            pc   = 0x08;
+            cpu.pc   = 0x08;
-            spsr = cpsr;
+            cpu.spsr = cpu.cpsr;
         },
         [](auto& data) {
             glogger.error("Unimplemented {} instruction", typeid(data).name());

src/cpu/arm/instruction.cc

@@ -1,10 +1,7 @@
-#include "instruction.hh"
+#include "cpu/arm/instruction.hh"
 #include "util/bits.hh"
-#include <iterator>
-
-namespace matar {
-namespace arm {
 
+namespace matar::arm {
 Instruction::Instruction(uint32_t insn)
   : condition(static_cast<Condition>(bit_range(insn, 28, 31))) {
     // Branch and exhcange
@@ -16,12 +13,10 @@ Instruction::Instruction(uint32_t insn)
         // Branch
     } else if ((insn & 0x0E000000) == 0x0A000000) {
         bool link      = get_bit(insn, 24);
-        uint32_t offset = bit_range(insn, 0, 23);
+        int32_t offset = static_cast<int32_t>(bit_range(insn, 0, 23));
 
         // lsh 2 and sign extend the 26 bit offset to 32 bits
-        offset = (static_cast<int32_t>(offset) << 8) >> 6;
+        offset = (offset << 8) >> 6;
-
-        offset += 2 * INSTRUCTION_SIZE;
 
         data = Branch{ .link = link, .offset = offset };
 
@@ -275,261 +270,4 @@ Instruction::Instruction(uint32_t insn)
         data = Undefined{};
     }
 }
-
-std::string
-Instruction::disassemble() {
-    // goddamn this is gore
-    // TODO: make this less ugly
-    return std::visit(
-      overloaded{
-        [this](BranchAndExchange& data) {
-            return fmt::format("BX{} R{:d}", condition, data.rn);
-        },
-        [this](Branch& data) {
-            return fmt::format(
-              "B{}{} 0x{:06X}", (data.link ? "L" : ""), condition, data.offset);
-        },
-        [this](Multiply& data) {
-            if (data.acc) {
-                return fmt::format("MLA{}{} R{:d},R{:d},R{:d},R{:d}",
-                                   condition,
-                                   (data.set ? "S" : ""),
-                                   data.rd,
-                                   data.rm,
-                                   data.rs,
-                                   data.rn);
-            } else {
-                return fmt::format("MUL{}{} R{:d},R{:d},R{:d}",
-                                   condition,
-                                   (data.set ? "S" : ""),
-                                   data.rd,
-                                   data.rm,
-                                   data.rs);
-            }
-        },
-        [this](MultiplyLong& data) {
-            return fmt::format("{}{}{}{} R{:d},R{:d},R{:d},R{:d}",
-                               (data.uns ? 'U' : 'S'),
-                               (data.acc ? "MLAL" : "MULL"),
-                               condition,
-                               (data.set ? "S" : ""),
-                               data.rdlo,
-                               data.rdhi,
-                               data.rm,
-                               data.rs);
-        },
-        [](Undefined) { return std::string("UND"); },
-        [this](SingleDataSwap& data) {
-            return fmt::format("SWP{}{} R{:d},R{:d},[R{:d}]",
-                               condition,
-                               (data.byte ? "B" : ""),
-                               data.rd,
-                               data.rm,
-                               data.rn);
-        },
-        [this](SingleDataTransfer& data) {
-            std::string expression;
-            std::string address;
-
-            if (const uint16_t* offset = std::get_if<uint16_t>(&data.offset)) {
-                if (*offset == 0) {
-                    expression = "";
-                } else {
-                    expression =
-                      fmt::format(",{}#{:d}", (data.up ? '+' : '-'), *offset);
-                }
-            } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
-                // Shifts are always immediate in single data transfer
-                expression = fmt::format(",{}R{:d},{} #{:d}",
-                                         (data.up ? '+' : '-'),
-                                         shift->rm,
-                                         shift->data.type,
-                                         shift->data.operand);
-            }
-
-            return fmt::format(
-              "{}{}{}{} R{:d},[R{:d}{}]{}",
-              (data.load ? "LDR" : "STR"),
-              condition,
-              (data.byte ? "B" : ""),
-              (!data.pre && data.write ? "T" : ""),
-              data.rd,
-              data.rn,
-              (data.pre ? expression : ""),
-              (data.pre ? (data.write ? "!" : "") : expression));
-        },
-        [this](HalfwordTransfer& data) {
-            std::string expression;
-
-            if (data.imm) {
-                if (data.offset == 0) {
-                    expression = "";
-                } else {
-                    expression = fmt::format(
-                      ",{}#{:d}", (data.up ? '+' : '-'), data.offset);
-                }
-            } else {
-                expression =
-                  fmt::format(",{}R{:d}", (data.up ? '+' : '-'), data.offset);
-            }
-
-            return fmt::format(
-              "{}{}{}{} R{:d},[R{:d}{}]{}",
-              (data.load ? "LDR" : "STR"),
-              condition,
-              (data.sign ? "S" : ""),
-              (data.half ? 'H' : 'B'),
-              data.rd,
-              data.rn,
-              (data.pre ? expression : ""),
-              (data.pre ? (data.write ? "!" : "") : expression));
-        },
-        [this](BlockDataTransfer& data) {
-            std::string regs;
-
-            for (uint8_t i = 0; i < 16; i++) {
-                if (get_bit(data.regs, i))
-                    fmt::format_to(std::back_inserter(regs), "R{:d},", i);
-            };
-
-            regs.pop_back();
-
-            return fmt::format("{}{}{}{} R{:d}{},{{{}}}{}",
-                               (data.load ? "LDM" : "STM"),
-                               condition,
-                               (data.up ? 'I' : 'D'),
-                               (data.pre ? 'B' : 'A'),
-                               data.rn,
-                               (data.write ? "!" : ""),
-                               regs,
-                               (data.s ? "^" : ""));
-        },
-        [this](PsrTransfer& data) {
-            if (data.type == PsrTransfer::Type::Mrs) {
-                return fmt::format("MRS{} R{:d},{}",
-                                   condition,
-                                   data.operand,
-                                   (data.spsr ? "SPSR_all" : "CPSR_all"));
-            } else {
-                return fmt::format(
-                  "MSR{} {}_{},{}{}",
-                  condition,
-                  (data.spsr ? "SPSR" : "CPSR"),
-                  (data.type == PsrTransfer::Type::Msr_flg ? "flg" : "all"),
-                  (data.imm ? '#' : 'R'),
-                  data.operand);
-            }
-        },
-        [this](DataProcessing& data) {
-            using OpCode = DataProcessing::OpCode;
-
-            std::string op_2;
-
-            if (const uint32_t* operand =
-                  std::get_if<uint32_t>(&data.operand)) {
-                op_2 = fmt::format("#{:d}", *operand);
-            } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
-                op_2 = fmt::format("R{:d},{} {}{:d}",
-                                   shift->rm,
-                                   shift->data.type,
-                                   (shift->data.immediate ? '#' : 'R'),
-                                   shift->data.operand);
-            }
-
-            switch (data.opcode) {
-                case OpCode::MOV:
-                case OpCode::MVN:
-                    return fmt::format("{}{}{} R{:d},{}",
-                                       data.opcode,
-                                       condition,
-                                       (data.set ? "S" : ""),
-                                       data.rd,
-                                       op_2);
-                case OpCode::TST:
-                case OpCode::TEQ:
-                case OpCode::CMP:
-                case OpCode::CMN:
-                    return fmt::format(
-                      "{}{} R{:d},{}", data.opcode, condition, data.rn, op_2);
-                default:
-                    return fmt::format("{}{}{} R{:d},R{:d},{}",
-                                       data.opcode,
-                                       condition,
-                                       (data.set ? "S" : ""),
-                                       data.rd,
-                                       data.rn,
-                                       op_2);
-            }
-        },
-        [this](SoftwareInterrupt) { return fmt::format("SWI{}", condition); },
-        [this](CoprocessorDataTransfer& data) {
-            std::string expression = fmt::format(",#{:d}", data.offset);
-            return fmt::format(
-              "{}{}{} p{:d},c{:d},[R{:d}{}]{}",
-              (data.load ? "LDC" : "STC"),
-              condition,
-              (data.len ? "L" : ""),
-              data.cpn,
-              data.crd,
-              data.rn,
-              (data.pre ? expression : ""),
-              (data.pre ? (data.write ? "!" : "") : expression));
-        },
-        [this](CoprocessorDataOperation& data) {
-            return fmt::format("CDP{} p{},{},c{},c{},c{},{}",
-                               condition,
-                               data.cpn,
-                               data.cp_opc,
-                               data.crd,
-                               data.crn,
-                               data.crm,
-                               data.cp);
-        },
-        [this](CoprocessorRegisterTransfer& data) {
-            return fmt::format("{}{} p{},{},R{},c{},c{},{}",
-                               (data.load ? "MRC" : "MCR"),
-                               condition,
-                               data.cpn,
-                               data.cp_opc,
-                               data.rd,
-                               data.crn,
-                               data.crm,
-                               data.cp);
-        },
-        [](auto) { return std::string("unknown instruction"); } },
-      data);
-}
-
-std::ostream&
-operator<<(std::ostream& os, const DataProcessing::OpCode opcode) {
-
-#define CASE(opcode)                                                           \
-    case DataProcessing::OpCode::opcode:                                       \
-        os << #opcode;                                                         \
-        break;
-
-    switch (opcode) {
-        CASE(AND)
-        CASE(EOR)
-        CASE(SUB)
-        CASE(RSB)
-        CASE(ADD)
-        CASE(ADC)
-        CASE(SBC)
-        CASE(RSC)
-        CASE(TST)
-        CASE(TEQ)
-        CASE(CMP)
-        CASE(CMN)
-        CASE(ORR)
-        CASE(MOV)
-        CASE(BIC)
-        CASE(MVN)
-    }
-
-#undef CASE
-
-    return os;
-}
-}
 }

src/cpu/arm/meson.build

@@ -2,3 +2,7 @@ lib_sources += files(
   'instruction.cc',
   'exec.cc'
 )
+
+if get_option('disassembler')
+  lib_sources += files('disassembler.cc')
+endif

src/cpu/cpu-impl.cc

@@ -1,142 +0,0 @@
-#include "cpu-impl.hh"
-#include "util/bits.hh"
-#include "util/log.hh"
-#include <algorithm>
-#include <cstdio>
-
-namespace matar {
-CpuImpl::CpuImpl(const Bus& bus) noexcept
-  : bus(std::make_shared<Bus>(bus))
-  , gpr({ 0 })
-  , cpsr(0)
-  , spsr(0)
-  , is_flushed(false)
-  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
-  , spsr_banked({ 0, 0, 0, 0, 0 }) {
-    cpsr.set_mode(Mode::Supervisor);
-    cpsr.set_irq_disabled(true);
-    cpsr.set_fiq_disabled(true);
-    cpsr.set_state(State::Arm);
-    glogger.info("CPU successfully initialised");
-
-    // PC always points to two instructions ahead
-    // PC - 2 is the instruction being executed
-    pc += 2 * arm::INSTRUCTION_SIZE;
-}
-
-/* change modes */
-void
-CpuImpl::chg_mode(const Mode to) {
-    Mode from = cpsr.mode();
-
-    if (from == to)
-        return;
-
-/* TODO: replace visible registers with view once I understand how to
- * concatenate views */
-#define STORE_BANKED(mode, MODE)                                               \
-    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
-              gpr.begin() + gpr.size() - 1,                                    \
-              gpr_banked.mode.begin())
-
-    switch (from) {
-        case Mode::Fiq:
-            STORE_BANKED(fiq, FIQ);
-            spsr_banked.fiq = spsr;
-            break;
-
-        case Mode::Supervisor:
-            STORE_BANKED(svc, SVC);
-            spsr_banked.svc = spsr;
-            break;
-
-        case Mode::Abort:
-            STORE_BANKED(abt, ABT);
-            spsr_banked.abt = spsr;
-            break;
-
-        case Mode::Irq:
-            STORE_BANKED(irq, IRQ);
-            spsr_banked.irq = spsr;
-            break;
-
-        case Mode::Undefined:
-            STORE_BANKED(und, UND);
-            spsr_banked.und = spsr;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#define RESTORE_BANKED(mode, MODE)                                             \
-    std::copy(gpr_banked.mode.begin(),                                         \
-              gpr_banked.mode.end(),                                           \
-              gpr.begin() + GPR_##MODE##_FIRST)
-
-    switch (to) {
-        case Mode::Fiq:
-            RESTORE_BANKED(fiq, FIQ);
-            spsr = spsr_banked.fiq;
-            break;
-
-        case Mode::Supervisor:
-            RESTORE_BANKED(svc, SVC);
-            spsr = spsr_banked.svc;
-            break;
-
-        case Mode::Abort:
-            RESTORE_BANKED(abt, ABT);
-            spsr = spsr_banked.abt;
-            break;
-
-        case Mode::Irq:
-            RESTORE_BANKED(irq, IRQ);
-            spsr = spsr_banked.irq;
-            break;
-
-        case Mode::Undefined:
-            RESTORE_BANKED(und, UND);
-            spsr = spsr_banked.und;
-            break;
-
-        case Mode::User:
-        case Mode::System:
-            STORE_BANKED(old, SYS_USR);
-            break;
-    }
-
-#undef RESTORE_BANKED
-
-    cpsr.set_mode(to);
-}
-
-void
-CpuImpl::step() {
-    // Current instruction is two instructions behind PC
-    uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
-
-    if (cpsr.state() == State::Arm) {
-        uint32_t x = bus->read_word(cur_pc);
-        arm::Instruction instruction(x);
-        glogger.info("{:#034b}", x);
-
-        exec_arm(instruction);
-
-        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
-
-        if (is_flushed) {
-            // if flushed, do not increment the PC, instead set it to two
-            // instructions ahead to account for flushed "fetch" and "decode"
-            // instructions
-            pc += 2 * arm::INSTRUCTION_SIZE;
-            is_flushed = false;
-        } else {
-            // if not flushed continue like normal
-            pc += arm::INSTRUCTION_SIZE;
-        }
-    }
-}
-}

src/cpu/cpu-impl.hh

@@ -1,59 +0,0 @@
-#pragma once
-
-#include "bus.hh"
-#include "cpu/arm/instruction.hh"
-#include "cpu/psr.hh"
-
-#include <cstdint>
-
-namespace matar {
-class CpuImpl {
-  public:
-    CpuImpl(const Bus& bus) noexcept;
-
-    void step();
-    void chg_mode(const Mode to);
-    void exec_arm(const arm::Instruction instruction);
-
-    static constexpr uint8_t GPR_COUNT = 16;
-
-    static constexpr uint8_t GPR_FIQ_FIRST     = 8;
-    static constexpr uint8_t GPR_SVC_FIRST     = 13;
-    static constexpr uint8_t GPR_ABT_FIRST     = 13;
-    static constexpr uint8_t GPR_IRQ_FIRST     = 13;
-    static constexpr uint8_t GPR_UND_FIRST     = 13;
-    static constexpr uint8_t GPR_SYS_USR_FIRST = 8;
-
-    std::shared_ptr<Bus> bus;
-    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
-
-    Psr cpsr; // current program status register
-    Psr spsr; // status program status register
-
-    static constexpr uint8_t PC_INDEX = 15;
-    static_assert(PC_INDEX < GPR_COUNT);
-
-    uint32_t& pc = gpr[PC_INDEX];
-
-    bool is_flushed;
-
-    struct {
-        std::array<uint32_t, GPR_COUNT - GPR_FIQ_FIRST - 1> fiq;
-        std::array<uint32_t, GPR_COUNT - GPR_SVC_FIRST - 1> svc;
-        std::array<uint32_t, GPR_COUNT - GPR_ABT_FIRST - 1> abt;
-        std::array<uint32_t, GPR_COUNT - GPR_IRQ_FIRST - 1> irq;
-        std::array<uint32_t, GPR_COUNT - GPR_UND_FIRST - 1> und;
-
-        // visible registers before the mode switch
-        std::array<uint32_t, GPR_COUNT - GPR_SYS_USR_FIRST> old;
-    } gpr_banked; // banked general purpose registers
-
-    struct {
-        Psr fiq;
-        Psr svc;
-        Psr abt;
-        Psr irq;
-        Psr und;
-    } spsr_banked; // banked saved program status registers
-};
-}

src/cpu/cpu.cc

@@ -1,14 +1,177 @@
 #include "cpu/cpu.hh"
-#include "cpu-impl.hh"
+#include "cpu/arm/instruction.hh"
+#include "cpu/thumb/instruction.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+#include <algorithm>
+#include <cstdio>
 
 namespace matar {
 Cpu::Cpu(const Bus& bus) noexcept
-  : impl(std::make_unique<CpuImpl>(bus)){};
+  : bus(std::make_shared<Bus>(bus))
+  , gpr({ 0 })
+  , cpsr(0)
+  , spsr(0)
+  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
+  , spsr_banked({ 0, 0, 0, 0, 0 })
+  , is_flushed(false) {
+    cpsr.set_mode(Mode::Supervisor);
+    cpsr.set_irq_disabled(true);
+    cpsr.set_fiq_disabled(true);
+    cpsr.set_state(State::Arm);
+    glogger.info("CPU successfully initialised");
 
-Cpu::~Cpu() = default;
+    // PC always points to two instructions ahead
+    // PC - 2 is the instruction being executed
+    pc += 2 * arm::INSTRUCTION_SIZE;
+}
+
+/* change modes */
+void
+Cpu::chg_mode(const Mode to) {
+    Mode from = cpsr.mode();
+
+    if (from == to)
+        return;
+
+/* TODO: replace visible registers with view once I understand how to
+ * concatenate views */
+#define STORE_BANKED(mode, MODE)                                               \
+    std::copy(gpr.begin() + GPR_##MODE##_FIRST,                                \
+              gpr.end() - 1,                                                   \
+              gpr_banked.mode.begin())
+
+    switch (from) {
+        case Mode::Fiq:
+            STORE_BANKED(fiq, FIQ);
+            spsr_banked.fiq = spsr;
+            std::copy(gpr_banked.old.begin(),
+                      gpr_banked.old.end() - 2, // dont copy R13 and R14
+                      gpr.begin() + GPR_OLD_FIRST);
+            break;
+
+        case Mode::Supervisor:
+            STORE_BANKED(svc, SVC);
+            spsr_banked.svc = spsr;
+            break;
+
+        case Mode::Abort:
+            STORE_BANKED(abt, ABT);
+            spsr_banked.abt = spsr;
+            break;
+
+        case Mode::Irq:
+            STORE_BANKED(irq, IRQ);
+            spsr_banked.irq = spsr;
+            break;
+
+        case Mode::Undefined:
+            STORE_BANKED(und, UND);
+            spsr_banked.und = spsr;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            // we only take care of r13 and r14, because FIQ takes care of the
+            // rest
+            gpr_banked.old[5] = gpr[13];
+            gpr_banked.old[6] = gpr[14];
+            break;
+    }
+
+#undef STORE_BANKED
+
+#define RESTORE_BANKED(mode, MODE)                                             \
+    std::copy(gpr_banked.mode.begin(),                                         \
+              gpr_banked.mode.end(),                                           \
+              gpr.begin() + GPR_##MODE##_FIRST)
+
+    switch (to) {
+        case Mode::Fiq:
+            RESTORE_BANKED(fiq, FIQ);
+            spsr = spsr_banked.fiq;
+            std::copy(gpr.begin() + GPR_FIQ_FIRST,
+                      gpr.end() - 2, // dont copy R13 and R14
+                      gpr_banked.old.begin());
+            break;
+
+        case Mode::Supervisor:
+            RESTORE_BANKED(svc, SVC);
+            spsr = spsr_banked.svc;
+            break;
+
+        case Mode::Abort:
+            RESTORE_BANKED(abt, ABT);
+            spsr = spsr_banked.abt;
+            break;
+
+        case Mode::Irq:
+            RESTORE_BANKED(irq, IRQ);
+            spsr = spsr_banked.irq;
+            break;
+
+        case Mode::Undefined:
+            RESTORE_BANKED(und, UND);
+            spsr = spsr_banked.und;
+            break;
+
+        case Mode::User:
+        case Mode::System:
+            gpr[13] = gpr_banked.old[5];
+            gpr[14] = gpr_banked.old[6];
+            break;
+    }
+
+#undef RESTORE_BANKED
+
+    cpsr.set_mode(to);
+    glogger.info_bold("Mode changed from {:b} to {:b}",
+                      static_cast<uint32_t>(from),
+                      static_cast<uint32_t>(to));
+}
 
 void
 Cpu::step() {
-    impl->step();
+    // halfword align
-};
+    rst_bit(pc, 0);
+    if (cpsr.state() == State::Arm) {
+        // word align
+        rst_bit(pc, 1);
+        // Current instruction is two instructions behind PC
+        uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
+        arm::Instruction instruction(bus->read_word(cur_pc));
+
+#ifdef DISASSEMBLER
+        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
+#endif
+
+        instruction.exec(*this);
+    } else {
+        uint32_t cur_pc = pc - 2 * thumb::INSTRUCTION_SIZE;
+        thumb::Instruction instruction(bus->read_halfword(cur_pc));
+
+#ifdef DISASSEMBLER
+        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
+#endif
+
+        instruction.exec(*this);
+    }
+
+    // advance PC
+    {
+        size_t size = cpsr.state() == State::Arm ? arm::INSTRUCTION_SIZE
+                                                 : thumb::INSTRUCTION_SIZE;
+
+        if (is_flushed) {
+            // if flushed, do not increment the PC, instead set it to two
+            // instructions ahead to account for flushed "fetch" and "decode"
+            // instructions
+            pc += 2 * size;
+            is_flushed = false;
+        } else {
+            // if not flushed continue like normal
+            pc += size;
+        }
+    }
+}
 }

src/cpu/meson.build

@@ -1,8 +1,8 @@
 lib_sources += files(
-  'cpu-impl.cc',
   'cpu.cc',
   'psr.cc',
   'alu.cc'
 )
 
 subdir('arm')
+subdir('thumb')

src/cpu/psr.cc

@@ -1,6 +1,5 @@
-#include "psr.hh"
+#include "cpu/psr.hh"
 #include "util/bits.hh"
-#include "util/log.hh"
 
 namespace matar {
 Psr::Psr(uint32_t raw)
@@ -13,17 +12,17 @@ Psr::raw() const {
 
 void
 Psr::set_all(uint32_t raw) {
-    psr = raw & ~PSR_CLEAR_RESERVED;
+    psr = raw;
 }
 
 Mode
 Psr::mode() const {
-    return static_cast<Mode>(psr & ~PSR_CLEAR_MODE);
+    return static_cast<Mode>(psr & 0b11111);
 }
 
 void
 Psr::set_mode(Mode mode) {
-    psr &= PSR_CLEAR_MODE;
+    psr &= 0b00000;
     psr |= static_cast<uint32_t>(mode);
 }
 
@@ -91,42 +90,9 @@ Psr::condition(Condition cond) const {
         case Condition::LE:
             return z() || (n() != v());
         case Condition::AL:
-            return true && state() == State::Arm;
+            return true;
     }
 
     return false;
 }
-
-std::ostream&
-operator<<(std::ostream& os, const Condition cond) {
-
-#define CASE(cond)                                                             \
-    case Condition::cond:                                                      \
-        os << #cond;                                                           \
-        break;
-
-    switch (cond) {
-        CASE(EQ)
-        CASE(NE)
-        CASE(CS)
-        CASE(CC)
-        CASE(MI)
-        CASE(PL)
-        CASE(VS)
-        CASE(VC)
-        CASE(HI)
-        CASE(LS)
-        CASE(GE)
-        CASE(LT)
-        CASE(GT)
-        CASE(LE)
-        case Condition::AL: {
-            // empty
-        }
-    }
-
-#undef CASE
-
-    return os;
-}
 }

src/cpu/thumb/disassembler.cc

@@ -0,0 +1,155 @@
+#include "cpu/thumb/instruction.hh"
+#include "util/bits.hh"
+#include <format>
+
+namespace matar::thumb {
+std::string
+Instruction::disassemble() {
+    return std::visit(
+      overloaded{
+        [](MoveShiftedRegister& data) {
+            return std::format("{} R{:d},R{:d},#{:d}",
+                               stringify(data.opcode),
+                               data.rd,
+                               data.rs,
+                               data.offset);
+        },
+        [](AddSubtract& data) {
+            return std::format("{} R{:d},R{:d},{}{:d}",
+                               stringify(data.opcode),
+                               data.rd,
+                               data.rs,
+                               (data.imm ? '#' : 'R'),
+                               data.offset);
+        },
+        [](MovCmpAddSubImmediate& data) {
+            return std::format(
+              "{} R{:d},#{:d}", stringify(data.opcode), data.rd, data.offset);
+        },
+        [](AluOperations& data) {
+            return std::format(
+              "{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
+        },
+        [](HiRegisterOperations& data) {
+            if (data.opcode == HiRegisterOperations::OpCode::BX) {
+                return std::format("{} R{:d}", stringify(data.opcode), data.rs);
+            }
+
+            return std::format(
+              "{} R{:d},R{:d}", stringify(data.opcode), data.rd, data.rs);
+        },
+
+        [](PcRelativeLoad& data) {
+            return std::format("LDR R{:d},[PC,#{:d}]", data.rd, data.word);
+        },
+        [](LoadStoreRegisterOffset& data) {
+            return std::format("{}{} R{:d},[R{:d},R{:d}]",
+                               (data.load ? "LDR" : "STR"),
+                               (data.byte ? "B" : ""),
+                               data.rd,
+                               data.rb,
+                               data.ro);
+        },
+        [](LoadStoreSignExtendedHalfword& data) {
+            if (!data.s && !data.h) {
+                return std::format(
+                  "STRH R{:d},[R{:d},R{:d}]", data.rd, data.rb, data.ro);
+            }
+
+            return std::format("{}{} R{:d},[R{:d},R{:d}]",
+                               (data.s ? "LDS" : "LDR"),
+                               (data.h ? 'H' : 'B'),
+                               data.rd,
+                               data.rb,
+                               data.ro);
+        },
+        [](LoadStoreImmediateOffset& data) {
+            return std::format("{}{} R{:d},[R{:d},#{:d}]",
+                               (data.load ? "LDR" : "STR"),
+                               (data.byte ? "B" : ""),
+                               data.rd,
+                               data.rb,
+                               data.offset);
+        },
+        [](LoadStoreHalfword& data) {
+            return std::format("{} R{:d},[R{:d},#{:d}]",
+                               (data.load ? "LDRH" : "STRH"),
+                               data.rd,
+                               data.rb,
+                               data.offset);
+        },
+        [](SpRelativeLoad& data) {
+            return std::format("{} R{:d},[SP,#{:d}]",
+                               (data.load ? "LDR" : "STR"),
+                               data.rd,
+                               data.word);
+        },
+        [](LoadAddress& data) {
+            return std::format("ADD R{:d},{},#{:d}",
+                               data.rd,
+                               (data.sp ? "SP" : "PC"),
+                               data.word);
+        },
+        [](AddOffsetStackPointer& data) {
+            return std::format("ADD SP,#{:d}", data.word);
+        },
+        [](PushPopRegister& data) {
+            std::string regs;
+
+            for (uint8_t i = 0; i < 16; i++) {
+                if (get_bit(data.regs, i))
+                    std::format_to(std::back_inserter(regs), "R{:d},", i);
+            };
+
+            if (data.load) {
+                if (data.pclr)
+                    regs += "PC";
+                else
+                    regs.pop_back();
+
+                return std::format("POP {{{}}}", regs);
+            } else {
+                if (data.pclr)
+                    regs += "LR";
+                else
+                    regs.pop_back();
+
+                return std::format("PUSH {{{}}}", regs);
+            }
+        },
+        [](MultipleLoad& data) {
+            std::string regs;
+
+            for (uint8_t i = 0; i < 16; i++) {
+                if (get_bit(data.regs, i))
+                    std::format_to(std::back_inserter(regs), "R{:d},", i);
+            };
+
+            regs.pop_back();
+
+            return std::format(
+              "{} R{}!,{{{}}}", (data.load ? "LDMIA" : "STMIA"), data.rb, regs);
+        },
+        [](SoftwareInterrupt& data) {
+            return std::format("SWI {:d}", data.vector);
+        },
+        [](ConditionalBranch& data) {
+            return std::format(
+              "B{} #{:d}",
+              stringify(data.condition),
+              static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
+        },
+        [](UnconditionalBranch& data) {
+            return std::format(
+              "B #{:d}",
+              static_cast<int32_t>(data.offset + 2 * INSTRUCTION_SIZE));
+        },
+        [](LongBranchWithLink& data) {
+            // duh this manual be empty for H = 0
+            return std::format(
+              "BL{} #{:d}", (data.high ? "H" : ""), data.offset);
+        },
+        [](auto) { return std::string("unknown instruction"); } },
+      data);
+}
+}

src/cpu/thumb/exec.cc

@@ -0,0 +1,391 @@
+#include "cpu/cpu.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+namespace matar::thumb {
+void
+Instruction::exec(Cpu& cpu) {
+    auto set_cc = [&cpu](bool c, bool v, bool n, bool z) {
+        cpu.cpsr.set_c(c);
+        cpu.cpsr.set_v(v);
+        cpu.cpsr.set_n(n);
+        cpu.cpsr.set_z(z);
+    };
+
+    std::visit(
+      overloaded{
+        [&cpu, set_cc](MoveShiftedRegister& data) {
+            if (data.opcode == ShiftType::ROR)
+                glogger.error("Invalid opcode in {}", typeid(data).name());
+
+            bool carry = cpu.cpsr.c();
+
+            uint32_t shifted =
+              eval_shift(data.opcode, cpu.gpr[data.rs], data.offset, carry);
+
+            cpu.gpr[data.rd] = shifted;
+
+            set_cc(carry, cpu.cpsr.v(), get_bit(shifted, 31), shifted == 0);
+        },
+        [&cpu, set_cc](AddSubtract& data) {
+            uint32_t offset =
+              data.imm ? static_cast<uint32_t>(static_cast<int8_t>(data.offset))
+                       : cpu.gpr[data.offset];
+            uint32_t result = 0;
+            bool carry      = cpu.cpsr.c();
+            bool overflow   = cpu.cpsr.v();
+
+            switch (data.opcode) {
+                case AddSubtract::OpCode::ADD:
+                    result = add(cpu.gpr[data.rs], offset, carry, overflow);
+                    break;
+                case AddSubtract::OpCode::SUB:
+                    result = sub(cpu.gpr[data.rs], offset, carry, overflow);
+                    break;
+            }
+
+            cpu.gpr[data.rd] = result;
+            set_cc(carry, overflow, get_bit(result, 31), result == 0);
+        },
+        [&cpu, set_cc](MovCmpAddSubImmediate& data) {
+            uint32_t result = 0;
+            bool carry      = cpu.cpsr.c();
+            bool overflow   = cpu.cpsr.v();
+
+            switch (data.opcode) {
+                case MovCmpAddSubImmediate::OpCode::MOV:
+                    result = data.offset;
+                    carry  = 0;
+                    break;
+                case MovCmpAddSubImmediate::OpCode::ADD:
+                    result =
+                      add(cpu.gpr[data.rd], data.offset, carry, overflow);
+                    break;
+                case MovCmpAddSubImmediate::OpCode::SUB:
+                case MovCmpAddSubImmediate::OpCode::CMP:
+                    result =
+                      sub(cpu.gpr[data.rd], data.offset, carry, overflow);
+                    break;
+            }
+
+            set_cc(carry, overflow, get_bit(result, 31), result == 0);
+            if (data.opcode != MovCmpAddSubImmediate::OpCode::CMP)
+                cpu.gpr[data.rd] = result;
+        },
+        [&cpu, set_cc](AluOperations& data) {
+            uint32_t op_1   = cpu.gpr[data.rd];
+            uint32_t op_2   = cpu.gpr[data.rs];
+            uint32_t result = 0;
+
+            bool carry    = cpu.cpsr.c();
+            bool overflow = cpu.cpsr.v();
+
+            switch (data.opcode) {
+                case AluOperations::OpCode::AND:
+                case AluOperations::OpCode::TST:
+                    result = op_1 & op_2;
+                    break;
+                case AluOperations::OpCode::EOR:
+                    result = op_1 ^ op_2;
+                    break;
+                case AluOperations::OpCode::LSL:
+                    result = eval_shift(ShiftType::LSL, op_1, op_2, carry);
+                    break;
+                case AluOperations::OpCode::LSR:
+                    result = eval_shift(ShiftType::LSR, op_1, op_2, carry);
+                    break;
+                case AluOperations::OpCode::ASR:
+                    result = eval_shift(ShiftType::ASR, op_1, op_2, carry);
+                    break;
+                case AluOperations::OpCode::ADC:
+                    result = add(op_1, op_2, carry, overflow, carry);
+                    break;
+                case AluOperations::OpCode::SBC:
+                    result = sbc(op_1, op_2, carry, overflow, carry);
+                    break;
+                case AluOperations::OpCode::ROR:
+                    result = eval_shift(ShiftType::ROR, op_1, op_2, carry);
+                    break;
+                case AluOperations::OpCode::NEG:
+                    result = -op_2;
+                    break;
+                case AluOperations::OpCode::CMP:
+                    result = sub(op_1, op_2, carry, overflow);
+                    break;
+                case AluOperations::OpCode::CMN:
+                    result = add(op_1, op_2, carry, overflow);
+                    break;
+                case AluOperations::OpCode::ORR:
+                    result = op_1 | op_2;
+                    break;
+                case AluOperations::OpCode::MUL:
+                    result = op_1 * op_2;
+                    break;
+                case AluOperations::OpCode::BIC:
+                    result = op_1 & ~op_2;
+                    break;
+                case AluOperations::OpCode::MVN:
+                    result = ~op_2;
+                    break;
+            }
+
+            if (data.opcode != AluOperations::OpCode::TST &&
+                data.opcode != AluOperations::OpCode::CMP &&
+                data.opcode != AluOperations::OpCode::CMN)
+                cpu.gpr[data.rd] = result;
+
+            set_cc(carry, overflow, get_bit(result, 31), result == 0);
+        },
+        [&cpu, set_cc](HiRegisterOperations& data) {
+            uint32_t op_1 = cpu.gpr[data.rd];
+            uint32_t op_2 = cpu.gpr[data.rs];
+
+            bool carry    = cpu.cpsr.c();
+            bool overflow = cpu.cpsr.v();
+
+            // PC is already current + 4, so dont need to do that
+            if (data.rd == cpu.PC_INDEX)
+                rst_bit(op_1, 0);
+
+            if (data.rs == cpu.PC_INDEX)
+                rst_bit(op_2, 0);
+
+            switch (data.opcode) {
+                case HiRegisterOperations::OpCode::ADD: {
+                    cpu.gpr[data.rd] = add(op_1, op_2, carry, overflow);
+
+                    if (data.rd == cpu.PC_INDEX)
+                        cpu.is_flushed = true;
+                } break;
+                case HiRegisterOperations::OpCode::CMP: {
+                    uint32_t result = sub(op_1, op_2, carry, overflow);
+                    set_cc(carry, overflow, get_bit(result, 31), result == 0);
+                } break;
+                case HiRegisterOperations::OpCode::MOV: {
+                    cpu.gpr[data.rd] = op_2;
+
+                    if (data.rd == cpu.PC_INDEX)
+                        cpu.is_flushed = true;
+                } break;
+                case HiRegisterOperations::OpCode::BX: {
+                    State state = static_cast<State>(get_bit(op_2, 0));
+
+                    if (state != cpu.cpsr.state())
+                        glogger.info_bold("State changed");
+
+                    // set state
+                    cpu.cpsr.set_state(state);
+
+                    // copy to PC
+                    cpu.pc = op_2;
+
+                    // ignore [1:0] bits for arm and 0 bit for thumb
+                    rst_bit(cpu.pc, 0);
+
+                    if (state == State::Arm)
+                        rst_bit(cpu.pc, 1);
+
+                    // pc is affected so flush the pipeline
+                    cpu.is_flushed = true;
+                } break;
+            }
+        },
+        [&cpu](PcRelativeLoad& data) {
+            uint32_t pc = cpu.pc;
+            rst_bit(pc, 0);
+            rst_bit(pc, 1);
+
+            cpu.gpr[data.rd] = cpu.bus->read_word(pc + data.word);
+        },
+        [&cpu](LoadStoreRegisterOffset& data) {
+            uint32_t address = cpu.gpr[data.rb] + cpu.gpr[data.ro];
+
+            if (data.load) {
+                if (data.byte) {
+                    cpu.gpr[data.rd] = cpu.bus->read_byte(address);
+                } else {
+                    cpu.gpr[data.rd] = cpu.bus->read_word(address);
+                }
+            } else {
+                if (data.byte) {
+                    cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
+                } else {
+                    cpu.bus->write_word(address, cpu.gpr[data.rd]);
+                }
+            }
+        },
+        [&cpu](LoadStoreSignExtendedHalfword& data) {
+            uint32_t address = cpu.gpr[data.rb] + cpu.gpr[data.ro];
+
+            switch (data.s << 1 | data.h) {
+                case 0b00:
+                    cpu.bus->write_halfword(address, cpu.gpr[data.rd] & 0xFFFF);
+                    break;
+                case 0b01:
+                    cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
+                    break;
+                case 0b10:
+                    // sign extend and load the byte
+                    cpu.gpr[data.rd] =
+                      (static_cast<int32_t>(cpu.bus->read_byte(address))
+                       << 24) >>
+                      24;
+                    break;
+                case 0b11:
+                    // sign extend the halfword
+                    cpu.gpr[data.rd] =
+                      (static_cast<int32_t>(cpu.bus->read_halfword(address))
+                       << 16) >>
+                      16;
+                    break;
+
+                    // unreachable
+                default: {
+                }
+            }
+        },
+        [&cpu](LoadStoreImmediateOffset& data) {
+            uint32_t address = cpu.gpr[data.rb] + data.offset;
+
+            if (data.load) {
+                if (data.byte) {
+                    cpu.gpr[data.rd] = cpu.bus->read_byte(address);
+                } else {
+                    cpu.gpr[data.rd] = cpu.bus->read_word(address);
+                }
+            } else {
+                if (data.byte) {
+                    cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
+                } else {
+                    cpu.bus->write_word(address, cpu.gpr[data.rd]);
+                }
+            }
+        },
+        [&cpu](LoadStoreHalfword& data) {
+            uint32_t address = cpu.gpr[data.rb] + data.offset;
+
+            if (data.load) {
+                cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
+            } else {
+                cpu.bus->write_halfword(address, cpu.gpr[data.rd] & 0xFFFF);
+            }
+        },
+        [&cpu](SpRelativeLoad& data) {
+            uint32_t address = cpu.sp + data.word;
+
+            if (data.load) {
+                cpu.gpr[data.rd] = cpu.bus->read_word(address);
+            } else {
+                cpu.bus->write_word(address, cpu.gpr[data.rd]);
+            }
+        },
+        [&cpu](LoadAddress& data) {
+            if (data.sp) {
+                cpu.gpr[data.rd] = cpu.sp + data.word;
+            } else {
+                // PC is already current + 4, so dont need to do that
+                // force bit 1 to 0
+                cpu.gpr[data.rd] = (cpu.pc & ~(1 << 1)) + data.word;
+            }
+        },
+        [&cpu](AddOffsetStackPointer& data) { cpu.sp += data.word; },
+        [&cpu](PushPopRegister& data) {
+            static constexpr uint8_t alignment = 4;
+
+            if (data.load) {
+                for (uint8_t i = 0; i < 8; i++) {
+                    if (get_bit(data.regs, i)) {
+                        cpu.gpr[i] = cpu.bus->read_word(cpu.sp);
+                        cpu.sp += alignment;
+                    }
+                }
+
+                if (data.pclr) {
+                    cpu.pc = cpu.bus->read_word(cpu.sp);
+                    cpu.sp += alignment;
+                    cpu.is_flushed = true;
+                }
+            } else {
+                if (data.pclr) {
+                    cpu.sp -= alignment;
+                    cpu.bus->write_word(cpu.sp, cpu.lr);
+                }
+
+                for (int8_t i = 7; i >= 0; i--) {
+                    if (get_bit(data.regs, i)) {
+                        cpu.sp -= alignment;
+                        cpu.bus->write_word(cpu.sp, cpu.gpr[i]);
+                    }
+                }
+            }
+        },
+        [&cpu](MultipleLoad& data) {
+            static constexpr uint8_t alignment = 4;
+
+            uint32_t rb = cpu.gpr[data.rb];
+
+            if (data.load) {
+                for (uint8_t i = 0; i < 8; i++) {
+                    if (get_bit(data.regs, i)) {
+                        cpu.gpr[i] = cpu.bus->read_word(rb);
+                        rb += alignment;
+                    }
+                }
+            } else {
+                for (int8_t i = 7; i >= 0; i--) {
+                    if (get_bit(data.regs, i)) {
+                        rb -= alignment;
+                        cpu.bus->write_word(rb, cpu.gpr[i]);
+                    }
+                }
+            }
+
+            cpu.gpr[data.rb] = rb;
+        },
+        [&cpu](ConditionalBranch& data) {
+            if (data.condition == Condition::AL)
+                glogger.warn("Condition 1110 (AL) is undefined");
+
+            if (!cpu.cpsr.condition(data.condition))
+                return;
+
+            cpu.pc += data.offset;
+            cpu.is_flushed = true;
+        },
+        [&cpu](SoftwareInterrupt& data) {
+            // next instruction is one instruction behind PC
+            cpu.lr   = cpu.pc - INSTRUCTION_SIZE;
+            cpu.spsr = cpu.cpsr;
+            cpu.pc   = data.vector;
+            cpu.cpsr.set_state(State::Arm);
+            cpu.chg_mode(Mode::Supervisor);
+            cpu.is_flushed = true;
+        },
+        [&cpu](UnconditionalBranch& data) {
+            cpu.pc += data.offset;
+            cpu.is_flushed = true;
+        },
+        [&cpu](LongBranchWithLink& data) {
+            // 12 bit integer
+            int32_t offset = data.offset;
+
+            if (data.high) {
+                uint32_t old_pc = cpu.pc;
+
+                cpu.pc         = cpu.lr + offset;
+                cpu.lr         = (old_pc - INSTRUCTION_SIZE) | 1;
+                cpu.is_flushed = true;
+            } else {
+                // 12 + 11 = 23 bit
+                offset <<= 11;
+                // sign extend
+                offset = (offset << 9) >> 9;
+                cpu.lr = cpu.pc + offset;
+            }
+        },
+        [](auto& data) {
+            glogger.error("Unknown thumb format : {}", typeid(data).name());
+        } },
+      data);
+}
+}

src/cpu/thumb/instruction.cc

@@ -0,0 +1,213 @@
+#include "cpu/thumb/instruction.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+namespace matar::thumb {
+Instruction::Instruction(uint16_t insn) {
+    // Format 2: Add/Subtract
+    if ((insn & 0xF800) == 0x1800) {
+        uint8_t rd     = bit_range(insn, 0, 2);
+        uint8_t rs     = bit_range(insn, 3, 5);
+        uint8_t offset = bit_range(insn, 6, 8);
+        AddSubtract::OpCode opcode =
+          static_cast<AddSubtract::OpCode>(get_bit(insn, 9));
+        bool imm = get_bit(insn, 10);
+
+        data = AddSubtract{
+            .rd = rd, .rs = rs, .offset = offset, .opcode = opcode, .imm = imm
+        };
+
+        // Format 1:  Move Shifted Register
+    } else if ((insn & 0xE000) == 0x0000) {
+        uint8_t rd       = bit_range(insn, 0, 2);
+        uint8_t rs       = bit_range(insn, 3, 5);
+        uint8_t offset   = bit_range(insn, 6, 10);
+        ShiftType opcode = static_cast<ShiftType>(bit_range(insn, 11, 12));
+
+        data = MoveShiftedRegister{
+            .rd = rd, .rs = rs, .offset = offset, .opcode = opcode
+        };
+
+        // Format 3: Move/compare/add/subtract immediate
+    } else if ((insn & 0xE000) == 0x2000) {
+        uint8_t offset = bit_range(insn, 0, 7);
+        uint8_t rd     = bit_range(insn, 8, 10);
+        MovCmpAddSubImmediate::OpCode opcode =
+          static_cast<MovCmpAddSubImmediate::OpCode>(bit_range(insn, 11, 12));
+
+        data =
+          MovCmpAddSubImmediate{ .offset = offset, .rd = rd, .opcode = opcode };
+
+        // Format 4: ALU operations
+    } else if ((insn & 0xFC00) == 0x4000) {
+        uint8_t rd = bit_range(insn, 0, 2);
+        uint8_t rs = bit_range(insn, 3, 5);
+        AluOperations::OpCode opcode =
+          static_cast<AluOperations::OpCode>(bit_range(insn, 6, 9));
+
+        data = AluOperations{ .rd = rd, .rs = rs, .opcode = opcode };
+
+        // Format 5: Hi register operations/branch exchange
+    } else if ((insn & 0xFC00) == 0x4400) {
+        uint8_t rd = bit_range(insn, 0, 2);
+        uint8_t rs = bit_range(insn, 3, 5);
+        bool hi_2  = get_bit(insn, 6);
+        bool hi_1  = get_bit(insn, 7);
+        HiRegisterOperations::OpCode opcode =
+          static_cast<HiRegisterOperations::OpCode>(bit_range(insn, 8, 9));
+
+        if (opcode == HiRegisterOperations::OpCode::BX && hi_1)
+            glogger.warn("H1 set with BX");
+
+        rd += (hi_1 ? LO_GPR_COUNT : 0);
+        rs += (hi_2 ? LO_GPR_COUNT : 0);
+
+        data = HiRegisterOperations{ .rd = rd, .rs = rs, .opcode = opcode };
+        // Format 6: PC-relative load
+    } else if ((insn & 0xF800) == 0x4800) {
+        uint16_t word = bit_range(insn, 0, 7);
+        uint8_t rd    = bit_range(insn, 8, 10);
+
+        data =
+          PcRelativeLoad{ .word = static_cast<uint16_t>(word << 2), .rd = rd };
+
+        // Format 7: Load/store with register offset
+    } else if ((insn & 0xF200) == 0x5000) {
+        uint8_t rd = bit_range(insn, 0, 2);
+        uint8_t rb = bit_range(insn, 3, 5);
+        uint8_t ro = bit_range(insn, 6, 8);
+        bool byte  = get_bit(insn, 10);
+        bool load  = get_bit(insn, 11);
+
+        data = LoadStoreRegisterOffset{
+            .rd = rd, .rb = rb, .ro = ro, .byte = byte, .load = load
+        };
+
+        // Format 8: Load/store sign-extended byte/halfword
+    } else if ((insn & 0xF200) == 0x5200) {
+        uint8_t rd = bit_range(insn, 0, 2);
+        uint8_t rb = bit_range(insn, 3, 5);
+        uint8_t ro = bit_range(insn, 6, 8);
+        bool s     = get_bit(insn, 10);
+        bool h     = get_bit(insn, 11);
+
+        data = LoadStoreSignExtendedHalfword{
+            .rd = rd, .rb = rb, .ro = ro, .s = s, .h = h
+        };
+
+        // Format 9: Load/store with immediate offset
+    } else if ((insn & 0xE000) == 0x6000) {
+        uint8_t rd     = bit_range(insn, 0, 2);
+        uint8_t rb     = bit_range(insn, 3, 5);
+        uint8_t offset = bit_range(insn, 6, 10);
+        bool load      = get_bit(insn, 11);
+        bool byte      = get_bit(insn, 12);
+
+        if (!byte)
+            offset <<= 2;
+
+        data = LoadStoreImmediateOffset{
+            .rd = rd, .rb = rb, .offset = offset, .load = load, .byte = byte
+        };
+
+        // Format 10: Load/store halfword
+    } else if ((insn & 0xF000) == 0x8000) {
+        uint8_t rd     = bit_range(insn, 0, 2);
+        uint8_t rb     = bit_range(insn, 3, 5);
+        uint8_t offset = bit_range(insn, 6, 10);
+        bool load      = get_bit(insn, 11);
+
+        offset <<= 1;
+
+        data = LoadStoreHalfword{
+            .rd = rd, .rb = rb, .offset = offset, .load = load
+        };
+
+        // Format 11: SP-relative load/store
+    } else if ((insn & 0xF000) == 0x9000) {
+        uint16_t word = bit_range(insn, 0, 7);
+        uint8_t rd    = bit_range(insn, 8, 10);
+        bool load     = get_bit(insn, 11);
+
+        word <<= 2;
+
+        data = SpRelativeLoad{ .word = word, .rd = rd, .load = load };
+
+        // Format 12: Load address
+    } else if ((insn & 0xF000) == 0xA000) {
+        uint16_t word = bit_range(insn, 0, 7);
+        uint8_t rd    = bit_range(insn, 8, 10);
+        bool sp       = get_bit(insn, 11);
+
+        word <<= 2;
+
+        data = LoadAddress{ .word = word, .rd = rd, .sp = sp };
+
+        // Format 13: Add offset to stack pointer
+    } else if ((insn & 0xFF00) == 0xB000) {
+        int16_t word = static_cast<int16_t>(bit_range(insn, 0, 6));
+        bool sign    = get_bit(insn, 7);
+
+        word <<= 2;
+        word = static_cast<int16_t>(word * (sign ? -1 : 1));
+
+        data = AddOffsetStackPointer{
+            .word = word,
+        };
+
+        // Format 14: Push/pop registers
+    } else if ((insn & 0xF600) == 0xB400) {
+        uint8_t regs = bit_range(insn, 0, 7);
+        bool pclr    = get_bit(insn, 8);
+        bool load    = get_bit(insn, 11);
+
+        data = PushPopRegister{ .regs = regs, .pclr = pclr, .load = load };
+
+        // Format 15: Multiple load/store
+    } else if ((insn & 0xF000) == 0xC000) {
+        uint8_t regs = bit_range(insn, 0, 7);
+        uint8_t rb   = bit_range(insn, 8, 10);
+        bool load    = get_bit(insn, 11);
+
+        data = MultipleLoad{ .regs = regs, .rb = rb, .load = load };
+
+        // Format 17: Software interrupt
+    } else if ((insn & 0xFF00) == 0xDF00) {
+        uint8_t vector = bit_range(insn, 0, 7);
+
+        data = SoftwareInterrupt{ .vector = vector };
+
+        // Format 16: Conditional branch
+    } else if ((insn & 0xF000) == 0xD000) {
+        int32_t offset      = bit_range(insn, 0, 7);
+        Condition condition = static_cast<Condition>(bit_range(insn, 8, 11));
+
+        offset <<= 1;
+
+        // sign extend the 9 bit integer
+        offset = (offset << 23) >> 23;
+
+        data = ConditionalBranch{ .offset = offset, .condition = condition };
+
+        // Format 18: Unconditional branch
+    } else if ((insn & 0xF800) == 0xE000) {
+        int32_t offset = bit_range(insn, 0, 10);
+
+        offset <<= 1;
+
+        // sign extend the 12 bit integer
+        offset = (offset << 20) >> 20;
+
+        data = UnconditionalBranch{ .offset = offset };
+
+        // Format 19: Long branch with link
+    } else if ((insn & 0xF000) == 0xF000) {
+        uint16_t offset = bit_range(insn, 0, 10);
+        bool high       = get_bit(insn, 11);
+
+        offset <<= 1;
+
+        data = LongBranchWithLink{ .offset = offset, .high = high };
+    }
+}
+}

src/cpu/thumb/meson.build

@@ -0,0 +1,8 @@
+lib_sources += files(
+  'instruction.cc',
+  'exec.cc'
+)
+
+if get_option('disassembler')
+  lib_sources += files('disassembler.cc')
+endif

src/io/io.cc

@@ -0,0 +1,279 @@
+#include "io/io.hh"
+#include "util/bits.hh"
+#include "util/log.hh"
+
+namespace matar {
+#define ADDR static constexpr uint32_t
+
+// lcd
+ADDR DISPCNT  = 0x4000000;
+ADDR DISPSTAT = 0x4000004;
+ADDR VCOUNT   = 0x4000006;
+ADDR BG0CNT   = 0x4000008;
+ADDR BG1CNT   = 0x400000A;
+ADDR BG2CNT   = 0x400000C;
+ADDR BG3CNT   = 0x400000E;
+ADDR BG0HOFS  = 0x4000010;
+ADDR BG0VOFS  = 0x4000012;
+ADDR BG1HOFS  = 0x4000014;
+ADDR BG1VOFS  = 0x4000016;
+ADDR BG2HOFS  = 0x4000018;
+ADDR BG2VOFS  = 0x400001A;
+ADDR BG3HOFS  = 0x400001C;
+ADDR BG3VOFS  = 0x400001E;
+ADDR BG2PA    = 0x4000020;
+ADDR BG2PB    = 0x4000022;
+ADDR BG2PC    = 0x4000024;
+ADDR BG2PD    = 0x4000026;
+ADDR BG2X_L   = 0x4000028;
+ADDR BG2X_H   = 0x400002A;
+ADDR BG2Y_L   = 0x400002C;
+ADDR BG2Y_H   = 0x400002E;
+ADDR BG3PA    = 0x4000030;
+ADDR BG3PB    = 0x4000032;
+ADDR BG3PC    = 0x4000034;
+ADDR BG3PD    = 0x4000036;
+ADDR BG3X_L   = 0x4000038;
+ADDR BG3X_H   = 0x400003A;
+ADDR BG3Y_L   = 0x400003C;
+ADDR BG3Y_H   = 0x400003E;
+ADDR WIN0H    = 0x4000040;
+ADDR WIN1H    = 0x4000042;
+ADDR WIN0V    = 0x4000044;
+ADDR WIN1V    = 0x4000046;
+ADDR WININ    = 0x4000048;
+ADDR WINOUT   = 0x400004A;
+ADDR MOSAIC   = 0x400004C;
+ADDR BLDCNT   = 0x4000050;
+ADDR BLDALPHA = 0x4000052;
+ADDR BLDY     = 0x4000054;
+
+// sound
+ADDR SOUND1CNT_L = 0x4000060;
+ADDR SOUND1CNT_H = 0x4000062;
+ADDR SOUND1CNT_X = 0x4000064;
+ADDR SOUND2CNT_L = 0x4000068;
+ADDR SOUND2CNT_H = 0x400006C;
+ADDR SOUND3CNT_L = 0x4000070;
+ADDR SOUND3CNT_H = 0x4000072;
+ADDR SOUND3CNT_X = 0x4000074;
+ADDR SOUND4CNT_L = 0x4000078;
+ADDR SOUND4CNT_H = 0x400007C;
+ADDR SOUNDCNT_L  = 0x4000080;
+ADDR SOUNDCNT_H  = 0x4000082;
+ADDR SOUNDCNT_X  = 0x4000084;
+ADDR SOUNDBIAS   = 0x4000088;
+ADDR WAVE_RAM0_L = 0x4000090;
+ADDR WAVE_RAM0_H = 0x4000092;
+ADDR WAVE_RAM1_L = 0x4000094;
+ADDR WAVE_RAM1_H = 0x4000096;
+ADDR WAVE_RAM2_L = 0x4000098;
+ADDR WAVE_RAM2_H = 0x400009A;
+ADDR WAVE_RAM3_L = 0x400009C;
+ADDR WAVE_RAM3_H = 0x400009E;
+ADDR FIFO_A_L    = 0x40000A0;
+ADDR FIFO_A_H    = 0x40000A2;
+ADDR FIFO_B_L    = 0x40000A4;
+ADDR FIFO_B_H    = 0x40000A6;
+
+// system
+ADDR POSTFLG = 0x4000300;
+ADDR IME     = 0x4000208;
+ADDR IE      = 0x4000200;
+ADDR IF      = 0x4000202;
+ADDR WAITCNT = 0x4000204;
+ADDR HALTCNT = 0x4000301;
+
+#undef ADDR
+
+uint8_t
+IoDevices::read_byte(uint32_t address) const {
+    uint16_t halfword = read_halfword(address & ~1);
+
+    if (address & 1)
+        halfword >>= 8;
+
+    return halfword & 0xFF;
+}
+
+void
+IoDevices::write_byte(uint32_t address, uint8_t byte) {
+    uint16_t halfword = read_halfword(address & ~1);
+
+    if (address & 1)
+        write_halfword(address & ~1,
+                       (static_cast<uint16_t>(byte) << 8) | (halfword & 0xFF));
+    else
+        write_halfword(address & ~1,
+                       (static_cast<uint16_t>(byte) | (halfword & 0xFF00)));
+}
+
+uint32_t
+IoDevices::read_word(uint32_t address) const {
+    return read_halfword(address) | read_halfword(address + 2) << 16;
+}
+
+void
+IoDevices::write_word(uint32_t address, uint32_t word) {
+    write_halfword(address, word & 0xFFFF);
+    write_halfword(address + 2, (word >> 16) & 0xFFFF);
+}
+
+uint16_t
+IoDevices::read_halfword(uint32_t address) const {
+    switch (address) {
+
+#define READ(name, var)                                                        \
+    case name:                                                                 \
+        return var;
+
+        // lcd
+        READ(DISPCNT, lcd.lcd_control)
+        READ(DISPSTAT, lcd.general_lcd_status)
+        READ(VCOUNT, lcd.vertical_counter)
+        READ(WININ, lcd.inside_win_0_1)
+        READ(WINOUT, lcd.outside_win)
+        READ(BLDCNT, lcd.color_special_effects_selection)
+        READ(BLDALPHA, lcd.alpha_blending_coefficients)
+
+        // sound
+        READ(SOUND1CNT_L, sound.ch1_sweep)
+        READ(SOUND1CNT_H, sound.ch1_duty_length_env)
+        READ(SOUND1CNT_X, sound.ch1_freq_control)
+        READ(SOUND2CNT_L, sound.ch2_duty_length_env)
+        READ(SOUND2CNT_H, sound.ch2_freq_control)
+        READ(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
+        READ(SOUND3CNT_H, sound.ch3_length_volume)
+        READ(SOUND3CNT_X, sound.ch3_freq_control)
+        READ(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
+        READ(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
+        READ(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
+        READ(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
+        READ(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
+        READ(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
+        READ(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
+        READ(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
+        READ(SOUND4CNT_L, sound.ch4_length_env);
+        READ(SOUND4CNT_H, sound.ch4_freq_control);
+        READ(SOUNDCNT_L, sound.ctrl_stereo_volume);
+        READ(SOUNDCNT_H, sound.ctrl_mixing);
+        READ(SOUNDCNT_X, sound.ctrl_sound_on_off);
+        READ(SOUNDBIAS, sound.pwm_control);
+
+        // system
+        READ(POSTFLG, system.post_boot_flag)
+        READ(IME, system.interrupt_master_enabler)
+        READ(IE, system.interrupt_enable);
+        READ(IF, system.interrupt_request_flags);
+        READ(WAITCNT, system.waitstate_control);
+
+#undef READ
+
+        default:
+            glogger.warn("Unused IO address read at 0x{:08X}", address);
+    }
+
+    return 0xFF;
+}
+
+void
+IoDevices::write_halfword(uint32_t address, uint16_t halfword) {
+    switch (address) {
+
+#define WRITE(name, var)                                                       \
+    case name:                                                                 \
+        var = halfword;                                                        \
+        break;
+
+#define WRITE_2(name, var, val)                                                \
+    case name:                                                                 \
+        var = val;                                                             \
+        break;
+
+        // lcd
+        WRITE(DISPCNT, lcd.lcd_control)
+        WRITE(DISPSTAT, lcd.general_lcd_status)
+        WRITE(BG0CNT, lcd.bg0_control)
+        WRITE(BG1CNT, lcd.bg1_control)
+        WRITE(BG2CNT, lcd.bg2_control)
+        WRITE(BG3CNT, lcd.bg3_control)
+        WRITE(BG0HOFS, lcd.bg0_x_offset)
+        WRITE(BG0VOFS, lcd.bg0_y_offset)
+        WRITE(BG1HOFS, lcd.bg1_x_offset)
+        WRITE(BG1VOFS, lcd.bg1_y_offset)
+        WRITE(BG2HOFS, lcd.bg2_x_offset)
+        WRITE(BG2VOFS, lcd.bg2_y_offset)
+        WRITE(BG3HOFS, lcd.bg3_x_offset)
+        WRITE(BG3VOFS, lcd.bg3_y_offset)
+        WRITE(BG2PA, lcd.bg2_rot_scaling_parameters[0])
+        WRITE(BG2PB, lcd.bg2_rot_scaling_parameters[1])
+        WRITE(BG2PC, lcd.bg2_rot_scaling_parameters[2])
+        WRITE(BG2PD, lcd.bg2_rot_scaling_parameters[3])
+        WRITE(BG2X_L, lcd.bg2_reference_x[0])
+        WRITE(BG2X_H, lcd.bg2_reference_x[1])
+        WRITE(BG2Y_L, lcd.bg2_reference_y[0])
+        WRITE(BG2Y_H, lcd.bg2_reference_y[1])
+        WRITE(BG3PA, lcd.bg3_rot_scaling_parameters[0])
+        WRITE(BG3PB, lcd.bg3_rot_scaling_parameters[1])
+        WRITE(BG3PC, lcd.bg3_rot_scaling_parameters[2])
+        WRITE(BG3PD, lcd.bg3_rot_scaling_parameters[3])
+        WRITE(BG3X_L, lcd.bg3_reference_x[0])
+        WRITE(BG3X_H, lcd.bg3_reference_x[1])
+        WRITE(BG3Y_L, lcd.bg3_reference_y[0])
+        WRITE(BG3Y_H, lcd.bg3_reference_y[1])
+        WRITE(WIN0H, lcd.win0_horizontal_dimensions)
+        WRITE(WIN1H, lcd.win1_horizontal_dimensions)
+        WRITE(WIN0V, lcd.win0_vertical_dimensions)
+        WRITE(WIN1V, lcd.win1_vertical_dimensions)
+        WRITE(WININ, lcd.inside_win_0_1)
+        WRITE(WINOUT, lcd.outside_win)
+        WRITE(MOSAIC, lcd.mosaic_size)
+        WRITE(BLDCNT, lcd.color_special_effects_selection)
+        WRITE(BLDALPHA, lcd.alpha_blending_coefficients)
+        WRITE(BLDY, lcd.brightness_coefficient)
+
+        // sound
+        WRITE(SOUND1CNT_L, sound.ch1_sweep)
+        WRITE(SOUND1CNT_H, sound.ch1_duty_length_env)
+        WRITE(SOUND1CNT_X, sound.ch1_freq_control)
+        WRITE(SOUND2CNT_L, sound.ch2_duty_length_env)
+        WRITE(SOUND2CNT_H, sound.ch2_freq_control)
+        WRITE(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
+        WRITE(SOUND3CNT_H, sound.ch3_length_volume)
+        WRITE(SOUND3CNT_X, sound.ch3_freq_control)
+        WRITE(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
+        WRITE(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
+        WRITE(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
+        WRITE(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
+        WRITE(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
+        WRITE(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
+        WRITE(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
+        WRITE(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
+        WRITE(SOUND4CNT_L, sound.ch4_length_env);
+        WRITE(SOUND4CNT_H, sound.ch4_freq_control);
+        WRITE(SOUNDCNT_L, sound.ctrl_stereo_volume);
+        WRITE(SOUNDCNT_H, sound.ctrl_mixing);
+        WRITE(SOUNDCNT_X, sound.ctrl_sound_on_off);
+        WRITE(SOUNDBIAS, sound.pwm_control);
+        WRITE(FIFO_A_L, sound.fifo_a[0]);
+        WRITE(FIFO_A_H, sound.fifo_a[1]);
+        WRITE(FIFO_B_L, sound.fifo_b[0]);
+        WRITE(FIFO_B_H, sound.fifo_b[1]);
+
+        // system
+        WRITE_2(POSTFLG, system.post_boot_flag, halfword & 1)
+        WRITE_2(IME, system.interrupt_master_enabler, halfword & 1)
+        WRITE(IE, system.interrupt_enable);
+        WRITE(IF, system.interrupt_request_flags);
+        WRITE(WAITCNT, system.waitstate_control);
+        WRITE_2(HALTCNT, system.low_power_mode, get_bit(halfword, 7));
+
+#undef WRITE
+#undef WRITE_2
+
+        default:
+            glogger.warn("Unused IO address written at 0x{:08X}", address);
+    }
+    return;
+}
+}

src/io/meson.build

@@ -0,0 +1,3 @@
+lib_sources += files(
+  'io.cc',
+)

src/memory.cc

@@ -1,9 +1,7 @@
 #include "memory.hh"
 #include "header.hh"
-#include "util/bits.hh"
 #include "util/crypto.hh"
 #include "util/log.hh"
-#include <bitset>
 #include <stdexcept>
 
 namespace matar {
@@ -34,64 +32,49 @@ Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
     glogger.info("Cartridge Title: {}", header.title);
 };
 
-#define MATCHES(area) address >= area##_START&& address <= area##_END
-
 uint8_t
-Memory::read(size_t address) const {
+Memory::read(uint32_t address) const {
-    if (MATCHES(BIOS)) {
+#define MATCHES(AREA, area)                                                    \
-        return bios[address];
+    if (address >= AREA##_START && address < AREA##_START + area.size())       \
-    } else if (MATCHES(BOARD_WRAM)) {
+        return area[address - AREA##_START];
-        return board_wram[address - BOARD_WRAM_START];
+
-    } else if (MATCHES(CHIP_WRAM)) {
+    MATCHES(BIOS, bios)
-        return chip_wram[address - CHIP_WRAM_START];
+    MATCHES(BOARD_WRAM, board_wram)
-    } else if (MATCHES(PALETTE_RAM)) {
+    MATCHES(CHIP_WRAM, chip_wram)
-        return palette_ram[address - PALETTE_RAM_START];
+    MATCHES(PALETTE_RAM, palette_ram)
-    } else if (MATCHES(VRAM)) {
+    MATCHES(VRAM, vram)
-        return vram[address - VRAM_START];
+    MATCHES(OAM_OBJ_ATTR, oam_obj_attr)
-    } else if (MATCHES(OAM_OBJ_ATTR)) {
+    MATCHES(ROM_0, rom)
-        return oam_obj_attr[address - OAM_OBJ_ATTR_START];
+    MATCHES(ROM_1, rom)
-    } else if (MATCHES(ROM_0)) {
+    MATCHES(ROM_2, rom)
-        return rom[address - ROM_0_START];
+
-    } else if (MATCHES(ROM_1)) {
-        return rom[address - ROM_1_START];
-    } else if (MATCHES(ROM_2)) {
-        return rom[address - ROM_2_START];
-    } else {
     glogger.error("Invalid memory region accessed");
     return 0xFF;
-    }
+
+#undef MATCHES
 }
 
 void
-Memory::write(size_t address, uint8_t byte) {
+Memory::write(uint32_t address, uint8_t byte) {
-    if (MATCHES(BIOS)) {
+#define MATCHES(AREA, area)                                                    \
-        bios[address] = byte;
+    if (address >= AREA##_START && address < AREA##_START + area.size()) {     \
-    } else if (MATCHES(BOARD_WRAM)) {
+        area[address - AREA##_START] = byte;                                   \
-        board_wram[address - BOARD_WRAM_START] = byte;
+        return;                                                                \
-    } else if (MATCHES(CHIP_WRAM)) {
-        chip_wram[address - CHIP_WRAM_START] = byte;
-    } else if (MATCHES(PALETTE_RAM)) {
-        palette_ram[address - PALETTE_RAM_START] = byte;
-    } else if (MATCHES(VRAM)) {
-        vram[address - VRAM_START] = byte;
-    } else if (MATCHES(OAM_OBJ_ATTR)) {
-        oam_obj_attr[address - OAM_OBJ_ATTR_START] = byte;
-    } else if (MATCHES(ROM_0)) {
-        rom[address - ROM_0_START] = byte;
-    } else if (MATCHES(ROM_1)) {
-        rom[address - ROM_1_START] = byte;
-    } else if (MATCHES(ROM_2)) {
-        rom[address - ROM_2_START] = byte;
-    } else {
-        glogger.error("Invalid memory region accessed");
     }
-}
+
+    MATCHES(BOARD_WRAM, board_wram)
+    MATCHES(CHIP_WRAM, chip_wram)
+    MATCHES(PALETTE_RAM, palette_ram)
+    MATCHES(VRAM, vram)
+    MATCHES(OAM_OBJ_ATTR, oam_obj_attr)
+
+    glogger.error("Invalid memory region accessed");
 
 #undef MATCHES
+}
 
 void
 Memory::parse_header() {
-
     if (rom.size() < header.HEADER_SIZE) {
         throw std::out_of_range(
           "ROM is not large enough to even have a header");
@@ -174,7 +157,7 @@ Memory::parse_header() {
     if (rom[0xB2] != 0x96)
         glogger.error("HEADER: invalid fixed byte at 0xB2");
 
-    for (size_t i = 0xB5; i < 0xBC; i++) {
+    for (uint32_t i = 0xB5; i < 0xBC; i++) {
         if (rom[i] != 0x00)
             glogger.error("HEADER: invalid fixed bytes at 0xB5");
     }
@@ -183,7 +166,7 @@ Memory::parse_header() {
 
     // checksum
     {
-        size_t i = 0xA0, chk = 0;
+        uint32_t i = 0xA0, chk = 0;
         while (i <= 0xBC)
             chk -= rom[i++];
         chk -= 0x19;

src/meson.build

@@ -1,23 +1,21 @@
 lib_sources = files(
   'memory.cc',
-  'bus.cc'
+  'bus.cc',
 )
 
 subdir('util')
 subdir('cpu')
+subdir('io')
 
-lib_cpp_args = [ ]
+lib_cpp_args = []
 
-fmt = dependency('fmt', version : '>=10.1.0', static: true)
+if get_option('disassembler')
-if not fmt.found()
+  lib_cpp_args += '-DDISASSEMBLER'
-  fmt = dependency('fmt', version : '>=10.1.0', static: false)
-  lib_cpp_args += 'DFMT_HEADER_ONLY'
 endif
 
 lib = library(
   meson.project_name(),
   lib_sources,
-  dependencies: [fmt],
   include_directories: inc,
   install: true,
   cpp_args: lib_cpp_args

src/util/bits.hh

@@ -35,6 +35,6 @@ inline Int
 bit_range(Int num, size_t start, size_t end) {
     // NOTE: we do not require -1 if it is a signed integral
     Int left =
-      std::numeric_limits<Int>::digits - (std::is_unsigned<Int>::value) - end;
+      std::numeric_limits<Int>::digits - (!std::is_signed<Int>::value) - end;
     return static_cast<Int>(num << left) >> (left + start);
 }

src/util/crypto.hh

@@ -2,7 +2,7 @@
 
 #include <array>
 #include <bit>
-#include <fmt/core.h>
+#include <format>
 #include <string>
 
 // Why I wrote this myself? I do not know
@@ -110,7 +110,7 @@ sha256(std::array<uint8_t, N>& data) {
 
     for (j = 0; j < 8; j++)
         for (i = 0; i < 4; i++)
-            fmt::format_to(std::back_inserter(string),
+            std::format_to(std::back_inserter(string),
                            "{:02x}",
                            ((h[j] >> (24 - i * 8)) & 0xFF));
 

src/util/log.hh

@@ -1,8 +1,7 @@
 #pragma once
 
 #include "util/loglevel.hh"
-#include <fmt/ostream.h>
+#include <print>
-#include <iostream>
 
 namespace logging {
 namespace ansi {
@@ -14,25 +13,25 @@ static constexpr auto BOLD    = "\033[1m";
 static constexpr auto RESET   = "\033[0m";
 }
 
-using fmt::print;
+using std::print;
 
 class Logger {
     using LogLevel = matar::LogLevel;
 
   public:
-    Logger(LogLevel level = LogLevel::Debug, FILE* stream = stderr)
+    Logger(LogLevel level = LogLevel::Debug, FILE* stream = stdout)
       : level(0)
       , stream(stream) {
         set_level(level);
     }
 
     template<typename... Args>
-    void log(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void log(const std::format_string<Args...>& fmt, Args&&... args) {
-        fmt::println(stream, fmt, std::forward<Args>(args)...);
+        std::println(stream, fmt, std::forward<Args>(args)...);
     }
 
     template<typename... Args>
-    void debug(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void debug(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Debug)) {
             print(stream, "{}{}[DEBUG] ", ansi::MAGENTA, ansi::BOLD);
             log(fmt, std::forward<Args>(args)...);
@@ -41,7 +40,7 @@ class Logger {
     }
 
     template<typename... Args>
-    void info(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void info(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Info)) {
             print(stream, "{}[INFO] ", ansi::WHITE);
             log(fmt, std::forward<Args>(args)...);
@@ -50,7 +49,16 @@ class Logger {
     }
 
     template<typename... Args>
-    void warn(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void info_bold(const std::format_string<Args...>& fmt, Args&&... args) {
+        if (level & static_cast<uint8_t>(LogLevel::Info)) {
+            print(stream, "{}{}[INFO] ", ansi::WHITE, ansi::BOLD);
+            log(fmt, std::forward<Args>(args)...);
+            print(stream, ansi::RESET);
+        }
+    }
+
+    template<typename... Args>
+    void warn(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Warn)) {
             print(stream, "{}[WARN] ", ansi::YELLOW);
             log(fmt, std::forward<Args>(args)...);
@@ -59,7 +67,7 @@ class Logger {
     }
 
     template<typename... Args>
-    void error(const fmt::format_string<Args...>& fmt, Args&&... args) {
+    void error(const std::format_string<Args...>& fmt, Args&&... args) {
         if (level & static_cast<uint8_t>(LogLevel::Error)) {
             print(stream, "{}{}[ERROR] ", ansi::RED, ansi::BOLD);
             log(fmt, std::forward<Args>(args)...);
@@ -80,4 +88,4 @@ class Logger {
 
 extern logging::Logger glogger;
 
-#define debug(x) glogger.debug("{} = {}", #x, x);
+#define dbg(x) glogger.debug("{} = {}", #x, x);

tests/bus.cc

@@ -1,7 +1,7 @@
 #include "bus.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[bus]";
+#define TAG "[bus]"
 
 using namespace matar;
 
@@ -16,28 +16,30 @@ class BusFixture {
 };
 
 TEST_CASE_METHOD(BusFixture, "Byte", TAG) {
-    CHECK(bus.read_byte(3349) == 0);
+    CHECK(bus.read_byte(0x30001A9) == 0);
 
-    bus.write_byte(3349, 0xEC);
+    bus.write_byte(0x30001A9, 0xEC);
-    CHECK(bus.read_byte(3349) == 0xEC);
+    CHECK(bus.read_byte(0x30001A9) == 0xEC);
-    CHECK(bus.read_word(3349) == 0xEC);
+    CHECK(bus.read_word(0x30001A9) == 0xEC);
-    CHECK(bus.read_halfword(3349) == 0xEC);
+    CHECK(bus.read_halfword(0x30001A9) == 0xEC);
 }
 
 TEST_CASE_METHOD(BusFixture, "Halfword", TAG) {
-    CHECK(bus.read_halfword(33750745) == 0);
+    CHECK(bus.read_halfword(0x202FED9) == 0);
 
-    bus.write_halfword(33750745, 0x1A4A);
+    bus.write_halfword(0x202FED9, 0x1A4A);
-    CHECK(bus.read_halfword(33750745) == 0x1A4A);
+    CHECK(bus.read_halfword(0x202FED9) == 0x1A4A);
-    CHECK(bus.read_word(33750745) == 0x1A4A);
+    CHECK(bus.read_word(0x202FED9) == 0x1A4A);
-    CHECK(bus.read_byte(33750745) == 0x4A);
+    CHECK(bus.read_byte(0x202FED9) == 0x4A);
 }
 
 TEST_CASE_METHOD(BusFixture, "Word", TAG) {
-    CHECK(bus.read_word(100724276) == 0);
+    CHECK(bus.read_word(0x600EE34) == 0);
 
-    bus.write_word(100724276, 0x3ACC491D);
+    bus.write_word(0x600EE34, 0x3ACC491D);
-    CHECK(bus.read_word(100724276) == 0x3ACC491D);
+    CHECK(bus.read_word(0x600EE34) == 0x3ACC491D);
-    CHECK(bus.read_halfword(100724276) == 0x491D);
+    CHECK(bus.read_halfword(0x600EE34) == 0x491D);
-    CHECK(bus.read_byte(100724276) == 0x1D);
+    CHECK(bus.read_byte(0x600EE34) == 0x1D);
 }
+
+#undef TAG

tests/cpu/arm/instruction.cc

@@ -1,7 +1,7 @@
 #include "cpu/arm/instruction.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[arm][disassembly]";
+#define TAG "[arm][disassembly]"
 
 using namespace matar;
 using namespace arm;
@@ -16,7 +16,9 @@ TEST_CASE("Branch and Exchange", TAG) {
 
     CHECK(bx->rn == 10);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "BXGT R10");
+#endif
 }
 
 TEST_CASE("Branch", TAG) {
@@ -29,14 +31,17 @@ TEST_CASE("Branch", TAG) {
 
     // last 24 bits = 8748995
     // (8748995 << 8) >> 6 sign extended = 0xFE15FF0C
-    // Also +8 since PC is two instructions ahead
+    CHECK(b->offset == static_cast<int32_t>(0xfe15ff0c));
-    CHECK(b->offset == 0xFE15FF14);
     CHECK(b->link == true);
 
-    CHECK(instruction.disassemble() == "BL 0xFE15FF14");
+#ifdef DISASSEMBLER
+    // take prefetch into account
+    // offset + 8 = 0xfe15ff0c + 8 = -0x1ea00e4 + 8
+    CHECK(instruction.disassemble() == "BL -0x1ea00ec");
 
     b->link = false;
-    CHECK(instruction.disassemble() == "B 0xFE15FF14");
+    CHECK(instruction.disassemble() == "B -0x1ea00ec");
+#endif
 }
 
 TEST_CASE("Multiply", TAG) {
@@ -54,11 +59,13 @@ TEST_CASE("Multiply", TAG) {
     CHECK(mul->acc == true);
     CHECK(mul->set == true);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "MLAEQS R10,R0,R15,R14");
 
     mul->acc = false;
     mul->set = false;
     CHECK(instruction.disassemble() == "MULEQ R10,R0,R15");
+#endif
 }
 
 TEST_CASE("Multiply Long", TAG) {
@@ -77,6 +84,7 @@ TEST_CASE("Multiply Long", TAG) {
     CHECK(mull->set == true);
     CHECK(mull->uns == true);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "UMULLNES R7,R14,R2,R6");
 
     mull->acc = true;
@@ -85,6 +93,7 @@ TEST_CASE("Multiply Long", TAG) {
     mull->uns = false;
     mull->set = false;
     CHECK(instruction.disassemble() == "SMLALNE R7,R14,R2,R6");
+#endif
 }
 
 TEST_CASE("Undefined", TAG) {
@@ -94,7 +103,10 @@ TEST_CASE("Undefined", TAG) {
     Instruction instruction(raw);
 
     CHECK(instruction.condition == Condition::AL);
+
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "UND");
+#endif
 }
 
 TEST_CASE("Single Data Swap", TAG) {
@@ -110,10 +122,12 @@ TEST_CASE("Single Data Swap", TAG) {
     CHECK(swp->rn == 9);
     CHECK(swp->byte == false);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "SWPGE R5,R6,[R9]");
 
     swp->byte = true;
     CHECK(instruction.disassemble() == "SWPGEB R5,R6,[R9]");
+#endif
 }
 
 TEST_CASE("Single Data Transfer", TAG) {
@@ -138,6 +152,7 @@ TEST_CASE("Single Data Transfer", TAG) {
     CHECK(ldr->up == true);
     CHECK(ldr->pre == true);
 
+#ifdef DISASSEMBLER
     ldr->load        = true;
     ldr->byte        = true;
     ldr->write       = false;
@@ -153,6 +168,7 @@ TEST_CASE("Single Data Transfer", TAG) {
 
     ldr->pre = true;
     CHECK(instruction.disassemble() == "LDRB R10,[R2,-#9023]");
+#endif
 }
 
 TEST_CASE("Halfword Transfer", TAG) {
@@ -176,6 +192,7 @@ TEST_CASE("Halfword Transfer", TAG) {
     CHECK(ldr->up == true);
     CHECK(ldr->pre == true);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "STRCCH R2,[R15,+R6]!");
 
     ldr->pre  = false;
@@ -193,6 +210,7 @@ TEST_CASE("Halfword Transfer", TAG) {
     ldr->imm    = 1;
     ldr->offset = 90;
     CHECK(instruction.disassemble() == "STRCCSB R2,[R15],-#90");
+#endif
 }
 
 TEST_CASE("Block Data Transfer", TAG) {
@@ -223,6 +241,7 @@ TEST_CASE("Block Data Transfer", TAG) {
     CHECK(ldm->up == false);
     CHECK(ldm->pre == true);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "LDMLSDB R7,{R0,R2,R3,R5,R6,R8,R14}^");
 
     ldm->write = true;
@@ -238,6 +257,7 @@ TEST_CASE("Block Data Transfer", TAG) {
     ldm->pre  = false;
 
     CHECK(instruction.disassemble() == "STMLSIA R7!,{R0,R2,R5,R14}");
+#endif
 }
 
 TEST_CASE("PSR Transfer", TAG) {
@@ -256,7 +276,9 @@ TEST_CASE("PSR Transfer", TAG) {
         CHECK(mrs->operand == 10);
         CHECK(mrs->spsr == true);
 
+#ifdef DISASSEMBLER
         CHECK(instruction.disassemble() == "MRSMI R10,SPSR_all");
+#endif
     }
 
     SECTION("MSR") {
@@ -272,7 +294,9 @@ TEST_CASE("PSR Transfer", TAG) {
         CHECK(msr->operand == 8);
         CHECK(msr->spsr == false);
 
+#ifdef DISASSEMBLER
         CHECK(instruction.disassemble() == "MSR CPSR_all,R8");
+#endif
     }
 
     SECTION("MSR_flg with register operand") {
@@ -287,7 +311,9 @@ TEST_CASE("PSR Transfer", TAG) {
         CHECK(msr->operand == 8);
         CHECK(msr->spsr == false);
 
+#ifdef DISASSEMBLER
         CHECK(instruction.disassemble() == "MSRVS CPSR_flg,R8");
+#endif
     }
 
     SECTION("MSR_flg with immediate operand") {
@@ -304,7 +330,9 @@ TEST_CASE("PSR Transfer", TAG) {
         CHECK(msr->operand == 27262976);
         CHECK(msr->spsr == true);
 
+#ifdef DISASSEMBLER
         CHECK(instruction.disassemble() == "MSR SPSR_flg,#27262976");
+#endif
     }
 }
 
@@ -331,6 +359,7 @@ TEST_CASE("Data Processing", TAG) {
     CHECK(alu->set == true);
     CHECK(alu->opcode == OpCode::AND);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "ANDS R7,R14,R1,ROR #22");
 
     shift->data.immediate = false;
@@ -392,6 +421,7 @@ TEST_CASE("Data Processing", TAG) {
         alu->opcode = OpCode::MVN;
         CHECK(instruction.disassemble() == "MVN R7,#3300012");
     }
+#endif
 }
 
 TEST_CASE("Coprocessor Data Transfer", TAG) {
@@ -412,6 +442,7 @@ TEST_CASE("Coprocessor Data Transfer", TAG) {
     CHECK(ldc->up == true);
     CHECK(ldc->pre == true);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "STCGE p1,c15,[R5,#70]!");
 
     ldc->load  = true;
@@ -420,6 +451,7 @@ TEST_CASE("Coprocessor Data Transfer", TAG) {
     ldc->len   = true;
 
     CHECK(instruction.disassemble() == "LDCGEL p1,c15,[R5],#70");
+#endif
 }
 
 TEST_CASE("Coprocessor Operand Operation", TAG) {
@@ -437,7 +469,9 @@ TEST_CASE("Coprocessor Operand Operation", TAG) {
     CHECK(cdp->crn == 5);
     CHECK(cdp->cp_opc == 10);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "CDP p1,10,c15,c5,c6,2");
+#endif
 }
 
 TEST_CASE("Coprocessor Register Transfer", TAG) {
@@ -457,7 +491,9 @@ TEST_CASE("Coprocessor Register Transfer", TAG) {
     CHECK(mrc->load == false);
     CHECK(mrc->cp_opc == 5);
 
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "MCR p1,5,R15,c5,c6,2");
+#endif
 }
 
 TEST_CASE("Software Interrupt", TAG) {
@@ -465,5 +501,10 @@ TEST_CASE("Software Interrupt", TAG) {
     Instruction instruction(raw);
 
     CHECK(instruction.condition == Condition::EQ);
+
+#ifdef DISASSEMBLER
     CHECK(instruction.disassemble() == "SWIEQ");
+#endif
 }
+
+#undef TAG

tests/cpu/cpu-fixture.cc

@@ -0,0 +1,96 @@
+#include "cpu-fixture.hh"
+
+Psr
+CpuFixture::psr(bool spsr) {
+    Psr psr(0);
+    Cpu tmp = cpu;
+    arm::Instruction instruction(
+      Condition::AL,
+      arm::PsrTransfer{ .operand = 0,
+                        .spsr    = spsr,
+                        .type    = arm::PsrTransfer::Type::Mrs,
+                        .imm     = false });
+
+    instruction.exec(tmp);
+
+    psr.set_all(getr_(0, tmp));
+    return psr;
+}
+
+void
+CpuFixture::set_psr(Psr psr, bool spsr) {
+    // R0
+    uint32_t old = getr(0);
+
+    setr(0, psr.raw());
+
+    arm::Instruction instruction(
+      Condition::AL,
+      arm::PsrTransfer{ .operand = 0,
+                        .spsr    = spsr,
+                        .type    = arm::PsrTransfer::Type::Msr,
+                        .imm     = false });
+
+    instruction.exec(cpu);
+
+    setr(0, old);
+}
+
+// We need these workarounds to just use the public API and not private
+// fields. Assuming that these work correctly is necessary. Besides, all that
+// matters is that the public API is correct.
+uint32_t
+CpuFixture::getr_(uint8_t r, Cpu& cpu) {
+    uint32_t addr  = 0x02000000;
+    uint8_t offset = r == 15 ? 4 : 0;
+    uint32_t word  = bus.read_word(addr + offset);
+    Cpu tmp        = cpu;
+    uint32_t ret   = 0xFFFFFFFF;
+    uint8_t base   = r ? 0 : 1;
+
+    // set R0/R1 = addr
+    arm::Instruction zero(
+      Condition::AL,
+      arm::DataProcessing{ .operand = addr,
+                           .rd      = base,
+                           .rn      = 0,
+                           .set     = false,
+                           .opcode  = arm::DataProcessing::OpCode::MOV });
+
+    // get register
+    arm::Instruction get(
+      Condition::AL,
+      arm::SingleDataTransfer{ .offset = static_cast<uint16_t>(0),
+                               .rd     = r,
+                               .rn     = base,
+                               .load   = false,
+                               .write  = false,
+                               .byte   = false,
+                               .up     = true,
+                               .pre    = true });
+
+    zero.exec(tmp);
+    get.exec(tmp);
+
+    addr += offset;
+
+    ret = bus.read_word(addr);
+
+    bus.write_word(addr, word);
+
+    return ret;
+}
+
+void
+CpuFixture::setr_(uint8_t r, uint32_t value, Cpu& cpu) {
+    // set register
+    arm::Instruction set(
+      Condition::AL,
+      arm::DataProcessing{ .operand = value,
+                           .rd      = r,
+                           .rn      = 0,
+                           .set     = false,
+                           .opcode  = arm::DataProcessing::OpCode::MOV });
+
+    set.exec(cpu);
+}

tests/cpu/cpu-fixture.hh

@@ -0,0 +1,42 @@
+#include "cpu/cpu.hh"
+
+using namespace matar;
+
+class CpuFixture {
+  public:
+    CpuFixture()
+      : bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+                   std::vector<uint8_t>(Header::HEADER_SIZE)))
+      , cpu(bus) {}
+
+  protected:
+    void exec(arm::InstructionData data, Condition condition = Condition::AL) {
+        arm::Instruction instruction(condition, data);
+        instruction.exec(cpu);
+    }
+
+    void exec(thumb::InstructionData data) {
+        thumb::Instruction instruction(data);
+        instruction.exec(cpu);
+    }
+
+    void reset(uint32_t value = 0) { setr(15, value + 8); }
+
+    uint32_t getr(uint8_t r) { return getr_(r, cpu); }
+
+    void setr(uint8_t r, uint32_t value) { setr_(r, value, cpu); }
+
+    Psr psr(bool spsr = false);
+
+    void set_psr(Psr psr, bool spsr = false);
+
+    Bus bus;
+    Cpu cpu;
+
+  private:
+    // hack to get a register
+    uint32_t getr_(uint8_t r, Cpu& cpu);
+
+    // hack to set a register
+    void setr_(uint8_t r, uint32_t value, Cpu& cpu);
+};

tests/cpu/meson.build

@@ -1 +1,6 @@
+tests_sources += files(
+  'cpu-fixture.cc'
+)
+
 subdir('arm')
+subdir('thumb')

tests/cpu/thumb/exec.cc

@@ -0,0 +1,995 @@
+#include "cpu/cpu-fixture.hh"
+#include "cpu/thumb/instruction.hh"
+#include <catch2/catch_test_macros.hpp>
+
+using namespace matar;
+
+#define TAG "[thumb][execution]"
+
+using namespace thumb;
+
+TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
+    InstructionData data = MoveShiftedRegister{
+        .rd = 3, .rs = 5, .offset = 15, .opcode = ShiftType::LSL
+    };
+    MoveShiftedRegister* move = std::get_if<MoveShiftedRegister>(&data);
+
+    SECTION("LSL") {
+        setr(3, 0);
+        setr(5, 6687);
+        // LSL
+        exec(data);
+        CHECK(getr(3) == 219119616);
+
+        setr(5, 0);
+        // zero
+        exec(data);
+        CHECK(getr(3) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("LSR") {
+        move->opcode = ShiftType::LSR;
+        setr(5, -1827489745);
+        // LSR
+        exec(data);
+        CHECK(getr(3) == 75301);
+        CHECK(!psr().n());
+
+        setr(5, 4444);
+        // zero flag
+        exec(data);
+        CHECK(getr(3) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("ASR") {
+        setr(5, -1827489745);
+        move->opcode = ShiftType::ASR;
+        // ASR
+        exec(data);
+        CHECK(psr().n());
+        CHECK(getr(3) == 4294911525);
+
+        setr(5, 500);
+        // zero flag
+        exec(data);
+        CHECK(getr(3) == 0);
+        CHECK(psr().z());
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Add/Subtract", TAG) {
+    InstructionData data = AddSubtract{ .rd     = 5,
+                                        .rs     = 2,
+                                        .offset = 7,
+                                        .opcode = AddSubtract::OpCode::ADD,
+                                        .imm    = false };
+    AddSubtract* add     = std::get_if<AddSubtract>(&data);
+    setr(2, 378427891);
+    setr(7, -666666);
+
+    SECTION("ADD") {
+        // register
+        exec(data);
+        CHECK(getr(5) == 377761225);
+
+        add->imm = true;
+        setr(2, (1u << 31) - 1);
+        // immediate and overflow
+        exec(data);
+        CHECK(getr(5) == 2147483654);
+        CHECK(psr().v());
+
+        setr(2, -7);
+        // zero
+        exec(data);
+        CHECK(getr(5) == 0);
+        CHECK(psr().z());
+    }
+
+    add->imm = true;
+
+    SECTION("SUB") {
+        add->opcode = AddSubtract::OpCode::SUB;
+        setr(2, -((1u << 31) - 1));
+        add->offset = 4;
+        exec(data);
+        CHECK(getr(5) == 2147483645);
+        CHECK(psr().v());
+
+        setr(2, ~0u);
+        add->offset = -4;
+        // carry
+        exec(data);
+        CHECK(getr(5) == 3);
+        CHECK(psr().c());
+
+        setr(2, 0);
+        add->offset = 0;
+        // zero
+        exec(data);
+
+        CHECK(getr(5) == 0);
+        CHECK(psr().z());
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
+    InstructionData data = MovCmpAddSubImmediate{
+        .offset = 251, .rd = 5, .opcode = MovCmpAddSubImmediate::OpCode::MOV
+    };
+    MovCmpAddSubImmediate* move = std::get_if<MovCmpAddSubImmediate>(&data);
+
+    SECTION("MOV") {
+        exec(data);
+        CHECK(getr(5) == 251);
+
+        move->offset = 0;
+        // zero
+        exec(data);
+        CHECK(getr(5) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("CMP") {
+        setr(5, 251);
+        move->opcode = MovCmpAddSubImmediate::OpCode::CMP;
+        CHECK(!psr().z());
+        exec(data);
+        CHECK(getr(5) == 251);
+        CHECK(psr().z());
+
+        // overflow
+        setr(5, -((1u << 31) - 1));
+        CHECK(!psr().v());
+        exec(data);
+        CHECK(getr(5) == 2147483649);
+        CHECK(psr().v());
+    }
+
+    SECTION("ADD") {
+        move->opcode = MovCmpAddSubImmediate::OpCode::ADD;
+        setr(5, (1u << 31) - 1);
+        // immediate and overflow
+        exec(data);
+        CHECK(getr(5) == 2147483898);
+        CHECK(psr().v());
+
+        setr(5, -251);
+        // zero
+        exec(data);
+        CHECK(getr(5) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("SUB") {
+        // same as CMP but loaded
+        setr(5, 251);
+        move->opcode = MovCmpAddSubImmediate::OpCode::SUB;
+        CHECK(!psr().z());
+        exec(data);
+        CHECK(getr(5) == 0);
+        CHECK(psr().z());
+
+        // overflow
+        setr(5, -((1u << 31) - 1));
+        CHECK(!psr().v());
+        exec(data);
+        CHECK(getr(5) == 2147483398);
+        CHECK(psr().v());
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
+    InstructionData data =
+      AluOperations{ .rd = 1, .rs = 3, .opcode = AluOperations::OpCode::AND };
+    AluOperations* alu = std::get_if<AluOperations>(&data);
+
+    setr(1, 328940001);
+    setr(3, -991);
+
+    SECTION("AND") {
+        // 328940001 & -991
+        exec(data);
+        CHECK(getr(1) == 328939553);
+        CHECK(!psr().n());
+
+        setr(3, 0);
+        CHECK(!psr().z());
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("EOR") {
+        alu->opcode = AluOperations::OpCode::EOR;
+        // 328940001 ^ -991
+        exec(data);
+        CHECK(getr(1) == 3966027200);
+        CHECK(psr().n());
+
+        setr(3, 3966027200);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+        CHECK(!psr().n());
+    }
+
+    SECTION("LSL") {
+        setr(3, 3);
+        alu->opcode = AluOperations::OpCode::LSL;
+        // 328940001 << 3
+        exec(data);
+        CHECK(getr(1) == 2631520008);
+        CHECK(psr().n());
+
+        setr(1, 0);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("LSR") {
+        alu->opcode = AluOperations::OpCode::LSR;
+        setr(3, 991);
+        // 328940001 >> 991
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+
+        setr(1, -83885328);
+        setr(3, 5);
+        // -83885328 >> 5
+        exec(data);
+        CHECK(getr(1) == 131596311);
+        CHECK(!psr().z());
+        CHECK(!psr().n());
+    }
+
+    SECTION("ASR") {
+        alu->opcode = AluOperations::OpCode::ASR;
+        setr(3, 991);
+        // 328940001 >> 991
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+
+        setr(1, -83885328);
+        setr(3, 5);
+        // -83885328 >> 5
+        exec(data);
+        CHECK(getr(1) == 4292345879);
+        CHECK(!psr().z());
+        CHECK(psr().n());
+    }
+
+    SECTION("ADC") {
+        alu->opcode = AluOperations::OpCode::ADC;
+        setr(3, (1u << 31) - 1);
+        Psr cpsr = psr();
+        cpsr.set_c(true);
+        set_psr(cpsr);
+        // 2147483647 + 328940001 + 1
+        exec(data);
+        CHECK(getr(1) == 2476423649);
+        CHECK(psr().v());
+        CHECK(psr().n());
+        CHECK(!psr().c());
+
+        setr(3, -328940001);
+        setr(1, 328940001);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("SBC") {
+        alu->opcode = AluOperations::OpCode::SBC;
+        setr(3, -((1u << 31) - 1));
+
+        Psr cpsr = psr();
+        cpsr.set_c(false);
+        set_psr(cpsr);
+
+        // 328940001 - -2147483647 - 1
+        exec(data);
+        CHECK(getr(1) == 2476423647);
+        CHECK(psr().v());
+        CHECK(psr().n());
+        CHECK(!psr().c());
+
+        setr(1, -34892);
+        setr(3, -34893);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("ROR") {
+        setr(3, 993);
+        alu->opcode = AluOperations::OpCode::ROR;
+        // 328940001 ROR 993
+        exec(data);
+        CHECK(getr(1) == 2311953648);
+        CHECK(psr().n());
+        CHECK(psr().c());
+
+        setr(1, 0);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("TST") {
+        alu->opcode = AluOperations::OpCode::TST;
+        // 328940001 & -991
+        exec(data);
+        // no change
+        CHECK(getr(1) == 328940001);
+
+        setr(3, 0);
+        CHECK(!psr().z());
+        // zero
+        exec(data);
+        CHECK(getr(1) == 328940001);
+        CHECK(psr().z());
+    }
+
+    SECTION("NEG") {
+        alu->opcode = AluOperations::OpCode::NEG;
+        // -(-991)
+        exec(data);
+        CHECK(getr(1) == 991);
+
+        setr(3, 0);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("CMP") {
+        alu->opcode = AluOperations::OpCode::CMP;
+        setr(3, -((1u << 31) - 1));
+        // 328940001 - -2147483647
+        exec(data);
+        // no change
+        CHECK(getr(1) == 328940001);
+        CHECK(psr().v());
+        CHECK(psr().n());
+        CHECK(!psr().c());
+
+        setr(1, -34892);
+        setr(3, -34892);
+        // zero
+        exec(data);
+        // no change (-34892)
+        CHECK(getr(1) == 4294932404);
+        CHECK(psr().z());
+    }
+
+    SECTION("CMN") {
+        alu->opcode = AluOperations::OpCode::CMN;
+        setr(3, (1u << 31) - 1);
+        // 2147483647 + 328940001
+        exec(data);
+        CHECK(getr(1) == 328940001);
+        CHECK(psr().v());
+        CHECK(psr().n());
+        CHECK(!psr().c());
+
+        setr(3, -328940001);
+        setr(1, 328940001);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 328940001);
+        CHECK(psr().z());
+    }
+
+    SECTION("ORR") {
+        alu->opcode = AluOperations::OpCode::ORR;
+        // 328940001 | -991
+        exec(data);
+        CHECK(getr(1) == 4294966753);
+        CHECK(psr().n());
+
+        setr(1, 0);
+        setr(3, 0);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("MUL") {
+        alu->opcode = AluOperations::OpCode::MUL;
+        // 328940001 * -991 (lower 32 bits) (-325979540991 & 0xFFFFFFFF)
+        exec(data);
+        CHECK(getr(1) == 437973505);
+
+        setr(3, 0);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("BIC") {
+        alu->opcode = AluOperations::OpCode::BIC;
+        // 328940001 & ~ -991
+        exec(data);
+        CHECK(getr(1) == 448);
+        CHECK(!psr().n());
+
+        setr(3, ~0u);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+
+    SECTION("MVN") {
+        alu->opcode = AluOperations::OpCode::MVN;
+        //~ -991
+        exec(data);
+        CHECK(getr(1) == 990);
+        CHECK(!psr().n());
+
+        setr(3, 24358);
+        // negative
+        exec(data);
+        CHECK(getr(1) == 4294942937);
+        CHECK(psr().n());
+
+        setr(3, ~0u);
+        // zero
+        exec(data);
+        CHECK(getr(1) == 0);
+        CHECK(psr().z());
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
+    InstructionData data = HiRegisterOperations{
+        .rd = 5, .rs = 15, .opcode = HiRegisterOperations::OpCode::ADD
+    };
+    HiRegisterOperations* hi = std::get_if<HiRegisterOperations>(&data);
+
+    setr(15, 3452948950);
+    setr(5, 958656720);
+
+    SECTION("ADD") {
+        exec(data);
+        CHECK(getr(5) == 116638374);
+
+        // hi + hi
+        hi->rd = 14;
+        hi->rs = 15;
+        setr(14, 42589);
+        exec(data);
+        CHECK(getr(14) == 3452991539);
+    }
+
+    SECTION("CMP") {
+        hi->opcode = HiRegisterOperations::OpCode::CMP;
+        exec(data);
+
+        // no change
+        CHECK(getr(5) == 958656720);
+        CHECK(!psr().n());
+        CHECK(!psr().c());
+        CHECK(!psr().v());
+        CHECK(!psr().z());
+
+        setr(15, 958656720);
+        // zero
+        exec(data);
+        // no change
+        CHECK(getr(5) == 958656720);
+        CHECK(psr().z());
+    }
+
+    SECTION("MOV") {
+        hi->opcode = HiRegisterOperations::OpCode::MOV;
+        exec(data);
+
+        CHECK(getr(5) == 3452948950);
+    }
+
+    SECTION("BX") {
+        hi->opcode = HiRegisterOperations::OpCode::BX;
+        hi->rs     = 10;
+
+        SECTION("Arm") {
+            setr(10, 2189988);
+            exec(data);
+            CHECK(getr(15) == 2189988);
+            // switched to arm
+            CHECK(psr().state() == State::Arm);
+        }
+
+        SECTION("Thumb") {
+            setr(10, 2189989);
+            exec(data);
+            CHECK(getr(15) == 2189988);
+
+            // switched to thumb
+            CHECK(psr().state() == State::Thumb);
+        }
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "PC Relative Load", TAG) {
+    InstructionData data = PcRelativeLoad{ .word = 0x578, .rd = 0 };
+
+    setr(15, 0x3003FD5);
+    // resetting bit 0 for 0x3003FD5, we get 0x3003FD4
+    // 0x3003FD4 + 0x578
+    bus.write_word(0x300454C, 489753492);
+
+    CHECK(getr(0) == 0);
+    exec(data);
+    CHECK(getr(0) == 489753492);
+}
+
+TEST_CASE_METHOD(CpuFixture, "Load/Store with Register Offset", TAG) {
+    InstructionData data = LoadStoreRegisterOffset{
+        .rd = 3, .rb = 0, .ro = 7, .byte = false, .load = false
+    };
+    LoadStoreRegisterOffset* load = std::get_if<LoadStoreRegisterOffset>(&data);
+
+    setr(7, 0x3003000);
+    setr(0, 0x332);
+    setr(3, 389524259);
+
+    SECTION("store") {
+        // 0x3003000 + 0x332
+        CHECK(bus.read_word(0x3003332) == 0);
+        exec(data);
+        CHECK(bus.read_word(0x3003332) == 389524259);
+
+        // byte
+        load->byte = true;
+        bus.write_word(0x3003332, 0);
+        exec(data);
+        CHECK(bus.read_word(0x3003332) == 35);
+    }
+
+    SECTION("load") {
+        load->load = true;
+        bus.write_word(0x3003332, 11123489);
+        exec(data);
+        CHECK(getr(3) == 11123489);
+
+        // byte
+        load->byte = true;
+        exec(data);
+        CHECK(getr(3) == 33);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Load/Store Sign Extended Byte/Halfword", TAG) {
+    InstructionData data = LoadStoreSignExtendedHalfword{
+        .rd = 3, .rb = 0, .ro = 7, .s = false, .h = false
+    };
+    LoadStoreSignExtendedHalfword* load =
+      std::get_if<LoadStoreSignExtendedHalfword>(&data);
+
+    setr(7, 0x3003000);
+    setr(0, 0x332);
+    setr(3, 389524259);
+
+    SECTION("SH = 00") {
+        // 0x3003000 + 0x332
+        CHECK(bus.read_word(0x3003332) == 0);
+        exec(data);
+        CHECK(bus.read_word(0x3003332) == 43811);
+    }
+
+    SECTION("SH = 01") {
+        load->h = true;
+        bus.write_word(0x3003332, 11123489);
+        exec(data);
+        CHECK(getr(3) == 47905);
+    }
+
+    SECTION("SH = 10") {
+        load->s = true;
+        bus.write_word(0x3003332, 34521594);
+        exec(data);
+        // sign extended 250 byte (0xFA)
+        CHECK(getr(3) == 4294967290);
+    }
+
+    SECTION("SH = 11") {
+        load->s = true;
+        load->h = true;
+        bus.write_word(0x3003332, 11123489);
+        // sign extended 47905 halfword (0xBB21)
+        exec(data);
+        CHECK(getr(3) == 4294949665);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Load/Store with Immediate Offset", TAG) {
+    InstructionData data = LoadStoreImmediateOffset{
+        .rd = 3, .rb = 0, .offset = 0x6E, .load = false, .byte = false
+    };
+    LoadStoreImmediateOffset* load =
+      std::get_if<LoadStoreImmediateOffset>(&data);
+
+    setr(0, 0x300666A);
+    setr(3, 389524259);
+
+    SECTION("store") {
+        // 0x30066A + 0x6E
+        CHECK(bus.read_word(0x30066D8) == 0);
+        exec(data);
+        CHECK(bus.read_word(0x30066D8) == 389524259);
+
+        // byte
+        load->byte = true;
+        bus.write_word(0x30066D8, 0);
+        exec(data);
+        CHECK(bus.read_word(0x30066D8) == 35);
+    }
+
+    SECTION("load") {
+        load->load = true;
+        bus.write_word(0x30066D8, 11123489);
+        exec(data);
+        CHECK(getr(3) == 11123489);
+
+        // byte
+        load->byte = true;
+        exec(data);
+        CHECK(getr(3) == 33);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Load/Store Halfword", TAG) {
+    InstructionData data =
+      LoadStoreHalfword{ .rd = 3, .rb = 0, .offset = 0x6E, .load = false };
+    LoadStoreHalfword* load = std::get_if<LoadStoreHalfword>(&data);
+
+    setr(0, 0x300666A);
+    setr(3, 389524259);
+
+    SECTION("store") {
+        // 0x300666A + 0x6E
+        CHECK(bus.read_word(0x30066D8) == 0);
+        exec(data);
+        CHECK(bus.read_word(0x30066D8) == 43811);
+    }
+
+    SECTION("load") {
+        load->load = true;
+        bus.write_word(0x30066D8, 11123489);
+        exec(data);
+        CHECK(getr(3) == 47905);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "SP Relative Load", TAG) {
+    InstructionData data =
+      SpRelativeLoad{ .word = 0x328, .rd = 1, .load = false };
+    SpRelativeLoad* load = std::get_if<SpRelativeLoad>(&data);
+
+    setr(1, 2349505744);
+    // sp
+    setr(13, 0x3004A8A);
+
+    SECTION("store") {
+        // 0x3004A8A + 0x328
+        CHECK(bus.read_word(0x3004DB2) == 0);
+        exec(data);
+        CHECK(bus.read_word(0x3004DB2) == 2349505744);
+    }
+
+    SECTION("load") {
+        load->load = true;
+        bus.write_word(0x3004DB2, 11123489);
+        exec(data);
+        CHECK(getr(1) == 11123489);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Load Address", TAG) {
+    InstructionData data = LoadAddress{ .word = 808, .rd = 1, .sp = false };
+    LoadAddress* load    = std::get_if<LoadAddress>(&data);
+
+    // pc
+    setr(15, 336485);
+    // sp
+    setr(13, 69879977);
+
+    SECTION("PC") {
+        exec(data);
+        CHECK(getr(1) == 337293);
+    }
+
+    SECTION("SP") {
+        load->sp = true;
+        exec(data);
+        CHECK(getr(1) == 69880785);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Add Offset to Stack Pointer", TAG) {
+    InstructionData data       = AddOffsetStackPointer{ .word = 473 };
+    AddOffsetStackPointer* add = std::get_if<AddOffsetStackPointer>(&data);
+
+    // sp
+    setr(13, 69879977);
+
+    SECTION("positive") {
+        exec(data);
+        CHECK(getr(13) == 69880450);
+    }
+
+    SECTION("negative") {
+        add->word = -473;
+        exec(data);
+        CHECK(getr(13) == 69879504);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
+    InstructionData data =
+      PushPopRegister{ .regs = 0b11010011, .pclr = false, .load = false };
+    PushPopRegister* push = std::get_if<PushPopRegister>(&data);
+
+    static constexpr uint8_t alignment = 4;
+    static constexpr uint32_t address  = 0x30015AC;
+
+    // registers = 0, 1, 4, 6, 7
+    SECTION("push (store)") {
+
+        // populate registers
+        setr(0, 237164);
+        setr(1, 679785111);
+        setr(4, 905895898);
+        setr(6, 131313333);
+        setr(7, 131);
+
+        auto checker = [this]() {
+            // address
+            CHECK(bus.read_word(address) == 237164);
+            CHECK(bus.read_word(address + alignment) == 679785111);
+            CHECK(bus.read_word(address + alignment * 2) == 905895898);
+            CHECK(bus.read_word(address + alignment * 3) == 131313333);
+            CHECK(bus.read_word(address + alignment * 4) == 131);
+        };
+
+        // set stack pointer to top of stack
+        setr(13, address + alignment * 5);
+
+        SECTION("without LR") {
+            exec(data);
+            checker();
+            CHECK(getr(13) == address);
+        }
+
+        SECTION("with LR") {
+            push->pclr = true;
+            // populate lr
+            setr(14, 999304);
+            // add another word on stack (top + 4)
+            setr(13, address + alignment * 6);
+            exec(data);
+
+            CHECK(bus.read_word(address + alignment * 5) == 999304);
+            checker();
+            CHECK(getr(13) == address);
+        }
+    }
+
+    SECTION("pop (load)") {
+        push->load = true;
+
+        // populate memory
+        bus.write_word(address, 237164);
+        bus.write_word(address + alignment, 679785111);
+        bus.write_word(address + alignment * 2, 905895898);
+        bus.write_word(address + alignment * 3, 131313333);
+        bus.write_word(address + alignment * 4, 131);
+
+        auto checker = [this]() {
+            CHECK(getr(0) == 237164);
+            CHECK(getr(1) == 679785111);
+            CHECK(getr(2) == 0);
+            CHECK(getr(3) == 0);
+            CHECK(getr(4) == 905895898);
+            CHECK(getr(5) == 0);
+            CHECK(getr(6) == 131313333);
+            CHECK(getr(7) == 131);
+
+            for (uint8_t i = 0; i < 8; i++) {
+                setr(i, 0);
+            }
+        };
+
+        // set stack pointer to bottom of stack
+        setr(13, address);
+
+        SECTION("without SP") {
+            exec(data);
+            checker();
+            CHECK(getr(13) == address + alignment * 5);
+        }
+
+        SECTION("with SP") {
+            push->pclr = true;
+            // populate next address
+            bus.write_word(address + alignment * 5, 93333912);
+            exec(data);
+
+            CHECK(getr(15) == 93333912);
+            checker();
+            CHECK(getr(13) == address + alignment * 6);
+        }
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Multiple Load/Store", TAG) {
+    InstructionData data =
+      MultipleLoad{ .regs = 0b11010101, .rb = 2, .load = false };
+    MultipleLoad* push = std::get_if<MultipleLoad>(&data);
+    // registers = 0, 1, 4, 6, 7
+
+    static constexpr uint8_t alignment = 4;
+    static constexpr uint32_t address  = 0x30015AC;
+
+    SECTION("store") {
+
+        // populate registers
+        setr(0, 237164);
+        setr(4, 905895898);
+        setr(6, 131313333);
+        setr(7, 131);
+
+        // set R2 (base) to top of stack
+        setr(2, address + alignment * 5);
+
+        exec(data);
+
+        CHECK(bus.read_word(address) == 237164);
+        CHECK(bus.read_word(address + alignment) == address + alignment * 5);
+        CHECK(bus.read_word(address + alignment * 2) == 905895898);
+        CHECK(bus.read_word(address + alignment * 3) == 131313333);
+        CHECK(bus.read_word(address + alignment * 4) == 131);
+        // write back
+        CHECK(getr(2) == address);
+    }
+
+    SECTION("load") {
+        push->load = true;
+
+        // populate memory
+        bus.write_word(address, 237164);
+        bus.write_word(address + alignment, 679785111);
+        bus.write_word(address + alignment * 2, 905895898);
+        bus.write_word(address + alignment * 3, 131313333);
+        bus.write_word(address + alignment * 4, 131);
+
+        // base
+        setr(2, address);
+
+        exec(data);
+        CHECK(getr(0) == 237164);
+        CHECK(getr(1) == 0);
+        CHECK(getr(2) == address + alignment * 5); // write back
+        CHECK(getr(3) == 0);
+        CHECK(getr(4) == 905895898);
+        CHECK(getr(5) == 0);
+        CHECK(getr(6) == 131313333);
+        CHECK(getr(7) == 131);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Conditional Branch", TAG) {
+    InstructionData data =
+      ConditionalBranch{ .offset = -192, .condition = Condition::EQ };
+    ConditionalBranch* branch = std::get_if<ConditionalBranch>(&data);
+
+    setr(15, 4589344);
+
+    SECTION("z") {
+        Psr cpsr = psr();
+        // condition is false
+        exec(data);
+        CHECK(getr(15) == 4589344);
+
+        cpsr.set_z(true);
+        set_psr(cpsr);
+        // condition is true
+        exec(data);
+        CHECK(getr(15) == 4589152);
+    }
+
+    SECTION("c") {
+        branch->condition = Condition::CS;
+        Psr cpsr          = psr();
+        // condition is false
+        exec(data);
+        CHECK(getr(15) == 4589344);
+
+        cpsr.set_c(true);
+        set_psr(cpsr);
+        // condition is true
+        exec(data);
+        CHECK(getr(15) == 4589152);
+    }
+
+    SECTION("n") {
+        branch->condition = Condition::MI;
+        Psr cpsr          = psr();
+        // condition is false
+        exec(data);
+        CHECK(getr(15) == 4589344);
+
+        cpsr.set_n(true);
+        set_psr(cpsr);
+        // condition is true
+        exec(data);
+        CHECK(getr(15) == 4589152);
+    }
+
+    SECTION("v") {
+        branch->condition = Condition::VS;
+        Psr cpsr          = psr();
+        // condition is false
+        exec(data);
+        CHECK(getr(15) == 4589344);
+
+        cpsr.set_v(true);
+        set_psr(cpsr);
+        // condition is true
+        exec(data);
+        CHECK(getr(15) == 4589152);
+    }
+}
+
+TEST_CASE_METHOD(CpuFixture, "Software Interrupt", TAG) {
+    InstructionData data = SoftwareInterrupt{ .vector = 33 };
+
+    setr(15, 4492);
+    exec(data);
+    CHECK(psr().raw() == psr(true).raw());
+    CHECK(getr(14) == 4490);
+    CHECK(getr(15) == 33);
+    CHECK(psr().state() == State::Arm);
+    CHECK(psr().mode() == Mode::Supervisor);
+}
+
+TEST_CASE_METHOD(CpuFixture, "Unconditional Branch", TAG) {
+    InstructionData data = UnconditionalBranch{ .offset = -920 };
+
+    setr(15, 4589344);
+    exec(data);
+    CHECK(getr(15) == 4588424);
+}
+
+TEST_CASE_METHOD(CpuFixture, "Long Branch With Link", TAG) {
+    InstructionData data = LongBranchWithLink{ .offset = 3262, .high = false };
+    LongBranchWithLink* branch = std::get_if<LongBranchWithLink>(&data);
+
+    // high
+    setr(15, 4589344);
+
+    exec(data);
+    CHECK(getr(14) == 2881312);
+
+    // low
+    branch->high = true;
+    exec(data);
+    CHECK(getr(14) == 4589343);
+    CHECK(getr(15) == 2884574);
+}

tests/cpu/thumb/instruction.cc

@@ -0,0 +1,467 @@
+#include "cpu/thumb/instruction.hh"
+#include <catch2/catch_test_macros.hpp>
+
+#define TAG "[thumb][disassembly]"
+
+using namespace matar;
+using namespace thumb;
+
+TEST_CASE("Move Shifted Register", TAG) {
+    uint16_t raw = 0b0001001101100011;
+    Instruction instruction(raw);
+    MoveShiftedRegister* lsl = nullptr;
+
+    REQUIRE((lsl = std::get_if<MoveShiftedRegister>(&instruction.data)));
+    CHECK(lsl->rd == 3);
+    CHECK(lsl->rs == 4);
+    CHECK(lsl->offset == 13);
+    CHECK(lsl->opcode == ShiftType::ASR);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "ASR R3,R4,#13");
+
+    lsl->opcode = ShiftType::LSR;
+    CHECK(instruction.disassemble() == "LSR R3,R4,#13");
+
+    lsl->opcode = ShiftType::LSL;
+    CHECK(instruction.disassemble() == "LSL R3,R4,#13");
+#endif
+}
+
+TEST_CASE("Add/Subtract", TAG) {
+    uint16_t raw = 0b0001111101001111;
+    Instruction instruction(raw);
+    AddSubtract* add = nullptr;
+
+    REQUIRE((add = std::get_if<AddSubtract>(&instruction.data)));
+    CHECK(add->rd == 7);
+    CHECK(add->rs == 1);
+    CHECK(add->offset == 5);
+    CHECK(add->opcode == AddSubtract::OpCode::SUB);
+    CHECK(add->imm == true);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "SUB R7,R1,#5");
+
+    add->imm = false;
+    CHECK(instruction.disassemble() == "SUB R7,R1,R5");
+
+    add->opcode = AddSubtract::OpCode::ADD;
+    CHECK(instruction.disassemble() == "ADD R7,R1,R5");
+#endif
+}
+
+TEST_CASE("Move/Compare/Add/Subtract Immediate", TAG) {
+    uint16_t raw = 0b0010111001011011;
+    Instruction instruction(raw);
+    MovCmpAddSubImmediate* mov = nullptr;
+
+    REQUIRE((mov = std::get_if<MovCmpAddSubImmediate>(&instruction.data)));
+    CHECK(mov->offset == 91);
+    CHECK(mov->rd == 6);
+    CHECK(mov->opcode == MovCmpAddSubImmediate::OpCode::CMP);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "CMP R6,#91");
+
+    mov->opcode = MovCmpAddSubImmediate::OpCode::ADD;
+    CHECK(instruction.disassemble() == "ADD R6,#91");
+
+    mov->opcode = MovCmpAddSubImmediate::OpCode::SUB;
+    CHECK(instruction.disassemble() == "SUB R6,#91");
+
+    mov->opcode = MovCmpAddSubImmediate::OpCode::MOV;
+    CHECK(instruction.disassemble() == "MOV R6,#91");
+#endif
+}
+
+TEST_CASE("ALU Operations", TAG) {
+    uint16_t raw = 0b0100000110011111;
+    Instruction instruction(raw);
+    AluOperations* alu = nullptr;
+
+    REQUIRE((alu = std::get_if<AluOperations>(&instruction.data)));
+    CHECK(alu->rd == 7);
+    CHECK(alu->rs == 3);
+    CHECK(alu->opcode == AluOperations::OpCode::SBC);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "SBC R7,R3");
+
+#define OPCODE(op)                                                             \
+    alu->opcode = AluOperations::OpCode::op;                                   \
+    CHECK(instruction.disassemble() == #op " R7,R3");
+
+    OPCODE(AND)
+    OPCODE(EOR)
+    OPCODE(LSL)
+    OPCODE(LSR)
+    OPCODE(ASR)
+    OPCODE(ADC)
+    OPCODE(SBC)
+    OPCODE(ROR)
+    OPCODE(TST)
+    OPCODE(NEG)
+    OPCODE(CMP)
+    OPCODE(CMN)
+    OPCODE(ORR)
+    OPCODE(MUL)
+    OPCODE(BIC)
+    OPCODE(MVN)
+
+#undef OPCODE
+#endif
+}
+
+TEST_CASE("Hi Register Operations/Branch Exchange", TAG) {
+    HiRegisterOperations* hi = nullptr;
+
+    uint16_t raw = 0b0100011000011010;
+
+    SECTION("both lo") {
+        Instruction instruction(raw);
+        REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
+
+        CHECK(hi->rd == 2);
+        CHECK(hi->rs == 3);
+    }
+
+    SECTION("hi rd") {
+        raw |= 1 << 7;
+        Instruction instruction(raw);
+        REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
+
+        CHECK(hi->rd == 10);
+        CHECK(hi->rs == 3);
+    }
+
+    SECTION("hi rs") {
+        raw |= 1 << 6;
+        Instruction instruction(raw);
+        REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
+
+        CHECK(hi->rd == 2);
+        CHECK(hi->rs == 11);
+    }
+
+    if (hi)
+        CHECK(hi->opcode == HiRegisterOperations::OpCode::MOV);
+
+    SECTION("both hi") {
+        raw |= 1 << 6;
+        raw |= 1 << 7;
+        Instruction instruction(raw);
+        REQUIRE((hi = std::get_if<HiRegisterOperations>(&instruction.data)));
+
+        CHECK(hi->rd == 10);
+        CHECK(hi->rs == 11);
+        CHECK(hi->opcode == HiRegisterOperations::OpCode::MOV);
+
+#ifdef DISASSEMBLER
+        CHECK(instruction.disassemble() == "MOV R10,R11");
+
+        hi->opcode = HiRegisterOperations::OpCode::ADD;
+        CHECK(instruction.disassemble() == "ADD R10,R11");
+
+        hi->opcode = HiRegisterOperations::OpCode::CMP;
+        CHECK(instruction.disassemble() == "CMP R10,R11");
+
+        hi->opcode = HiRegisterOperations::OpCode::BX;
+        CHECK(instruction.disassemble() == "BX R11");
+#endif
+    }
+}
+
+TEST_CASE("PC Relative Load", TAG) {
+    uint16_t raw = 0b0100101011100110;
+    Instruction instruction(raw);
+    PcRelativeLoad* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<PcRelativeLoad>(&instruction.data)));
+    // 230 << 2
+    CHECK(ldr->word == 920);
+    CHECK(ldr->rd == 2);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "LDR R2,[PC,#920]");
+#endif
+}
+
+TEST_CASE("Load/Store with Register Offset", TAG) {
+    uint16_t raw = 0b0101000110011101;
+    Instruction instruction(raw);
+    LoadStoreRegisterOffset* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<LoadStoreRegisterOffset>(&instruction.data)));
+    CHECK(ldr->rd == 5);
+    CHECK(ldr->rb == 3);
+    CHECK(ldr->ro == 6);
+    CHECK(ldr->byte == false);
+    CHECK(ldr->load == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "STR R5,[R3,R6]");
+
+    ldr->byte = true;
+    CHECK(instruction.disassemble() == "STRB R5,[R3,R6]");
+
+    ldr->load = true;
+    CHECK(instruction.disassemble() == "LDRB R5,[R3,R6]");
+
+    ldr->byte = false;
+    CHECK(instruction.disassemble() == "LDR R5,[R3,R6]");
+#endif
+}
+
+TEST_CASE("Load/Store Sign-Extended Byte/Halfword", TAG) {
+    uint16_t raw = 0b0101001110011101;
+    Instruction instruction(raw);
+    LoadStoreSignExtendedHalfword* ldr = nullptr;
+
+    REQUIRE(
+      (ldr = std::get_if<LoadStoreSignExtendedHalfword>(&instruction.data)));
+    CHECK(ldr->rd == 5);
+    CHECK(ldr->rb == 3);
+    CHECK(ldr->ro == 6);
+    CHECK(ldr->s == false);
+    CHECK(ldr->h == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "STRH R5,[R3,R6]");
+
+    ldr->h = true;
+    CHECK(instruction.disassemble() == "LDRH R5,[R3,R6]");
+
+    ldr->s = true;
+    CHECK(instruction.disassemble() == "LDSH R5,[R3,R6]");
+
+    ldr->h = false;
+    CHECK(instruction.disassemble() == "LDSB R5,[R3,R6]");
+#endif
+}
+
+TEST_CASE("Load/Store with Immediate Offset", TAG) {
+    uint16_t raw = 0b0110010110011101;
+    Instruction instruction(raw);
+    LoadStoreImmediateOffset* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
+    CHECK(ldr->rd == 5);
+    CHECK(ldr->rb == 3);
+    // 22 << 4 when byte == false
+    CHECK(ldr->offset == 88);
+    CHECK(ldr->byte == false);
+    CHECK(ldr->load == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "STR R5,[R3,#88]");
+
+    ldr->load = true;
+    CHECK(instruction.disassemble() == "LDR R5,[R3,#88]");
+#endif
+
+    // byte
+    raw         = 0b0111010110011101;
+    instruction = Instruction(raw);
+
+    INFO(instruction.data.index());
+    REQUIRE((ldr = std::get_if<LoadStoreImmediateOffset>(&instruction.data)));
+    CHECK(ldr->byte == true);
+    CHECK(ldr->offset == 22);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "STRB R5,[R3,#22]");
+
+    ldr->load = true;
+    CHECK(instruction.disassemble() == "LDRB R5,[R3,#22]");
+#endif
+}
+
+TEST_CASE("Load/Store Halfword", TAG) {
+    uint16_t raw = 0b1000011010011101;
+    Instruction instruction(raw);
+    LoadStoreHalfword* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<LoadStoreHalfword>(&instruction.data)));
+    CHECK(ldr->rd == 5);
+    CHECK(ldr->rb == 3);
+    // 26 << 1
+    CHECK(ldr->offset == 52);
+    CHECK(ldr->load == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "STRH R5,[R3,#52]");
+
+    ldr->load = true;
+    CHECK(instruction.disassemble() == "LDRH R5,[R3,#52]");
+#endif
+}
+
+TEST_CASE("SP-Relative Load/Store", TAG) {
+    uint16_t raw = 0b1001010010011101;
+    Instruction instruction(raw);
+    SpRelativeLoad* ldr = nullptr;
+
+    REQUIRE((ldr = std::get_if<SpRelativeLoad>(&instruction.data)));
+    CHECK(ldr->rd == 4);
+    // 157 << 2
+    CHECK(ldr->word == 628);
+    CHECK(ldr->load == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "STR R4,[SP,#628]");
+
+    ldr->load = true;
+    CHECK(instruction.disassemble() == "LDR R4,[SP,#628]");
+#endif
+}
+
+TEST_CASE("Load Adress", TAG) {
+    uint16_t raw = 0b1010000110001111;
+    Instruction instruction(raw);
+    LoadAddress* add = nullptr;
+
+    REQUIRE((add = std::get_if<LoadAddress>(&instruction.data)));
+    // 143 << 2
+    CHECK(add->word == 572);
+    CHECK(add->rd == 1);
+    CHECK(add->sp == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "ADD R1,PC,#572");
+
+    add->sp = true;
+    CHECK(instruction.disassemble() == "ADD R1,SP,#572");
+#endif
+}
+
+TEST_CASE("Add Offset to Stack Pointer", TAG) {
+    uint16_t raw = 0b1011000000100101;
+    Instruction instruction(raw);
+    AddOffsetStackPointer* add = nullptr;
+
+    REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
+    // 37 << 2
+    CHECK(add->word == 148);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "ADD SP,#148");
+#endif
+
+    raw         = 0b1011000010100101;
+    instruction = Instruction(raw);
+
+    REQUIRE((add = std::get_if<AddOffsetStackPointer>(&instruction.data)));
+    CHECK(add->word == -148);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "ADD SP,#-148");
+#endif
+}
+
+TEST_CASE("Push/Pop Registers", TAG) {
+    uint16_t raw = 0b1011010000110101;
+    Instruction instruction(raw);
+    PushPopRegister* push = nullptr;
+
+    REQUIRE((push = std::get_if<PushPopRegister>(&instruction.data)));
+    CHECK(push->regs == 53);
+    CHECK(push->pclr == false);
+    CHECK(push->load == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "PUSH {R0,R2,R4,R5}");
+
+    push->pclr = true;
+    CHECK(instruction.disassemble() == "PUSH {R0,R2,R4,R5,LR}");
+
+    push->load = true;
+    CHECK(instruction.disassemble() == "POP {R0,R2,R4,R5,PC}");
+
+    push->pclr = false;
+    CHECK(instruction.disassemble() == "POP {R0,R2,R4,R5}");
+#endif
+}
+
+TEST_CASE("Multiple Load/Store", TAG) {
+    uint16_t raw = 0b1100011001100101;
+    Instruction instruction(raw);
+    MultipleLoad* ldm = nullptr;
+
+    REQUIRE((ldm = std::get_if<MultipleLoad>(&instruction.data)));
+    CHECK(ldm->regs == 101);
+    CHECK(ldm->rb == 6);
+    CHECK(ldm->load == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "STMIA R6!,{R0,R2,R5,R6}");
+
+    ldm->load = true;
+    CHECK(instruction.disassemble() == "LDMIA R6!,{R0,R2,R5,R6}");
+#endif
+}
+
+TEST_CASE("Conditional Branch", TAG) {
+    uint16_t raw = 0b1101100110110100;
+    Instruction instruction(raw);
+    ConditionalBranch* b = nullptr;
+
+    REQUIRE((b = std::get_if<ConditionalBranch>(&instruction.data)));
+    // (-76 << 1)
+    CHECK(b->offset == -152);
+    CHECK(b->condition == Condition::LS);
+
+#ifdef DISASSEMBLER
+    // take prefetch into account
+    // offset + 4 = -152 + 4
+    CHECK(instruction.disassemble() == "BLS #-148");
+#endif
+}
+
+TEST_CASE("SoftwareInterrupt") {
+    uint16_t raw = 0b1101111100110011;
+    Instruction instruction(raw);
+    SoftwareInterrupt* swi = nullptr;
+
+    REQUIRE((swi = std::get_if<SoftwareInterrupt>(&instruction.data)));
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "SWI 51");
+#endif
+}
+
+TEST_CASE("Unconditional Branch") {
+    uint16_t raw = 0b1110011100110011;
+    Instruction instruction(raw);
+    UnconditionalBranch* b = nullptr;
+
+    REQUIRE((b = std::get_if<UnconditionalBranch>(&instruction.data)));
+    // (2147483443 << 1)
+    REQUIRE(b->offset == -410);
+
+#ifdef DISASSEMBLER
+    // take prefetch into account
+    // offset + 4 = -410 + 4
+    CHECK(instruction.disassemble() == "B #-406");
+#endif
+}
+
+TEST_CASE("Long Branch with link") {
+    uint16_t raw = 0b1111010011101100;
+    Instruction instruction(raw);
+    LongBranchWithLink* bl = nullptr;
+
+    REQUIRE((bl = std::get_if<LongBranchWithLink>(&instruction.data)));
+    // 1260 << 1
+    CHECK(bl->offset == 2520);
+    CHECK(bl->high == false);
+
+#ifdef DISASSEMBLER
+    CHECK(instruction.disassemble() == "BL #2520");
+
+    bl->high = true;
+    CHECK(instruction.disassemble() == "BLH #2520");
+#endif
+}
+
+#undef TAG

tests/cpu/thumb/meson.build

@@ -0,0 +1,4 @@
+tests_sources += files(
+  'instruction.cc',
+  'exec.cc'
+)

tests/memory.cc

@@ -1,7 +1,7 @@
 #include "memory.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[memory]";
+#define TAG "[memory]"
 
 using namespace matar;
 
@@ -15,14 +15,18 @@ class MemFixture {
     Memory memory;
 };
 
-TEST_CASE_METHOD(MemFixture, "bios", TAG) {
+TEST_CASE("bios", TAG) {
-    memory.write(0, 0xAC);
+    std::array<uint8_t, Memory::BIOS_SIZE> bios = { 0 };
+
+    // populate bios
+    bios[0]      = 0xAC;
+    bios[0x3FFF] = 0x48;
+    bios[0x2A56] = 0x10;
+
+    Memory memory(std::move(bios), std::vector<uint8_t>(Header::HEADER_SIZE));
+
     CHECK(memory.read(0) == 0xAC);
-
-    memory.write(0x3FFF, 0x48);
     CHECK(memory.read(0x3FFF) == 0x48);
-
-    memory.write(0x2A56, 0x10);
     CHECK(memory.read(0x2A56) == 0x10);
 }
 
@@ -82,40 +86,33 @@ TEST_CASE_METHOD(MemFixture, "oam obj ram", TAG) {
 }
 
 TEST_CASE("rom", TAG) {
+    std::vector<uint8_t> rom(32 * 1024 * 1024, 0);
+
+    // populate rom
+    rom[0]         = 0xAC;
+    rom[0x1FFFFFF] = 0x48;
+    rom[0x0EF0256] = 0x10;
+
     // 32 megabyte ROM
-    Memory memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+    Memory memory(std::array<uint8_t, Memory::BIOS_SIZE>(), std::move(rom));
-                  std::vector<uint8_t>(32 * 1024 * 1024));
 
     SECTION("ROM1") {
-        memory.write(0x8000000, 0xAC);
         CHECK(memory.read(0x8000000) == 0xAC);
-
-        memory.write(0x9FFFFFF, 0x48);
         CHECK(memory.read(0x9FFFFFF) == 0x48);
-
+        CHECK(memory.read(0x8EF0256) == 0x10);
-        memory.write(0x8ef0256, 0x10);
-        CHECK(memory.read(0x8ef0256) == 0x10);
     }
 
     SECTION("ROM2") {
-        memory.write(0xA000000, 0xAC);
         CHECK(memory.read(0xA000000) == 0xAC);
-
-        memory.write(0xBFFFFFF, 0x48);
         CHECK(memory.read(0xBFFFFFF) == 0x48);
-
-        memory.write(0xAEF0256, 0x10);
         CHECK(memory.read(0xAEF0256) == 0x10);
     }
 
     SECTION("ROM3") {
-        memory.write(0xC000000, 0xAC);
         CHECK(memory.read(0xC000000) == 0xAC);
-
-        memory.write(0xDFFFFFF, 0x48);
         CHECK(memory.read(0xDFFFFFF) == 0x48);
-
-        memory.write(0xCEF0256, 0x10);
         CHECK(memory.read(0xCEF0256) == 0x10);
     }
 }
+
+#undef TAG

tests/meson.build

@@ -13,6 +13,12 @@ tests_sources = files(
 subdir('cpu')
 subdir('util')
 
+tests_cpp_args = []
+
+if get_option('disassembler')
+  tests_cpp_args += '-DDISASSEMBLER'
+endif
+
 catch2 = dependency('catch2', version: '>=3.4.0', static: true)
 catch2_tests = executable(
   'matar_tests',
@@ -21,6 +27,7 @@ catch2_tests = executable(
   link_with: tests_deps,
   include_directories: [inc, src],
   build_by_default: false,
+  cpp_args: tests_cpp_args
 )
 
 test('catch2 tests', catch2_tests)

tests/util/bits.cc

@@ -1,7 +1,7 @@
 #include "util/bits.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[util][bits]";
+#define TAG "[util][bits]"
 
 TEST_CASE("8 bits", TAG) {
     uint8_t num = 45;
@@ -104,3 +104,5 @@ TEST_CASE("64 bits", TAG) {
     // 0b011010001
     CHECK(bit_range(num, 39, 47) == 209);
 }
+
+#undef TAG

tests/util/crypto.cc

@@ -1,7 +1,7 @@
 #include "util/crypto.hh"
 #include <catch2/catch_test_macros.hpp>
 
-static constexpr auto TAG = "[util][crypto]";
+#define TAG "[util][crypto]"
 
 TEST_CASE("sha256 matar", TAG) {
     std::array<uint8_t, 5> data = { 'm', 'a', 't', 'a', 'r' };
@@ -19,3 +19,5 @@ TEST_CASE("sha256 forgis", TAG) {
     CHECK(crypto::sha256(data) ==
           "cfddca2ce2673f355518cbe2df2a8522693c54723a469e8b36a4f68b90d2b759");
 }
+
+#undef TAG