io: add display unit

added rendering for modes 3,4,5
also changed how memory structuring works

Signed-off-by: Amneesh Singh <natto@weirdnatto.in>

.github/workflows/clang.yml

@@ -9,19 +9,19 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v3
-      - uses: cachix/install-nix-action@v20
+      - uses: cachix/install-nix-action@v27
         with:
           extra_nix_config: |
             auto-optimise-store = true
             experimental-features = nix-command flakes
-      - uses: cachix/cachix-action@v12
+      - uses: cachix/cachix-action@v15
         with:
           name: pain
           authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
 
 
       - name: setup
-        run: nix develop .#matar-clang -c meson setup $BUILDDIR
+        run: nix develop .#matar-clang -c meson setup $BUILDDIR -Dgdb_debug=true
 
       - name: fmt
         run: nix develop .#matar-clang -c ninja clang-format-check -C $BUILDDIR
@@ -29,8 +29,8 @@ jobs:
       - name: lint
         run: nix develop .#matar-clang -c ninja clang-tidy -C $BUILDDIR
 
-      - name: tests
-        run: nix develop .#matar-clang -c ninja test -C $BUILDDIR
-
       - name: build
         run: nix develop .#matar-clang -c ninja -C $BUILDDIR
+
+      - name: tests
+        run: nix develop .#matar-clang -c ninja test -C $BUILDDIR

.github/workflows/gcc.yml

@@ -9,22 +9,22 @@ jobs:
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v3
-      - uses: cachix/install-nix-action@v20
+      - uses: cachix/install-nix-action@v27
         with:
           extra_nix_config: |
             auto-optimise-store = true
             experimental-features = nix-command flakes
-      - uses: cachix/cachix-action@v12
+      - uses: cachix/cachix-action@v15
         with:
           name: pain
           authToken: '${{ secrets.CACHIX_AUTH_TOKEN }}'
 
 
       - name: setup
-        run: nix develop .#matar -c meson setup $BUILDDIR
+        run: nix develop .#matar -c meson setup $BUILDDIR -Dgdb_debug=true
-
-      - name: tests
-        run: nix develop .#matar -c ninja test -C $BUILDDIR
 
       - name: build
         run: nix develop .#matar -c ninja -C $BUILDDIR
+
+      - name: tests
+        run: nix develop .#matar -c ninja test -C $BUILDDIR

README.md

@@ -19,7 +19,63 @@ I am using LLVM's clang and libcxx as the primary toolchain.
 
 This goes without saying but using a different toolchain to compile these libraries before linking probably won't work.
 
+# Status
+- [x] CPU
+
+  - [x] Arm
+    - [x] Dissassembler
+    - [x] Execution
+
+  - [x] Thumb
+    - [x] Dissassembler
+    - [x] Execution
+    
+- [ ] Bus
+  - [x] Cycle counting with CPU
+  - [x] Reading memory
+  - [x] Writing memory
+  
+- [ ] Scheduler (maybe?)
+  - [ ] Sync PPU and CPU
+  - [ ] Sync APU and CPU
+  - [ ] Sync other stuff
+
+- [ ] I/O
+  - [ ] PPU
+  - [ ] APU
+  - [ ] Timers
+  - [ ] DMA
+  - [ ] Keypad
+
+- Debugging
+  - [x] GDB Remote Serial Protocol support
+  
+- Misc
+  - [ ] Save/Load states
+  - [x] Header Parsing
+
+- Internal utilities
+  - [x] Bit manipulation
+  - [x] A global logger
+  - [x] TCP Server (for GDB RSP)
+  - [x] SHA256 hash (why? idk)
+
+## Available unit tests so far
+- CPU
+  - Arm
+    - Disassembler
+    - Execution
+  - Thumb
+    - Disassembler
+    - Execution
+- Bus
+  - Memory read/writes
+  - Cycle Counting
+- Some internal utility tests (idk why)
+  
+
 -----
 
 # LOG
 - June 11, 2024: After almost an year, I have come back to this silly abandoned project, will probably complete it soon.
+- June 16, 2024: I ought to complete this soon

apps/target/main.cc

@@ -1,8 +1,8 @@
 #include "bus.hh"
 #include "cpu/cpu.hh"
-#include "memory.hh"
 #include "util/loglevel.hh"
 #include <array>
+#include <chrono>
 #include <cstdlib>
 #include <fstream>
 #include <iostream>
@@ -15,7 +15,7 @@
 int
 main(int argc, const char* argv[]) {
     std::vector<uint8_t> rom;
-    std::array<uint8_t, matar::Memory::BIOS_SIZE> bios = { 0 };
+    std::array<uint8_t, matar::Bus::BIOS_SIZE> bios = { 0 };
 
     auto usage = [argv]() {
         std::cerr << "Usage: " << argv[0] << " <file> [-b <bios>]" << std::endl;
@@ -65,7 +65,7 @@ main(int argc, const char* argv[]) {
         ifile.seekg(0, std::ios::end);
         bios_size = ifile.tellg();
 
-        if (bios_size != matar::Memory::BIOS_SIZE) {
+        if (bios_size != matar::Bus::BIOS_SIZE) {
             throw std::ios::failure("BIOS file has invalid size",
                                     std::error_code());
         }
@@ -87,12 +87,14 @@ main(int argc, const char* argv[]) {
     matar::set_log_level(matar::LogLevel::Debug);
 
     try {
-        matar::Memory memory(std::move(bios), std::move(rom));
+        std::shared_ptr<matar::Bus> bus =
-        matar::Bus bus(memory);
+          matar::Bus::init(std::move(bios), std::move(rom));
+
         matar::Cpu cpu(bus);
+
         while (true) {
             cpu.step();
-            std::this_thread::sleep_for(std::chrono::seconds(1));
+            //    std::this_thread::sleep_for(std::chrono::milliseconds(10));
         }
     } catch (const std::exception& e) {
         std::cerr << "Exception: " << e.what() << std::endl;

include/bus.hh

@@ -1,13 +1,63 @@
 #pragma once
 
-#include "memory.hh"
+#include "header.hh"
 #include "io/io.hh"
+#include "memory.hh"
 #include <memory>
+#include <vector>
 
 namespace matar {
+enum CpuAccess {
+    Sequential,
+    NonSequential
+};
+
+enum CpuAccessWidth {
+    Word,
+    Halfword,
+    Byte
+};
+
 class Bus {
+  private:
+    struct Private {
+        explicit Private() = default;
+    };
+
   public:
-    Bus(const Memory& memory);
+    static constexpr uint32_t BIOS_SIZE = 1024 * 16;
+
+    Bus(Private, std::array<uint8_t, BIOS_SIZE>&&, std::vector<uint8_t>&&);
+
+    static std::shared_ptr<Bus> init(std::array<uint8_t, BIOS_SIZE>&&,
+                                     std::vector<uint8_t>&&);
+
+    uint8_t read_byte(uint32_t address, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
+        return read_byte(address);
+    };
+    void write_byte(uint32_t address, uint8_t byte, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Byte>(address, access);
+        write_byte(address, byte);
+    };
+
+    uint16_t read_halfword(uint32_t address, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
+        return read_halfword(address);
+    }
+    void write_halfword(uint32_t address, uint16_t halfword, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Halfword>(address, access);
+        write_halfword(address, halfword);
+    }
+
+    uint32_t read_word(uint32_t address, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Word>(address, access);
+        return read_word(address);
+    }
+    void write_word(uint32_t address, uint32_t word, CpuAccess access) {
+        add_cpu_cycles<CpuAccessWidth::Word>(address, access);
+        write_word(address, word);
+    }
 
     uint8_t read_byte(uint32_t address);
     void write_byte(uint32_t address, uint8_t byte);
@@ -18,8 +68,44 @@ class Bus {
     uint32_t read_word(uint32_t address);
     void write_word(uint32_t address, uint32_t word);
 
+    // not sure what else to do?
+    void internal_cycle() { cycles++; }
+    uint32_t get_cycles() { return cycles; }
+
   private:
-    IoDevices io;
+    template<CpuAccessWidth W>
-    std::shared_ptr<Memory> memory;
+    void add_cpu_cycles(uint32_t address, CpuAccess access) {
+        auto cc = cycle_map[address >> 24 & 0xF];
+        if constexpr (W == CpuAccessWidth::Word) {
+            cycles += (access == CpuAccess::Sequential ? cc.s32 : cc.n32);
+        } else {
+            cycles += (access == CpuAccess::Sequential ? cc.s16 : cc.n16);
+        }
+    }
+
+    template<typename T>
+    T read(uint32_t address) const;
+
+    template<typename T>
+    void write(uint32_t address, T value);
+
+    uint32_t cycles = 0;
+    struct cycle_count {
+        uint8_t n16; // non sequential 8/16 bit width access
+        uint8_t n32; // non sequential 32 bit width access
+        uint8_t s16; // seuquential 8/16 bit width access
+        uint8_t s32; // sequential 32 bit width access
+    };
+    std::array<cycle_count, 0x10> cycle_map;
+    static constexpr decltype(cycle_map) init_cycle_count();
+
+    std::unique_ptr<IoDevices> io;
+    Memory<BIOS_SIZE> bios     = {};
+    Memory<0x40000> board_wram = {};
+    Memory<0x80000> chip_wram  = {};
+    Memory<> rom;
+
+    Header header;
+    void parse_header();
 };
 }

include/cpu/alu.hh

@@ -49,4 +49,7 @@ add(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c = 0);
 
 uint32_t
 sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c);
+
+uint8_t
+multiplier_array_cycles(uint32_t x, bool zeroes_only = false);
 }

include/cpu/cpu.hh

@@ -4,17 +4,39 @@
 #include "bus.hh"
 #include "cpu/psr.hh"
 #include "thumb/instruction.hh"
-
 #include <cstdint>
+#include <memory>
+
+#ifdef GDB_DEBUG
+#include <unordered_set>
+#endif
 
 namespace matar {
+
+#ifdef GDB_DEBUG
+class GdbRsp;
+#endif
+
 class Cpu {
   public:
-    Cpu(const Bus& bus) noexcept;
+    Cpu(std::shared_ptr<Bus> bus) noexcept;
 
     void step();
     void chg_mode(const Mode to);
 
+    void exec(arm::Instruction& instruction);
+    void exec(thumb::Instruction& instruction);
+
+#ifdef GDB_DEBUG
+    bool breakpoint_reached() {
+        if (breakpoints.contains(pc - 2 * (cpsr.state() == State::Arm
+                                             ? arm::INSTRUCTION_SIZE
+                                             : thumb::INSTRUCTION_SIZE))) {
+            return true;
+        }
+        return false;
+    }
+#endif
   private:
     friend void arm::Instruction::exec(Cpu& cpu);
     friend void thumb::Instruction::exec(Cpu& cpu);
@@ -29,10 +51,10 @@ class Cpu {
     static constexpr uint8_t GPR_OLD_FIRST = 8;
 
     std::shared_ptr<Bus> bus;
-    std::array<uint32_t, GPR_COUNT> gpr; // general purpose registers
+    std::array<uint32_t, GPR_COUNT> gpr = {}; // general purpose registers
 
-    Psr cpsr; // current program status register
+    Psr cpsr = {}; // current program status register
-    Psr spsr; // status program status register
+    Psr spsr = {}; // status program status register
 
     static constexpr uint8_t SP_INDEX = 13;
     static_assert(SP_INDEX < GPR_COUNT);
@@ -55,7 +77,7 @@ class Cpu {
 
         // visible registers before the mode switch
         std::array<uint32_t, GPR_COUNT - GPR_OLD_FIRST - 1> old;
-    } gpr_banked; // banked general purpose registers
+    } gpr_banked = {}; // banked general purpose registers
 
     struct {
         Psr fiq;
@@ -63,8 +85,38 @@ class Cpu {
         Psr abt;
         Psr irq;
         Psr und;
-    } spsr_banked; // banked saved program status registers
+    } spsr_banked = {}; // banked saved program status registers
 
-    bool is_flushed;
+    void internal_cycle() { bus->internal_cycle(); }
+
+    // whether read is going to be sequential or not
+    CpuAccess next_access = CpuAccess::Sequential;
+
+    // raw instructions in the pipeline
+    std::array<uint32_t, 2> opcodes = {};
+
+    void advance_pc_arm();
+    void advance_pc_thumb();
+
+    template<State S>
+    void flush_pipeline() {
+        if constexpr (S == State::Arm) {
+            opcodes[0] = bus->read_word(pc, CpuAccess::NonSequential);
+            advance_pc_arm();
+            opcodes[1] = bus->read_word(pc, CpuAccess::Sequential);
+            advance_pc_arm();
+        } else {
+            opcodes[0] = bus->read_halfword(pc, CpuAccess::NonSequential);
+            advance_pc_thumb();
+            opcodes[1] = bus->read_halfword(pc, CpuAccess::Sequential);
+            advance_pc_thumb();
+        }
+        next_access = CpuAccess::Sequential;
+    }
+
+#ifdef GDB_DEBUG
+    friend class GdbRsp;
+    std::unordered_set<uint32_t> breakpoints = {};
+#endif
 };
 }

include/cpu/psr.hh

@@ -71,7 +71,7 @@ stringify(Condition cond) {
 
 class Psr {
   public:
-    // clear the reserved bits i.e, [8:27]
+    Psr() = default;
     Psr(uint32_t raw);
 
     uint32_t raw() const;

include/cpu/thumb/instruction.hh

@@ -251,7 +251,7 @@ struct UnconditionalBranch {
 
 struct LongBranchWithLink {
     uint16_t offset;
-    bool high;
+    bool low;
 };
 
 using InstructionData = std::variant<MoveShiftedRegister,

include/io/display/display.hh

@@ -0,0 +1,159 @@
+#include "memory.hh"
+#include <array>
+#include <bit>
+#include <cstdint>
+#include <sys/types.h>
+
+// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
+namespace matar {
+namespace display {
+static constexpr int LCD_WIDTH = 240;
+
+// there are 5 modes
+static constexpr uint N_MODES = 6;
+// there are 4 backgrounds that can be layered depending on mode
+// there is also 1 object layer
+static constexpr uint N_BACKGROUNDS = 4;
+
+static constexpr uint32_t PRAM_START = 0x5000000;
+static constexpr uint32_t VRAM_START = 0x6000000;
+static constexpr uint32_t OAM_START  = 0x7000000;
+
+template<typename T, typename = std::enable_if_t<std::is_arithmetic_v<T>>>
+struct Point {
+    T x;
+    T y;
+};
+
+struct Color {
+  public:
+    Color(uint16_t raw)
+      : red(raw & 0b11111)
+      , green(raw >> 5 & 0b11111)
+      , blue(raw >> 10 & 0b11111) {}
+
+    uint16_t read() const {
+        return (red & 0b11111) | ((green << 5) & 0b11111) |
+               ((blue << 10) & 0b11111);
+    }
+
+  private:
+    uint8_t red;
+    uint8_t green;
+    uint8_t blue;
+};
+
+struct DisplayControl {
+    struct {
+        uint8_t mode : 3;
+        int : 1; // unused
+        bool frame_select_1 : 1;
+        bool hblank_free_interval : 1;
+        bool obj_character_vram_mapping : 1;
+        bool forced_blank : 1;
+        bool screen_display_0 : 1;
+        bool screen_display_1 : 1;
+        bool screen_display_2 : 1;
+        bool screen_display_3 : 1;
+        bool screen_display_obj : 1;
+        bool window_display_0 : 1;
+        bool window_display_1 : 1;
+        bool obj_window_display : 1;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value); };
+    void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
+};
+
+struct DisplayStatus {
+    struct {
+        bool vblank_flag : 1;
+        bool hblank_flag : 1;
+        bool vcounter_flag : 1;
+        bool vblank_irq_enable : 1;
+        bool hblank_irq_enable : 1;
+        bool vcounter_irq_enable : 1;
+        int : 2; // unused
+        uint8_t vcount_setting : 8;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value); };
+    void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
+};
+
+struct BackgroundControl {
+    struct {
+        uint8_t priority : 2;
+        uint8_t character_base_block : 2;
+        int : 2; // unused
+        bool mosaic : 1;
+        bool colors256 : 1;
+        uint8_t screen_base_block : 5;
+        bool bg_2_3_wraparound : 1;
+        uint8_t screen_size : 2;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value); };
+    void write(uint16_t raw) { value = std::bit_cast<decltype(value)>(raw); };
+};
+
+struct RotationScaling {
+    // these are all 16 bit signed "fixed point" floats
+    // shifted by 8
+    int16_t a;
+    int16_t b;
+    int16_t c;
+    int16_t d;
+
+    // following points have 28 bit signed "fixed point" floats as coords
+    // shifted by 8
+    Point<int32_t> ref;
+
+  private:
+    Point<int32_t> internal [[maybe_unused]]
+    ;
+};
+
+struct Display {
+  public:
+    using u16 = uint16_t;
+
+    Memory<0x400> pram;
+    Memory<0x18000> vram;
+    Memory<0x400> oam;
+
+    DisplayControl lcd_control;
+    DisplayStatus general_lcd_status;
+    u16 vertical_counter;
+    BackgroundControl bg_control[4];
+    Point<u16> bg0_offset;
+    Point<u16> bg1_offset;
+    Point<u16> bg2_offset;
+    Point<u16> bg3_offset;
+    RotationScaling bg2_rot_scale;
+    RotationScaling bg3_rot_scale;
+    u16 win0_horizontal_dimensions;
+    u16 win1_horizontal_dimensions;
+    u16 win0_vertical_dimensions;
+    u16 win1_vertical_dimensions;
+    u16 inside_win_0_1;
+    u16 outside_win;
+    u16 mosaic_size;
+    u16 color_special_effects_selection;
+    u16 alpha_blending_coefficients;
+    u16 brightness_coefficient;
+
+  private:
+    // 1 color is 16 bits in ARGB555 format
+    std::array<std::array<uint16_t, LCD_WIDTH>, N_BACKGROUNDS> scanline_buffers;
+
+    template<int MODE,
+             typename = std::enable_if_t<MODE == 3 || MODE == 4 || MODE == 5>>
+    void render_bitmap_mode();
+
+    template<int LAYER, typename = std::enable_if_t<LAYER >= 0 && LAYER <= 3>>
+    void render_text_layer();
+};
+}
+}
+// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

include/io/dma.hh

@@ -0,0 +1,39 @@
+#include <bit>
+#include <cstdint>
+
+namespace matar {
+// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
+struct DmaControl {
+    struct {
+        int : 4; // this is supposed to be 5 bits, however, to align the struct
+                 // to 16 bits, we will adjust for the first LSB in the
+                 // read/write
+        uint8_t dst_adjustment : 2;
+        uint8_t src_adjustment : 2;
+        bool repeat : 1;
+        bool transfer_32 : 1;
+        int : 1;
+        uint8_t start_timing : 2;
+        bool irq_enable : 1;
+        bool enable : 1;
+    } value;
+
+    uint16_t read() const { return std::bit_cast<uint16_t>(value) << 1; };
+    void write(uint16_t raw) {
+        value = std::bit_cast<decltype(value)>(static_cast<uint16_t>(raw >> 1));
+    };
+};
+
+struct Dma {
+    using u16 = uint16_t;
+
+    struct {
+        u16 source[2];
+        u16 destination[2];
+        u16 word_count;
+        DmaControl control;
+    } channels[4];
+};
+// NOLINTEND(cppcoreguidelines-avoid-c-arrays)
+
+}

include/io/io.hh

@@ -1,11 +1,18 @@
 #pragma once
-#include "lcd.hh"
+
+#include "display/display.hh"
+#include "dma.hh"
 #include "sound.hh"
 #include <cstdint>
+#include <memory>
 
 namespace matar {
+class Bus; // forward declaration
+
 class IoDevices {
   public:
+    IoDevices(std::weak_ptr<Bus>);
+
     uint8_t read_byte(uint32_t) const;
     void write_byte(uint32_t, uint8_t);
 
@@ -26,7 +33,11 @@ class IoDevices {
         bool low_power_mode;
     } system = {};
 
-    struct lcd lcd     = {};
+    display::Display display = {};
-    struct sound sound = {};
+    Sound sound              = {};
+    Dma dma                  = {};
+
+    std::weak_ptr<Bus> bus;
+    friend class Bus;
 };
 }

include/io/lcd.hh

@@ -1,84 +0,0 @@
-#include <cstdint>
-
-// NOLINTBEGIN(cppcoreguidelines-avoid-c-arrays)
-
-/*
-  4000000h  2    R/W  DISPCNT   LCD Control
-  4000002h  2    R/W  -         Undocumented - Green Swap
-  4000004h  2    R/W  DISPSTAT  General LCD Status (STAT,LYC)
-  4000006h  2    R    VCOUNT    Vertical Counter (LY)
-  4000008h  2    R/W  BG0CNT    BG0 Control
-  400000Ah  2    R/W  BG1CNT    BG1 Control
-  400000Ch  2    R/W  BG2CNT    BG2 Control
-  400000Eh  2    R/W  BG3CNT    BG3 Control
-  4000010h  2    W    BG0HOFS   BG0 X-Offset
-  4000012h  2    W    BG0VOFS   BG0 Y-Offset
-  4000014h  2    W    BG1HOFS   BG1 X-Offset
-  4000016h  2    W    BG1VOFS   BG1 Y-Offset
-  4000018h  2    W    BG2HOFS   BG2 X-Offset
-  400001Ah  2    W    BG2VOFS   BG2 Y-Offset
-  400001Ch  2    W    BG3HOFS   BG3 X-Offset
-  400001Eh  2    W    BG3VOFS   BG3 Y-Offset
-  4000020h  2    W    BG2PA     BG2 Rotation/Scaling Parameter A (dx)
-  4000022h  2    W    BG2PB     BG2 Rotation/Scaling Parameter B (dmx)
-  4000024h  2    W    BG2PC     BG2 Rotation/Scaling Parameter C (dy)
-  4000026h  2    W    BG2PD     BG2 Rotation/Scaling Parameter D (dmy)
-  4000028h  4    W    BG2X      BG2 Reference Point X-Coordinate
-  400002Ch  4    W    BG2Y      BG2 Reference Point Y-Coordinate
-  4000030h  2    W    BG3PA     BG3 Rotation/Scaling Parameter A (dx)
-  4000032h  2    W    BG3PB     BG3 Rotation/Scaling Parameter B (dmx)
-  4000034h  2    W    BG3PC     BG3 Rotation/Scaling Parameter C (dy)
-  4000036h  2    W    BG3PD     BG3 Rotation/Scaling Parameter D (dmy)
-  4000038h  4    W    BG3X      BG3 Reference Point X-Coordinate
-  400003Ch  4    W    BG3Y      BG3 Reference Point Y-Coordinate
-  4000040h  2    W    WIN0H     Window 0 Horizontal Dimensions
-  4000042h  2    W    WIN1H     Window 1 Horizontal Dimensions
-  4000044h  2    W    WIN0V     Window 0 Vertical Dimensions
-  4000046h  2    W    WIN1V     Window 1 Vertical Dimensions
-  4000048h  2    R/W  WININ     Inside of Window 0 and 1
-  400004Ah  2    R/W  WINOUT    Inside of OBJ Window & Outside of Windows
-  400004Ch  2    W    MOSAIC    Mosaic Size
-  400004Eh       -    -         Not used
-  4000050h  2    R/W  BLDCNT    Color Special Effects Selection
-  4000052h  2    R/W  BLDALPHA  Alpha Blending Coefficients
-  4000054h  2    W    BLDY      Brightness (Fade-In/Out) Coefficient
-  4000056h       -    -         Not used
-*/
-
-struct lcd {
-    using u16 = uint16_t;
-
-    u16 lcd_control;
-    u16 general_lcd_status;
-    u16 vertical_counter;
-    u16 bg0_control;
-    u16 bg1_control;
-    u16 bg2_control;
-    u16 bg3_control;
-    u16 bg0_x_offset;
-    u16 bg0_y_offset;
-    u16 bg1_x_offset;
-    u16 bg1_y_offset;
-    u16 bg2_x_offset;
-    u16 bg2_y_offset;
-    u16 bg3_x_offset;
-    u16 bg3_y_offset;
-    u16 bg2_rot_scaling_parameters[4];
-    u16 bg2_reference_x[2];
-    u16 bg2_reference_y[2];
-    u16 bg3_rot_scaling_parameters[4];
-    u16 bg3_reference_x[2];
-    u16 bg3_reference_y[2];
-    u16 win0_horizontal_dimensions;
-    u16 win1_horizontal_dimensions;
-    u16 win0_vertical_dimensions;
-    u16 win1_vertical_dimensions;
-    u16 inside_win_0_1;
-    u16 outside_win;
-    u16 mosaic_size;
-    u16 color_special_effects_selection;
-    u16 alpha_blending_coefficients;
-    u16 brightness_coefficient;
-};
-
-// NOLINTEND(cppcoreguidelines-avoid-c-arrays)

include/io/sound.hh

@@ -30,7 +30,7 @@
   40000A4h  4    W    FIFO_B    Channel B FIFO, Data 0-3
 */
 
-struct sound{
+struct Sound {
     using u16 = uint16_t;
 
     // channel 1

include/memory.hh

@@ -1,58 +1,60 @@
 #pragma once
 
-#include "header.hh"
 #include <array>
 #include <cstddef>
 #include <cstdint>
-#include <unordered_map>
 #include <vector>
 
+// ill use [] instead of at because i dont want if (...) throw conditions for
+// all accesses to improve performance (?)
+
+// we are also not gonna perform bound checks, as i expect the user to handle
+// those
+
 namespace matar {
+template<std::size_t N = 0>
 class Memory {
+    // we can use either a vector or an array with this
+    using Container = std::
+      conditional_t<(N != 0), std::array<uint8_t, N>, std::vector<uint8_t>>;
+
   public:
-    static constexpr uint32_t BIOS_SIZE = 1024 * 16;
+    Memory() = default;
+    Memory(auto x)
+      : memory(x) {}
 
-    Memory(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom);
+    uint8_t read_byte(std::size_t idx) const { return memory[idx]; }
 
-    uint8_t read(uint32_t address) const;
+    void write_byte(std::size_t idx, uint8_t byte) { memory[idx] = byte; }
-    void write(uint32_t address, uint8_t byte);
+
+    uint16_t read_halfword(std::size_t idx) const {
+        return memory[idx] | memory[idx + 1] << 8;
+    }
+
+    void write_halfword(std::size_t idx, uint16_t halfword) {
+        memory[idx]     = halfword & 0xFF;
+        memory[idx + 1] = halfword >> 8 & 0xFF;
+    }
+
+    uint32_t read_word(std::size_t idx) const {
+        return memory[idx] | memory[idx + 1] << 8 | memory[idx + 2] << 16 |
+               memory[idx + 3] << 24;
+    }
+
+    void write_word(std::size_t idx, uint32_t word) {
+        memory[idx]     = word & 0xFF;
+        memory[idx + 1] = word >> 8 & 0xFF;
+        memory[idx + 2] = word >> 16 & 0xFF;
+        memory[idx + 3] = word >> 24 & 0xFF;
+    }
+
+    uint8_t& operator[](std::size_t idx) { return memory.at(idx); }
+
+    Container& data() { return memory; }
+
+    std::size_t size() const { return memory.size(); }
 
   private:
-#define MEMORY_REGION(name, start)                                             \
+    Container memory;
-    static constexpr uint32_t name##_START = start;
-
-#define DECL_MEMORY(name, ident, start, end)                                   \
-    MEMORY_REGION(name, start)                                                 \
-    std::array<uint8_t, end - start + 1> ident;
-
-    MEMORY_REGION(BIOS, 0x00000000)
-    std::array<uint8_t, BIOS_SIZE> bios;
-
-    // board working RAM
-    DECL_MEMORY(BOARD_WRAM, board_wram, 0x02000000, 0x0203FFFF)
-
-    // chip working RAM
-    DECL_MEMORY(CHIP_WRAM, chip_wram, 0x03000000, 0x03007FFF)
-
-    // palette RAM
-    DECL_MEMORY(PALETTE_RAM, palette_ram, 0x05000000, 0x050003FF)
-
-    // video RAM
-    DECL_MEMORY(VRAM, vram, 0x06000000, 0x06017FFF)
-
-    // OAM OBJ attributes
-    DECL_MEMORY(OAM_OBJ_ATTR, oam_obj_attr, 0x07000000, 0x070003FF)
-
-#undef DECL_MEMORY
-
-    MEMORY_REGION(ROM_0, 0x08000000)
-    MEMORY_REGION(ROM_1, 0x0A000000)
-    MEMORY_REGION(ROM_2, 0x0C000000)
-
-#undef MEMORY_REGION
-    std::unordered_map<uint32_t, uint8_t> invalid_mem;
-    std::vector<uint8_t> rom;
-    Header header;
-    void parse_header();
 };
 }

include/meson.build

@@ -1,5 +1,4 @@
 headers = files(
-  'memory.hh',
   'bus.hh',
   'header.hh',
 )
@@ -10,4 +9,4 @@ subdir('cpu')
 subdir('util')
 subdir('io')
 
-install_headers(headers, subdir: meson.project_name(), preserve_path: true)
+install_headers(headers, subdir: meson.project_name(), preserve_path: true)

meson.build

@@ -7,8 +7,18 @@ project('matar', 'cpp',
                      'cpp_std=c++23',
                      'default_library=static'])
 
+lib_cpp_args = []
 compiler = meson.get_compiler('cpp')
 
+if get_option('disassembler')
+  lib_cpp_args += '-DDISASSEMBLER'
+endif
+
+if get_option('gdb_debug')
+  lib_cpp_args += '-DGDB_DEBUG'
+endif
+
+
 subdir('include')
 subdir('src')
 subdir('apps')

meson.options

@@ -1,2 +1,3 @@
 option('tests', type : 'boolean', value : true, description: 'enable tests')
 option('disassembler', type: 'boolean', value: true, description: 'enable disassembler')
+option('gdb_debug', type: 'boolean', value: false, description: 'enable GDB RSP server')

src/bus.cc

@@ -1,31 +1,212 @@
 #include "bus.hh"
+#include "io/io.hh"
+#include "util/crypto.hh"
 #include "util/log.hh"
-#include <memory>
 
 namespace matar {
 
+// Constants
+#define MEMORY(AREA, start)                                                    \
+    static constexpr uint32_t AREA##_START = start;                            \
+    static constexpr uint8_t AREA##_REGION = (AREA##_START >> 24) & 0xFF;
+
+MEMORY(BIOS, 0x0000000);
+MEMORY(BOARD_WRAM, 0x2000000);
+MEMORY(CHIP_WRAM, 0x3000000);
+MEMORY(PRAM, display::PRAM_START);
+MEMORY(VRAM, display::VRAM_START);
+MEMORY(OAM, display::OAM_START);
+MEMORY(ROM_0, 0x8000000);
+MEMORY(ROM_1, 0xA000000);
+MEMORY(ROM_2, 0xC000000);
 static constexpr uint32_t IO_START = 0x4000000;
 static constexpr uint32_t IO_END   = 0x40003FE;
 
-Bus::Bus(const Memory& memory)
+#undef MEMORY
-  : memory(std::make_shared<Memory>(memory)) {}
+
+Bus::Bus(Private,
+         std::array<uint8_t, BIOS_SIZE>&& bios,
+         std::vector<uint8_t>&& rom)
+  : cycle_map(init_cycle_count())
+  , bios(std::move(bios))
+  , rom(std::move(rom)) {
+    std::string bios_hash = crypto::sha256(this->bios.data());
+    static constexpr std::string_view expected_hash =
+      "fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
+
+    if (bios_hash != expected_hash) {
+        glogger.warn("BIOS hash failed to match, run at your own risk"
+                     "\nExpected : {} "
+                     "\nGot      : {}",
+                     expected_hash,
+                     bios_hash);
+    }
+
+    parse_header();
+
+    glogger.info("Memory successfully initialised");
+    glogger.info("Cartridge Title: {}", header.title);
+};
+
+std::shared_ptr<Bus>
+Bus::init(std::array<uint8_t, BIOS_SIZE>&& bios, std::vector<uint8_t>&& rom) {
+    auto self =
+      std::make_shared<Bus>(Private(), std::move(bios), std::move(rom));
+    self->io = std::make_unique<IoDevices>(self);
+    return self;
+}
+
+constexpr decltype(Bus::cycle_map)
+Bus::init_cycle_count() {
+    /*
+      Region        Bus   Read      Write     Cycles
+      BIOS ROM      32    8/16/32   -         1/1/1
+      Work RAM 32K  32    8/16/32   8/16/32   1/1/1
+      I/O           32    8/16/32   8/16/32   1/1/1
+      OAM           32    8/16/32   16/32     1/1/1 *
+      Work RAM 256K 16    8/16/32   8/16/32   3/3/6 **
+      Palette RAM   16    8/16/32   16/32     1/1/2 *
+      VRAM          16    8/16/32   16/32     1/1/2 *
+      GamePak ROM   16    8/16/32   -         5/5/8 **|***
+      GamePak Flash 16    8/16/32   16/32     5/5/8 **|***
+      GamePak SRAM  8     8         8         5     **
+
+    Timing Notes:
+
+      *   Plus 1 cycle if GBA accesses video memory at the same time.
+      **  Default waitstate settings, see System Control chapter.
+      *** Separate timings for sequential, and non-sequential accesses.
+      One cycle equals approx. 59.59ns (ie. 16.78MHz clock).
+    */
+
+    decltype(cycle_map) map;
+    map.fill({ 1, 1, 1, 1 });
+
+    /* used fill instead of this
+    map[BIOS_REGION]      = { 1, 1, 1, 1 };
+    map[CHIP_WRAM_REGION] = { 1, 1, 1, 1 };
+    map[IO_REGION]        = { 1, 1, 1, 1 };
+    map[OAM_REGION]       = { 1, 1, 1, 1 };
+    */
+    map[BOARD_WRAM_REGION] = { .n16 = 3, .n32 = 6, .s16 = 3, .s32 = 6 };
+    map[PRAM_REGION]       = { .n16 = 1, .n32 = 2, .s16 = 1, .s32 = 2 };
+    map[VRAM_REGION]       = { .n16 = 1, .n32 = 2, .s16 = 1, .s32 = 2 };
+    // TODO: GamePak access cycles
+
+    return map;
+}
+
+template<typename T>
+T
+Bus::read(uint32_t address) const {
+
+    // this is cleaned than std::enable_if
+    static_assert(std::is_same_v<T, uint8_t> || std::is_same_v<T, uint16_t> ||
+                    std::is_same_v<T, uint32_t>,
+                  "Can only read uint8_t, uin16_t or uint32_t");
+
+    constexpr int N = std::is_same_v<T, uint8_t>    ? 1
+                      : std::is_same_v<T, uint16_t> ? 2
+                      : std::is_same_v<T, uint32_t> ? 4
+                                                    : 0;
+
+    switch (address >> 24 & 0xF) {
+#define MATCHES(AREA, area)                                                    \
+    case AREA##_REGION: {                                                      \
+        uint32_t i = address - AREA##_START;                                   \
+        if (i > area.size() - N)                                               \
+            break;                                                             \
+        if constexpr (std::is_same_v<T, uint8_t>)                              \
+            return area.read_byte(i);                                          \
+        else if constexpr (std::is_same_v<T, uint16_t>)                        \
+            return area.read_halfword(i);                                      \
+        else if constexpr (std::is_same_v<T, uint32_t>)                        \
+            return area.read_word(i);                                          \
+    }
+
+#define MATCHES_PAK(AREA, area)                                                \
+    case AREA##_REGION + 1:                                                    \
+        MATCHES(AREA, area)
+
+        MATCHES(BIOS, bios)
+        MATCHES(BOARD_WRAM, board_wram)
+        MATCHES(CHIP_WRAM, chip_wram)
+        MATCHES(PRAM, io->display.pram)
+        MATCHES(VRAM, io->display.vram)
+        MATCHES(OAM, io->display.oam)
+
+        MATCHES_PAK(ROM_0, rom)
+        MATCHES_PAK(ROM_1, rom)
+        MATCHES_PAK(ROM_2, rom)
+#undef MATCHES_PAK
+#undef MATCHES
+    }
+
+    glogger.error("invalid memory region read at {:08x}", address);
+
+    if constexpr (std::is_same_v<T, uint8_t>)
+        return 0xFF;
+    else if constexpr (std::is_same_v<T, uint16_t>)
+        return 0xFFFF;
+    else if constexpr (std::is_same_v<T, uint32_t>)
+        return 0xFFFFFFFF;
+}
+
+template<typename T>
+void
+Bus::write(uint32_t address, T value) {
+    static_assert(std::is_same_v<T, uint8_t> || std::is_same_v<T, uint16_t> ||
+                    std::is_same_v<T, uint32_t>,
+                  "Can only write uint8_t, uin16_t or uint32_t");
+
+    constexpr int N = std::is_same_v<T, uint8_t>    ? 1
+                      : std::is_same_v<T, uint16_t> ? 2
+                      : std::is_same_v<T, uint32_t> ? 4
+                                                    : 0;
+
+    switch (address >> 24 & 0xF) {
+#define MATCHES(AREA, area)                                                    \
+    case AREA##_REGION: {                                                      \
+        uint32_t i = address - AREA##_START;                                   \
+        if (i > area.size() - N)                                               \
+            break;                                                             \
+        if constexpr (std::is_same_v<T, uint8_t>)                              \
+            area.write_byte(i, value);                                         \
+        else if constexpr (std::is_same_v<T, uint16_t>)                        \
+            area.write_halfword(i, value);                                     \
+        else if constexpr (std::is_same_v<T, uint32_t>)                        \
+            area.write_word(i, value);                                         \
+        return;                                                                \
+    }
+
+        MATCHES(BOARD_WRAM, board_wram)
+        MATCHES(CHIP_WRAM, chip_wram)
+        MATCHES(PRAM, io->display.pram)
+        MATCHES(VRAM, io->display.vram)
+        MATCHES(OAM, io->display.oam)
+
+#undef MATCHES
+    }
+
+    glogger.error("invalid memory region written at {:08x}", address);
+}
 
 uint8_t
 Bus::read_byte(uint32_t address) {
     if (address >= IO_START && address <= IO_END)
-        return io.read_byte(address);
+        return io->read_byte(address);
 
-    return memory->read(address);
+    return read<uint8_t>(address);
 }
 
 void
 Bus::write_byte(uint32_t address, uint8_t byte) {
     if (address >= IO_START && address <= IO_END) {
-        io.write_byte(address, byte);
+        io->write_byte(address, byte);
         return;
     }
 
-    memory->write(address, byte);
+    write<uint8_t>(address, byte);
 }
 
 uint16_t
@@ -34,9 +215,9 @@ Bus::read_halfword(uint32_t address) {
         glogger.warn("Reading a non aligned halfword address");
 
     if (address >= IO_START && address <= IO_END)
-        return io.read_halfword(address);
+        return io->read_halfword(address);
 
-    return read_byte(address) | read_byte(address + 1) << 8;
+    return read<uint16_t>(address);
 }
 
 void
@@ -45,12 +226,11 @@ Bus::write_halfword(uint32_t address, uint16_t halfword) {
         glogger.warn("Writing to a non aligned halfword address");
 
     if (address >= IO_START && address <= IO_END) {
-        io.write_halfword(address, halfword);
+        io->write_halfword(address, halfword);
         return;
     }
 
-    write_byte(address, halfword & 0xFF);
+    write<uint16_t>(address, halfword);
-    write_byte(address + 1, halfword >> 8 & 0xFF);
 }
 
 uint32_t
@@ -59,10 +239,9 @@ Bus::read_word(uint32_t address) {
         glogger.warn("Reading a non aligned word address");
 
     if (address >= IO_START && address <= IO_END)
-        return io.read_word(address);
+        return io->read_word(address);
 
-    return read_byte(address) | read_byte(address + 1) << 8 |
+    return read<uint32_t>(address);
-           read_byte(address + 2) << 16 | read_byte(address + 3) << 24;
 }
 
 void
@@ -71,13 +250,116 @@ Bus::write_word(uint32_t address, uint32_t word) {
         glogger.warn("Writing to a non aligned word address");
 
     if (address >= IO_START && address <= IO_END) {
-        io.write_word(address, word);
+        io->write_word(address, word);
         return;
     }
 
-    write_byte(address, word & 0xFF);
+    write<uint32_t>(address, word);
-    write_byte(address + 1, word >> 8 & 0xFF);
+}
-    write_byte(address + 2, word >> 16 & 0xFF);
+
-    write_byte(address + 3, word >> 24 & 0xFF);
+void
+Bus::parse_header() {
+    if (rom.size() < header.HEADER_SIZE) {
+        throw std::out_of_range(
+          "ROM is not large enough to even have a header");
+    }
+
+    // entrypoint
+    header.entrypoint =
+      rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
+
+    // nintendo logo
+    if (rom[0x9C] != 0x21)
+        glogger.info("HEADER: BIOS debugger bits not set to 0");
+
+    // game info
+    header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
+
+    switch (rom[0xAC]) {
+        case 'A':
+            header.unique_code = Header::UniqueCode::Old;
+            break;
+        case 'B':
+            header.unique_code = Header::UniqueCode::New;
+            break;
+        case 'C':
+            header.unique_code = Header::UniqueCode::Newer;
+            break;
+        case 'F':
+            header.unique_code = Header::UniqueCode::Famicom;
+            break;
+        case 'K':
+            header.unique_code = Header::UniqueCode::YoshiKoro;
+            break;
+        case 'P':
+            header.unique_code = Header::UniqueCode::Ereader;
+            break;
+        case 'R':
+            header.unique_code = Header::UniqueCode::Warioware;
+            break;
+        case 'U':
+            header.unique_code = Header::UniqueCode::Boktai;
+            break;
+        case 'V':
+            header.unique_code = Header::UniqueCode::DrillDozer;
+            break;
+
+        default:
+            glogger.error("HEADER: invalid unique code: {}", rom[0xAC]);
+    }
+
+    header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
+
+    switch (rom[0xAF]) {
+        case 'J':
+            header.i18n = Header::I18n::Japan;
+            break;
+        case 'P':
+            header.i18n = Header::I18n::Europe;
+            break;
+        case 'F':
+            header.i18n = Header::I18n::French;
+            break;
+        case 'S':
+            header.i18n = Header::I18n::Spanish;
+            break;
+        case 'E':
+            header.i18n = Header::I18n::Usa;
+            break;
+        case 'D':
+            header.i18n = Header::I18n::German;
+            break;
+        case 'I':
+            header.i18n = Header::I18n::Italian;
+            break;
+
+        default:
+            glogger.error("HEADER: invalid destination/language: {}",
+                          rom[0xAF]);
+    }
+
+    if (rom[0xB2] != 0x96)
+        glogger.error("HEADER: invalid fixed byte at 0xB2");
+
+    for (uint32_t i = 0xB5; i < 0xBC; i++) {
+        if (rom[i] != 0x00)
+            glogger.error("HEADER: invalid fixed bytes at 0xB5");
+    }
+
+    header.version = rom[0xBC];
+
+    // checksum
+    {
+        uint32_t i = 0xA0, chk = 0;
+        while (i <= 0xBC)
+            chk -= rom[i++];
+        chk -= 0x19;
+        chk &= 0xFF;
+
+        if (chk != rom[0xBD])
+            glogger.error("HEADER: checksum does not match");
+    }
+
+    // multiboot not required right now
 }
 }

src/cpu/alu.cc

@@ -88,4 +88,21 @@ sbc(uint32_t a, uint32_t b, bool& carry, bool& overflow, bool c) {
 
     return result & 0xFFFFFFFF;
 }
+
+uint8_t
+multiplier_array_cycles(uint32_t x, bool zeroes_only) {
+    // set zeroes_only to evaluate first condition that checks ones to false
+
+    if ((!zeroes_only && (x & 0xFFFFFF00) == 0xFFFFFF00) ||
+        (x & 0xFFFFFF00) == 0)
+        return 1;
+    if ((!zeroes_only && (x & 0xFFFF0000) == 0xFFFF0000) ||
+        (x & 0xFFFF0000) == 0)
+        return 2;
+    if ((!zeroes_only && (x & 0xFF000000) == 0xFF000000) ||
+        (x & 0xFF000000) == 0)
+        return 3;
+    return 4;
+};
+
 }

src/cpu/arm/exec.cc

@@ -1,21 +1,25 @@
+#include "bus.hh"
 #include "cpu/cpu.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
-namespace matar::arm {
+namespace matar {
 void
-Instruction::exec(Cpu& cpu) {
+Cpu::exec(arm::Instruction& instruction) {
-    if (!cpu.cpsr.condition(condition)) {
+    bool is_flushed = false;
+
+    if (!cpsr.condition(instruction.condition)) {
+        advance_pc_arm();
         return;
     }
 
-    auto pc_error = [cpu](uint8_t r) {
+    auto pc_error = [](uint8_t r) {
-        if (r == cpu.PC_INDEX)
+        if (r == PC_INDEX)
             glogger.error("Using PC (R15) as operand register");
     };
 
-    auto pc_warn = [cpu](uint8_t r) {
+    auto pc_warn = [](uint8_t r) {
-        if (r == cpu.PC_INDEX)
+        if (r == PC_INDEX)
             glogger.warn("Using PC (R15) as operand register");
     };
 
@@ -23,40 +27,69 @@ Instruction::exec(Cpu& cpu) {
 
     std::visit(
       overloaded{
-        [&cpu, pc_warn](BranchAndExchange& data) {
+        [this, pc_warn, &is_flushed](BranchAndExchange& data) {
-            uint32_t addr = cpu.gpr[data.rn];
+            /*
+              S -> reading instruction in step()
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              Total = 2S + N cycles
+                      1S done, S+N taken care of by flush_pipeline()
+            */
+
+            uint32_t addr = gpr[data.rn];
             State state   = static_cast<State>(get_bit(addr, 0));
 
             pc_warn(data.rn);
 
-            if (state != cpu.cpsr.state())
+            if (state != cpsr.state())
                 glogger.info_bold("State changed");
 
             // set state
-            cpu.cpsr.set_state(state);
+            cpsr.set_state(state);
 
             // copy to PC
-            cpu.pc = addr;
+            pc = addr;
 
             // ignore [1:0] bits for arm and 0 bit for thumb
-            rst_bit(cpu.pc, 0);
+            rst_bit(pc, 0);
 
             if (state == State::Arm)
-                rst_bit(cpu.pc, 1);
+                rst_bit(pc, 1);
 
             // PC is affected so flush the pipeline
-            cpu.is_flushed = true;
+            is_flushed = true;
         },
-        [&cpu](Branch& data) {
+        [this, &is_flushed](Branch& data) {
-            if (data.link)
+            /*
-                cpu.gpr[14] = cpu.pc - INSTRUCTION_SIZE;
+              S -> reading instruction in step()
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              Total = 2S + N cycles
+                      1S done, S+N taken care of by flush_pipeline()
+            */
 
-            cpu.pc += data.offset;
+            if (data.link)
+                gpr[14] = pc - INSTRUCTION_SIZE;
+
+            pc += data.offset;
 
             // pc is affected so flush the pipeline
-            cpu.is_flushed = true;
+            is_flushed = true;
         },
-        [&cpu, pc_error](Multiply& data) {
+        [this, pc_error](Multiply& data) {
+            /*
+              S -> reading instruction in step()
+              mI -> m internal cycles
+              I -> only when accumulating
+              let v = data at rn
+              m = 1 if bits [32:8] of v are all zero or all one
+              m = 2         [32:16]
+              m = 3         [32:24]
+              m = 4         otherwise
+
+              Total = S + mI or S + (m+1)I
+            */
+
             if (data.rd == data.rm)
                 glogger.error("rd and rm are not distinct in {}",
                               typeid(data).name());
@@ -65,16 +98,38 @@ Instruction::exec(Cpu& cpu) {
             pc_error(data.rd);
             pc_error(data.rd);
 
-            cpu.gpr[data.rd] = cpu.gpr[data.rm] * cpu.gpr[data.rs] +
+            // mI
-                               (data.acc ? cpu.gpr[data.rn] : 0);
+            for (int i = 0; i < multiplier_array_cycles(gpr[data.rs]); i++)
+                internal_cycle();
+
+            gpr[data.rd] = gpr[data.rm] * gpr[data.rs];
+
+            if (data.acc) {
+                gpr[data.rd] += gpr[data.rn];
+                // 1I
+                internal_cycle();
+            }
 
             if (data.set) {
-                cpu.cpsr.set_z(cpu.gpr[data.rd] == 0);
+                cpsr.set_z(gpr[data.rd] == 0);
-                cpu.cpsr.set_n(get_bit(cpu.gpr[data.rd], 31));
+                cpsr.set_n(get_bit(gpr[data.rd], 31));
-                cpu.cpsr.set_c(0);
+                cpsr.set_c(0);
             }
         },
-        [&cpu, pc_error](MultiplyLong& data) {
+        [this, pc_error](MultiplyLong& data) {
+            /*
+              S -> reading instruction in step()
+              (m+1)I -> m + 1 internal cycles
+              I -> only when accumulating
+              let v = data at rs
+              m = 1 if bits [32:8] of v are all zeroes (or all ones if signed)
+              m = 2         [32:16]
+              m = 3         [32:24]
+              m = 4         otherwise
+
+              Total = S + (m+1)I or S + (m+2)I
+            */
+
             if (data.rdhi == data.rdlo || data.rdhi == data.rm ||
                 data.rdlo == data.rm)
                 glogger.error("rdhi, rdlo and rm are not distinct in {}",
@@ -85,65 +140,108 @@ Instruction::exec(Cpu& cpu) {
             pc_error(data.rm);
             pc_error(data.rs);
 
+            // 1I
+            if (data.acc)
+                internal_cycle();
+
+            // m+1 internal cycles
+            for (int i = 0;
+                 i <= multiplier_array_cycles(gpr[data.rs], data.uns);
+                 i++)
+                internal_cycle();
+
             if (data.uns) {
                 auto cast = [](uint32_t x) -> uint64_t {
                     return static_cast<uint64_t>(x);
                 };
 
-                uint64_t eval =
+                uint64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
-                  cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
+                                (data.acc ? (cast(gpr[data.rdhi]) << 32) |
-                  (data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
+                                              cast(gpr[data.rdlo])
-                                cast(cpu.gpr[data.rdlo])
+                                          : 0);
-                            : 0);
 
-                cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
-                cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
 
             } else {
                 auto cast = [](uint32_t x) -> int64_t {
                     return static_cast<int64_t>(static_cast<int32_t>(x));
                 };
 
-                int64_t eval = cast(cpu.gpr[data.rm]) * cast(cpu.gpr[data.rs]) +
+                int64_t eval = cast(gpr[data.rm]) * cast(gpr[data.rs]) +
-                               (data.acc ? (cast(cpu.gpr[data.rdhi]) << 32) |
+                               (data.acc ? (cast(gpr[data.rdhi]) << 32) |
-                                             cast(cpu.gpr[data.rdlo])
+                                             cast(gpr[data.rdlo])
                                          : 0);
 
-                cpu.gpr[data.rdlo] = bit_range(eval, 0, 31);
+                gpr[data.rdlo] = bit_range(eval, 0, 31);
-                cpu.gpr[data.rdhi] = bit_range(eval, 32, 63);
+                gpr[data.rdhi] = bit_range(eval, 32, 63);
             }
 
             if (data.set) {
-                cpu.cpsr.set_z(cpu.gpr[data.rdhi] == 0 &&
+                cpsr.set_z(gpr[data.rdhi] == 0 && gpr[data.rdlo] == 0);
-                               cpu.gpr[data.rdlo] == 0);
+                cpsr.set_n(get_bit(gpr[data.rdhi], 31));
-                cpu.cpsr.set_n(get_bit(cpu.gpr[data.rdhi], 31));
+                cpsr.set_c(0);
-                cpu.cpsr.set_c(0);
+                cpsr.set_v(0);
-                cpu.cpsr.set_v(0);
             }
         },
-        [](Undefined) { glogger.warn("Undefined instruction"); },
+        [](Undefined) {
-        [&cpu, pc_error](SingleDataSwap& data) {
+            // this should be 2S + N + I, should i flush the pipeline? i
+            // dont know. TODO: study
+            glogger.warn("Undefined instruction");
+        },
+        [this, pc_error](SingleDataSwap& data) {
+            /*
+              N -> reading instruction in step()
+              N -> unrelated read
+              S -> related write
+              I -> earlier read value is written to register
+              Total = S + 2N +I
+            */
+
             pc_error(data.rm);
             pc_error(data.rn);
             pc_error(data.rd);
 
             if (data.byte) {
-                cpu.gpr[data.rd] = cpu.bus->read_byte(cpu.gpr[data.rn]);
+                gpr[data.rd] =
-                cpu.bus->write_byte(cpu.gpr[data.rn], cpu.gpr[data.rm] & 0xFF);
+                  bus->read_byte(gpr[data.rn], CpuAccess::NonSequential);
+                bus->write_byte(
+                  gpr[data.rn], gpr[data.rm] & 0xFF, CpuAccess::Sequential);
             } else {
-                cpu.gpr[data.rd] = cpu.bus->read_word(cpu.gpr[data.rn]);
+                gpr[data.rd] =
-                cpu.bus->write_word(cpu.gpr[data.rn], cpu.gpr[data.rm]);
+                  bus->read_word(gpr[data.rn], CpuAccess::NonSequential);
+                bus->write_word(
+                  gpr[data.rn], gpr[data.rm], CpuAccess::Sequential);
             }
+
+            internal_cycle();
+            // last write address is unrelated to next
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu, pc_warn, pc_error](SingleDataTransfer& data) {
+        [this, pc_warn, pc_error, &is_flushed](SingleDataTransfer& data) {
+            /*
+              Load
+              ====
+              S   -> reading instruction in step()
+              N   -> read from target
+              I   -> stored in register
+              N+S -> if PC is written - taken care of by flush_pipeline()
+              Total = S + N + I or 2S + 2N + I
+
+              Store
+              =====
+              N -> calculating memory address
+              N -> write at target
+              Total = 2N
+            */
             uint32_t offset  = 0;
-            uint32_t address = cpu.gpr[data.rn];
+            uint32_t address = gpr[data.rn];
 
             if (!data.pre && data.write)
                 glogger.warn("Write-back enabled with post-indexing in {}",
                              typeid(data).name());
 
-            if (data.rn == cpu.PC_INDEX && data.write)
+            if (data.rn == PC_INDEX && data.write)
                 glogger.warn("Write-back enabled with base register as PC {}",
                              typeid(data).name());
 
@@ -157,18 +255,18 @@ Instruction::exec(Cpu& cpu) {
             } else if (const Shift* shift = std::get_if<Shift>(&data.offset)) {
                 uint8_t amount =
                   (shift->data.immediate ? shift->data.operand
-                                         : cpu.gpr[shift->data.operand] & 0xFF);
+                                         : gpr[shift->data.operand] & 0xFF);
 
-                bool carry = cpu.cpsr.c();
+                bool carry = cpsr.c();
 
                 if (!shift->data.immediate)
                     pc_error(shift->data.operand);
                 pc_error(shift->rm);
 
-                offset = eval_shift(
+                offset =
-                  shift->data.type, cpu.gpr[shift->rm], amount, carry);
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
 
-                cpu.cpsr.set_c(carry);
+                cpsr.set_c(carry);
             }
 
             if (data.pre)
@@ -178,35 +276,63 @@ Instruction::exec(Cpu& cpu) {
             if (data.load) {
                 // byte
                 if (data.byte)
-                    cpu.gpr[data.rd] = cpu.bus->read_byte(address);
+                    gpr[data.rd] =
+                      bus->read_byte(address, CpuAccess::NonSequential);
                 // word
                 else
-                    cpu.gpr[data.rd] = cpu.bus->read_word(address);
+                    gpr[data.rd] =
+                      bus->read_word(address, CpuAccess::NonSequential);
+
+                // N + S
+                if (data.rd == PC_INDEX)
+                    is_flushed = true;
+
+                // I
+                internal_cycle();
                 // store
             } else {
                 // take PC into consideration
-                if (data.rd == cpu.PC_INDEX)
+                uint32_t value = gpr[data.rd];
-                    address += INSTRUCTION_SIZE;
+
+                if (data.rd == PC_INDEX)
+                    value += INSTRUCTION_SIZE;
 
                 // byte
                 if (data.byte)
-                    cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
+                    bus->write_byte(
+                      address, value & 0xFF, CpuAccess::NonSequential);
                 // word
                 else
-                    cpu.bus->write_word(address, cpu.gpr[data.rd]);
+                    bus->write_word(address, value, CpuAccess::NonSequential);
             }
 
             if (!data.pre)
                 address += (data.up ? offset : -offset);
 
             if (!data.pre || data.write)
-                cpu.gpr[data.rn] = address;
+                gpr[data.rn] = address;
 
-            if (data.rd == cpu.PC_INDEX && data.load)
+            // last read/write is unrelated, this will be overwriten if
-                cpu.is_flushed = true;
+            // flushed
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu, pc_warn, pc_error](HalfwordTransfer& data) {
+        [this, pc_warn, pc_error, &is_flushed](HalfwordTransfer& data) {
-            uint32_t address = cpu.gpr[data.rn];
+            /*
+              Load
+              ====
+              S   -> reading instruction in step()
+              N   -> read from target
+              I   -> stored in register
+              N+S -> if PC is written - taken care of by flush_pipeline()
+              Total = S + N + I or 2S + 2N + I
+
+              Store
+              =====
+              N -> calculating memory address
+              N -> write at target
+              Total = 2N
+            */
+            uint32_t address = gpr[data.rn];
             uint32_t offset  = 0;
 
             if (!data.pre && data.write)
@@ -222,15 +348,11 @@ Instruction::exec(Cpu& cpu) {
             // offset is register number (4 bits) when not an immediate
             if (!data.imm) {
                 pc_error(data.offset);
-                offset = cpu.gpr[data.offset];
+                offset = gpr[data.offset];
             } else {
                 offset = data.offset;
             }
 
-            // PC is always two instructions ahead
-            if (data.rn == cpu.PC_INDEX)
-                address -= 2 * INSTRUCTION_SIZE;
-
             if (data.pre)
                 address += (data.up ? offset : -offset);
 
@@ -240,62 +362,95 @@ Instruction::exec(Cpu& cpu) {
                 if (data.sign) {
                     // halfword
                     if (data.half) {
-                        cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
+                        gpr[data.rd] =
+                          bus->read_halfword(address, CpuAccess::NonSequential);
 
                         // sign extend the halfword
-                        cpu.gpr[data.rd] =
+                        gpr[data.rd] =
-                          (static_cast<int32_t>(cpu.gpr[data.rd]) << 16) >> 16;
+                          (static_cast<int32_t>(gpr[data.rd]) << 16) >> 16;
 
                         // byte
                     } else {
-                        cpu.gpr[data.rd] = cpu.bus->read_byte(address);
+                        gpr[data.rd] =
+                          bus->read_byte(address, CpuAccess::NonSequential);
 
                         // sign extend the byte
-                        cpu.gpr[data.rd] =
+                        gpr[data.rd] =
-                          (static_cast<int32_t>(cpu.gpr[data.rd]) << 24) >> 24;
+                          (static_cast<int32_t>(gpr[data.rd]) << 24) >> 24;
                     }
                     // unsigned halfword
                 } else if (data.half) {
-                    cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
+                    gpr[data.rd] =
+                      bus->read_halfword(address, CpuAccess::NonSequential);
                 }
+
+                // I
+                internal_cycle();
+
+                if (data.rd == PC_INDEX)
+                    is_flushed = true;
+
                 // store
             } else {
+                uint32_t value = gpr[data.rd];
+
                 // take PC into consideration
-                if (data.rd == cpu.PC_INDEX)
+                if (data.rd == PC_INDEX)
-                    address += INSTRUCTION_SIZE;
+                    value += INSTRUCTION_SIZE;
 
                 // halfword
                 if (data.half)
-                    cpu.bus->write_halfword(address, cpu.gpr[data.rd]);
+                    bus->write_halfword(
+                      address, value & 0xFFFF, CpuAccess::NonSequential);
             }
 
             if (!data.pre)
                 address += (data.up ? offset : -offset);
 
             if (!data.pre || data.write)
-                cpu.gpr[data.rn] = address;
+                gpr[data.rn] = address;
 
-            if (data.rd == cpu.PC_INDEX && data.load)
+            // last read/write is unrelated, this will be overwriten if
-                cpu.is_flushed = true;
+            // flushed
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu, pc_error](BlockDataTransfer& data) {
+        [this, pc_error, &is_flushed](BlockDataTransfer& data) {
+            /*
+              Load
+              ====
+              S       -> reading instruction in step()
+              N       -> unrelated read from target
+              (n-1) S -> next n - 1 related reads from target
+              I       -> stored in register
+              N+S     -> if PC is written - taken care of by
+              flush_pipeline() Total = nS + N + I or (n+1)S + 2N + I
+
+              Store
+              =====
+              N       -> calculating memory address
+              N       -> unrelated write at target
+              (n-1) S -> next n - 1 related writes
+              Total = 2N + (n-1)S
+            */
+
             static constexpr uint8_t alignment = 4; // word
 
-            uint32_t address = cpu.gpr[data.rn];
+            uint32_t address = gpr[data.rn];
-            Mode mode        = cpu.cpsr.mode();
+            Mode mode        = cpsr.mode();
-            int8_t i        = 0;
+            int8_t i         = 0;
+            CpuAccess access = CpuAccess::NonSequential;
 
             pc_error(data.rn);
 
-            if (cpu.cpsr.mode() == Mode::User && data.s) {
+            if (cpsr.mode() == Mode::User && data.s) {
                 glogger.error("Bit S is set outside priviliged modes in block "
                               "data transfer");
             }
 
             // we just change modes to load user registers
-            if ((!get_bit(data.regs, cpu.PC_INDEX) && data.s) ||
+            if ((!get_bit(data.regs, PC_INDEX) && data.s) ||
                 (!data.load && data.s)) {
-                cpu.chg_mode(Mode::User);
+                chg_mode(Mode::User);
 
                 if (data.write) {
                     glogger.error("Write-back enable for user bank registers "
@@ -308,40 +463,50 @@ Instruction::exec(Cpu& cpu) {
                 address += (data.up ? alignment : -alignment);
 
             if (data.load) {
-                if (get_bit(data.regs, cpu.PC_INDEX) && data.s && data.load) {
+                if (get_bit(data.regs, PC_INDEX)) {
-                    // current mode's cpu.spsr is already loaded when it was
+                    is_flushed = true;
+
+                    // current mode's spsr is already loaded when it was
                     // switched
-                    cpu.spsr = cpu.cpsr;
+                    if (data.s)
+                        spsr = cpsr;
                 }
 
                 if (data.up) {
-                    for (i = 0; i < cpu.GPR_COUNT; i++) {
+                    for (i = 0; i < GPR_COUNT; i++) {
                         if (get_bit(data.regs, i)) {
-                            cpu.gpr[i] = cpu.bus->read_word(address);
+                            gpr[i] = bus->read_word(address, access);
                             address += alignment;
+                            access = CpuAccess::Sequential;
                         }
                     }
                 } else {
-                    for (i = cpu.GPR_COUNT - 1; i >= 0; i--) {
+                    for (i = GPR_COUNT - 1; i >= 0; i--) {
                         if (get_bit(data.regs, i)) {
-                            cpu.gpr[i] = cpu.bus->read_word(address);
+                            gpr[i] = bus->read_word(address, access);
                             address -= alignment;
+                            access = CpuAccess::Sequential;
                         }
                     }
                 }
+
+                // I
+                internal_cycle();
             } else {
                 if (data.up) {
-                    for (i = 0; i < cpu.GPR_COUNT; i++) {
+                    for (i = 0; i < GPR_COUNT; i++) {
                         if (get_bit(data.regs, i)) {
-                            cpu.bus->write_word(address, cpu.gpr[i]);
+                            bus->write_word(address, gpr[i], access);
                             address += alignment;
+                            access = CpuAccess::Sequential;
                         }
                     }
                 } else {
-                    for (i = cpu.GPR_COUNT - 1; i >= 0; i--) {
+                    for (i = GPR_COUNT - 1; i >= 0; i--) {
                         if (get_bit(data.regs, i)) {
-                            cpu.bus->write_word(address, cpu.gpr[i]);
+                            bus->write_word(address, gpr[i], access);
                             address -= alignment;
+                            access = CpuAccess::Sequential;
                         }
                     }
                 }
@@ -352,37 +517,48 @@ Instruction::exec(Cpu& cpu) {
                 address += (data.up ? -alignment : alignment);
 
             if (!data.pre || data.write)
-                cpu.gpr[data.rn] = address;
+                gpr[data.rn] = address;
-
-            if (data.load && get_bit(data.regs, cpu.PC_INDEX))
-                cpu.is_flushed = true;
 
             // load back the original mode registers
-            cpu.chg_mode(mode);
+            chg_mode(mode);
+
+            // last read/write is unrelated, this will be overwriten if
+            // flushed
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu, pc_error](PsrTransfer& data) {
+        [this, pc_error](PsrTransfer& data) {
-            if (data.spsr && cpu.cpsr.mode() == Mode::User) {
+            /*
-                glogger.error("Accessing CPU.SPSR in User mode in {}",
+              S -> prefetched instruction in step()
+              Total = 1S cycle
+            */
+
+            if (data.spsr && cpsr.mode() == Mode::User) {
+                glogger.error("Accessing SPSR in User mode in {}",
                               typeid(data).name());
             }
 
-            Psr& psr = data.spsr ? cpu.spsr : cpu.cpsr;
+            Psr& psr = data.spsr ? spsr : cpsr;
 
             switch (data.type) {
                 case PsrTransfer::Type::Mrs:
                     pc_error(data.operand);
-                    cpu.gpr[data.operand] = psr.raw();
+                    gpr[data.operand] = psr.raw();
                     break;
                 case PsrTransfer::Type::Msr:
                     pc_error(data.operand);
 
-                    if (cpu.cpsr.mode() != Mode::User) {
+                    if (cpsr.mode() != Mode::User) {
-                        psr.set_all(cpu.gpr[data.operand]);
+                        if (!data.spsr) {
+                            Psr tmp = Psr(gpr[data.operand]);
+                            chg_mode(tmp.mode());
+                        }
+
+                        psr.set_all(gpr[data.operand]);
                     }
                     break;
                 case PsrTransfer::Type::Msr_flg:
                     uint32_t operand =
-                      (data.imm ? data.operand : cpu.gpr[data.operand]);
+                      (data.imm ? data.operand : gpr[data.operand]);
                     psr.set_n(get_bit(operand, 31));
                     psr.set_z(get_bit(operand, 30));
                     psr.set_c(get_bit(operand, 29));
@@ -390,10 +566,28 @@ Instruction::exec(Cpu& cpu) {
                     break;
             }
         },
-        [&cpu, pc_error](DataProcessing& data) {
+        [this, pc_error, &is_flushed](DataProcessing& data) {
+            /*
+              Always
+              ======
+              S -> prefetched instruction in step()
+
+              With Register specified shift
+              =============================
+              I -> internal cycle
+
+              When PC is written
+              ==================
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              S+N taken care of by flush_pipeline()
+
+              Total = S or S + I or 2S + N + I or 2S + N cycles
+            */
+
             using OpCode = DataProcessing::OpCode;
 
-            uint32_t op_1 = cpu.gpr[data.rn];
+            uint32_t op_1 = gpr[data.rn];
             uint32_t op_2 = 0;
 
             uint32_t result = 0;
@@ -404,26 +598,30 @@ Instruction::exec(Cpu& cpu) {
             } else if (const Shift* shift = std::get_if<Shift>(&data.operand)) {
                 uint8_t amount =
                   (shift->data.immediate ? shift->data.operand
-                                         : cpu.gpr[shift->data.operand] & 0xFF);
+                                         : gpr[shift->data.operand] & 0xFF);
 
-                bool carry = cpu.cpsr.c();
+                bool carry = cpsr.c();
 
                 if (!shift->data.immediate)
                     pc_error(shift->data.operand);
                 pc_error(shift->rm);
 
-                op_2 = eval_shift(
+                op_2 =
-                  shift->data.type, cpu.gpr[shift->rm], amount, carry);
+                  eval_shift(shift->data.type, gpr[shift->rm], amount, carry);
 
-                cpu.cpsr.set_c(carry);
+                cpsr.set_c(carry);
 
                 // PC is 12 bytes ahead when shifting
-                if (data.rn == cpu.PC_INDEX)
+                if (data.rn == PC_INDEX)
                     op_1 += INSTRUCTION_SIZE;
+
+                // 1I when register specified shift
+                if (!shift->data.immediate)
+                    internal_cycle();
             }
 
-            bool overflow = cpu.cpsr.v();
+            bool overflow = cpsr.v();
-            bool carry    = cpu.cpsr.c();
+            bool carry    = cpsr.c();
 
             switch (data.opcode) {
                 case OpCode::AND:
@@ -469,19 +667,19 @@ Instruction::exec(Cpu& cpu) {
                     break;
             }
 
-            auto set_conditions = [&cpu, carry, overflow, result]() {
+            auto set_conditions = [this, carry, overflow, result]() {
-                cpu.cpsr.set_c(carry);
+                cpsr.set_c(carry);
-                cpu.cpsr.set_v(overflow);
+                cpsr.set_v(overflow);
-                cpu.cpsr.set_n(get_bit(result, 31));
+                cpsr.set_n(get_bit(result, 31));
-                cpu.cpsr.set_z(result == 0);
+                cpsr.set_z(result == 0);
             };
 
             if (data.set) {
-                if (data.rd == cpu.PC_INDEX) {
+                if (data.rd == PC_INDEX) {
-                    if (cpu.cpsr.mode() == Mode::User)
+                    if (cpsr.mode() == Mode::User)
                         glogger.error("Running {} in User mode",
                                       typeid(data).name());
-                    cpu.spsr = cpu.cpsr;
+                    spsr = cpsr;
                 } else {
                     set_conditions();
                 }
@@ -491,19 +689,25 @@ Instruction::exec(Cpu& cpu) {
                 data.opcode == OpCode::CMP || data.opcode == OpCode::CMN) {
                 set_conditions();
             } else {
-                cpu.gpr[data.rd] = result;
+                gpr[data.rd] = result;
-                if (data.rd == cpu.PC_INDEX || data.opcode == OpCode::MVN)
+                if (data.rd == PC_INDEX || data.opcode == OpCode::MVN)
-                    cpu.is_flushed = true;
+                    is_flushed = true;
             }
         },
-        [&cpu](SoftwareInterrupt) {
+        [this, &is_flushed](SoftwareInterrupt) {
-            cpu.chg_mode(Mode::Supervisor);
+            chg_mode(Mode::Supervisor);
-            cpu.pc   = 0x08;
+            pc         = 0x00;
-            cpu.spsr = cpu.cpsr;
+            spsr       = cpsr;
+            is_flushed = true;
         },
         [](auto& data) {
             glogger.error("Unimplemented {} instruction", typeid(data).name());
         } },
-      data);
+      instruction.data);
+
+    if (is_flushed)
+        flush_pipeline<State::Arm>();
+    else
+        advance_pc_arm();
 }
 }

src/cpu/cpu.cc

@@ -1,19 +1,12 @@
 #include "cpu/cpu.hh"
 #include "cpu/arm/instruction.hh"
 #include "cpu/thumb/instruction.hh"
+#include "util/bits.hh"
 #include "util/log.hh"
-#include <algorithm>
-#include <cstdio>
 
 namespace matar {
-Cpu::Cpu(const Bus& bus) noexcept
+Cpu::Cpu(std::shared_ptr<Bus> bus) noexcept
-  : bus(std::make_shared<Bus>(bus))
+  : bus(bus) {
-  , gpr({ 0 })
-  , cpsr(0)
-  , spsr(0)
-  , gpr_banked({ { 0 }, { 0 }, { 0 }, { 0 }, { 0 }, { 0 } })
-  , spsr_banked({ 0, 0, 0, 0, 0 })
-  , is_flushed(false) {
     cpsr.set_mode(Mode::Supervisor);
     cpsr.set_irq_disabled(true);
     cpsr.set_fiq_disabled(true);
@@ -21,8 +14,7 @@ Cpu::Cpu(const Bus& bus) noexcept
     glogger.info("CPU successfully initialised");
 
     // PC always points to two instructions ahead
-    // PC - 2 is the instruction being executed
+    flush_pipeline<State::Arm>();
-    pc += 2 * arm::INSTRUCTION_SIZE;
 }
 
 /* change modes */
@@ -131,42 +123,50 @@ Cpu::chg_mode(const Mode to) {
 
 void
 Cpu::step() {
-    // Current instruction is two instructions behind PC
+    // halfword align
+    rst_bit(pc, 0);
     if (cpsr.state() == State::Arm) {
-        uint32_t cur_pc = pc - 2 * arm::INSTRUCTION_SIZE;
+        // word align
-        arm::Instruction instruction(bus->read_word(cur_pc));
+        rst_bit(pc, 1);
+
+        arm::Instruction instruction(opcodes[0]);
+
+        opcodes[0] = opcodes[1];
+        opcodes[1] = bus->read_word(pc, next_access);
 
 #ifdef DISASSEMBLER
-        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
+        glogger.info("0x{:08X} : {}",
+                     pc - 2 * arm::INSTRUCTION_SIZE,
+                     instruction.disassemble());
 #endif
 
-        instruction.exec(*this);
+        exec(instruction);
     } else {
-        uint32_t cur_pc = pc - 2 * thumb::INSTRUCTION_SIZE;
+        thumb::Instruction instruction(opcodes[0]);
-        thumb::Instruction instruction(bus->read_halfword(cur_pc));
+
+        opcodes[0] = opcodes[1];
+        opcodes[1] = bus->read_halfword(pc, next_access);
 
 #ifdef DISASSEMBLER
-        glogger.info("0x{:08X} : {}", cur_pc, instruction.disassemble());
+        glogger.info("0x{:08X} : {}",
+                     pc - 2 * thumb::INSTRUCTION_SIZE,
+                     instruction.disassemble());
 #endif
 
-        instruction.exec(*this);
+        exec(instruction);
-    }
-
-    // advance PC
-    {
-        size_t size = cpsr.state() == State::Arm ? arm::INSTRUCTION_SIZE
-                                                 : thumb::INSTRUCTION_SIZE;
-
-        if (is_flushed) {
-            // if flushed, do not increment the PC, instead set it to two
-            // instructions ahead to account for flushed "fetch" and "decode"
-            // instructions
-            pc += 2 * size;
-            is_flushed = false;
-        } else {
-            // if not flushed continue like normal
-            pc += size;
-        }
     }
 }
+
+void
+Cpu::advance_pc_arm() {
+    rst_bit(pc, 0);
+    rst_bit(pc, 1);
+    pc += arm::INSTRUCTION_SIZE;
+};
+
+void
+Cpu::advance_pc_thumb() {
+    rst_bit(pc, 0);
+    pc += thumb::INSTRUCTION_SIZE;
+}
 }

src/cpu/thumb/disassembler.cc

@@ -147,7 +147,7 @@ Instruction::disassemble() {
         [](LongBranchWithLink& data) {
             // duh this manual be empty for H = 0
             return std::format(
-              "BL{} #{:d}", (data.high ? "H" : ""), data.offset);
+              "BL{} #{:d}", (data.low ? "" : "H"), data.offset);
         },
         [](auto) { return std::string("unknown instruction"); } },
       data);

src/cpu/thumb/exec.cc

@@ -1,56 +1,78 @@
+#include "bus.hh"
+#include "cpu/alu.hh"
 #include "cpu/cpu.hh"
 #include "util/bits.hh"
 #include "util/log.hh"
 
-namespace matar::thumb {
+namespace matar {
 void
-Instruction::exec(Cpu& cpu) {
+Cpu::exec(thumb::Instruction& instruction) {
-    auto set_cc = [&cpu](bool c, bool v, bool n, bool z) {
+    bool is_flushed = false;
-        cpu.cpsr.set_c(c);
+    dbg(pc);
-        cpu.cpsr.set_v(v);
+
-        cpu.cpsr.set_n(n);
+    auto set_cc = [this](bool c, bool v, bool n, bool z) {
-        cpu.cpsr.set_z(z);
+        cpsr.set_c(c);
+        cpsr.set_v(v);
+        cpsr.set_n(n);
+        cpsr.set_z(z);
     };
 
+    using namespace thumb;
+
     std::visit(
       overloaded{
-        [&cpu, set_cc](MoveShiftedRegister& data) {
+        [this, set_cc](MoveShiftedRegister& data) {
+            /*
+              S -> prefetched instruction in step()
+
+              Total = S cycle
+            */
             if (data.opcode == ShiftType::ROR)
                 glogger.error("Invalid opcode in {}", typeid(data).name());
 
-            bool carry = cpu.cpsr.c();
+            bool carry = cpsr.c();
 
             uint32_t shifted =
-              eval_shift(data.opcode, cpu.gpr[data.rs], data.offset, carry);
+              eval_shift(data.opcode, gpr[data.rs], data.offset, carry);
 
-            cpu.gpr[data.rd] = shifted;
+            gpr[data.rd] = shifted;
 
-            set_cc(carry, cpu.cpsr.v(), get_bit(shifted, 31), shifted == 0);
+            set_cc(carry, cpsr.v(), get_bit(shifted, 31), shifted == 0);
         },
-        [&cpu, set_cc](AddSubtract& data) {
+        [this, set_cc](AddSubtract& data) {
+            /*
+              S -> prefetched instruction in step()
+
+              Total = S cycle
+            */
             uint32_t offset =
               data.imm ? static_cast<uint32_t>(static_cast<int8_t>(data.offset))
-                       : cpu.gpr[data.offset];
+                       : gpr[data.offset];
             uint32_t result = 0;
-            bool carry      = cpu.cpsr.c();
+            bool carry      = cpsr.c();
-            bool overflow   = cpu.cpsr.v();
+            bool overflow   = cpsr.v();
 
             switch (data.opcode) {
                 case AddSubtract::OpCode::ADD:
-                    result = add(cpu.gpr[data.rs], offset, carry, overflow);
+                    result = add(gpr[data.rs], offset, carry, overflow);
                     break;
                 case AddSubtract::OpCode::SUB:
-                    result = sub(cpu.gpr[data.rs], offset, carry, overflow);
+                    result = sub(gpr[data.rs], offset, carry, overflow);
                     break;
             }
 
-            cpu.gpr[data.rd] = result;
+            gpr[data.rd] = result;
             set_cc(carry, overflow, get_bit(result, 31), result == 0);
         },
-        [&cpu, set_cc](MovCmpAddSubImmediate& data) {
+        [this, set_cc](MovCmpAddSubImmediate& data) {
+            /*
+              S -> prefetched instruction in step()
+
+              Total = S cycle
+            */
             uint32_t result = 0;
-            bool carry      = cpu.cpsr.c();
+            bool carry      = cpsr.c();
-            bool overflow   = cpu.cpsr.v();
+            bool overflow   = cpsr.v();
 
             switch (data.opcode) {
                 case MovCmpAddSubImmediate::OpCode::MOV:
@@ -58,27 +80,44 @@ Instruction::exec(Cpu& cpu) {
                     carry  = 0;
                     break;
                 case MovCmpAddSubImmediate::OpCode::ADD:
-                    result =
+                    result = add(gpr[data.rd], data.offset, carry, overflow);
-                      add(cpu.gpr[data.rd], data.offset, carry, overflow);
                     break;
                 case MovCmpAddSubImmediate::OpCode::SUB:
                 case MovCmpAddSubImmediate::OpCode::CMP:
-                    result =
+                    result = sub(gpr[data.rd], data.offset, carry, overflow);
-                      sub(cpu.gpr[data.rd], data.offset, carry, overflow);
                     break;
             }
 
             set_cc(carry, overflow, get_bit(result, 31), result == 0);
             if (data.opcode != MovCmpAddSubImmediate::OpCode::CMP)
-                cpu.gpr[data.rd] = result;
+                gpr[data.rd] = result;
         },
-        [&cpu, set_cc](AluOperations& data) {
+        [this, set_cc](AluOperations& data) {
-            uint32_t op_1   = cpu.gpr[data.rd];
+            /*
-            uint32_t op_2   = cpu.gpr[data.rs];
+              Data Processing
+              ===============
+              S -> prefetched instruction in step()
+              I -> only when register specified shift
+              Total = S or S + I cycles
+
+              Multiply
+              ========
+              S -> reading instruction in step()
+              mI -> m internal cycles
+              let v = data at rn
+              m = 1 if bits [32:8] of v are all zero or all one
+              m = 2         [32:16]
+              m = 3         [32:24]
+              m = 4         otherwise
+
+              Total = S + mI cycles
+            */
+            uint32_t op_1   = gpr[data.rd];
+            uint32_t op_2   = gpr[data.rs];
             uint32_t result = 0;
 
-            bool carry    = cpu.cpsr.c();
+            bool carry    = cpsr.c();
-            bool overflow = cpu.cpsr.v();
+            bool overflow = cpsr.v();
 
             switch (data.opcode) {
                 case AluOperations::OpCode::AND:
@@ -90,12 +129,15 @@ Instruction::exec(Cpu& cpu) {
                     break;
                 case AluOperations::OpCode::LSL:
                     result = eval_shift(ShiftType::LSL, op_1, op_2, carry);
+                    internal_cycle();
                     break;
                 case AluOperations::OpCode::LSR:
                     result = eval_shift(ShiftType::LSR, op_1, op_2, carry);
+                    internal_cycle();
                     break;
                 case AluOperations::OpCode::ASR:
                     result = eval_shift(ShiftType::ASR, op_1, op_2, carry);
+                    internal_cycle();
                     break;
                 case AluOperations::OpCode::ADC:
                     result = add(op_1, op_2, carry, overflow, carry);
@@ -105,6 +147,7 @@ Instruction::exec(Cpu& cpu) {
                     break;
                 case AluOperations::OpCode::ROR:
                     result = eval_shift(ShiftType::ROR, op_1, op_2, carry);
+                    internal_cycle();
                     break;
                 case AluOperations::OpCode::NEG:
                     result = -op_2;
@@ -120,6 +163,9 @@ Instruction::exec(Cpu& cpu) {
                     break;
                 case AluOperations::OpCode::MUL:
                     result = op_1 * op_2;
+                    // mI cycles
+                    for (int i = 0; i < multiplier_array_cycles(op_2); i++)
+                        internal_cycle();
                     break;
                 case AluOperations::OpCode::BIC:
                     result = op_1 & ~op_2;
@@ -132,260 +178,435 @@ Instruction::exec(Cpu& cpu) {
             if (data.opcode != AluOperations::OpCode::TST &&
                 data.opcode != AluOperations::OpCode::CMP &&
                 data.opcode != AluOperations::OpCode::CMN)
-                cpu.gpr[data.rd] = result;
+                gpr[data.rd] = result;
 
             set_cc(carry, overflow, get_bit(result, 31), result == 0);
         },
-        [&cpu, set_cc](HiRegisterOperations& data) {
+        [this, set_cc, &is_flushed](HiRegisterOperations& data) {
-            uint32_t op_1 = cpu.gpr[data.rd];
+            /*
-            uint32_t op_2 = cpu.gpr[data.rs];
+              Always
+              ======
+              S -> prefetched instruction in step()
 
-            bool carry    = cpu.cpsr.c();
+              When PC is written
-            bool overflow = cpu.cpsr.v();
+              ==================
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              S+N taken care of by flush_pipeline()
+
+              Total = S or 2S + N cycles
+            */
+
+            uint32_t op_1 = gpr[data.rd];
+            uint32_t op_2 = gpr[data.rs];
+
+            bool carry    = cpsr.c();
+            bool overflow = cpsr.v();
 
             // PC is already current + 4, so dont need to do that
-            if (data.rd == cpu.PC_INDEX)
+            if (data.rd == PC_INDEX)
                 rst_bit(op_1, 0);
 
-            if (data.rs == cpu.PC_INDEX)
+            if (data.rs == PC_INDEX)
                 rst_bit(op_2, 0);
 
             switch (data.opcode) {
                 case HiRegisterOperations::OpCode::ADD: {
-                    cpu.gpr[data.rd] = add(op_1, op_2, carry, overflow);
+                    gpr[data.rd] = add(op_1, op_2, carry, overflow);
 
-                    if (data.rd == cpu.PC_INDEX)
+                    if (data.rd == PC_INDEX)
-                        cpu.is_flushed = true;
+                        is_flushed = true;
                 } break;
                 case HiRegisterOperations::OpCode::CMP: {
                     uint32_t result = sub(op_1, op_2, carry, overflow);
                     set_cc(carry, overflow, get_bit(result, 31), result == 0);
                 } break;
                 case HiRegisterOperations::OpCode::MOV: {
-                    cpu.gpr[data.rd] = op_2;
+                    gpr[data.rd] = op_2;
 
-                    if (data.rd == cpu.PC_INDEX)
+                    if (data.rd == PC_INDEX)
-                        cpu.is_flushed = true;
+                        is_flushed = true;
                 } break;
                 case HiRegisterOperations::OpCode::BX: {
                     State state = static_cast<State>(get_bit(op_2, 0));
 
-                    if (state != cpu.cpsr.state())
+                    if (state != cpsr.state())
                         glogger.info_bold("State changed");
 
                     // set state
-                    cpu.cpsr.set_state(state);
+                    cpsr.set_state(state);
 
                     // copy to PC
-                    cpu.pc = op_2;
+                    pc = op_2;
 
                     // ignore [1:0] bits for arm and 0 bit for thumb
-                    rst_bit(cpu.pc, 0);
+                    rst_bit(pc, 0);
 
                     if (state == State::Arm)
-                        rst_bit(cpu.pc, 1);
+                        rst_bit(pc, 1);
 
                     // pc is affected so flush the pipeline
-                    cpu.is_flushed = true;
+                    is_flushed = true;
                 } break;
             }
         },
-        [&cpu](PcRelativeLoad& data) {
+        [this](PcRelativeLoad& data) {
-            uint32_t pc = cpu.pc;
+            /*
-            rst_bit(pc, 0);
+              S   -> reading instruction in step()
-            rst_bit(pc, 1);
+              N   -> read from target
+              I   -> stored in register
+              Total = S + N + I cycles
+            */
+            uint32_t pc_ = pc;
+            rst_bit(pc_, 0);
+            rst_bit(pc_, 1);
 
-            cpu.gpr[data.rd] = cpu.bus->read_word(pc + data.word);
+            gpr[data.rd] =
+              bus->read_word(pc_ + data.word, CpuAccess::NonSequential);
+
+            internal_cycle();
+
+            // last read is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](LoadStoreRegisterOffset& data) {
+        [this](LoadStoreRegisterOffset& data) {
-            uint32_t address = cpu.gpr[data.rb] + cpu.gpr[data.ro];
+            /*
+              Load
+              ====
+              S   -> reading instruction in step()
+              N   -> read from target
+              I   -> stored in register
+              Total = S + N + I
+
+              Store
+              =====
+              N -> calculating memory address
+              N -> write at target
+              Total = 2N
+            */
+
+            uint32_t address = gpr[data.rb] + gpr[data.ro];
 
             if (data.load) {
                 if (data.byte) {
-                    cpu.gpr[data.rd] = cpu.bus->read_byte(address);
+                    gpr[data.rd] =
+                      bus->read_byte(address, CpuAccess::NonSequential);
                 } else {
-                    cpu.gpr[data.rd] = cpu.bus->read_word(address);
+                    gpr[data.rd] =
+                      bus->read_word(address, CpuAccess::NonSequential);
                 }
+                internal_cycle();
             } else {
                 if (data.byte) {
-                    cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
+                    bus->write_byte(
+                      address, gpr[data.rd] & 0xFF, CpuAccess::NonSequential);
                 } else {
-                    cpu.bus->write_word(address, cpu.gpr[data.rd]);
+                    bus->write_word(
+                      address, gpr[data.rd], CpuAccess::NonSequential);
                 }
             }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](LoadStoreSignExtendedHalfword& data) {
+        [this](LoadStoreSignExtendedHalfword& data) {
-            uint32_t address = cpu.gpr[data.rb] + cpu.gpr[data.ro];
+            // Same cycles as above
+
+            uint32_t address = gpr[data.rb] + gpr[data.ro];
 
             switch (data.s << 1 | data.h) {
                 case 0b00:
-                    cpu.bus->write_halfword(address, cpu.gpr[data.rd] & 0xFFFF);
+                    bus->write_halfword(
+                      address, gpr[data.rd] & 0xFFFF, CpuAccess::NonSequential);
                     break;
                 case 0b01:
-                    cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
+                    gpr[data.rd] =
+                      bus->read_halfword(address, CpuAccess::NonSequential);
+                    internal_cycle();
                     break;
                 case 0b10:
                     // sign extend and load the byte
-                    cpu.gpr[data.rd] =
+                    gpr[data.rd] = (static_cast<int32_t>(bus->read_byte(
-                      (static_cast<int32_t>(cpu.bus->read_byte(address))
+                                      address, CpuAccess::NonSequential))
-                       << 24) >>
+                                    << 24) >>
-                      24;
+                                   24;
+                    internal_cycle();
                     break;
                 case 0b11:
                     // sign extend the halfword
-                    cpu.gpr[data.rd] =
+                    gpr[data.rd] = (static_cast<int32_t>(bus->read_halfword(
-                      (static_cast<int32_t>(cpu.bus->read_halfword(address))
+                                      address, CpuAccess::NonSequential))
-                       << 16) >>
+                                    << 16) >>
-                      16;
+                                   16;
+                    internal_cycle();
                     break;
 
                     // unreachable
                 default: {
                 }
             }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](LoadStoreImmediateOffset& data) {
+        [this](LoadStoreImmediateOffset& data) {
-            uint32_t address = cpu.gpr[data.rb] + data.offset;
+            // Same cycles as above
+
+            uint32_t address = gpr[data.rb] + data.offset;
+            dbg(address);
 
             if (data.load) {
                 if (data.byte) {
-                    cpu.gpr[data.rd] = cpu.bus->read_byte(address);
+                    gpr[data.rd] =
+                      bus->read_byte(address, CpuAccess::NonSequential);
                 } else {
-                    cpu.gpr[data.rd] = cpu.bus->read_word(address);
+                    gpr[data.rd] =
+                      bus->read_word(address, CpuAccess::NonSequential);
                 }
+                internal_cycle();
             } else {
                 if (data.byte) {
-                    cpu.bus->write_byte(address, cpu.gpr[data.rd] & 0xFF);
+                    bus->write_byte(
+                      address, gpr[data.rd] & 0xFF, CpuAccess::NonSequential);
                 } else {
-                    cpu.bus->write_word(address, cpu.gpr[data.rd]);
+                    bus->write_word(
+                      address, gpr[data.rd], CpuAccess::NonSequential);
                 }
             }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](LoadStoreHalfword& data) {
+        [this](LoadStoreHalfword& data) {
-            uint32_t address = cpu.gpr[data.rb] + data.offset;
+            // Same cycles as above
+
+            uint32_t address = gpr[data.rb] + data.offset;
 
             if (data.load) {
-                cpu.gpr[data.rd] = cpu.bus->read_halfword(address);
+                gpr[data.rd] =
+                  bus->read_halfword(address, CpuAccess::NonSequential);
+                internal_cycle();
             } else {
-                cpu.bus->write_halfword(address, cpu.gpr[data.rd] & 0xFFFF);
+                bus->write_halfword(
+                  address, gpr[data.rd] & 0xFFFF, CpuAccess::NonSequential);
             }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](SpRelativeLoad& data) {
+        [this](SpRelativeLoad& data) {
-            uint32_t address = cpu.sp + data.word;
+            // Same cycles as above
+
+            uint32_t address = sp + data.word;
 
             if (data.load) {
-                cpu.gpr[data.rd] = cpu.bus->read_word(address);
+                gpr[data.rd] = bus->read_word(address, CpuAccess::Sequential);
+                internal_cycle();
             } else {
-                cpu.bus->write_word(address, cpu.gpr[data.rd]);
+                bus->write_word(address, gpr[data.rd], CpuAccess::Sequential);
             }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](LoadAddress& data) {
+        [this](LoadAddress& data) {
+            // 1S cycle in step()
+
             if (data.sp) {
-                cpu.gpr[data.rd] = cpu.sp + data.word;
+                gpr[data.rd] = sp + data.word;
             } else {
                 // PC is already current + 4, so dont need to do that
                 // force bit 1 to 0
-                cpu.gpr[data.rd] = (cpu.pc & ~(1 << 1)) + data.word;
+                gpr[data.rd] = (pc & ~(1 << 1)) + data.word;
             }
         },
-        [&cpu](AddOffsetStackPointer& data) { cpu.sp += data.word; },
+        [this](AddOffsetStackPointer& data) {
-        [&cpu](PushPopRegister& data) {
+            // 1S cycle in step()
+
+            sp += data.word;
+        },
+        [this, &is_flushed](PushPopRegister& data) {
+            /*
+              Load
+              ====
+              S       -> reading instruction in step()
+              N       -> unrelated read from target
+              (n-1) S -> next n - 1 related reads from target
+              I       -> stored in register
+              N+S     -> if PC is written - taken care of by flush_pipeline()
+              S       -> if PC, memory read for PC write
+              Total = nS + N + I or (n+2)S + 2N + I
+
+              Store
+              =====
+              N       -> calculating memory address
+              N       -> if LR, memory read for PC write
+              N/S     -> unrelated write at target
+              (n-1) S -> next n - 1 related writes
+              Total = 2N + nS or 2N + (n-1)S
+            */
             static constexpr uint8_t alignment = 4;
+            CpuAccess access                   = CpuAccess::NonSequential;
 
             if (data.load) {
                 for (uint8_t i = 0; i < 8; i++) {
                     if (get_bit(data.regs, i)) {
-                        cpu.gpr[i] = cpu.bus->read_word(cpu.sp);
+                        gpr[i] = bus->read_word(sp, access);
-                        cpu.sp += alignment;
+                        sp += alignment;
+                        access = CpuAccess::Sequential;
                     }
                 }
 
                 if (data.pclr) {
-                    cpu.pc = cpu.bus->read_word(cpu.sp);
+                    pc = bus->read_word(sp, access);
-                    cpu.sp += alignment;
+                    sp += alignment;
-                    cpu.is_flushed = true;
+                    is_flushed = true;
                 }
+
+                // I
+                internal_cycle();
             } else {
                 if (data.pclr) {
-                    cpu.sp -= alignment;
+                    sp -= alignment;
-                    cpu.bus->write_word(cpu.sp, cpu.lr);
+                    bus->write_word(sp, lr, access);
+                    access = CpuAccess::Sequential;
                 }
 
                 for (int8_t i = 7; i >= 0; i--) {
                     if (get_bit(data.regs, i)) {
-                        cpu.sp -= alignment;
+                        sp -= alignment;
-                        cpu.bus->write_word(cpu.sp, cpu.gpr[i]);
+                        bus->write_word(sp, gpr[i], access);
+                        access = CpuAccess::Sequential;
                     }
                 }
             }
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](MultipleLoad& data) {
+        [this](MultipleLoad& data) {
+            /*
+              Load
+              ====
+              S       -> reading instruction in step()
+              N       -> unrelated read from target
+              (n-1) S -> next n - 1 related reads from target
+              I       -> stored in register
+              Total = nS + N + I
+
+              Store
+              =====
+              N       -> calculating memory address
+              N       -> unrelated write at target
+              (n-1) S -> next n - 1 related writes
+              Total = 2N + (n-1)S
+            */
+
             static constexpr uint8_t alignment = 4;
 
-            uint32_t rb = cpu.gpr[data.rb];
+            uint32_t rb      = gpr[data.rb];
+            CpuAccess access = CpuAccess::NonSequential;
 
             if (data.load) {
                 for (uint8_t i = 0; i < 8; i++) {
                     if (get_bit(data.regs, i)) {
-                        cpu.gpr[i] = cpu.bus->read_word(rb);
+                        gpr[i] = bus->read_word(rb, access);
                         rb += alignment;
+                        access = CpuAccess::Sequential;
                     }
                 }
+                internal_cycle();
             } else {
-                for (int8_t i = 7; i >= 0; i--) {
+                for (uint8_t i = 0; i < 8; i++) {
                     if (get_bit(data.regs, i)) {
-                        rb -= alignment;
+                        bus->write_word(rb, gpr[i], access);
-                        cpu.bus->write_word(rb, cpu.gpr[i]);
+                        rb += alignment;
+                        access = CpuAccess::Sequential;
                     }
                 }
             }
 
-            cpu.gpr[data.rb] = rb;
+            gpr[data.rb] = rb;
+
+            // last read/write is unrelated
+            next_access = CpuAccess::NonSequential;
         },
-        [&cpu](ConditionalBranch& data) {
+        [this, &is_flushed](ConditionalBranch& data) {
+            /*
+              S   -> reading instruction in step()
+              N+S -> if condition is true, branch and refill pipeline
+              Total = S or 2S + N
+            */
+
             if (data.condition == Condition::AL)
                 glogger.warn("Condition 1110 (AL) is undefined");
 
-            if (!cpu.cpsr.condition(data.condition))
+            if (!cpsr.condition(data.condition))
                 return;
 
-            cpu.pc += data.offset;
+            pc += data.offset;
-            cpu.is_flushed = true;
+            is_flushed = true;
         },
-        [&cpu](SoftwareInterrupt& data) {
+        [this, &is_flushed](SoftwareInterrupt& data) {
+            /*
+              S   -> reading instruction in step()
+              N+S -> refill pipeline
+              Total = 2S + N
+            */
+
             // next instruction is one instruction behind PC
-            cpu.lr   = cpu.pc - INSTRUCTION_SIZE;
+            lr   = pc - INSTRUCTION_SIZE;
-            cpu.spsr = cpu.cpsr;
+            spsr = cpsr;
-            cpu.pc   = data.vector;
+            pc   = data.vector;
-            cpu.cpsr.set_state(State::Arm);
+            cpsr.set_state(State::Arm);
-            cpu.chg_mode(Mode::Supervisor);
+            chg_mode(Mode::Supervisor);
-            cpu.is_flushed = true;
+            is_flushed = true;
         },
-        [&cpu](UnconditionalBranch& data) {
+        [this, &is_flushed](UnconditionalBranch& data) {
-            cpu.pc += data.offset;
+            /*
-            cpu.is_flushed = true;
+              S   -> reading instruction in step()
+              N+S -> branch and refill pipeline
+              Total = 2S + N
+            */
+
+            pc += data.offset;
+            is_flushed = true;
         },
-        [&cpu](LongBranchWithLink& data) {
+        [this, &is_flushed](LongBranchWithLink& data) {
+            /*
+              S -> prefetched instruction in step()
+              N -> fetch from the new address in branch
+              S -> last opcode fetch at +L to refill the pipeline
+              Total = 2S + N cycles
+                      1S done, S+N taken care of by flush_pipeline()
+            */
+
             // 12 bit integer
             int32_t offset = data.offset;
 
-            if (data.high) {
+            if (data.low) {
-                uint32_t old_pc = cpu.pc;
+                uint32_t old_pc = pc;
+                offset <<= 1;
 
-                cpu.pc         = cpu.lr + offset;
+                pc         = lr + offset;
-                cpu.lr         = (old_pc - INSTRUCTION_SIZE) | 1;
+                lr         = (old_pc - INSTRUCTION_SIZE) | 1;
-                cpu.is_flushed = true;
+                is_flushed = true;
             } else {
                 // 12 + 11 = 23 bit
-                offset <<= 11;
+                offset <<= 12;
                 // sign extend
                 offset = (offset << 9) >> 9;
-                cpu.lr = cpu.pc + offset;
+                lr     = pc + offset;
             }
         },
         [](auto& data) {
             glogger.error("Unknown thumb format : {}", typeid(data).name());
         } },
-      data);
+      instruction.data);
+
+    if (is_flushed)
+        flush_pipeline<State::Thumb>();
+    else
+        advance_pc_thumb();
 }
 }

src/cpu/thumb/instruction.cc

@@ -203,11 +203,9 @@ Instruction::Instruction(uint16_t insn) {
         // Format 19: Long branch with link
     } else if ((insn & 0xF000) == 0xF000) {
         uint16_t offset = bit_range(insn, 0, 10);
-        bool high       = get_bit(insn, 11);
+        bool low        = get_bit(insn, 11);
 
-        offset <<= 1;
+        data = LongBranchWithLink{ .offset = offset, .low = low };
-
-        data = LongBranchWithLink{ .offset = offset, .high = high };
     }
 }
 }

src/gdb_rsp.cc

@@ -0,0 +1,487 @@
+#include "gdb_rsp.hh"
+#include "util/log.hh"
+#include <csignal>
+#include <numeric>
+#include <regex>
+#include <stdexcept>
+#include <string>
+
+namespace matar {
+
+template<typename... Args>
+static inline constexpr void
+gdb_log(const std::format_string<Args...>& fmt, Args&&... args) {
+    glogger.debug("GDB: {}", std::format(fmt, std::forward<Args>(args)...));
+}
+
+static inline void
+append_le(std::string& str, uint32_t value) {
+    // little endian only
+    str += std::format("{:02x}", value & 0xFF);
+    str += std::format("{:02x}", value >> 8 & 0xFF);
+    str += std::format("{:02x}", value >> 16 & 0xFF);
+    str += std::format("{:02x}", value >> 24 & 0xFF);
+}
+
+static inline std::string
+be_to_le(std::string str) {
+    if (str.length() != 8)
+        throw std::out_of_range("string is supposed to be 8 bytes");
+
+    std::string current;
+
+    for (int i = 7; i >= 0; i -= 2) {
+        current += str[i - 1];
+        current += str[i];
+    }
+
+    return current;
+}
+
+GdbRsp::GdbRsp(std::shared_ptr<Cpu> cpu, uint port)
+  : cpu(cpu) {
+    server.start(port);
+}
+
+void
+GdbRsp::start() {
+    server.run();
+
+    attach();
+
+    // attaching is not enough, we continue, until the last GDB communication
+    // happens for ARMv4t i.e, fetching of the CPSR
+    std::string msg;
+
+    while (msg != "$p19") {
+        msg = receive();
+        step(msg); // 25th (0x19) register is cpsr
+    }
+}
+
+void
+GdbRsp::attach() {
+    while (!attached) {
+        step();
+    }
+}
+
+void
+GdbRsp::satisfy_client() {
+    while (server.client_waiting() && attached) {
+        step();
+    }
+}
+
+void
+GdbRsp::step() {
+    std::string msg = receive();
+    step(msg);
+}
+
+void
+GdbRsp::step(std::string msg) {
+    switch (msg[0]) {
+        case '+':
+            break;
+        case '-':
+            break;
+        case '\x03':
+            gdb_log("ctrl+c interrupt received");
+            cmd_halted();
+            break;
+        case '$': {
+            acknowledge();
+            switch (msg[1]) {
+                case '?':
+                    cmd_halted();
+                    break;
+                case 'g':
+                    cmd_read_registers();
+                    break;
+                case 'G':
+                    cmd_write_registers(msg);
+                    break;
+                case 'p':
+                    cmd_read_register(msg);
+                    break;
+                case 'P':
+                    cmd_write_register(msg);
+                    break;
+                case 'm':
+                    cmd_read_memory(msg);
+                    break;
+                case 'M':
+                    cmd_write_memory(msg);
+                    break;
+                case 'z':
+                    cmd_rm_breakpoint(msg);
+                    break;
+                case 'Z':
+                    cmd_add_breakpoint(msg);
+                    break;
+                case 'c':
+                    cmd_continue();
+                    break;
+                case 'D':
+                    cmd_detach();
+                    break;
+                case 'Q':
+                    if (msg == "$QStartNoAckMode")
+                        ack_mode = true;
+                    send_ok();
+                    break;
+                case 'q':
+                    if (msg.starts_with("$qSupported")) {
+                        cmd_supported(msg);
+                        break;
+                    } else if (msg == "$qAttached") {
+                        cmd_attached();
+                        break;
+                    }
+                    [[fallthrough]];
+                default:
+                    gdb_log("unknown command");
+                    send_empty();
+            }
+            break;
+        }
+        default:
+            gdb_log("unknown message received");
+    }
+}
+
+std::string
+GdbRsp::receive() {
+    std::string msg = server.receive(1);
+    char ch         = msg[0];
+    uint checksum   = 0;
+
+    if (ch == '$') {
+        while ((ch = server.receive(1)[0]) != '#') {
+            checksum += static_cast<uint>(ch);
+            msg += ch;
+            if (msg.length() > MAX_MSG_LEN) {
+                throw std::logic_error("GDB: received message is too long");
+            }
+        }
+
+        if (std::stoul(server.receive(2), nullptr, 16) != (checksum & 0xFF)) {
+            gdb_log("{}", msg);
+            throw std::logic_error("GDB: bad message checksum");
+        }
+    }
+
+    gdb_log("received message \"{}\"", msg);
+    return msg;
+}
+
+std::string
+GdbRsp::make_packet(std::string raw) {
+    uint checksum = std::accumulate(raw.begin(), raw.end(), 0);
+    return std::format("${}#{:02x}", raw, checksum & 0xFF);
+}
+
+void
+GdbRsp::acknowledge() {
+    if (ack_mode)
+        server.send("+");
+}
+
+void
+GdbRsp::send_empty() {
+    server.send(make_packet(""));
+}
+
+void
+GdbRsp::send_ok() {
+    acknowledge();
+    server.send(make_packet("OK"));
+}
+
+void
+GdbRsp::notify_breakpoint_reached() {
+    gdb_log("reached breakpoint, sending signal");
+    server.send(make_packet(std::format("S{:02x}", SIGTRAP)));
+}
+
+void
+GdbRsp::cmd_attached() {
+    attached = true;
+
+    gdb_log("server is now attached");
+    server.send(make_packet("1"));
+}
+
+void
+GdbRsp::cmd_supported(std::string msg) {
+    std::string response;
+
+    if (msg.find("hwbreak+;") != std::string::npos)
+        response += "hwbreak+;";
+
+    // no acknowledgement mode
+    response += "QStartNoAckMode+";
+
+    gdb_log("sending response for qSupported");
+    server.send(make_packet(response));
+}
+
+void
+GdbRsp::cmd_halted() {
+    gdb_log("sending reason for upcoming halt");
+    server.send(make_packet(std::format("S{:02x}", SIGTRAP)));
+}
+
+void
+GdbRsp::cmd_read_registers() {
+    std::string response;
+
+    for (int i = 0; i < cpu->GPR_COUNT - 1; i++)
+        append_le(response, cpu->gpr[i]);
+
+    // for some reason this PC needs to be the address of executing instruction
+    // i.e, two instructions behind actual PC
+    append_le(response,
+              cpu->pc - 2 * (cpu->cpsr.state() == State::Arm
+                               ? arm::INSTRUCTION_SIZE
+                               : thumb::INSTRUCTION_SIZE));
+
+    gdb_log("sending register values");
+    server.send(make_packet(response));
+}
+
+void
+GdbRsp::cmd_write_registers(std::string msg) {
+    static std::regex rgx("\\$G([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 2 || sm[1].str().size() != 16 * 8) {
+        gdb_log("invalid arguments to write registers");
+        send_empty();
+        return;
+    }
+
+    try {
+        std::string values = sm[1].str();
+
+        for (uint i = 0, j = 0; i < values.length() - 8; i += 8, j++) {
+            cpu->gpr[i] = std::stoul(sm[i + 1].str(), nullptr, 16);
+            cpu->gpr[j] =
+              std::stoul(be_to_le(values.substr(i, 8)), nullptr, 16);
+        }
+
+        gdb_log("register values written");
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_read_register(std::string msg) {
+    std::string response;
+
+    try {
+        uint reg = std::stoul(msg.substr(2), nullptr, 16);
+        // 25th register is CPSR in gdb ARM
+        if (reg == 25)
+            append_le(response, cpu->cpsr.raw());
+        else if (reg < cpu->GPR_COUNT)
+            append_le(response, cpu->gpr[reg]);
+        else
+            response += "xxxxxxxx";
+
+        gdb_log("sending single register value");
+        server.send(make_packet(response));
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_write_register(std::string msg) {
+    static std::regex rgx("\\$P([0-9A-Fa-f]+)\\=([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 3 && sm[2].str().length() != 8) {
+        gdb_log("invalid arguments to write single register");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint reg       = std::stoul(sm[1].str(), nullptr, 16);
+        uint32_t value = std::stoul(be_to_le(sm[2].str()), nullptr, 16);
+
+        dbg(value);
+
+        if (reg == 25)
+            cpu->cpsr.set_all(value);
+        else if (reg < cpu->GPR_COUNT)
+            cpu->gpr[reg] = value;
+
+        gdb_log("single register value written");
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_read_memory(std::string msg) {
+    std::string response;
+
+    static std::regex rgx("\\$m([0-9A-Fa-f]+),([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 3) {
+        gdb_log("invalid arguments to read memory");
+        send_empty();
+        return;
+    }
+
+    uint32_t address = 0, length = 0;
+
+    try {
+        address = std::stoul(sm[1].str(), nullptr, 16);
+        length  = std::stoul(sm[2].str(), nullptr, 16);
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+        return;
+    }
+
+    for (uint i = 0; i < length; i++) {
+        response += std::format("{:02x}", cpu->bus->read_byte(address + i));
+    }
+
+    gdb_log("sending memory values values");
+    server.send(make_packet(response));
+}
+
+void
+GdbRsp::cmd_write_memory(std::string msg) {
+    static std::regex rgx("\\$M([0-9A-Fa-f]+),([0-9A-Fa-f]+):([0-9A-Fa-f]+)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 4) {
+        gdb_log("invalid arguments to write memory");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint32_t address = std::stoul(sm[1].str(), nullptr, 16);
+        uint32_t length  = std::stoul(sm[2].str(), nullptr, 16);
+
+        std::string values = sm[3].str();
+
+        for (uint i = 0, j = 0; i < length && j < values.size(); i++, j += 2) {
+            cpu->bus->write_byte(
+              address + i, std::stoul(values.substr(j, 2), nullptr, 16) & 0xFF);
+        }
+
+        gdb_log("register values written");
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_rm_breakpoint(std::string msg) {
+    static std::regex rgx("\\$z(0|1),([0-9A-Fa-f]+),(2|3|4)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+
+    if (sm.size() != 4) {
+        gdb_log("invalid arguments to remove breakpoint");
+        send_empty();
+        return;
+    }
+
+    if (sm[1].str() != "0" && sm[0].str() != "1") {
+        gdb_log("unrecognized breakpoint type encountered");
+        send_empty();
+        return;
+    }
+
+    if (sm[3].str() != "3" && sm[3].str() != "4") {
+        gdb_log("only 32 bit breakpoints supported");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint32_t address = std::stoul(sm[2].str(), nullptr, 16);
+
+        cpu->breakpoints.erase(address);
+        gdb_log("breakpoint {:#08x} removed", address);
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_add_breakpoint(std::string msg) {
+    static std::regex rgx("\\$Z(0|1),([0-9A-Fa-f]+),(2|3|4)");
+    std::smatch sm;
+    regex_match(msg, sm, rgx);
+    dbg(sm.size());
+    dbg(sm[0].str());
+
+    if (sm.size() != 4) {
+        gdb_log("invalid arguments to add breakpoint");
+        send_empty();
+        return;
+    }
+
+    if (sm[1].str() != "0" && sm[0].str() != "1") {
+        gdb_log("unrecognized breakpoint type encountered");
+        send_empty();
+        return;
+    }
+
+    if (sm[3].str() != "3" && sm[3].str() != "4") {
+        gdb_log("only 32 bit breakpoints supported");
+        send_empty();
+        return;
+    }
+
+    try {
+        uint32_t address = std::stoul(sm[2].str(), nullptr, 16);
+
+        cpu->breakpoints.insert(address);
+        gdb_log("breakpoint {:#08x} added", address);
+        send_ok();
+    } catch (const std::exception& e) {
+        gdb_log("{}", e.what());
+        send_empty();
+    }
+}
+
+void
+GdbRsp::cmd_detach() {
+    attached = false;
+    gdb_log("detached");
+    send_ok();
+}
+
+void
+GdbRsp::cmd_continue() {
+    // what to do?
+    gdb_log("cpu continued");
+    send_ok();
+}
+}

src/gdb_rsp.hh

@@ -0,0 +1,47 @@
+#include "cpu/cpu.hh"
+#include "util/tcp_server.hh"
+
+namespace matar {
+class GdbRsp {
+  public:
+    GdbRsp(std::shared_ptr<Cpu> cpu, uint port);
+    ~GdbRsp() = default;
+    void start();
+    void attach();
+    void satisfy_client();
+    void step();
+    void step(std::string msg);
+    void notify_breakpoint_reached();
+    inline bool is_attached() { return attached; }
+
+  private:
+    bool attached = false;
+
+    std::shared_ptr<Cpu> cpu;
+    net::TcpServer server;
+    std::string receive();
+    std::string make_packet(std::string raw);
+
+    bool ack_mode = true;
+    void acknowledge();
+    void send_empty();
+    void send_ok();
+
+    // Commands
+    void cmd_attached();
+    void cmd_supported(std::string msg);
+    void cmd_halted();
+    void cmd_read_registers();
+    void cmd_write_registers(std::string msg);
+    void cmd_read_register(std::string msg);
+    void cmd_write_register(std::string msg);
+    void cmd_read_memory(std::string msg);
+    void cmd_write_memory(std::string msg);
+    void cmd_rm_breakpoint(std::string msg);
+    void cmd_add_breakpoint(std::string msg);
+    void cmd_detach();
+    void cmd_continue();
+
+    static constexpr uint MAX_MSG_LEN = 4096;
+};
+}

src/io/display/display.cc

@@ -0,0 +1,23 @@
+#include "io/display/display.hh"
+
+namespace matar {
+namespace display {
+
+/*
+static constexpr uint LCD_HEIGHT = 160;
+static constexpr uint LCD_WIDTH  = 240;
+static constexpr uint BLANK      = 68;
+
+static constexpr uint PIXEL_CYCLES    = 4;                             // 4
+static constexpr uint HDRAW_CYCLES    = LCD_WIDTH * PIXEL_CYCLES + 46; // 1006
+static constexpr uint HBLANK_CYCLES   = BLANK * PIXEL_CYCLES - 46;     // 226
+static constexpr uint HREFRESH_CYCLES = HDRAW_CYCLES + HBLANK_CYCLES;  // 1232
+static constexpr uint VDRAW_CYCLES    = LCD_HEIGHT * HREFRESH_CYCLES;  // 197120
+static constexpr uint VBLANK_CYCLES   = BLANK * HREFRESH_CYCLES;       // 83776
+static constexpr uint VREFRESH_CYCLES = VDRAW_CYCLES + VBLANK_CYCLES;  // 280896
+*/
+
+void
+Display::mode_3() {}
+}
+}

src/io/display/meson.build

@@ -0,0 +1,3 @@
+lib_sources += files(
+  'display.cc'
+)

src/io/display/render.cc

@@ -0,0 +1,51 @@
+#include "io/display/display.hh"
+
+namespace matar {
+namespace display {
+
+struct TextScreen {
+    uint16_t tile_number : 10;
+    bool mirror_horizontal : 1;
+    bool mirror_vertical : 1;
+    uint8_t palette_number : 4;
+};
+
+// if 16th bit is set, this will denote the transparent color in rgb555 format
+static constexpr uint16_t TRANSPARENT_RGB555 = 0x8000;
+
+template<int MODE, typename>
+void
+Display::render_bitmap_mode() {
+    static constexpr std::size_t VIEWPORT_WIDTH = MODE == 5 ? 160 : 240;
+
+    for (int x = 0; x < LCD_WIDTH; x++) {
+        // pixel to texel for x
+        // shift by 8 cuz both ref.x and a are fixed point floats shifted by 8
+        int32_t x_ = (bg2_rot_scale.ref.x + x * bg2_rot_scale.a) >> 8;
+        int32_t y_ = (bg2_rot_scale.ref.y + x * bg2_rot_scale.c) >> 8;
+
+        // ignore handling area overflow for bitmap modes
+        // i am not sure how well this will turn out
+
+        std::size_t idx = y_ * VIEWPORT_WIDTH + x_;
+
+        // mode 3 and 5 takes 2 bytes per pixel
+        if constexpr (MODE != 4)
+            idx *= 2;
+
+        // offset
+        if constexpr (MODE != 3) {
+            std::size_t offset =
+              lcd_control.value.frame_select_1 ? 0xA000 : 0x0000;
+            idx += offset;
+        }
+
+        // read two bytes
+        if constexpr (MODE == 4)
+            scanline_buffers[2][x] = pram.read_halfword(vram.read_byte(idx));
+        else
+            scanline_buffers[2][x] = vram.read_halfword(idx);
+    }
+}
+}
+}

src/io/io.cc

@@ -76,6 +76,24 @@ ADDR FIFO_A_H    = 0x40000A2;
 ADDR FIFO_B_L    = 0x40000A4;
 ADDR FIFO_B_H    = 0x40000A6;
 
+// dma
+ADDR DMA0SAD   = 0x40000B0;
+ADDR DMA0DAD   = 0x40000B4;
+ADDR DMA0CNT_L = 0x40000B8;
+ADDR DMA0CNT_H = 0x40000BA;
+ADDR DMA1SAD   = 0x40000BC;
+ADDR DMA1DAD   = 0x40000C0;
+ADDR DMA1CNT_L = 0x40000C4;
+ADDR DMA1CNT_H = 0x40000C6;
+ADDR DMA2SAD   = 0x40000C8;
+ADDR DMA2DAD   = 0x40000CC;
+ADDR DMA2CNT_L = 0x40000D0;
+ADDR DMA2CNT_H = 0x40000D2;
+ADDR DMA3SAD   = 0x40000D4;
+ADDR DMA3DAD   = 0x40000D8;
+ADDR DMA3CNT_L = 0x40000DC;
+ADDR DMA3CNT_H = 0x40000DE;
+
 // system
 ADDR POSTFLG = 0x4000300;
 ADDR IME     = 0x4000208;
@@ -86,6 +104,9 @@ ADDR HALTCNT = 0x4000301;
 
 #undef ADDR
 
+IoDevices::IoDevices(std::weak_ptr<Bus> bus)
+  : bus(bus) {}
+
 uint8_t
 IoDevices::read_byte(uint32_t address) const {
     uint16_t halfword = read_halfword(address & ~1);
@@ -127,45 +148,87 @@ IoDevices::read_halfword(uint32_t address) const {
     case name:                                                                 \
         return var;
 
-        // lcd
+            // lcd
-        READ(DISPCNT, lcd.lcd_control)
+        case DISPCNT:
-        READ(DISPSTAT, lcd.general_lcd_status)
+            return display.lcd_control.read();
-        READ(VCOUNT, lcd.vertical_counter)
+        case DISPSTAT:
-        READ(WININ, lcd.inside_win_0_1)
+            return display.general_lcd_status.read();
-        READ(WINOUT, lcd.outside_win)
+        case BG0CNT:
-        READ(BLDCNT, lcd.color_special_effects_selection)
+            return display.bg_control[0].read();
-        READ(BLDALPHA, lcd.alpha_blending_coefficients)
+        case BG1CNT:
+            return display.bg_control[1].read();
+        case BG2CNT:
+            return display.bg_control[2].read();
+        case BG3CNT:
+            return display.bg_control[3].read();
 
-        // sound
+            READ(VCOUNT, display.vertical_counter)
-        READ(SOUND1CNT_L, sound.ch1_sweep)
+            READ(WININ, display.inside_win_0_1)
-        READ(SOUND1CNT_H, sound.ch1_duty_length_env)
+            READ(WINOUT, display.outside_win)
-        READ(SOUND1CNT_X, sound.ch1_freq_control)
+            READ(BLDCNT, display.color_special_effects_selection)
-        READ(SOUND2CNT_L, sound.ch2_duty_length_env)
+            READ(BLDALPHA, display.alpha_blending_coefficients)
-        READ(SOUND2CNT_H, sound.ch2_freq_control)
-        READ(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
-        READ(SOUND3CNT_H, sound.ch3_length_volume)
-        READ(SOUND3CNT_X, sound.ch3_freq_control)
-        READ(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
-        READ(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
-        READ(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
-        READ(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
-        READ(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
-        READ(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
-        READ(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
-        READ(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
-        READ(SOUND4CNT_L, sound.ch4_length_env);
-        READ(SOUND4CNT_H, sound.ch4_freq_control);
-        READ(SOUNDCNT_L, sound.ctrl_stereo_volume);
-        READ(SOUNDCNT_H, sound.ctrl_mixing);
-        READ(SOUNDCNT_X, sound.ctrl_sound_on_off);
-        READ(SOUNDBIAS, sound.pwm_control);
 
-        // system
+            // sound
-        READ(POSTFLG, system.post_boot_flag)
+            READ(SOUND1CNT_L, sound.ch1_sweep)
-        READ(IME, system.interrupt_master_enabler)
+            READ(SOUND1CNT_H, sound.ch1_duty_length_env)
-        READ(IE, system.interrupt_enable);
+            READ(SOUND1CNT_X, sound.ch1_freq_control)
-        READ(IF, system.interrupt_request_flags);
+            READ(SOUND2CNT_L, sound.ch2_duty_length_env)
-        READ(WAITCNT, system.waitstate_control);
+            READ(SOUND2CNT_H, sound.ch2_freq_control)
+            READ(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
+            READ(SOUND3CNT_H, sound.ch3_length_volume)
+            READ(SOUND3CNT_X, sound.ch3_freq_control)
+            READ(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
+            READ(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
+            READ(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
+            READ(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
+            READ(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
+            READ(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
+            READ(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
+            READ(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
+            READ(SOUND4CNT_L, sound.ch4_length_env);
+            READ(SOUND4CNT_H, sound.ch4_freq_control);
+            READ(SOUNDCNT_L, sound.ctrl_stereo_volume);
+            READ(SOUNDCNT_H, sound.ctrl_mixing);
+            READ(SOUNDCNT_X, sound.ctrl_sound_on_off);
+            READ(SOUNDBIAS, sound.pwm_control);
+
+            // dma
+        case DMA0CNT_H:
+            return dma.channels[0].control.read();
+        case DMA1CNT_H:
+            return dma.channels[1].control.read();
+        case DMA2CNT_H:
+            return dma.channels[2].control.read();
+        case DMA3CNT_H:
+            return dma.channels[3].control.read();
+
+            READ(DMA0SAD, dma.channels[0].source[0]);
+            READ(DMA0SAD + 2, dma.channels[0].source[1]);
+            READ(DMA0DAD, dma.channels[0].destination[0]);
+            READ(DMA0DAD + 2, dma.channels[0].destination[1]);
+            READ(DMA0CNT_L, dma.channels[0].word_count);
+            READ(DMA1SAD, dma.channels[1].source[0]);
+            READ(DMA1SAD + 2, dma.channels[1].source[1]);
+            READ(DMA1DAD, dma.channels[1].destination[0]);
+            READ(DMA1DAD + 2, dma.channels[1].destination[1]);
+            READ(DMA1CNT_L, dma.channels[1].word_count);
+            READ(DMA2SAD, dma.channels[2].source[0]);
+            READ(DMA2SAD + 2, dma.channels[2].source[1]);
+            READ(DMA2DAD, dma.channels[2].destination[0]);
+            READ(DMA2DAD + 2, dma.channels[2].destination[1]);
+            READ(DMA2CNT_L, dma.channels[2].word_count);
+            READ(DMA3SAD, dma.channels[3].source[0]);
+            READ(DMA3SAD + 2, dma.channels[3].source[1]);
+            READ(DMA3DAD, dma.channels[3].destination[0]);
+            READ(DMA3DAD + 2, dma.channels[3].destination[1]);
+            READ(DMA3CNT_L, dma.channels[3].word_count);
+
+            // system
+            READ(POSTFLG, system.post_boot_flag)
+            READ(IME, system.interrupt_master_enabler)
+            READ(IE, system.interrupt_enable);
+            READ(IF, system.interrupt_request_flags);
+            READ(WAITCNT, system.waitstate_control);
 
 #undef READ
 
@@ -178,6 +241,18 @@ IoDevices::read_halfword(uint32_t address) const {
 
 void
 IoDevices::write_halfword(uint32_t address, uint16_t halfword) {
+    // set lower 16 bits for reference points (BG 2/3)
+    auto ref_low = [](uint32_t original, uint16_t low) {
+        return static_cast<int32_t>((original & 0xFFFF0000) | low);
+    };
+
+    // set upper 12 bits for reference points (BG 2/3)
+    // and sign extend
+    auto ref_high = [](uint32_t original, uint16_t high) {
+        return static_cast<int32_t>(
+          ((((high & 0xFFF) << 16) | (original & 0xFFFF)) << 4) >> 4);
+    };
+
     switch (address) {
 
 #define WRITE(name, var)                                                       \
@@ -191,82 +266,146 @@ IoDevices::write_halfword(uint32_t address, uint16_t halfword) {
         break;
 
         // lcd
-        WRITE(DISPCNT, lcd.lcd_control)
+        case DISPCNT:
-        WRITE(DISPSTAT, lcd.general_lcd_status)
+            display.lcd_control.write(halfword);
-        WRITE(BG0CNT, lcd.bg0_control)
+            break;
-        WRITE(BG1CNT, lcd.bg1_control)
+        case DISPSTAT:
-        WRITE(BG2CNT, lcd.bg2_control)
+            display.general_lcd_status.write(halfword);
-        WRITE(BG3CNT, lcd.bg3_control)
+            break;
-        WRITE(BG0HOFS, lcd.bg0_x_offset)
+        case BG0CNT:
-        WRITE(BG0VOFS, lcd.bg0_y_offset)
+            display.bg_control[0].write(halfword);
-        WRITE(BG1HOFS, lcd.bg1_x_offset)
+            break;
-        WRITE(BG1VOFS, lcd.bg1_y_offset)
+        case BG1CNT:
-        WRITE(BG2HOFS, lcd.bg2_x_offset)
+            display.bg_control[1].write(halfword);
-        WRITE(BG2VOFS, lcd.bg2_y_offset)
+            break;
-        WRITE(BG3HOFS, lcd.bg3_x_offset)
+        case BG2CNT:
-        WRITE(BG3VOFS, lcd.bg3_y_offset)
+            display.bg_control[2].write(halfword);
-        WRITE(BG2PA, lcd.bg2_rot_scaling_parameters[0])
+            break;
-        WRITE(BG2PB, lcd.bg2_rot_scaling_parameters[1])
+        case BG3CNT:
-        WRITE(BG2PC, lcd.bg2_rot_scaling_parameters[2])
+            display.bg_control[3].write(halfword);
-        WRITE(BG2PD, lcd.bg2_rot_scaling_parameters[3])
+            break;
-        WRITE(BG2X_L, lcd.bg2_reference_x[0])
-        WRITE(BG2X_H, lcd.bg2_reference_x[1])
-        WRITE(BG2Y_L, lcd.bg2_reference_y[0])
-        WRITE(BG2Y_H, lcd.bg2_reference_y[1])
-        WRITE(BG3PA, lcd.bg3_rot_scaling_parameters[0])
-        WRITE(BG3PB, lcd.bg3_rot_scaling_parameters[1])
-        WRITE(BG3PC, lcd.bg3_rot_scaling_parameters[2])
-        WRITE(BG3PD, lcd.bg3_rot_scaling_parameters[3])
-        WRITE(BG3X_L, lcd.bg3_reference_x[0])
-        WRITE(BG3X_H, lcd.bg3_reference_x[1])
-        WRITE(BG3Y_L, lcd.bg3_reference_y[0])
-        WRITE(BG3Y_H, lcd.bg3_reference_y[1])
-        WRITE(WIN0H, lcd.win0_horizontal_dimensions)
-        WRITE(WIN1H, lcd.win1_horizontal_dimensions)
-        WRITE(WIN0V, lcd.win0_vertical_dimensions)
-        WRITE(WIN1V, lcd.win1_vertical_dimensions)
-        WRITE(WININ, lcd.inside_win_0_1)
-        WRITE(WINOUT, lcd.outside_win)
-        WRITE(MOSAIC, lcd.mosaic_size)
-        WRITE(BLDCNT, lcd.color_special_effects_selection)
-        WRITE(BLDALPHA, lcd.alpha_blending_coefficients)
-        WRITE(BLDY, lcd.brightness_coefficient)
 
-        // sound
+            WRITE(BG0HOFS, display.bg0_offset.x)
-        WRITE(SOUND1CNT_L, sound.ch1_sweep)
+            WRITE(BG0VOFS, display.bg0_offset.y)
-        WRITE(SOUND1CNT_H, sound.ch1_duty_length_env)
+            WRITE(BG1HOFS, display.bg1_offset.x)
-        WRITE(SOUND1CNT_X, sound.ch1_freq_control)
+            WRITE(BG1VOFS, display.bg1_offset.y)
-        WRITE(SOUND2CNT_L, sound.ch2_duty_length_env)
+            WRITE(BG2HOFS, display.bg2_offset.x)
-        WRITE(SOUND2CNT_H, sound.ch2_freq_control)
+            WRITE(BG2VOFS, display.bg2_offset.y)
-        WRITE(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
+            WRITE(BG3HOFS, display.bg3_offset.x)
-        WRITE(SOUND3CNT_H, sound.ch3_length_volume)
+            WRITE(BG3VOFS, display.bg3_offset.y)
-        WRITE(SOUND3CNT_X, sound.ch3_freq_control)
+            WRITE(BG2PA, display.bg2_rot_scale.a)
-        WRITE(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
+            WRITE(BG2PB, display.bg2_rot_scale.b)
-        WRITE(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
+            WRITE(BG2PC, display.bg2_rot_scale.c)
-        WRITE(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
+            WRITE(BG2PD, display.bg2_rot_scale.d)
-        WRITE(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
+            WRITE_2(BG2X_L,
-        WRITE(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
+                    display.bg2_rot_scale.ref.x,
-        WRITE(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
+                    ref_low(display.bg2_rot_scale.ref.x, halfword));
-        WRITE(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
+            WRITE_2(BG2X_H,
-        WRITE(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
+                    display.bg2_rot_scale.ref.x,
-        WRITE(SOUND4CNT_L, sound.ch4_length_env);
+                    ref_high(display.bg2_rot_scale.ref.x, halfword));
-        WRITE(SOUND4CNT_H, sound.ch4_freq_control);
+            WRITE_2(BG2Y_L,
-        WRITE(SOUNDCNT_L, sound.ctrl_stereo_volume);
+                    display.bg2_rot_scale.ref.y,
-        WRITE(SOUNDCNT_H, sound.ctrl_mixing);
+                    ref_low(display.bg2_rot_scale.ref.y, halfword));
-        WRITE(SOUNDCNT_X, sound.ctrl_sound_on_off);
+            WRITE_2(BG2Y_H,
-        WRITE(SOUNDBIAS, sound.pwm_control);
+                    display.bg2_rot_scale.ref.y,
-        WRITE(FIFO_A_L, sound.fifo_a[0]);
+                    ref_high(display.bg2_rot_scale.ref.y, halfword));
-        WRITE(FIFO_A_H, sound.fifo_a[1]);
+            WRITE(BG3PA, display.bg3_rot_scale.a)
-        WRITE(FIFO_B_L, sound.fifo_b[0]);
+            WRITE(BG3PB, display.bg3_rot_scale.b)
-        WRITE(FIFO_B_H, sound.fifo_b[1]);
+            WRITE(BG3PC, display.bg3_rot_scale.c)
+            WRITE(BG3PD, display.bg3_rot_scale.d)
+            WRITE_2(BG3X_L,
+                    display.bg3_rot_scale.ref.x,
+                    ref_low(display.bg3_rot_scale.ref.x, halfword));
+            WRITE_2(BG3X_H,
+                    display.bg3_rot_scale.ref.x,
+                    ref_high(display.bg3_rot_scale.ref.x, halfword));
+            WRITE_2(BG3Y_L,
+                    display.bg3_rot_scale.ref.y,
+                    ref_low(display.bg3_rot_scale.ref.y, halfword));
+            WRITE_2(BG3Y_H,
+                    display.bg3_rot_scale.ref.y,
+                    ref_high(display.bg3_rot_scale.ref.y, halfword));
+            WRITE(WIN0H, display.win0_horizontal_dimensions)
+            WRITE(WIN1H, display.win1_horizontal_dimensions)
+            WRITE(WIN0V, display.win0_vertical_dimensions)
+            WRITE(WIN1V, display.win1_vertical_dimensions)
+            WRITE(WININ, display.inside_win_0_1)
+            WRITE(WINOUT, display.outside_win)
+            WRITE(MOSAIC, display.mosaic_size)
+            WRITE(BLDCNT, display.color_special_effects_selection)
+            WRITE(BLDALPHA, display.alpha_blending_coefficients)
+            WRITE(BLDY, display.brightness_coefficient)
 
-        // system
+            // sound
-        WRITE_2(POSTFLG, system.post_boot_flag, halfword & 1)
+            WRITE(SOUND1CNT_L, sound.ch1_sweep)
-        WRITE_2(IME, system.interrupt_master_enabler, halfword & 1)
+            WRITE(SOUND1CNT_H, sound.ch1_duty_length_env)
-        WRITE(IE, system.interrupt_enable);
+            WRITE(SOUND1CNT_X, sound.ch1_freq_control)
-        WRITE(IF, system.interrupt_request_flags);
+            WRITE(SOUND2CNT_L, sound.ch2_duty_length_env)
-        WRITE(WAITCNT, system.waitstate_control);
+            WRITE(SOUND2CNT_H, sound.ch2_freq_control)
-        WRITE_2(HALTCNT, system.low_power_mode, get_bit(halfword, 7));
+            WRITE(SOUND3CNT_L, sound.ch3_stop_wave_ram_select)
+            WRITE(SOUND3CNT_H, sound.ch3_length_volume)
+            WRITE(SOUND3CNT_X, sound.ch3_freq_control)
+            WRITE(WAVE_RAM0_L, sound.ch3_wave_pattern[0]);
+            WRITE(WAVE_RAM0_H, sound.ch3_wave_pattern[1]);
+            WRITE(WAVE_RAM1_L, sound.ch3_wave_pattern[2]);
+            WRITE(WAVE_RAM1_H, sound.ch3_wave_pattern[3]);
+            WRITE(WAVE_RAM2_L, sound.ch3_wave_pattern[4]);
+            WRITE(WAVE_RAM2_H, sound.ch3_wave_pattern[5]);
+            WRITE(WAVE_RAM3_L, sound.ch3_wave_pattern[6]);
+            WRITE(WAVE_RAM3_H, sound.ch3_wave_pattern[7]);
+            WRITE(SOUND4CNT_L, sound.ch4_length_env);
+            WRITE(SOUND4CNT_H, sound.ch4_freq_control);
+            WRITE(SOUNDCNT_L, sound.ctrl_stereo_volume);
+            WRITE(SOUNDCNT_H, sound.ctrl_mixing);
+            WRITE(SOUNDCNT_X, sound.ctrl_sound_on_off);
+            WRITE(SOUNDBIAS, sound.pwm_control);
+            WRITE(FIFO_A_L, sound.fifo_a[0]);
+            WRITE(FIFO_A_H, sound.fifo_a[1]);
+            WRITE(FIFO_B_L, sound.fifo_b[0]);
+            WRITE(FIFO_B_H, sound.fifo_b[1]);
+
+            // dma
+        case DMA0CNT_H:
+            dma.channels[0].control.write(halfword);
+            break;
+        case DMA1CNT_H:
+            dma.channels[1].control.write(halfword);
+            break;
+        case DMA2CNT_H:
+            dma.channels[2].control.write(halfword);
+            break;
+        case DMA3CNT_H:
+            dma.channels[3].control.write(halfword);
+            break;
+
+            WRITE(DMA0SAD, dma.channels[0].source[0]);
+            WRITE(DMA0SAD + 2, dma.channels[0].source[1]);
+            WRITE(DMA0DAD, dma.channels[0].destination[0]);
+            WRITE(DMA0DAD + 2, dma.channels[0].destination[1]);
+            WRITE(DMA0CNT_L, dma.channels[0].word_count);
+            WRITE(DMA1SAD, dma.channels[1].source[0]);
+            WRITE(DMA1SAD + 2, dma.channels[1].source[1]);
+            WRITE(DMA1DAD, dma.channels[1].destination[0]);
+            WRITE(DMA1DAD + 2, dma.channels[1].destination[1]);
+            WRITE(DMA1CNT_L, dma.channels[1].word_count);
+            WRITE(DMA2SAD, dma.channels[2].source[0]);
+            WRITE(DMA2SAD + 2, dma.channels[2].source[1]);
+            WRITE(DMA2DAD, dma.channels[2].destination[0]);
+            WRITE(DMA2DAD + 2, dma.channels[2].destination[1]);
+            WRITE(DMA2CNT_L, dma.channels[2].word_count);
+            WRITE(DMA3SAD, dma.channels[3].source[0]);
+            WRITE(DMA3SAD + 2, dma.channels[3].source[1]);
+            WRITE(DMA3DAD, dma.channels[3].destination[0]);
+            WRITE(DMA3DAD + 2, dma.channels[3].destination[1]);
+            WRITE(DMA3CNT_L, dma.channels[3].word_count);
+
+            // system
+            WRITE_2(POSTFLG, system.post_boot_flag, halfword & 1)
+            WRITE_2(IME, system.interrupt_master_enabler, halfword & 1)
+            WRITE(IE, system.interrupt_enable);
+            WRITE(IF, system.interrupt_request_flags);
+            WRITE(WAITCNT, system.waitstate_control);
+            WRITE_2(HALTCNT, system.low_power_mode, get_bit(halfword, 7));
 
 #undef WRITE
 #undef WRITE_2
@@ -276,4 +415,5 @@ IoDevices::write_halfword(uint32_t address, uint16_t halfword) {
     }
     return;
 }
+
 }

src/io/meson.build

@@ -1,3 +1,3 @@
 lib_sources += files(
-  'io.cc',
+  'io.cc'
 )

src/memory.cc

@@ -1,181 +0,0 @@
-#include "memory.hh"
-#include "header.hh"
-#include "util/crypto.hh"
-#include "util/log.hh"
-#include <stdexcept>
-
-namespace matar {
-Memory::Memory(std::array<uint8_t, BIOS_SIZE>&& bios,
-               std::vector<uint8_t>&& rom)
-  : bios(std::move(bios))
-  , board_wram({ 0 })
-  , chip_wram({ 0 })
-  , palette_ram({ 0 })
-  , vram({ 0 })
-  , oam_obj_attr({ 0 })
-  , rom(std::move(rom)) {
-    std::string bios_hash = crypto::sha256(this->bios);
-    static constexpr std::string_view expected_hash =
-      "fd2547724b505f487e6dcb29ec2ecff3af35a841a77ab2e85fd87350abd36570";
-
-    if (bios_hash != expected_hash) {
-        glogger.warn("BIOS hash failed to match, run at your own risk"
-                     "\nExpected : {} "
-                     "\nGot      : {}",
-                     expected_hash,
-                     bios_hash);
-    }
-
-    parse_header();
-
-    glogger.info("Memory successfully initialised");
-    glogger.info("Cartridge Title: {}", header.title);
-};
-
-uint8_t
-Memory::read(uint32_t address) const {
-#define MATCHES(AREA, area)                                                    \
-    if (address >= AREA##_START && address < AREA##_START + area.size())       \
-        return area[address - AREA##_START];
-
-    MATCHES(BIOS, bios)
-    MATCHES(BOARD_WRAM, board_wram)
-    MATCHES(CHIP_WRAM, chip_wram)
-    MATCHES(PALETTE_RAM, palette_ram)
-    MATCHES(VRAM, vram)
-    MATCHES(OAM_OBJ_ATTR, oam_obj_attr)
-    MATCHES(ROM_0, rom)
-    MATCHES(ROM_1, rom)
-    MATCHES(ROM_2, rom)
-
-    glogger.error("Invalid memory region accessed");
-    return 0xFF;
-
-#undef MATCHES
-}
-
-void
-Memory::write(uint32_t address, uint8_t byte) {
-#define MATCHES(AREA, area)                                                    \
-    if (address >= AREA##_START && address < AREA##_START + area.size()) {     \
-        area[address - AREA##_START] = byte;                                   \
-        return;                                                                \
-    }
-
-    MATCHES(BOARD_WRAM, board_wram)
-    MATCHES(CHIP_WRAM, chip_wram)
-    MATCHES(PALETTE_RAM, palette_ram)
-    MATCHES(VRAM, vram)
-    MATCHES(OAM_OBJ_ATTR, oam_obj_attr)
-
-    glogger.error("Invalid memory region accessed");
-
-#undef MATCHES
-}
-
-void
-Memory::parse_header() {
-    if (rom.size() < header.HEADER_SIZE) {
-        throw std::out_of_range(
-          "ROM is not large enough to even have a header");
-    }
-
-    // entrypoint
-    header.entrypoint =
-      rom[0x00] | rom[0x01] << 8 | rom[0x02] << 16 | rom[0x03] << 24;
-
-    // nintendo logo
-    if (rom[0x9C] != 0x21)
-        glogger.info("HEADER: BIOS debugger bits not set to 0");
-
-    // game info
-    header.title = std::string(&rom[0xA0], &rom[0xA0 + 12]);
-
-    switch (rom[0xAC]) {
-        case 'A':
-            header.unique_code = Header::UniqueCode::Old;
-            break;
-        case 'B':
-            header.unique_code = Header::UniqueCode::New;
-            break;
-        case 'C':
-            header.unique_code = Header::UniqueCode::Newer;
-            break;
-        case 'F':
-            header.unique_code = Header::UniqueCode::Famicom;
-            break;
-        case 'K':
-            header.unique_code = Header::UniqueCode::YoshiKoro;
-            break;
-        case 'P':
-            header.unique_code = Header::UniqueCode::Ereader;
-            break;
-        case 'R':
-            header.unique_code = Header::UniqueCode::Warioware;
-            break;
-        case 'U':
-            header.unique_code = Header::UniqueCode::Boktai;
-            break;
-        case 'V':
-            header.unique_code = Header::UniqueCode::DrillDozer;
-            break;
-
-        default:
-            glogger.error("HEADER: invalid unique code: {}", rom[0xAC]);
-    }
-
-    header.title_code = std::string(&rom[0xAD], &rom[0xAE]);
-
-    switch (rom[0xAF]) {
-        case 'J':
-            header.i18n = Header::I18n::Japan;
-            break;
-        case 'P':
-            header.i18n = Header::I18n::Europe;
-            break;
-        case 'F':
-            header.i18n = Header::I18n::French;
-            break;
-        case 'S':
-            header.i18n = Header::I18n::Spanish;
-            break;
-        case 'E':
-            header.i18n = Header::I18n::Usa;
-            break;
-        case 'D':
-            header.i18n = Header::I18n::German;
-            break;
-        case 'I':
-            header.i18n = Header::I18n::Italian;
-            break;
-
-        default:
-            glogger.error("HEADER: invalid destination/language: {}",
-                          rom[0xAF]);
-    }
-
-    if (rom[0xB2] != 0x96)
-        glogger.error("HEADER: invalid fixed byte at 0xB2");
-
-    for (uint32_t i = 0xB5; i < 0xBC; i++) {
-        if (rom[i] != 0x00)
-            glogger.error("HEADER: invalid fixed bytes at 0xB5");
-    }
-
-    header.version = rom[0xBC];
-
-    // checksum
-    {
-        uint32_t i = 0xA0, chk = 0;
-        while (i <= 0xBC)
-            chk -= rom[i++];
-        chk -= 0x19;
-        chk &= 0xFF;
-
-        if (chk != rom[0xBD])
-            glogger.error("HEADER: checksum does not match");
-    }
-
-    // multiboot not required right now
-}
-}

src/meson.build

@@ -1,18 +1,15 @@
 lib_sources = files(
-  'memory.cc',
   'bus.cc',
 )
 
+if get_option('gdb_debug')
+  lib_sources += files('gdb_rsp.cc')
+endif
+
 subdir('util')
 subdir('cpu')
 subdir('io')
 
-lib_cpp_args = []
-
-if get_option('disassembler')
-  lib_cpp_args += '-DDISASSEMBLER'
-endif
-
 lib = library(
   meson.project_name(),
   lib_sources,

src/util/meson.build

@@ -1,3 +1,8 @@
 lib_sources += files(
-  'log.cc'
+  'log.cc',
-)
+  'tcp_server.cc'
+)
+
+if get_option('gdb_debug')
+  lib_sources += files('tcp_server.cc')
+endif

src/util/tcp_server.cc

@@ -0,0 +1,89 @@
+#include "tcp_server.hh"
+#include <netinet/tcp.h>
+
+#include <cstring>
+#include <format>
+#include <sys/ioctl.h>
+#include <unistd.h>
+
+namespace net {
+TcpServer::TcpServer()
+  : server_fd(0)
+  , client_fd(0) {}
+
+TcpServer::~TcpServer() {
+    close(server_fd);
+    close(client_fd);
+}
+
+bool
+TcpServer::client_waiting() {
+    int count = 0;
+    ioctl(client_fd, FIONREAD, &count);
+    return static_cast<bool>(count);
+}
+
+void
+TcpServer::run() {
+    socklen_t cli_addr_size = sizeof(client_addr);
+
+    client_fd = ::accept(
+      server_fd, reinterpret_cast<sockaddr*>(&client_addr), &cli_addr_size);
+
+    if (client_fd == -1)
+        throw std::runtime_error("accept failed");
+}
+
+void
+TcpServer::start(uint port) {
+    int opts  = 0;
+    server_fd = socket(PF_INET, SOCK_STREAM, 0);
+    if (server_fd == -1) {
+        throw std::runtime_error("creating socket failed");
+    }
+
+    int option = 1;
+
+    opts +=
+      setsockopt(server_fd, SOL_SOCKET, SO_REUSEADDR, &option, sizeof(option));
+    opts +=
+      setsockopt(server_fd, IPPROTO_TCP, TCP_NODELAY, &option, sizeof(option));
+
+    if (opts != 0) {
+        throw std::runtime_error("failed to set socket opts");
+    }
+
+    std::memset(&server_addr, 0, sizeof(server_addr));
+    server_addr.sin_family      = PF_INET;
+    server_addr.sin_addr.s_addr = htonl(INADDR_ANY);
+    server_addr.sin_port        = htons(port);
+
+    if (::bind(server_fd,
+               reinterpret_cast<sockaddr*>(&server_addr),
+               sizeof(server_addr)) == -1) {
+        throw std::runtime_error("binding socket failed");
+    }
+    if (::listen(server_fd, 1) == -1) {
+        throw std::runtime_error("listening failed");
+    }
+}
+
+void
+TcpServer::send(std::string msg) {
+    if (::send(client_fd, msg.data(), msg.length(), 0) == -1) {
+        throw std::runtime_error(
+          std::format("failed to send message: {}\n", strerror(errno)));
+    }
+}
+
+std::string
+TcpServer::receive(uint length) {
+    ssize_t num_bytes = recv(client_fd, msg, length, 0);
+    msg[num_bytes]    = '\0';
+    if (num_bytes < 0) {
+        throw std::runtime_error(
+          std::format("failed to receive messages: {}\n", strerror(errno)));
+    }
+    return std::string(msg);
+}
+}

src/util/tcp_server.hh

@@ -0,0 +1,28 @@
+#pragma once
+
+#include <netinet/in.h>
+#include <string>
+
+namespace net {
+
+class TcpServer {
+  public:
+    TcpServer();
+    ~TcpServer();
+
+    void run();
+    void start(uint port);
+    void send(std::string msg);
+    std::string receive(uint length);
+    std::string receive_all() { return receive(MAX_PACKET_SIZE); };
+    bool client_waiting();
+
+  private:
+    static constexpr uint MAX_PACKET_SIZE = 4096;
+    char msg[MAX_PACKET_SIZE];
+    int server_fd;
+    int client_fd;
+    sockaddr_in server_addr;
+    sockaddr_in client_addr;
+};
+}

tests/bus.cc

@@ -8,38 +8,121 @@ using namespace matar;
 class BusFixture {
   public:
     BusFixture()
-      : bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+      : bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
-                   std::vector<uint8_t>(Header::HEADER_SIZE))) {}
+                      std::vector<uint8_t>(Header::HEADER_SIZE))) {}
 
   protected:
-    Bus bus;
+    std::shared_ptr<Bus> bus;
 };
 
-TEST_CASE_METHOD(BusFixture, "Byte", TAG) {
+TEST_CASE("bios", TAG) {
-    CHECK(bus.read_byte(0x30001A9) == 0);
+    std::array<uint8_t, Bus::BIOS_SIZE> bios = { 0 };
 
-    bus.write_byte(0x30001A9, 0xEC);
+    // populate bios
-    CHECK(bus.read_byte(0x30001A9) == 0xEC);
+    bios[0]      = 0xAC;
-    CHECK(bus.read_word(0x30001A9) == 0xEC);
+    bios[0x3FFF] = 0x48;
-    CHECK(bus.read_halfword(0x30001A9) == 0xEC);
+    bios[0x2A56] = 0x10;
+
+    auto bus =
+      Bus::init(std::move(bios), std::vector<uint8_t>(Header::HEADER_SIZE));
+
+    CHECK(bus->read_byte(0) == 0xAC);
+    CHECK(bus->read_byte(0x3FFF) == 0x48);
+    CHECK(bus->read_byte(0x2A56) == 0x10);
 }
 
-TEST_CASE_METHOD(BusFixture, "Halfword", TAG) {
+TEST_CASE_METHOD(BusFixture, "board wram", TAG) {
-    CHECK(bus.read_halfword(0x202FED9) == 0);
+    bus->write_byte(0x2000000, 0xAC);
+    CHECK(bus->read_byte(0x2000000) == 0xAC);
 
-    bus.write_halfword(0x202FED9, 0x1A4A);
+    bus->write_byte(0x203FFFF, 0x48);
-    CHECK(bus.read_halfword(0x202FED9) == 0x1A4A);
+    CHECK(bus->read_byte(0x203FFFF) == 0x48);
-    CHECK(bus.read_word(0x202FED9) == 0x1A4A);
+
-    CHECK(bus.read_byte(0x202FED9) == 0x4A);
+    bus->write_byte(0x2022A56, 0x10);
+    CHECK(bus->read_byte(0x2022A56) == 0x10);
 }
 
-TEST_CASE_METHOD(BusFixture, "Word", TAG) {
+TEST_CASE_METHOD(BusFixture, "chip wram", TAG) {
-    CHECK(bus.read_word(0x600EE34) == 0);
+    bus->write_byte(0x3000000, 0xAC);
+    CHECK(bus->read_byte(0x3000000) == 0xAC);
 
-    bus.write_word(0x600EE34, 0x3ACC491D);
+    bus->write_byte(0x3007FFF, 0x48);
-    CHECK(bus.read_word(0x600EE34) == 0x3ACC491D);
+    CHECK(bus->read_byte(0x3007FFF) == 0x48);
-    CHECK(bus.read_halfword(0x600EE34) == 0x491D);
+
-    CHECK(bus.read_byte(0x600EE34) == 0x1D);
+    bus->write_byte(0x3002A56, 0x10);
+    CHECK(bus->read_byte(0x3002A56) == 0x10);
+}
+
+TEST_CASE_METHOD(BusFixture, "palette ram", TAG) {
+    bus->write_byte(0x5000000, 0xAC);
+    CHECK(bus->read_byte(0x5000000) == 0xAC);
+
+    bus->write_byte(0x50003FF, 0x48);
+    CHECK(bus->read_byte(0x50003FF) == 0x48);
+
+    bus->write_byte(0x5000156, 0x10);
+    CHECK(bus->read_byte(0x5000156) == 0x10);
+}
+
+TEST_CASE_METHOD(BusFixture, "video ram", TAG) {
+    bus->write_byte(0x6000000, 0xAC);
+    CHECK(bus->read_byte(0x6000000) == 0xAC);
+
+    bus->write_byte(0x6017FFF, 0x48);
+    CHECK(bus->read_byte(0x6017FFF) == 0x48);
+
+    bus->write_byte(0x6012A56, 0x10);
+    CHECK(bus->read_byte(0x6012A56) == 0x10);
+}
+
+TEST_CASE_METHOD(BusFixture, "oam obj ram", TAG) {
+    bus->write_byte(0x7000000, 0xAC);
+    CHECK(bus->read_byte(0x7000000) == 0xAC);
+
+    bus->write_byte(0x70003FF, 0x48);
+    CHECK(bus->read_byte(0x70003FF) == 0x48);
+
+    bus->write_byte(0x7000156, 0x10);
+    CHECK(bus->read_byte(0x7000156) == 0x10);
+}
+
+TEST_CASE("rom", TAG) {
+    std::vector<uint8_t> rom(32 * 1024 * 1024, 0);
+
+    // populate rom
+    rom[0]         = 0xAC;
+    rom[0x1FFFFFF] = 0x48;
+    rom[0x0EF0256] = 0x10;
+
+    // 32 megabyte ROM
+    auto bus = Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(), std::move(rom));
+
+    SECTION("ROM1") {
+        CHECK(bus->read_byte(0x8000000) == 0xAC);
+        CHECK(bus->read_byte(0x9FFFFFF) == 0x48);
+        CHECK(bus->read_byte(0x8EF0256) == 0x10);
+    }
+
+    SECTION("ROM2") {
+        CHECK(bus->read_byte(0xA000000) == 0xAC);
+        CHECK(bus->read_byte(0xBFFFFFF) == 0x48);
+        CHECK(bus->read_byte(0xAEF0256) == 0x10);
+    }
+
+    SECTION("ROM3") {
+        CHECK(bus->read_byte(0xC000000) == 0xAC);
+        CHECK(bus->read_byte(0xDFFFFFF) == 0x48);
+        CHECK(bus->read_byte(0xCEF0256) == 0x10);
+    }
+}
+
+TEST_CASE_METHOD(BusFixture, "internal cycle", TAG) {
+    uint32_t cycles = bus->get_cycles();
+
+    bus->internal_cycle();
+    bus->internal_cycle();
+
+    CHECK(bus->get_cycles() == cycles + 2);
 }
 
 #undef TAG

tests/cpu/arm/exec.cc

@@ -15,9 +15,16 @@ TEST_CASE_METHOD(CpuFixture, "Branch and Exchange", TAG) {
 
     setr(3, 342800);
 
+    uint32_t cycles = bus->get_cycles();
     exec(data);
+    CHECK(bus->get_cycles() == cycles + 3);
 
-    CHECK(getr(15) == 342800);
+    INFO(getr(15));
+    INFO(getr(15));
+    INFO(getr(15));
+    INFO(getr(15));
+    // +8 cuz pipeline flush
+    CHECK(getr(15) == 342808);
 }
 
 TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
@@ -27,10 +34,13 @@ TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
     // set PC to 48
     setr(15, 48);
 
+    uint32_t cycles = bus->get_cycles();
     exec(data);
+    CHECK(bus->get_cycles() == cycles + 3);
 
     // 48 + offset
-    CHECK(getr(15) == 3489796);
+    // +8 cuz pipeline flush
+    CHECK(getr(15) == 3489804);
     CHECK(getr(14) == 0);
 
     // with link
@@ -40,7 +50,8 @@ TEST_CASE_METHOD(CpuFixture, "Branch", TAG) {
     exec(data);
 
     // 48 + offset
-    CHECK(getr(15) == 3489796);
+    // +8 cuz pipeline flush
+    CHECK(getr(15) == 3489804);
     // pc was set to 48
     CHECK(getr(14) == 48 - INSTRUCTION_SIZE);
 }
@@ -53,11 +64,13 @@ TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
 
     setr(10, 234912349);
     setr(11, 124897);
-    setr(3, 99999);
+    setr(3, 99999); // m = 3 since [32:24] bits are 0
 
     {
         uint32_t result = 234912349ull * 124897ull & 0xFFFFFFFF;
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 4); // S + mI
 
         CHECK(getr(5) == result);
     }
@@ -66,7 +79,9 @@ TEST_CASE_METHOD(CpuFixture, "Multiply", TAG) {
     {
         uint32_t result = (234912349ull * 124897ull + 99999ull) & 0xFFFFFFFF;
         multiply->acc   = true;
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 5); // S + mI + I
 
         CHECK(getr(5) == result);
     }
@@ -105,12 +120,14 @@ TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
     MultiplyLong* multiply_long = std::get_if<MultiplyLong>(&data);
 
     setr(10, 234912349);
-    setr(11, 124897);
+    setr(11, 124897); // m = 3
 
     // unsigned
     {
         uint64_t result = 234912349ull * 124897ull;
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 5); // S + (m+1)I
 
         CHECK(getr(3) == bit_range(result, 0, 31));
         CHECK(getr(5) == bit_range(result, 32, 63));
@@ -121,7 +138,9 @@ TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
         int64_t result = 234912349ll * -124897ll;
         setr(11, getr(11) * -1);
         multiply_long->uns = false;
+        uint32_t cycles    = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 5); // S + (m+1)I
 
         CHECK(getr(3) == static_cast<uint32_t>(bit_range(result, 0, 31)));
         CHECK(getr(5) == static_cast<uint32_t>(bit_range(result, 32, 63)));
@@ -136,7 +155,9 @@ TEST_CASE_METHOD(CpuFixture, "Multiply Long", TAG) {
           234912349ll * -124897ll + (99999ll | -444333391ll << 32);
 
         multiply_long->acc = true;
+        uint32_t cycles    = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 6); // S + (m+2)I
 
         CHECK(getr(3) == static_cast<uint32_t>(bit_range(result, 0, 31)));
         CHECK(getr(5) == static_cast<uint32_t>(bit_range(result, 32, 63)));
@@ -182,13 +203,15 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Swap", TAG) {
     setr(9, 0x3003FED);
     setr(3, 94235087);
     setr(3, -259039045);
-    bus.write_word(getr(9), 3241011111);
+    bus->write_word(getr(9), 3241011111);
 
     SECTION("word") {
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 4); // S + 2N + I
 
         CHECK(getr(4) == 3241011111);
-        CHECK(bus.read_word(getr(9)) == static_cast<uint32_t>(-259039045));
+        CHECK(bus->read_word(getr(9)) == static_cast<uint32_t>(-259039045));
     }
 
     SECTION("byte") {
@@ -196,7 +219,7 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Swap", TAG) {
         exec(data);
 
         CHECK(getr(4) == (3241011111 & 0xFF));
-        CHECK(bus.read_byte(getr(9)) ==
+        CHECK(bus->read_byte(getr(9)) ==
               static_cast<uint8_t>(-259039045 & 0xFF));
     }
 }
@@ -226,8 +249,10 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
     // shifted register (immediate)
     {
         // 0x31E + 0x3000004
-        bus.write_word(0x30031E4, 95995);
+        bus->write_word(0x30031E4, 95995);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I
 
         CHECK(getr(5) == 95995);
         setr(5, 0);
@@ -244,7 +269,7 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
 
         setr(12, 2);
         // 6384 + 0x3000004
-        bus.write_word(0x30018F4, 3948123487);
+        bus->write_word(0x30018F4, 3948123487);
         exec(data);
 
         CHECK(getr(5) == 3948123487);
@@ -254,7 +279,7 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
     {
         data_transfer->offset = static_cast<uint16_t>(0xDA1);
         // 0xDA1 + 0x3000004
-        bus.write_word(0x3000DA5, 68795467);
+        bus->write_word(0x3000DA5, 68795467);
 
         exec(data);
 
@@ -266,7 +291,7 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
         setr(7, 0x3005E0D);
         data_transfer->up = false;
         // 0x3005E0D - 0xDA1
-        bus.write_word(0x300506C, 5949595);
+        bus->write_word(0x300506C, 5949595);
 
         exec(data);
 
@@ -279,7 +304,7 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
     {
         data_transfer->write = true;
         // 0x3005E0D - 0xDA1
-        bus.write_word(0x300506C, 967844);
+        bus->write_word(0x300506C, 967844);
 
         exec(data);
 
@@ -292,7 +317,7 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
     {
         data_transfer->write = false;
         data_transfer->pre   = false;
-        bus.write_word(0x300506C, 61119);
+        bus->write_word(0x300506C, 61119);
 
         exec(data);
 
@@ -305,9 +330,11 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
     {
         data_transfer->load = false;
 
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 2); // 2N for store
 
-        CHECK(bus.read_word(0x30042CB) == 61119);
+        CHECK(bus->read_word(0x30042CB) == 61119);
         // 0x30042CB - 0xDA1
         CHECK(getr(7) == 0x300352A);
     }
@@ -315,13 +342,15 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
     // r15 as rn
     {
         data_transfer->rn = 15;
-        setr(15, 0x300352A);
+        setr(15, 0x300352C); // word aligned
 
         exec(data);
 
-        CHECK(bus.read_word(0x300352A) == 61119);
+        CHECK(bus->read_word(0x300352C) == 61119);
-        // 0x300352A - 0xDA1
+        // 0x300352C - 0xDA1
-        CHECK(getr(15) == 0x3002789);
+        // +4 cuz PC advanced
+        // and then word aligned
+        CHECK(getr(15) == 0x300278C);
 
         // cleanup
         data_transfer->rn = 7;
@@ -334,13 +363,12 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
 
         exec(data);
 
-        CHECK(bus.read_word(0x300352A + INSTRUCTION_SIZE) == 444444);
+        CHECK(bus->read_word(0x300352A) == 444444 + 4);
         // 0x300352A - 0xDA1
-        CHECK(getr(7) == 0x3002789 + INSTRUCTION_SIZE);
+        CHECK(getr(7) == 0x3002789);
 
         // cleanup
         data_transfer->rd = 5;
-        setr(7, getr(7) - INSTRUCTION_SIZE);
     }
 
     // byte
@@ -351,10 +379,33 @@ TEST_CASE_METHOD(CpuFixture, "Single Data Transfer", TAG) {
 
         exec(data);
 
-        CHECK(bus.read_word(0x3002789) == (458267584 & 0xFF));
+        CHECK(bus->read_word(0x3002789) == (458267584 & 0xFF));
         // 0x3002789 - 0xDA1
         CHECK(getr(7) == 0x30019E8);
     }
+
+    // r15 as rd with load
+    {
+        data_transfer->rd   = 15;
+        data_transfer->load = true;
+        setr(15, 0);
+        bus->write_byte(0x30019E8, 0xE2);
+
+        uint32_t cycles = bus->get_cycles();
+        exec(data);
+        CHECK(bus->get_cycles() ==
+              cycles + 5); // 2S + 2N + I for load with rd=15
+
+        // +8 cuz pipeline flushed then word aligned
+        // so +6
+        CHECK(getr(15) == 0xE8);
+
+        // 0x30019E8 - 0xDA1
+        CHECK(getr(7) == 0x3000C47);
+
+        // cleanup
+        data_transfer->rd = 5;
+    }
 }
 
 TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
@@ -377,8 +428,11 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
     // register offset
     {
         //  0x300611E  + 0x384
-        bus.write_word(0x30064A2, 3948123487);
+        bus->write_word(0x30064A2, 3948123487);
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I
 
         CHECK(getr(11) == (3948123487 & 0xFFFF));
     }
@@ -388,7 +442,7 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
         hw_transfer->imm    = true;
         hw_transfer->offset = 0xA7;
         // 0x300611E + 0xA7
-        bus.write_word(0x30061C5, 594633302);
+        bus->write_word(0x30061C5, 594633302);
         exec(data);
 
         CHECK(getr(11) == (594633302 & 0xFFFF));
@@ -398,7 +452,7 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
     {
         hw_transfer->up = false;
         // 0x300611E - 0xA7
-        bus.write_word(0x3006077, 222221);
+        bus->write_word(0x3006077, 222221);
 
         exec(data);
 
@@ -411,7 +465,7 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
     {
         hw_transfer->write = true;
         // 0x300611E - 0xA7
-        bus.write_word(0x3006077, 100000005);
+        bus->write_word(0x3006077, 100000005);
 
         exec(data);
 
@@ -423,7 +477,7 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
     {
         hw_transfer->pre   = false;
         hw_transfer->write = false;
-        bus.write_word(0x3006077, 6111909);
+        bus->write_word(0x3006077, 6111909);
 
         exec(data);
 
@@ -436,9 +490,11 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
     {
         hw_transfer->load = false;
 
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 2); // 2N
 
-        CHECK(bus.read_halfword(0x3005FD0) == (6111909 & 0xFFFF));
+        CHECK(bus->read_halfword(0x3005FD0) == (6111909 & 0xFFFF));
         // 0x3005FD0 - 0xA7
         CHECK(getr(10) == 0x3005F29);
     }
@@ -446,14 +502,15 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
     // r15 as rn
     {
         hw_transfer->rn = 15;
-        setr(15, 0x3005F29);
+        setr(15, 0x3005F28); // word aligned
 
         exec(data);
 
-        CHECK(bus.read_halfword(0x3005F29 - 2 * INSTRUCTION_SIZE) ==
+        CHECK(bus->read_halfword(0x3005F28) == (6111909 & 0xFFFF));
-              (6111909 & 0xFFFF));
+        // 0x3005F28 - 0xA7
-        // 0x3005F29 - 0xA7
+        // +4 cuz PC advanced
-        CHECK(getr(15) == 0x3005E82 - 2 * INSTRUCTION_SIZE);
+        // and then word aligned
+        CHECK(getr(15) == 0x3005E84);
 
         // cleanup
         hw_transfer->rn = 10;
@@ -466,20 +523,19 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
 
         exec(data);
 
-        CHECK(bus.read_halfword(0x3005F29 + INSTRUCTION_SIZE) == 224);
+        CHECK(bus->read_halfword(0x3005F29) == 224 + 4);
         // 0x3005F29 - 0xA7
-        CHECK(getr(10) == 0x3005E82 + INSTRUCTION_SIZE);
+        CHECK(getr(10) == 0x3005E82);
 
         // cleanup
         hw_transfer->rd = 11;
-        setr(10, getr(10) - INSTRUCTION_SIZE);
     }
 
     // signed halfword
     {
         hw_transfer->load = true;
         hw_transfer->sign = true;
-        bus.write_halfword(0x3005E82, -12345);
+        bus->write_halfword(0x3005E82, -12345);
 
         exec(data);
 
@@ -491,7 +547,7 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
     // signed byte
     {
         hw_transfer->half = false;
-        bus.write_byte(0x3005DDB, -56);
+        bus->write_byte(0x3005DDB, -56);
 
         exec(data);
 
@@ -499,6 +555,28 @@ TEST_CASE_METHOD(CpuFixture, "Halfword Transfer", TAG) {
         // 0x3005DDB - 0xA7
         CHECK(getr(10) == 0x3005D34);
     }
+
+    // r15 as rd with load
+    {
+        hw_transfer->rd   = 15;
+        hw_transfer->load = true;
+        setr(15, 0);
+        bus->write_byte(0x3005D34, 56);
+
+        uint32_t cycles = bus->get_cycles();
+        exec(data);
+        CHECK(bus->get_cycles() ==
+              cycles + 5); // 2S + 2N + I for load with rd=15
+
+        // +8 cuz pipeline flushed then word aligned
+        CHECK(getr(15) == static_cast<uint32_t>(56 + 8));
+
+        // 0x3005D34 - 0xA7
+        CHECK(getr(10) == 0x3005C8D);
+
+        // cleanup
+        hw_transfer->rd = 11;
+    }
 }
 
 TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
@@ -517,14 +595,14 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
     SECTION("load") {
         static constexpr uint32_t address = 0x3000D78;
         // populate memory
-        bus.write_word(address, 38947234);
+        bus->write_word(address, 38947234);
-        bus.write_word(address + alignment, 237164);
+        bus->write_word(address + alignment, 237164);
-        bus.write_word(address + alignment * 2, 679785111);
+        bus->write_word(address + alignment * 2, 679785111);
-        bus.write_word(address + alignment * 3, 905895898);
+        bus->write_word(address + alignment * 3, 905895898);
-        bus.write_word(address + alignment * 4, 131313333);
+        bus->write_word(address + alignment * 4, 131313333);
-        bus.write_word(address + alignment * 5, 131);
+        bus->write_word(address + alignment * 5, 131);
-        bus.write_word(address + alignment * 6, 989231);
+        bus->write_word(address + alignment * 6, 989231);
-        bus.write_word(address + alignment * 7, 6);
+        bus->write_word(address + alignment * 7, 6);
 
         auto checker = [this](uint32_t rnval = 0) {
             CHECK(getr(0) == 237164);
@@ -542,7 +620,10 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
             CHECK(getr(12) == 0);
             CHECK(getr(13) == 989231);
             CHECK(getr(14) == 0);
-            CHECK(getr(15) == 6);
+
+            // setting r15 as 6, flushes the pipeline causing it to go 6 + 8
+            // i.e, 14. word aligning this, gives us 12
+            CHECK(getr(15) == 12);
 
             for (uint8_t i = 0; i < 16; i++) {
                 setr(i, 0);
@@ -550,7 +631,9 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
         };
 
         setr(10, address);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 11); // (n+1)S + 2N + I
         checker(address);
 
         // with write
@@ -610,23 +693,30 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
         setr(8, 131313333);
         setr(11, 131);
         setr(13, 989231);
-        setr(15, 6);
+        setr(15, 4); // word align
 
-        auto checker = [this]() {
+        // we will count the number of steps to count PC advances
-            CHECK(bus.read_word(address + alignment) == 237164);
+        uint8_t steps = 0;
-            CHECK(bus.read_word(address + alignment * 2) == 679785111);
+
-            CHECK(bus.read_word(address + alignment * 3) == 905895898);
+        auto checker = [this, &steps]() {
-            CHECK(bus.read_word(address + alignment * 4) == 131313333);
+            CHECK(bus->read_word(address + alignment) == 237164);
-            CHECK(bus.read_word(address + alignment * 5) == 131);
+            CHECK(bus->read_word(address + alignment * 2) == 679785111);
-            CHECK(bus.read_word(address + alignment * 6) == 989231);
+            CHECK(bus->read_word(address + alignment * 3) == 905895898);
-            CHECK(bus.read_word(address + alignment * 7) == 6);
+            CHECK(bus->read_word(address + alignment * 4) == 131313333);
+            CHECK(bus->read_word(address + alignment * 5) == 131);
+            CHECK(bus->read_word(address + alignment * 6) == 989231);
+            CHECK(bus->read_word(address + alignment * 7) ==
+                  4 + (4 * (steps - 1)));
 
             for (uint8_t i = 1; i < 8; i++)
-                bus.write_word(address + alignment * i, 0);
+                bus->write_word(address + alignment * i, 0);
         };
 
         setr(10, address); // base
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 8); // 2N + (n-1)S
+        steps++;
         checker();
 
         // decrement
@@ -635,6 +725,7 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
         // adjust rn
         setr(10, address + alignment * 8);
         exec(data);
+        steps++;
         checker();
 
         // post increment
@@ -643,6 +734,7 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
         // adjust rn
         setr(10, address + alignment);
         exec(data);
+        steps++;
         checker();
 
         // post decrement
@@ -650,14 +742,16 @@ TEST_CASE_METHOD(CpuFixture, "Block Data Transfer", TAG) {
         // adjust rn
         setr(10, address + alignment * 7);
         exec(data);
+        steps++;
         checker();
 
         // with s bit
         cpu.chg_mode(Mode::Fiq);
         block_transfer->s = true;
         exec(data);
+        steps++;
         // User's R13 is different (unset at this point)
-        CHECK(bus.read_word(address + alignment * 6) == 0);
+        CHECK(bus->read_word(address + alignment * 6) == 0);
     }
 }
 
@@ -674,7 +768,9 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
         setr(12, 12389398);
 
         CHECK(psr().raw() != getr(12));
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
         CHECK(psr().raw() == getr(12));
 
         psr_transfer->spsr = true;
@@ -691,7 +787,9 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
         setr(12, 16556u << 8);
 
         CHECK(psr().raw() != getr(12));
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
         CHECK(psr().raw() == getr(12));
 
         psr_transfer->spsr = true;
@@ -708,7 +806,9 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
         setr(12, 1490352945);
         // go to the reserved bits
 
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
         CHECK(psr().n() == get_bit(1490352945, 31));
         CHECK(psr().z() == get_bit(1490352945, 30));
         CHECK(psr().c() == get_bit(1490352945, 29));
@@ -719,6 +819,7 @@ TEST_CASE_METHOD(CpuFixture, "PSR Transfer", TAG) {
         psr_transfer->imm     = true;
         psr_transfer->spsr    = true;
         exec(data);
+        CHECK(psr().n() == get_bit(1490352945, 31));
         CHECK(psr(true).n() == get_bit(9933394, 31));
         CHECK(psr(true).z() == get_bit(9933394, 30));
         CHECK(psr(true).c() == get_bit(9933394, 29));
@@ -750,7 +851,9 @@ TEST_CASE_METHOD(CpuFixture, "Data Processing", TAG) {
     {
         // rm
         setr(3, 1596);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
         // -28717 & 12768
         CHECK(getr(5) == 448);
     }
@@ -767,7 +870,11 @@ TEST_CASE_METHOD(CpuFixture, "Data Processing", TAG) {
         setr(3, 1596);
         // rs
         setr(12, 2);
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 2); // 1S + 1I
+
         // -28717 & 6384
         CHECK(getr(5) == 2256);
     }
@@ -1063,10 +1170,12 @@ TEST_CASE_METHOD(CpuFixture, "Data Processing", TAG) {
         processing->rd     = 15;
         setr(15, 0);
         CHECK(psr(true).raw() != psr().raw());
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // 2S + N
 
-        // ~54924809
+        // ~54924809 + 8 (for flush) and then word adjust
-        CHECK(getr(15) == static_cast<uint32_t>(-54924810));
+        CHECK(getr(15) == static_cast<uint32_t>(-54924804));
 
         // flags are not set
         flags(false, false, false, false);

tests/cpu/cpu-fixture.cc

@@ -2,6 +2,7 @@
 
 Psr
 CpuFixture::psr(bool spsr) {
+    uint32_t pc = getr(15);
     Psr psr(0);
     Cpu tmp = cpu;
     arm::Instruction instruction(
@@ -11,17 +12,19 @@ CpuFixture::psr(bool spsr) {
                         .type    = arm::PsrTransfer::Type::Mrs,
                         .imm     = false });
 
-    instruction.exec(tmp);
+    tmp.exec(instruction);
 
     psr.set_all(getr_(0, tmp));
+
+    // reset pc
+    setr(15, pc);
     return psr;
 }
 
 void
 CpuFixture::set_psr(Psr psr, bool spsr) {
-    // R0
+    uint32_t pc  = getr(15);
     uint32_t old = getr(0);
-
     setr(0, psr.raw());
 
     arm::Instruction instruction(
@@ -31,22 +34,23 @@ CpuFixture::set_psr(Psr psr, bool spsr) {
                         .type    = arm::PsrTransfer::Type::Msr,
                         .imm     = false });
 
-    instruction.exec(cpu);
+    cpu.exec(instruction);
 
     setr(0, old);
+
+    // reset PC
+    setr(15, pc);
 }
 
 // We need these workarounds to just use the public API and not private
 // fields. Assuming that these work correctly is necessary. Besides, all that
 // matters is that the public API is correct.
 uint32_t
-CpuFixture::getr_(uint8_t r, Cpu& cpu) {
+CpuFixture::getr_(uint8_t r, Cpu tmp) {
-    uint32_t addr  = 0x02000000;
+    uint32_t addr = 0x02000000;
-    uint8_t offset = r == 15 ? 4 : 0;
+    uint32_t word = bus->read_word(addr);
-    uint32_t word  = bus.read_word(addr + offset);
+    uint32_t ret  = 0xFFFFFFFF;
-    Cpu tmp        = cpu;
+    uint8_t base  = r ? 0 : 1;
-    uint32_t ret   = 0xFFFFFFFF;
-    uint8_t base   = r ? 0 : 1;
 
     // set R0/R1 = addr
     arm::Instruction zero(
@@ -69,16 +73,14 @@ CpuFixture::getr_(uint8_t r, Cpu& cpu) {
                                .up     = true,
                                .pre    = true });
 
-    zero.exec(tmp);
+    tmp.exec(zero);
-    get.exec(tmp);
+    tmp.exec(get);
 
-    addr += offset;
+    ret = bus->read_word(addr);
 
-    ret = bus.read_word(addr);
+    bus->write_word(addr, word);
 
-    bus.write_word(addr, word);
+    return ret - (r == 15 ? 4 : 0); // +4 for rd = 15 in str
-
-    return ret;
 }
 
 void
@@ -86,11 +88,12 @@ CpuFixture::setr_(uint8_t r, uint32_t value, Cpu& cpu) {
     // set register
     arm::Instruction set(
       Condition::AL,
-      arm::DataProcessing{ .operand = value,
+      arm::DataProcessing{
-                           .rd      = r,
+        .operand = (r == 15 ? value - 8 : value), // account for pipeline flush
-                           .rn      = 0,
+        .rd      = r,
-                           .set     = false,
+        .rn      = 0,
-                           .opcode  = arm::DataProcessing::OpCode::MOV });
+        .set     = false,
+        .opcode  = arm::DataProcessing::OpCode::MOV });
 
-    set.exec(cpu);
+    cpu.exec(set);
 }

tests/cpu/cpu-fixture.hh

@@ -5,37 +5,66 @@ using namespace matar;
 class CpuFixture {
   public:
     CpuFixture()
-      : bus(Memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
+      : bus(Bus::init(std::array<uint8_t, Bus::BIOS_SIZE>(),
-                   std::vector<uint8_t>(Header::HEADER_SIZE)))
+                      std::vector<uint8_t>(Header::HEADER_SIZE)))
       , cpu(bus) {}
 
   protected:
     void exec(arm::InstructionData data, Condition condition = Condition::AL) {
+        // hack to account for one fetch cycle
+        bus->internal_cycle();
+
         arm::Instruction instruction(condition, data);
-        instruction.exec(cpu);
+        cpu.exec(instruction);
     }
 
     void exec(thumb::InstructionData data) {
+        // hack to account for one fetch cycle
+        bus->internal_cycle();
+
         thumb::Instruction instruction(data);
-        instruction.exec(cpu);
+        cpu.exec(instruction);
     }
 
     void reset(uint32_t value = 0) { setr(15, value + 8); }
 
-    uint32_t getr(uint8_t r) { return getr_(r, cpu); }
+    uint32_t getr(uint8_t r) {
+        uint32_t pc = 0;
 
-    void setr(uint8_t r, uint32_t value) { setr_(r, value, cpu); }
+        if (r != 15)
+            pc = getr_(15, cpu);
+
+        uint32_t ret = getr_(r, cpu);
+
+        if (r == 15)
+            pc = ret;
+
+        // undo PC advance
+        setr_(15, pc, cpu);
+
+        return ret;
+    }
+
+    void setr(uint8_t r, uint32_t value) {
+        uint32_t pc = getr_(15, cpu);
+        setr_(r, value, cpu);
+
+        // undo PC advance when r != 15
+        // when r is 15, setr_ takes account of pipeline flush
+        if (r != 15)
+            setr_(15, pc, cpu);
+    }
 
     Psr psr(bool spsr = false);
 
     void set_psr(Psr psr, bool spsr = false);
 
-    Bus bus;
+    std::shared_ptr<Bus> bus;
     Cpu cpu;
 
   private:
     // hack to get a register
-    uint32_t getr_(uint8_t r, Cpu& cpu);
+    uint32_t getr_(uint8_t r, Cpu tmp);
 
     // hack to set a register
     void setr_(uint8_t r, uint32_t value, Cpu& cpu);

tests/cpu/thumb/exec.cc

@@ -18,7 +18,9 @@ TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
         setr(3, 0);
         setr(5, 6687);
         // LSL
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
         CHECK(getr(3) == 219119616);
 
         setr(5, 0);
@@ -32,7 +34,11 @@ TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
         move->opcode = ShiftType::LSR;
         setr(5, -1827489745);
         // LSR
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(3) == 75301);
         CHECK(!psr().n());
 
@@ -47,7 +53,11 @@ TEST_CASE_METHOD(CpuFixture, "Move Shifted Register", TAG) {
         setr(5, -1827489745);
         move->opcode = ShiftType::ASR;
         // ASR
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(psr().n());
         CHECK(getr(3) == 4294911525);
 
@@ -71,7 +81,10 @@ TEST_CASE_METHOD(CpuFixture, "Add/Subtract", TAG) {
 
     SECTION("ADD") {
         // register
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(5) == 377761225);
 
         add->imm = true;
@@ -94,7 +107,11 @@ TEST_CASE_METHOD(CpuFixture, "Add/Subtract", TAG) {
         add->opcode = AddSubtract::OpCode::SUB;
         setr(2, -((1u << 31) - 1));
         add->offset = 4;
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(5) == 2147483645);
         CHECK(psr().v());
 
@@ -122,7 +139,10 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
     MovCmpAddSubImmediate* move = std::get_if<MovCmpAddSubImmediate>(&data);
 
     SECTION("MOV") {
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(5) == 251);
 
         move->offset = 0;
@@ -136,7 +156,11 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
         setr(5, 251);
         move->opcode = MovCmpAddSubImmediate::OpCode::CMP;
         CHECK(!psr().z());
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(5) == 251);
         CHECK(psr().z());
 
@@ -152,7 +176,11 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
         move->opcode = MovCmpAddSubImmediate::OpCode::ADD;
         setr(5, (1u << 31) - 1);
         // immediate and overflow
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(5) == 2147483898);
         CHECK(psr().v());
 
@@ -168,7 +196,11 @@ TEST_CASE_METHOD(CpuFixture, "Move/Compare/Add/Subtract Immediate", TAG) {
         setr(5, 251);
         move->opcode = MovCmpAddSubImmediate::OpCode::SUB;
         CHECK(!psr().z());
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(5) == 0);
         CHECK(psr().z());
 
@@ -190,8 +222,11 @@ TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
     setr(3, -991);
 
     SECTION("AND") {
+        uint32_t cycles = bus->get_cycles();
         // 328940001 & -991
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
         CHECK(getr(1) == 328939553);
         CHECK(!psr().n());
 
@@ -221,8 +256,12 @@ TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
     SECTION("LSL") {
         setr(3, 3);
         alu->opcode = AluOperations::OpCode::LSL;
+
+        uint32_t cycles = bus->get_cycles();
         // 328940001 << 3
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 2); // 1S + 1I (shift)
+
         CHECK(getr(1) == 2631520008);
         CHECK(psr().n());
 
@@ -410,8 +449,12 @@ TEST_CASE_METHOD(CpuFixture, "ALU Operations", TAG) {
 
     SECTION("MUL") {
         alu->opcode = AluOperations::OpCode::MUL;
+
+        uint32_t cycles = bus->get_cycles();
         // 328940001 * -991 (lower 32 bits) (-325979540991 & 0xFFFFFFFF)
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + mI (m = 2 for -991)
+
         CHECK(getr(1) == 437973505);
 
         setr(3, 0);
@@ -462,19 +505,22 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
     };
     HiRegisterOperations* hi = std::get_if<HiRegisterOperations>(&data);
 
-    setr(15, 3452948950);
+    setr(15, 3452948948);
     setr(5, 958656720);
 
     SECTION("ADD") {
+        uint32_t cycles = bus->get_cycles();
         exec(data);
-        CHECK(getr(5) == 116638374);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
+        CHECK(getr(5) == 116638372);
 
         // hi + hi
         hi->rd = 14;
         hi->rs = 15;
         setr(14, 42589);
         exec(data);
-        CHECK(getr(14) == 3452991539);
+        CHECK(getr(14) == 3452991537);
     }
 
     SECTION("CMP") {
@@ -500,7 +546,7 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
         hi->opcode = HiRegisterOperations::OpCode::MOV;
         exec(data);
 
-        CHECK(getr(5) == 3452948950);
+        CHECK(getr(5) == 3452948948);
     }
 
     SECTION("BX") {
@@ -509,8 +555,13 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
 
         SECTION("Arm") {
             setr(10, 2189988);
+
+            uint32_t cycles = bus->get_cycles();
             exec(data);
-            CHECK(getr(15) == 2189988);
+            CHECK(bus->get_cycles() == cycles + 3); // 2S + N cycles
+
+            // +4 for pipeline flush
+            CHECK(getr(15) == 2189988 + 4);
             // switched to arm
             CHECK(psr().state() == State::Arm);
         }
@@ -518,7 +569,9 @@ TEST_CASE_METHOD(CpuFixture, "Hi Register Operations/Branch Exchange", TAG) {
         SECTION("Thumb") {
             setr(10, 2189989);
             exec(data);
-            CHECK(getr(15) == 2189988);
+
+            // +4 for pipeline flush
+            CHECK(getr(15) == 2189988 + 4);
 
             // switched to thumb
             CHECK(psr().state() == State::Thumb);
@@ -532,10 +585,14 @@ TEST_CASE_METHOD(CpuFixture, "PC Relative Load", TAG) {
     setr(15, 0x3003FD5);
     // resetting bit 0 for 0x3003FD5, we get 0x3003FD4
     // 0x3003FD4 + 0x578
-    bus.write_word(0x300454C, 489753492);
+    bus->write_word(0x300454C, 489753492);
 
     CHECK(getr(0) == 0);
+
+    uint32_t cycles = bus->get_cycles();
     exec(data);
+    CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
+
     CHECK(getr(0) == 489753492);
 }
 
@@ -551,21 +608,29 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store with Register Offset", TAG) {
 
     SECTION("store") {
         // 0x3003000 + 0x332
-        CHECK(bus.read_word(0x3003332) == 0);
+        CHECK(bus->read_word(0x3003332) == 0);
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
-        CHECK(bus.read_word(0x3003332) == 389524259);
+        CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
+
+        CHECK(bus->read_word(0x3003332) == 389524259);
 
         // byte
         load->byte = true;
-        bus.write_word(0x3003332, 0);
+        bus->write_word(0x3003332, 0);
         exec(data);
-        CHECK(bus.read_word(0x3003332) == 35);
+        CHECK(bus->read_word(0x3003332) == 35);
     }
 
     SECTION("load") {
         load->load = true;
-        bus.write_word(0x3003332, 11123489);
+        bus->write_word(0x3003332, 11123489);
+
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
+
         CHECK(getr(3) == 11123489);
 
         // byte
@@ -588,22 +653,28 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store Sign Extended Byte/Halfword", TAG) {
 
     SECTION("SH = 00") {
         // 0x3003000 + 0x332
-        CHECK(bus.read_word(0x3003332) == 0);
+        CHECK(bus->read_word(0x3003332) == 0);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
-        CHECK(bus.read_word(0x3003332) == 43811);
+        CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
+        CHECK(bus->read_word(0x3003332) == 43811);
     }
 
     SECTION("SH = 01") {
         load->h = true;
-        bus.write_word(0x3003332, 11123489);
+        bus->write_word(0x3003332, 11123489);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
         CHECK(getr(3) == 47905);
     }
 
     SECTION("SH = 10") {
         load->s = true;
-        bus.write_word(0x3003332, 34521594);
+        bus->write_word(0x3003332, 34521594);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
         // sign extended 250 byte (0xFA)
         CHECK(getr(3) == 4294967290);
     }
@@ -611,9 +682,11 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store Sign Extended Byte/Halfword", TAG) {
     SECTION("SH = 11") {
         load->s = true;
         load->h = true;
-        bus.write_word(0x3003332, 11123489);
+        bus->write_word(0x3003332, 11123489);
         // sign extended 47905 halfword (0xBB21)
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
         CHECK(getr(3) == 4294949665);
     }
 }
@@ -630,21 +703,25 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store with Immediate Offset", TAG) {
 
     SECTION("store") {
         // 0x30066A + 0x6E
-        CHECK(bus.read_word(0x30066D8) == 0);
+        CHECK(bus->read_word(0x30066D8) == 0);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
-        CHECK(bus.read_word(0x30066D8) == 389524259);
+        CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
+        CHECK(bus->read_word(0x30066D8) == 389524259);
 
         // byte
         load->byte = true;
-        bus.write_word(0x30066D8, 0);
+        bus->write_word(0x30066D8, 0);
         exec(data);
-        CHECK(bus.read_word(0x30066D8) == 35);
+        CHECK(bus->read_word(0x30066D8) == 35);
     }
 
     SECTION("load") {
         load->load = true;
-        bus.write_word(0x30066D8, 11123489);
+        bus->write_word(0x30066D8, 11123489);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
         CHECK(getr(3) == 11123489);
 
         // byte
@@ -664,15 +741,19 @@ TEST_CASE_METHOD(CpuFixture, "Load/Store Halfword", TAG) {
 
     SECTION("store") {
         // 0x300666A + 0x6E
-        CHECK(bus.read_word(0x30066D8) == 0);
+        CHECK(bus->read_word(0x30066D8) == 0);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
-        CHECK(bus.read_word(0x30066D8) == 43811);
+        CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
+        CHECK(bus->read_word(0x30066D8) == 43811);
     }
 
     SECTION("load") {
         load->load = true;
-        bus.write_word(0x30066D8, 11123489);
+        bus->write_word(0x30066D8, 11123489);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
         CHECK(getr(3) == 47905);
     }
 }
@@ -688,15 +769,19 @@ TEST_CASE_METHOD(CpuFixture, "SP Relative Load", TAG) {
 
     SECTION("store") {
         // 0x3004A8A + 0x328
-        CHECK(bus.read_word(0x3004DB2) == 0);
+        CHECK(bus->read_word(0x3004DB2) == 0);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
-        CHECK(bus.read_word(0x3004DB2) == 2349505744);
+        CHECK(bus->get_cycles() == cycles + 2); // 2N cycles
+        CHECK(bus->read_word(0x3004DB2) == 2349505744);
     }
 
     SECTION("load") {
         load->load = true;
-        bus.write_word(0x3004DB2, 11123489);
+        bus->write_word(0x3004DB2, 11123489);
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 3); // S + N + I cycles
         CHECK(getr(1) == 11123489);
     }
 }
@@ -711,8 +796,11 @@ TEST_CASE_METHOD(CpuFixture, "Load Address", TAG) {
     setr(13, 69879977);
 
     SECTION("PC") {
+        uint32_t cycles = bus->get_cycles();
         exec(data);
-        CHECK(getr(1) == 337293);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+        // word align 337293
+        CHECK(getr(1) == 337292);
     }
 
     SECTION("SP") {
@@ -730,7 +818,9 @@ TEST_CASE_METHOD(CpuFixture, "Add Offset to Stack Pointer", TAG) {
     setr(13, 69879977);
 
     SECTION("positive") {
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
         CHECK(getr(13) == 69880450);
     }
 
@@ -761,18 +851,20 @@ TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
 
         auto checker = [this]() {
             // address
-            CHECK(bus.read_word(address) == 237164);
+            CHECK(bus->read_word(address) == 237164);
-            CHECK(bus.read_word(address + alignment) == 679785111);
+            CHECK(bus->read_word(address + alignment) == 679785111);
-            CHECK(bus.read_word(address + alignment * 2) == 905895898);
+            CHECK(bus->read_word(address + alignment * 2) == 905895898);
-            CHECK(bus.read_word(address + alignment * 3) == 131313333);
+            CHECK(bus->read_word(address + alignment * 3) == 131313333);
-            CHECK(bus.read_word(address + alignment * 4) == 131);
+            CHECK(bus->read_word(address + alignment * 4) == 131);
         };
 
         // set stack pointer to top of stack
         setr(13, address + alignment * 5);
 
         SECTION("without LR") {
+            uint32_t cycles = bus->get_cycles();
             exec(data);
+            CHECK(bus->get_cycles() == cycles + 6); // 2N + (n-1)S, n = 5
             checker();
             CHECK(getr(13) == address);
         }
@@ -783,9 +875,12 @@ TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
             setr(14, 999304);
             // add another word on stack (top + 4)
             setr(13, address + alignment * 6);
-            exec(data);
 
-            CHECK(bus.read_word(address + alignment * 5) == 999304);
+            uint32_t cycles = bus->get_cycles();
+            exec(data);
+            CHECK(bus->get_cycles() == cycles + 7); // 2N + nS, n = 5
+
+            CHECK(bus->read_word(address + alignment * 5) == 999304);
             checker();
             CHECK(getr(13) == address);
         }
@@ -795,11 +890,11 @@ TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
         push->load = true;
 
         // populate memory
-        bus.write_word(address, 237164);
+        bus->write_word(address, 237164);
-        bus.write_word(address + alignment, 679785111);
+        bus->write_word(address + alignment, 679785111);
-        bus.write_word(address + alignment * 2, 905895898);
+        bus->write_word(address + alignment * 2, 905895898);
-        bus.write_word(address + alignment * 3, 131313333);
+        bus->write_word(address + alignment * 3, 131313333);
-        bus.write_word(address + alignment * 4, 131);
+        bus->write_word(address + alignment * 4, 131);
 
         auto checker = [this]() {
             CHECK(getr(0) == 237164);
@@ -819,19 +914,25 @@ TEST_CASE_METHOD(CpuFixture, "Push/Pop Registers", TAG) {
         // set stack pointer to bottom of stack
         setr(13, address);
 
-        SECTION("without SP") {
+        SECTION("without PC") {
+            uint32_t cycles = bus->get_cycles();
             exec(data);
+            CHECK(bus->get_cycles() == cycles + 7); // nS + N + I, n = 5
             checker();
             CHECK(getr(13) == address + alignment * 5);
         }
 
-        SECTION("with SP") {
+        SECTION("with PC") {
             push->pclr = true;
             // populate next address
-            bus.write_word(address + alignment * 5, 93333912);
+            bus->write_word(address + alignment * 5, 93333912);
-            exec(data);
 
-            CHECK(getr(15) == 93333912);
+            uint32_t cycles = bus->get_cycles();
+            exec(data);
+            CHECK(bus->get_cycles() == cycles + 10); //(n+2)S + 2N + I, n = 5
+
+            // +4 for flushed pipeline
+            CHECK(getr(15) == 93333912 + 4);
             checker();
             CHECK(getr(13) == address + alignment * 6);
         }
@@ -855,34 +956,40 @@ TEST_CASE_METHOD(CpuFixture, "Multiple Load/Store", TAG) {
         setr(6, 131313333);
         setr(7, 131);
 
-        // set R2 (base) to top of stack
+        // base
-        setr(2, address + alignment * 5);
+        setr(2, address);
 
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 6); //(n-1)S + 2N, n = 5
+
+        CHECK(bus->read_word(address) == 237164);
+        CHECK(bus->read_word(address + alignment) == address);
+        CHECK(bus->read_word(address + alignment * 2) == 905895898);
+        CHECK(bus->read_word(address + alignment * 3) == 131313333);
+        CHECK(bus->read_word(address + alignment * 4) == 131);
 
-        CHECK(bus.read_word(address) == 237164);
-        CHECK(bus.read_word(address + alignment) == address + alignment * 5);
-        CHECK(bus.read_word(address + alignment * 2) == 905895898);
-        CHECK(bus.read_word(address + alignment * 3) == 131313333);
-        CHECK(bus.read_word(address + alignment * 4) == 131);
         // write back
-        CHECK(getr(2) == address);
+        CHECK(getr(2) == address + alignment * 5);
     }
 
     SECTION("load") {
         push->load = true;
 
         // populate memory
-        bus.write_word(address, 237164);
+        bus->write_word(address, 237164);
-        bus.write_word(address + alignment, 679785111);
+        bus->write_word(address + alignment, 679785111);
-        bus.write_word(address + alignment * 2, 905895898);
+        bus->write_word(address + alignment * 2, 905895898);
-        bus.write_word(address + alignment * 3, 131313333);
+        bus->write_word(address + alignment * 3, 131313333);
-        bus.write_word(address + alignment * 4, 131);
+        bus->write_word(address + alignment * 4, 131);
 
         // base
         setr(2, address);
 
+        uint32_t cycles = bus->get_cycles();
         exec(data);
+        CHECK(bus->get_cycles() == cycles + 7); // nS + N + 1, n = 5
+
         CHECK(getr(0) == 237164);
         CHECK(getr(1) == 0);
         CHECK(getr(2) == address + alignment * 5); // write back
@@ -899,72 +1006,93 @@ TEST_CASE_METHOD(CpuFixture, "Conditional Branch", TAG) {
       ConditionalBranch{ .offset = -192, .condition = Condition::EQ };
     ConditionalBranch* branch = std::get_if<ConditionalBranch>(&data);
 
+    Psr cpsr = psr();
+    cpsr.set_state(State::Thumb);
+
     setr(15, 4589344);
 
     SECTION("z") {
-        Psr cpsr = psr();
+        uint32_t cycles = bus->get_cycles();
         // condition is false
         exec(data);
-        CHECK(getr(15) == 4589344);
+        CHECK(bus->get_cycles() == cycles + 1); // 1S
+
+        // +2 for pc advance
+        CHECK(getr(15) == 4589344 + 2);
 
         cpsr.set_z(true);
         set_psr(cpsr);
+        cycles = bus->get_cycles();
         // condition is true
         exec(data);
-        CHECK(getr(15) == 4589152);
+        CHECK(bus->get_cycles() == cycles + 3); // 2S + N
+        // +4 for pipeline flush
+        CHECK(getr(15) == 4589156);
     }
 
     SECTION("c") {
         branch->condition = Condition::CS;
-        Psr cpsr          = psr();
         // condition is false
         exec(data);
-        CHECK(getr(15) == 4589344);
+
+        // +2 for pc advance
+        CHECK(getr(15) == 4589346);
 
         cpsr.set_c(true);
         set_psr(cpsr);
         // condition is true
         exec(data);
-        CHECK(getr(15) == 4589152);
+        // +4 for pipeline flush
+        CHECK(getr(15) == 4589156);
     }
 
     SECTION("n") {
         branch->condition = Condition::MI;
-        Psr cpsr          = psr();
         // condition is false
         exec(data);
-        CHECK(getr(15) == 4589344);
+
+        // +2 for pc advance
+        CHECK(getr(15) == 4589346);
 
         cpsr.set_n(true);
         set_psr(cpsr);
         // condition is true
         exec(data);
-        CHECK(getr(15) == 4589152);
+        // +4 for pipeline flush
+        CHECK(getr(15) == 4589156);
     }
 
     SECTION("v") {
         branch->condition = Condition::VS;
-        Psr cpsr          = psr();
         // condition is false
         exec(data);
-        CHECK(getr(15) == 4589344);
+
+        // +2 for pc advance
+        CHECK(getr(15) == 4589346);
 
         cpsr.set_v(true);
         set_psr(cpsr);
         // condition is true
         exec(data);
-        CHECK(getr(15) == 4589152);
+        // +4 for pipeline flush
+        CHECK(getr(15) == 4589156);
     }
 }
 
 TEST_CASE_METHOD(CpuFixture, "Software Interrupt", TAG) {
-    InstructionData data = SoftwareInterrupt{ .vector = 33 };
+    InstructionData data = SoftwareInterrupt{ .vector = 32 };
 
     setr(15, 4492);
+
+    uint32_t cycles = bus->get_cycles();
+    // condition is true
     exec(data);
+    CHECK(bus->get_cycles() == cycles + 3); // 2S + N
+
     CHECK(psr().raw() == psr(true).raw());
     CHECK(getr(14) == 4490);
-    CHECK(getr(15) == 33);
+    // +4 for flushed pipeline
+    CHECK(getr(15) == 36);
     CHECK(psr().state() == State::Arm);
     CHECK(psr().mode() == Mode::Supervisor);
 }
@@ -973,23 +1101,39 @@ TEST_CASE_METHOD(CpuFixture, "Unconditional Branch", TAG) {
     InstructionData data = UnconditionalBranch{ .offset = -920 };
 
     setr(15, 4589344);
+
+    uint32_t cycles = bus->get_cycles();
     exec(data);
-    CHECK(getr(15) == 4588424);
+    CHECK(bus->get_cycles() == cycles + 3); // 2S + N
+
+    // +4 for flushed pipeline
+    CHECK(getr(15) == 4588428);
 }
 
 TEST_CASE_METHOD(CpuFixture, "Long Branch With Link", TAG) {
-    InstructionData data = LongBranchWithLink{ .offset = 3262, .high = false };
+    InstructionData data =
+      LongBranchWithLink{ .offset = 0b10010111110, .low = false };
     LongBranchWithLink* branch = std::get_if<LongBranchWithLink>(&data);
 
     // high
     setr(15, 4589344);
 
+    uint32_t cycles = bus->get_cycles();
     exec(data);
-    CHECK(getr(14) == 2881312);
+    CHECK(bus->get_cycles() == cycles + 1); // 1S
+
+    CHECK(getr(14) == 1173280);
 
     // low
-    branch->high = true;
+    branch->low = true;
+
+    cycles = bus->get_cycles();
     exec(data);
+    CHECK(bus->get_cycles() == cycles + 3); // 2S + N
+
+    // +2 for advancing thumb, then -2 to get the next instruciton of current
+    // executing instruction, then set bit 0
     CHECK(getr(14) == 4589343);
-    CHECK(getr(15) == 2884574);
+    // 1175712 + 4 for flushed pipeline
+    CHECK(getr(15) == 1175712);
 }

tests/cpu/thumb/instruction.cc

@@ -447,20 +447,20 @@ TEST_CASE("Unconditional Branch") {
 }
 
 TEST_CASE("Long Branch with link") {
-    uint16_t raw = 0b1111010011101100;
+    uint16_t raw = 0b1111110011101100;
     Instruction instruction(raw);
     LongBranchWithLink* bl = nullptr;
 
     REQUIRE((bl = std::get_if<LongBranchWithLink>(&instruction.data)));
     // 1260 << 1
-    CHECK(bl->offset == 2520);
+    CHECK(bl->offset == 1260);
-    CHECK(bl->high == false);
+    CHECK(bl->low == true);
 
 #ifdef DISASSEMBLER
-    CHECK(instruction.disassemble() == "BL #2520");
+    CHECK(instruction.disassemble() == "BL #1260");
 
-    bl->high = true;
+    bl->low = false;
-    CHECK(instruction.disassemble() == "BLH #2520");
+    CHECK(instruction.disassemble() == "BLH #1260");
 #endif
 }
 

tests/memory.cc

@@ -1,118 +0,0 @@
-#include "memory.hh"
-#include <catch2/catch_test_macros.hpp>
-
-#define TAG "[memory]"
-
-using namespace matar;
-
-class MemFixture {
-  public:
-    MemFixture()
-      : memory(std::array<uint8_t, Memory::BIOS_SIZE>(),
-               std::vector<uint8_t>(Header::HEADER_SIZE)) {}
-
-  protected:
-    Memory memory;
-};
-
-TEST_CASE("bios", TAG) {
-    std::array<uint8_t, Memory::BIOS_SIZE> bios = { 0 };
-
-    // populate bios
-    bios[0]      = 0xAC;
-    bios[0x3FFF] = 0x48;
-    bios[0x2A56] = 0x10;
-
-    Memory memory(std::move(bios), std::vector<uint8_t>(Header::HEADER_SIZE));
-
-    CHECK(memory.read(0) == 0xAC);
-    CHECK(memory.read(0x3FFF) == 0x48);
-    CHECK(memory.read(0x2A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "board wram", TAG) {
-    memory.write(0x2000000, 0xAC);
-    CHECK(memory.read(0x2000000) == 0xAC);
-
-    memory.write(0x203FFFF, 0x48);
-    CHECK(memory.read(0x203FFFF) == 0x48);
-
-    memory.write(0x2022A56, 0x10);
-    CHECK(memory.read(0x2022A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "chip wram", TAG) {
-    memory.write(0x3000000, 0xAC);
-    CHECK(memory.read(0x3000000) == 0xAC);
-
-    memory.write(0x3007FFF, 0x48);
-    CHECK(memory.read(0x3007FFF) == 0x48);
-
-    memory.write(0x3002A56, 0x10);
-    CHECK(memory.read(0x3002A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "palette ram", TAG) {
-    memory.write(0x5000000, 0xAC);
-    CHECK(memory.read(0x5000000) == 0xAC);
-
-    memory.write(0x50003FF, 0x48);
-    CHECK(memory.read(0x50003FF) == 0x48);
-
-    memory.write(0x5000156, 0x10);
-    CHECK(memory.read(0x5000156) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "video ram", TAG) {
-    memory.write(0x6000000, 0xAC);
-    CHECK(memory.read(0x6000000) == 0xAC);
-
-    memory.write(0x6017FFF, 0x48);
-    CHECK(memory.read(0x6017FFF) == 0x48);
-
-    memory.write(0x6012A56, 0x10);
-    CHECK(memory.read(0x6012A56) == 0x10);
-}
-
-TEST_CASE_METHOD(MemFixture, "oam obj ram", TAG) {
-    memory.write(0x7000000, 0xAC);
-    CHECK(memory.read(0x7000000) == 0xAC);
-
-    memory.write(0x70003FF, 0x48);
-    CHECK(memory.read(0x70003FF) == 0x48);
-
-    memory.write(0x7000156, 0x10);
-    CHECK(memory.read(0x7000156) == 0x10);
-}
-
-TEST_CASE("rom", TAG) {
-    std::vector<uint8_t> rom(32 * 1024 * 1024, 0);
-
-    // populate rom
-    rom[0]         = 0xAC;
-    rom[0x1FFFFFF] = 0x48;
-    rom[0x0EF0256] = 0x10;
-
-    // 32 megabyte ROM
-    Memory memory(std::array<uint8_t, Memory::BIOS_SIZE>(), std::move(rom));
-
-    SECTION("ROM1") {
-        CHECK(memory.read(0x8000000) == 0xAC);
-        CHECK(memory.read(0x9FFFFFF) == 0x48);
-        CHECK(memory.read(0x8EF0256) == 0x10);
-    }
-
-    SECTION("ROM2") {
-        CHECK(memory.read(0xA000000) == 0xAC);
-        CHECK(memory.read(0xBFFFFFF) == 0x48);
-        CHECK(memory.read(0xAEF0256) == 0x10);
-    }
-
-    SECTION("ROM3") {
-        CHECK(memory.read(0xC000000) == 0xAC);
-        CHECK(memory.read(0xDFFFFFF) == 0x48);
-        CHECK(memory.read(0xCEF0256) == 0x10);
-    }
-}
-
-#undef TAG

tests/meson.build

@@ -6,19 +6,14 @@ src = include_directories('../src')
 
 tests_sources = files(
   'main.cc',
-  'bus.cc',
+  'bus.cc'
-  'memory.cc'
 )
 
+tests_cpp_args = lib_cpp_args
+
 subdir('cpu')
 subdir('util')
 
-tests_cpp_args = []
-
-if get_option('disassembler')
-  tests_cpp_args += '-DDISASSEMBLER'
-endif
-
 catch2 = dependency('catch2', version: '>=3.4.0', static: true)
 catch2_tests = executable(
   'matar_tests',